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gerrit-public.fairphone.software / kernel / msm-5.4 / b25ee66f2d4e5f14e69d75a7363e55889e9aff92 / . / drivers / scsi / qla4xxx / ql4_nx.c
blob: 74582cb46a283478cd7830efc48b921fcd6b8249 [file] [log] [blame]
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2009 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7#include <linux/delay.h>
Jiri Slabya6751cc2010-09-14 14:12:54 +0200[diff] [blame]8#include <linux/io.h>
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]9#include <linux/pci.h>
10#include "ql4_def.h"
11#include "ql4_glbl.h"
12
13#define MASK(n) DMA_BIT_MASK(n)
14#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
15#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
16#define MS_WIN(addr) (addr & 0x0ffc0000)
17#define QLA82XX_PCI_MN_2M (0)
18#define QLA82XX_PCI_MS_2M (0x80000)
19#define QLA82XX_PCI_OCM0_2M (0xc0000)
20#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
21#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
22
23/* CRB window related */
24#define CRB_BLK(off) ((off >> 20) & 0x3f)
25#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
26#define CRB_WINDOW_2M (0x130060)
27#define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \
28 ((off) & 0xf0000))
29#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
30#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
31#define CRB_INDIRECT_2M (0x1e0000UL)
32
33static inline void __iomem *
34qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
35{
36 if ((off < ha->first_page_group_end) &&
37 (off >= ha->first_page_group_start))
38 return (void __iomem *)(ha->nx_pcibase + off);
39
40 return NULL;
41}
42
43#define MAX_CRB_XFORM 60
44static unsigned long crb_addr_xform[MAX_CRB_XFORM];
45static int qla4_8xxx_crb_table_initialized;
46
47#define qla4_8xxx_crb_addr_transform(name) \
48 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
49 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
50static void
51qla4_8xxx_crb_addr_transform_setup(void)
52{
53 qla4_8xxx_crb_addr_transform(XDMA);
54 qla4_8xxx_crb_addr_transform(TIMR);
55 qla4_8xxx_crb_addr_transform(SRE);
56 qla4_8xxx_crb_addr_transform(SQN3);
57 qla4_8xxx_crb_addr_transform(SQN2);
58 qla4_8xxx_crb_addr_transform(SQN1);
59 qla4_8xxx_crb_addr_transform(SQN0);
60 qla4_8xxx_crb_addr_transform(SQS3);
61 qla4_8xxx_crb_addr_transform(SQS2);
62 qla4_8xxx_crb_addr_transform(SQS1);
63 qla4_8xxx_crb_addr_transform(SQS0);
64 qla4_8xxx_crb_addr_transform(RPMX7);
65 qla4_8xxx_crb_addr_transform(RPMX6);
66 qla4_8xxx_crb_addr_transform(RPMX5);
67 qla4_8xxx_crb_addr_transform(RPMX4);
68 qla4_8xxx_crb_addr_transform(RPMX3);
69 qla4_8xxx_crb_addr_transform(RPMX2);
70 qla4_8xxx_crb_addr_transform(RPMX1);
71 qla4_8xxx_crb_addr_transform(RPMX0);
72 qla4_8xxx_crb_addr_transform(ROMUSB);
73 qla4_8xxx_crb_addr_transform(SN);
74 qla4_8xxx_crb_addr_transform(QMN);
75 qla4_8xxx_crb_addr_transform(QMS);
76 qla4_8xxx_crb_addr_transform(PGNI);
77 qla4_8xxx_crb_addr_transform(PGND);
78 qla4_8xxx_crb_addr_transform(PGN3);
79 qla4_8xxx_crb_addr_transform(PGN2);
80 qla4_8xxx_crb_addr_transform(PGN1);
81 qla4_8xxx_crb_addr_transform(PGN0);
82 qla4_8xxx_crb_addr_transform(PGSI);
83 qla4_8xxx_crb_addr_transform(PGSD);
84 qla4_8xxx_crb_addr_transform(PGS3);
85 qla4_8xxx_crb_addr_transform(PGS2);
86 qla4_8xxx_crb_addr_transform(PGS1);
87 qla4_8xxx_crb_addr_transform(PGS0);
88 qla4_8xxx_crb_addr_transform(PS);
89 qla4_8xxx_crb_addr_transform(PH);
90 qla4_8xxx_crb_addr_transform(NIU);
91 qla4_8xxx_crb_addr_transform(I2Q);
92 qla4_8xxx_crb_addr_transform(EG);
93 qla4_8xxx_crb_addr_transform(MN);
94 qla4_8xxx_crb_addr_transform(MS);
95 qla4_8xxx_crb_addr_transform(CAS2);
96 qla4_8xxx_crb_addr_transform(CAS1);
97 qla4_8xxx_crb_addr_transform(CAS0);
98 qla4_8xxx_crb_addr_transform(CAM);
99 qla4_8xxx_crb_addr_transform(C2C1);
100 qla4_8xxx_crb_addr_transform(C2C0);
101 qla4_8xxx_crb_addr_transform(SMB);
102 qla4_8xxx_crb_addr_transform(OCM0);
103 qla4_8xxx_crb_addr_transform(I2C0);
104
105 qla4_8xxx_crb_table_initialized = 1;
106}
107
108static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
109 {{{0, 0, 0, 0} } }, /* 0: PCI */
110 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
111 {1, 0x0110000, 0x0120000, 0x130000},
112 {1, 0x0120000, 0x0122000, 0x124000},
113 {1, 0x0130000, 0x0132000, 0x126000},
114 {1, 0x0140000, 0x0142000, 0x128000},
115 {1, 0x0150000, 0x0152000, 0x12a000},
116 {1, 0x0160000, 0x0170000, 0x110000},
117 {1, 0x0170000, 0x0172000, 0x12e000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x01e0000, 0x01e0800, 0x122000},
125 {0, 0x0000000, 0x0000000, 0x000000} } },
126 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
127 {{{0, 0, 0, 0} } }, /* 3: */
128 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
129 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
130 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
131 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
132 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {1, 0x08f0000, 0x08f2000, 0x172000} } },
148 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {1, 0x09f0000, 0x09f2000, 0x176000} } },
164 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
180 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
196 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
197 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
198 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
199 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
200 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
201 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
202 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
203 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
204 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
205 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
206 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
207 {{{0, 0, 0, 0} } }, /* 23: */
208 {{{0, 0, 0, 0} } }, /* 24: */
209 {{{0, 0, 0, 0} } }, /* 25: */
210 {{{0, 0, 0, 0} } }, /* 26: */
211 {{{0, 0, 0, 0} } }, /* 27: */
212 {{{0, 0, 0, 0} } }, /* 28: */
213 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
214 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
215 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
216 {{{0} } }, /* 32: PCI */
217 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
218 {1, 0x2110000, 0x2120000, 0x130000},
219 {1, 0x2120000, 0x2122000, 0x124000},
220 {1, 0x2130000, 0x2132000, 0x126000},
221 {1, 0x2140000, 0x2142000, 0x128000},
222 {1, 0x2150000, 0x2152000, 0x12a000},
223 {1, 0x2160000, 0x2170000, 0x110000},
224 {1, 0x2170000, 0x2172000, 0x12e000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000} } },
233 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
234 {{{0} } }, /* 35: */
235 {{{0} } }, /* 36: */
236 {{{0} } }, /* 37: */
237 {{{0} } }, /* 38: */
238 {{{0} } }, /* 39: */
239 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
240 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
241 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
242 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
243 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
244 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
245 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
246 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
247 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
248 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
249 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
250 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
251 {{{0} } }, /* 52: */
252 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
253 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
254 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
255 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
256 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
257 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
258 {{{0} } }, /* 59: I2C0 */
259 {{{0} } }, /* 60: I2C1 */
260 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
261 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
262 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
263};
264
265/*
266 * top 12 bits of crb internal address (hub, agent)
267 */
268static unsigned qla4_8xxx_crb_hub_agt[64] = {
269 0,
270 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
273 0,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
296 0,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
299 0,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
301 0,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
303 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
304 0,
305 0,
306 0,
307 0,
308 0,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
310 0,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
321 0,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
326 0,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
330 0,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
332 0,
333};
334
335/* Device states */
336static char *qdev_state[] = {
337 "Unknown",
338 "Cold",
339 "Initializing",
340 "Ready",
341 "Need Reset",
342 "Need Quiescent",
343 "Failed",
344 "Quiescent",
345};
346
347/*
348 * In: 'off' is offset from CRB space in 128M pci map
349 * Out: 'off' is 2M pci map addr
350 * side effect: lock crb window
351 */
352static void
353qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
354{
355 u32 win_read;
356
357 ha->crb_win = CRB_HI(*off);
358 writel(ha->crb_win,
359 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
360
361 /* Read back value to make sure write has gone through before trying
362 * to use it. */
363 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
364 if (win_read != ha->crb_win) {
365 DEBUG2(ql4_printk(KERN_INFO, ha,
366 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
367 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
368 }
369 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
370}
371
372void
373qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
374{
375 unsigned long flags = 0;
376 int rv;
377
378 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
379
380 BUG_ON(rv == -1);
381
382 if (rv == 1) {
383 write_lock_irqsave(&ha->hw_lock, flags);
384 qla4_8xxx_crb_win_lock(ha);
385 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
386 }
387
388 writel(data, (void __iomem *)off);
389
390 if (rv == 1) {
391 qla4_8xxx_crb_win_unlock(ha);
392 write_unlock_irqrestore(&ha->hw_lock, flags);
393 }
394}
395
396int
397qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off)
398{
399 unsigned long flags = 0;
400 int rv;
401 u32 data;
402
403 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
404
405 BUG_ON(rv == -1);
406
407 if (rv == 1) {
408 write_lock_irqsave(&ha->hw_lock, flags);
409 qla4_8xxx_crb_win_lock(ha);
410 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
411 }
412 data = readl((void __iomem *)off);
413
414 if (rv == 1) {
415 qla4_8xxx_crb_win_unlock(ha);
416 write_unlock_irqrestore(&ha->hw_lock, flags);
417 }
418 return data;
419}
420
421#define CRB_WIN_LOCK_TIMEOUT 100000000
422
423int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha)
424{
425 int i;
426 int done = 0, timeout = 0;
427
428 while (!done) {
429 /* acquire semaphore3 from PCI HW block */
430 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
431 if (done == 1)
432 break;
433 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
434 return -1;
435
436 timeout++;
437
438 /* Yield CPU */
439 if (!in_interrupt())
440 schedule();
441 else {
442 for (i = 0; i < 20; i++)
443 cpu_relax(); /*This a nop instr on i386*/
444 }
445 }
446 qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
447 return 0;
448}
449
450void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha)
451{
452 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
453}
454
455#define IDC_LOCK_TIMEOUT 100000000
456
457/**
458 * qla4_8xxx_idc_lock - hw_lock
459 * @ha: pointer to adapter structure
460 *
461 * General purpose lock used to synchronize access to
462 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
463 **/
464int qla4_8xxx_idc_lock(struct scsi_qla_host *ha)
465{
466 int i;
467 int done = 0, timeout = 0;
468
469 while (!done) {
470 /* acquire semaphore5 from PCI HW block */
471 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
472 if (done == 1)
473 break;
474 if (timeout >= IDC_LOCK_TIMEOUT)
475 return -1;
476
477 timeout++;
478
479 /* Yield CPU */
480 if (!in_interrupt())
481 schedule();
482 else {
483 for (i = 0; i < 20; i++)
484 cpu_relax(); /*This a nop instr on i386*/
485 }
486 }
487 return 0;
488}
489
490void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha)
491{
492 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
493}
494
495int
496qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
497{
498 struct crb_128M_2M_sub_block_map *m;
499
500 if (*off >= QLA82XX_CRB_MAX)
501 return -1;
502
503 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
504 *off = (*off - QLA82XX_PCI_CAMQM) +
505 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
506 return 0;
507 }
508
509 if (*off < QLA82XX_PCI_CRBSPACE)
510 return -1;
511
512 *off -= QLA82XX_PCI_CRBSPACE;
513 /*
514 * Try direct map
515 */
516
517 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
518
519 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
520 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
521 return 0;
522 }
523
524 /*
525 * Not in direct map, use crb window
526 */
527 return 1;
528}
529
530/* PCI Windowing for DDR regions. */
531#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
532 (((addr) <= (high)) && ((addr) >= (low)))
533
534/*
535* check memory access boundary.
536* used by test agent. support ddr access only for now
537*/
538static unsigned long
539qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha,
540 unsigned long long addr, int size)
541{
542 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
543 QLA82XX_ADDR_DDR_NET_MAX) ||
544 !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
545 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
546 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
547 return 0;
548 }
549 return 1;
550}
551
552static int qla4_8xxx_pci_set_window_warning_count;
553
554static unsigned long
555qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
556{
557 int window;
558 u32 win_read;
559
560 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
561 QLA82XX_ADDR_DDR_NET_MAX)) {
562 /* DDR network side */
563 window = MN_WIN(addr);
564 ha->ddr_mn_window = window;
565 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
566 QLA82XX_PCI_CRBSPACE, window);
567 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
568 QLA82XX_PCI_CRBSPACE);
569 if ((win_read << 17) != window) {
570 ql4_printk(KERN_WARNING, ha,
571 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
572 __func__, window, win_read);
573 }
574 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
575 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
576 QLA82XX_ADDR_OCM0_MAX)) {
577 unsigned int temp1;
578 /* if bits 19:18&17:11 are on */
579 if ((addr & 0x00ff800) == 0xff800) {
580 printk("%s: QM access not handled.\n", __func__);
581 addr = -1UL;
582 }
583
584 window = OCM_WIN(addr);
585 ha->ddr_mn_window = window;
586 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
587 QLA82XX_PCI_CRBSPACE, window);
588 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
589 QLA82XX_PCI_CRBSPACE);
590 temp1 = ((window & 0x1FF) << 7) |
591 ((window & 0x0FFFE0000) >> 17);
592 if (win_read != temp1) {
593 printk("%s: Written OCMwin (0x%x) != Read"
594 " OCMwin (0x%x)\n", __func__, temp1, win_read);
595 }
596 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
597
598 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
599 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
600 /* QDR network side */
601 window = MS_WIN(addr);
602 ha->qdr_sn_window = window;
603 qla4_8xxx_wr_32(ha, ha->ms_win_crb |
604 QLA82XX_PCI_CRBSPACE, window);
605 win_read = qla4_8xxx_rd_32(ha,
606 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
607 if (win_read != window) {
608 printk("%s: Written MSwin (0x%x) != Read "
609 "MSwin (0x%x)\n", __func__, window, win_read);
610 }
611 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
612
613 } else {
614 /*
615 * peg gdb frequently accesses memory that doesn't exist,
616 * this limits the chit chat so debugging isn't slowed down.
617 */
618 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) ||
619 (qla4_8xxx_pci_set_window_warning_count%64 == 0)) {
620 printk("%s: Warning:%s Unknown address range!\n",
621 __func__, DRIVER_NAME);
622 }
623 addr = -1UL;
624 }
625 return addr;
626}
627
628/* check if address is in the same windows as the previous access */
629static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
630 unsigned long long addr)
631{
632 int window;
633 unsigned long long qdr_max;
634
635 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
636
637 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
638 QLA82XX_ADDR_DDR_NET_MAX)) {
639 /* DDR network side */
640 BUG(); /* MN access can not come here */
641 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
642 QLA82XX_ADDR_OCM0_MAX)) {
643 return 1;
644 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
645 QLA82XX_ADDR_OCM1_MAX)) {
646 return 1;
647 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
648 qdr_max)) {
649 /* QDR network side */
650 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
651 if (ha->qdr_sn_window == window)
652 return 1;
653 }
654
655 return 0;
656}
657
658static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
659 u64 off, void *data, int size)
660{
661 unsigned long flags;
662 void __iomem *addr;
663 int ret = 0;
664 u64 start;
665 void __iomem *mem_ptr = NULL;
666 unsigned long mem_base;
667 unsigned long mem_page;
668
669 write_lock_irqsave(&ha->hw_lock, flags);
670
671 /*
672 * If attempting to access unknown address or straddle hw windows,
673 * do not access.
674 */
675 start = qla4_8xxx_pci_set_window(ha, off);
676 if ((start == -1UL) ||
677 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
678 write_unlock_irqrestore(&ha->hw_lock, flags);
679 printk(KERN_ERR"%s out of bound pci memory access. "
680 "offset is 0x%llx\n", DRIVER_NAME, off);
681 return -1;
682 }
683
684 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
685 if (!addr) {
686 write_unlock_irqrestore(&ha->hw_lock, flags);
687 mem_base = pci_resource_start(ha->pdev, 0);
688 mem_page = start & PAGE_MASK;
689 /* Map two pages whenever user tries to access addresses in two
690 consecutive pages.
691 */
692 if (mem_page != ((start + size - 1) & PAGE_MASK))
693 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
694 else
695 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
696
697 if (mem_ptr == NULL) {
698 *(u8 *)data = 0;
699 return -1;
700 }
701 addr = mem_ptr;
702 addr += start & (PAGE_SIZE - 1);
703 write_lock_irqsave(&ha->hw_lock, flags);
704 }
705
706 switch (size) {
707 case 1:
708 *(u8 *)data = readb(addr);
709 break;
710 case 2:
711 *(u16 *)data = readw(addr);
712 break;
713 case 4:
714 *(u32 *)data = readl(addr);
715 break;
716 case 8:
717 *(u64 *)data = readq(addr);
718 break;
719 default:
720 ret = -1;
721 break;
722 }
723 write_unlock_irqrestore(&ha->hw_lock, flags);
724
725 if (mem_ptr)
726 iounmap(mem_ptr);
727 return ret;
728}
729
730static int
731qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
732 void *data, int size)
733{
734 unsigned long flags;
735 void __iomem *addr;
736 int ret = 0;
737 u64 start;
738 void __iomem *mem_ptr = NULL;
739 unsigned long mem_base;
740 unsigned long mem_page;
741
742 write_lock_irqsave(&ha->hw_lock, flags);
743
744 /*
745 * If attempting to access unknown address or straddle hw windows,
746 * do not access.
747 */
748 start = qla4_8xxx_pci_set_window(ha, off);
749 if ((start == -1UL) ||
750 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
751 write_unlock_irqrestore(&ha->hw_lock, flags);
752 printk(KERN_ERR"%s out of bound pci memory access. "
753 "offset is 0x%llx\n", DRIVER_NAME, off);
754 return -1;
755 }
756
757 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
758 if (!addr) {
759 write_unlock_irqrestore(&ha->hw_lock, flags);
760 mem_base = pci_resource_start(ha->pdev, 0);
761 mem_page = start & PAGE_MASK;
762 /* Map two pages whenever user tries to access addresses in two
763 consecutive pages.
764 */
765 if (mem_page != ((start + size - 1) & PAGE_MASK))
766 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
767 else
768 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
769 if (mem_ptr == NULL)
770 return -1;
771
772 addr = mem_ptr;
773 addr += start & (PAGE_SIZE - 1);
774 write_lock_irqsave(&ha->hw_lock, flags);
775 }
776
777 switch (size) {
778 case 1:
779 writeb(*(u8 *)data, addr);
780 break;
781 case 2:
782 writew(*(u16 *)data, addr);
783 break;
784 case 4:
785 writel(*(u32 *)data, addr);
786 break;
787 case 8:
788 writeq(*(u64 *)data, addr);
789 break;
790 default:
791 ret = -1;
792 break;
793 }
794 write_unlock_irqrestore(&ha->hw_lock, flags);
795 if (mem_ptr)
796 iounmap(mem_ptr);
797 return ret;
798}
799
800#define MTU_FUDGE_FACTOR 100
801
802static unsigned long
803qla4_8xxx_decode_crb_addr(unsigned long addr)
804{
805 int i;
806 unsigned long base_addr, offset, pci_base;
807
808 if (!qla4_8xxx_crb_table_initialized)
809 qla4_8xxx_crb_addr_transform_setup();
810
811 pci_base = ADDR_ERROR;
812 base_addr = addr & 0xfff00000;
813 offset = addr & 0x000fffff;
814
815 for (i = 0; i < MAX_CRB_XFORM; i++) {
816 if (crb_addr_xform[i] == base_addr) {
817 pci_base = i << 20;
818 break;
819 }
820 }
821 if (pci_base == ADDR_ERROR)
822 return pci_base;
823 else
824 return pci_base + offset;
825}
826
827static long rom_max_timeout = 100;
828static long qla4_8xxx_rom_lock_timeout = 100;
829
830static int
831qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
832{
833 int i;
834 int done = 0, timeout = 0;
835
836 while (!done) {
837 /* acquire semaphore2 from PCI HW block */
838
839 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
840 if (done == 1)
841 break;
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]842 if (timeout >= qla4_8xxx_rom_lock_timeout) {
843 ql4_printk(KERN_WARNING, ha,
844 "%s: Failed to acquire rom lock", __func__);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]845 return -1;
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]846 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]847
848 timeout++;
849
850 /* Yield CPU */
851 if (!in_interrupt())
852 schedule();
853 else {
854 for (i = 0; i < 20; i++)
855 cpu_relax(); /*This a nop instr on i386*/
856 }
857 }
858 qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
859 return 0;
860}
861
862static void
863qla4_8xxx_rom_unlock(struct scsi_qla_host *ha)
864{
865 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
866}
867
868static int
869qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha)
870{
871 long timeout = 0;
872 long done = 0 ;
873
874 while (done == 0) {
875 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
876 done &= 2;
877 timeout++;
878 if (timeout >= rom_max_timeout) {
879 printk("%s: Timeout reached waiting for rom done",
880 DRIVER_NAME);
881 return -1;
882 }
883 }
884 return 0;
885}
886
887static int
888qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
889{
890 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
891 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
892 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
893 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
894 if (qla4_8xxx_wait_rom_done(ha)) {
895 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
896 return -1;
897 }
898 /* reset abyte_cnt and dummy_byte_cnt */
899 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
900 udelay(10);
901 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
902
903 *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
904 return 0;
905}
906
907static int
908qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
909{
910 int ret, loops = 0;
911
912 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
913 udelay(100);
914 loops++;
915 }
916 if (loops >= 50000) {
917 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME);
918 return -1;
919 }
920 ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp);
921 qla4_8xxx_rom_unlock(ha);
922 return ret;
923}
924
925/**
926 * This routine does CRB initialize sequence
927 * to put the ISP into operational state
928 **/
929static int
930qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
931{
932 int addr, val;
933 int i ;
934 struct crb_addr_pair *buf;
935 unsigned long off;
936 unsigned offset, n;
937
938 struct crb_addr_pair {
939 long addr;
940 long data;
941 };
942
943 /* Halt all the indiviual PEGs and other blocks of the ISP */
944 qla4_8xxx_rom_lock(ha);
945 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
946 /* don't reset CAM block on reset */
947 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
948 else
949 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
950
951 qla4_8xxx_rom_unlock(ha);
952
953 /* Read the signature value from the flash.
954 * Offset 0: Contain signature (0xcafecafe)
955 * Offset 4: Offset and number of addr/value pairs
956 * that present in CRB initialize sequence
957 */
958 if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
959 qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) {
960 ql4_printk(KERN_WARNING, ha,
961 "[ERROR] Reading crb_init area: n: %08x\n", n);
962 return -1;
963 }
964
965 /* Offset in flash = lower 16 bits
966 * Number of enteries = upper 16 bits
967 */
968 offset = n & 0xffffU;
969 n = (n >> 16) & 0xffffU;
970
971 /* number of addr/value pair should not exceed 1024 enteries */
972 if (n >= 1024) {
973 ql4_printk(KERN_WARNING, ha,
974 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
975 DRIVER_NAME, __func__, n);
976 return -1;
977 }
978
979 ql4_printk(KERN_INFO, ha,
980 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
981
982 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
983 if (buf == NULL) {
984 ql4_printk(KERN_WARNING, ha,
985 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
986 return -1;
987 }
988
989 for (i = 0; i < n; i++) {
990 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
991 qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
992 0) {
993 kfree(buf);
994 return -1;
995 }
996
997 buf[i].addr = addr;
998 buf[i].data = val;
999 }
1000
1001 for (i = 0; i < n; i++) {
1002 /* Translate internal CRB initialization
1003 * address to PCI bus address
1004 */
1005 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) +
1006 QLA82XX_PCI_CRBSPACE;
1007 /* Not all CRB addr/value pair to be written,
1008 * some of them are skipped
1009 */
1010
1011 /* skip if LS bit is set*/
1012 if (off & 0x1) {
1013 DEBUG2(ql4_printk(KERN_WARNING, ha,
1014 "Skip CRB init replay for offset = 0x%lx\n", off));
1015 continue;
1016 }
1017
1018 /* skipping cold reboot MAGIC */
1019 if (off == QLA82XX_CAM_RAM(0x1fc))
1020 continue;
1021
1022 /* do not reset PCI */
1023 if (off == (ROMUSB_GLB + 0xbc))
1024 continue;
1025
1026 /* skip core clock, so that firmware can increase the clock */
1027 if (off == (ROMUSB_GLB + 0xc8))
1028 continue;
1029
1030 /* skip the function enable register */
1031 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1032 continue;
1033
1034 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1035 continue;
1036
1037 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1038 continue;
1039
1040 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1041 continue;
1042
1043 if (off == ADDR_ERROR) {
1044 ql4_printk(KERN_WARNING, ha,
1045 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1046 DRIVER_NAME, buf[i].addr);
1047 continue;
1048 }
1049
1050 qla4_8xxx_wr_32(ha, off, buf[i].data);
1051
1052 /* ISP requires much bigger delay to settle down,
1053 * else crb_window returns 0xffffffff
1054 */
1055 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1056 msleep(1000);
1057
1058 /* ISP requires millisec delay between
1059 * successive CRB register updation
1060 */
1061 msleep(1);
1062 }
1063
1064 kfree(buf);
1065
1066 /* Resetting the data and instruction cache */
1067 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1068 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1069 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1070
1071 /* Clear all protocol processing engines */
1072 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1073 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1074 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1075 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1076 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1077 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1078 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1079 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1080
1081 return 0;
1082}
1083
1084static int qla4_8xxx_check_for_bad_spd(struct scsi_qla_host *ha)
1085{
1086 u32 val = 0;
1087 val = qla4_8xxx_rd_32(ha, BOOT_LOADER_DIMM_STATUS) ;
1088 val &= QLA82XX_BOOT_LOADER_MN_ISSUE;
1089 if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) {
1090 printk("Memory DIMM SPD not programmed. Assumed valid.\n");
1091 return 1;
1092 } else if (val) {
1093 printk("Memory DIMM type incorrect. Info:%08X.\n", val);
1094 return 2;
1095 }
1096 return 0;
1097}
1098
1099static int
1100qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1101{
1102 int i;
1103 long size = 0;
1104 long flashaddr, memaddr;
1105 u64 data;
1106 u32 high, low;
1107
1108 flashaddr = memaddr = ha->hw.flt_region_bootload;
1109 size = (image_start - flashaddr)/8;
1110
1111 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1112 ha->host_no, __func__, flashaddr, image_start));
1113
1114 for (i = 0; i < size; i++) {
1115 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1116 (qla4_8xxx_rom_fast_read(ha, flashaddr + 4,
1117 (int *)&high))) {
1118 return -1;
1119 }
1120 data = ((u64)high << 32) | low ;
1121 qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8);
1122 flashaddr += 8;
1123 memaddr += 8;
1124
1125 if (i%0x1000 == 0)
1126 msleep(1);
1127
1128 }
1129
1130 udelay(100);
1131
1132 read_lock(&ha->hw_lock);
1133 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1134 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1135 read_unlock(&ha->hw_lock);
1136
1137 return 0;
1138}
1139
1140static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1141{
1142 u32 rst;
1143
1144 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1145 if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1146 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1147 __func__);
1148 return QLA_ERROR;
1149 }
1150
1151 udelay(500);
1152
1153 /* at this point, QM is in reset. This could be a problem if there are
1154 * incoming d* transition queue messages. QM/PCIE could wedge.
1155 * To get around this, QM is brought out of reset.
1156 */
1157
1158 rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1159 /* unreset qm */
1160 rst &= ~(1 << 28);
1161 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1162
1163 if (qla4_8xxx_load_from_flash(ha, image_start)) {
1164 printk("%s: Error trying to load fw from flash!\n", __func__);
1165 return QLA_ERROR;
1166 }
1167
1168 return QLA_SUCCESS;
1169}
1170
1171int
1172qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1173 u64 off, void *data, int size)
1174{
1175 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1176 int shift_amount;
1177 uint32_t temp;
1178 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1179
1180 /*
1181 * If not MN, go check for MS or invalid.
1182 */
1183
1184 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1185 mem_crb = QLA82XX_CRB_QDR_NET;
1186 else {
1187 mem_crb = QLA82XX_CRB_DDR_NET;
1188 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1189 return qla4_8xxx_pci_mem_read_direct(ha,
1190 off, data, size);
1191 }
1192
1193
1194 off8 = off & 0xfffffff0;
1195 off0[0] = off & 0xf;
1196 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1197 shift_amount = 4;
1198
1199 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1200 off0[1] = 0;
1201 sz[1] = size - sz[0];
1202
1203 for (i = 0; i < loop; i++) {
1204 temp = off8 + (i << shift_amount);
1205 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1206 temp = 0;
1207 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1208 temp = MIU_TA_CTL_ENABLE;
1209 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1210 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1211 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1212
1213 for (j = 0; j < MAX_CTL_CHECK; j++) {
1214 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1215 if ((temp & MIU_TA_CTL_BUSY) == 0)
1216 break;
1217 }
1218
1219 if (j >= MAX_CTL_CHECK) {
1220 if (printk_ratelimit())
1221 ql4_printk(KERN_ERR, ha,
1222 "failed to read through agent\n");
1223 break;
1224 }
1225
1226 start = off0[i] >> 2;
1227 end = (off0[i] + sz[i] - 1) >> 2;
1228 for (k = start; k <= end; k++) {
1229 temp = qla4_8xxx_rd_32(ha,
1230 mem_crb + MIU_TEST_AGT_RDDATA(k));
1231 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1232 }
1233 }
1234
1235 if (j >= MAX_CTL_CHECK)
1236 return -1;
1237
1238 if ((off0[0] & 7) == 0) {
1239 val = word[0];
1240 } else {
1241 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1242 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1243 }
1244
1245 switch (size) {
1246 case 1:
1247 *(uint8_t *)data = val;
1248 break;
1249 case 2:
1250 *(uint16_t *)data = val;
1251 break;
1252 case 4:
1253 *(uint32_t *)data = val;
1254 break;
1255 case 8:
1256 *(uint64_t *)data = val;
1257 break;
1258 }
1259 return 0;
1260}
1261
1262int
1263qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1264 u64 off, void *data, int size)
1265{
1266 int i, j, ret = 0, loop, sz[2], off0;
1267 int scale, shift_amount, startword;
1268 uint32_t temp;
1269 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1270
1271 /*
1272 * If not MN, go check for MS or invalid.
1273 */
1274 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1275 mem_crb = QLA82XX_CRB_QDR_NET;
1276 else {
1277 mem_crb = QLA82XX_CRB_DDR_NET;
1278 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1279 return qla4_8xxx_pci_mem_write_direct(ha,
1280 off, data, size);
1281 }
1282
1283 off0 = off & 0x7;
1284 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1285 sz[1] = size - sz[0];
1286
1287 off8 = off & 0xfffffff0;
1288 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1289 shift_amount = 4;
1290 scale = 2;
1291 startword = (off & 0xf)/8;
1292
1293 for (i = 0; i < loop; i++) {
1294 if (qla4_8xxx_pci_mem_read_2M(ha, off8 +
1295 (i << shift_amount), &word[i * scale], 8))
1296 return -1;
1297 }
1298
1299 switch (size) {
1300 case 1:
1301 tmpw = *((uint8_t *)data);
1302 break;
1303 case 2:
1304 tmpw = *((uint16_t *)data);
1305 break;
1306 case 4:
1307 tmpw = *((uint32_t *)data);
1308 break;
1309 case 8:
1310 default:
1311 tmpw = *((uint64_t *)data);
1312 break;
1313 }
1314
1315 if (sz[0] == 8)
1316 word[startword] = tmpw;
1317 else {
1318 word[startword] &=
1319 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1320 word[startword] |= tmpw << (off0 * 8);
1321 }
1322
1323 if (sz[1] != 0) {
1324 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1325 word[startword+1] |= tmpw >> (sz[0] * 8);
1326 }
1327
1328 for (i = 0; i < loop; i++) {
1329 temp = off8 + (i << shift_amount);
1330 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1331 temp = 0;
1332 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1333 temp = word[i * scale] & 0xffffffff;
1334 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1335 temp = (word[i * scale] >> 32) & 0xffffffff;
1336 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1337 temp = word[i*scale + 1] & 0xffffffff;
1338 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1339 temp);
1340 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1341 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1342 temp);
1343
1344 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1345 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1346 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1347 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1348
1349 for (j = 0; j < MAX_CTL_CHECK; j++) {
1350 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1351 if ((temp & MIU_TA_CTL_BUSY) == 0)
1352 break;
1353 }
1354
1355 if (j >= MAX_CTL_CHECK) {
1356 if (printk_ratelimit())
1357 ql4_printk(KERN_ERR, ha,
1358 "failed to write through agent\n");
1359 ret = -1;
1360 break;
1361 }
1362 }
1363
1364 return ret;
1365}
1366
1367static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1368{
1369 u32 val = 0;
1370 int retries = 60;
1371
1372 if (!pegtune_val) {
1373 do {
1374 val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE);
1375 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1376 (val == PHAN_INITIALIZE_ACK))
1377 return 0;
1378 set_current_state(TASK_UNINTERRUPTIBLE);
1379 schedule_timeout(500);
1380
1381 } while (--retries);
1382
1383 qla4_8xxx_check_for_bad_spd(ha);
1384
1385 if (!retries) {
1386 pegtune_val = qla4_8xxx_rd_32(ha,
1387 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1388 printk(KERN_WARNING "%s: init failed, "
1389 "pegtune_val = %x\n", __func__, pegtune_val);
1390 return -1;
1391 }
1392 }
1393 return 0;
1394}
1395
1396static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha)
1397{
1398 uint32_t state = 0;
1399 int loops = 0;
1400
1401 /* Window 1 call */
1402 read_lock(&ha->hw_lock);
1403 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1404 read_unlock(&ha->hw_lock);
1405
1406 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1407 udelay(100);
1408 /* Window 1 call */
1409 read_lock(&ha->hw_lock);
1410 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1411 read_unlock(&ha->hw_lock);
1412
1413 loops++;
1414 }
1415
1416 if (loops >= 30000) {
1417 DEBUG2(ql4_printk(KERN_INFO, ha,
1418 "Receive Peg initialization not complete: 0x%x.\n", state));
1419 return QLA_ERROR;
1420 }
1421
1422 return QLA_SUCCESS;
1423}
1424
Andrew Morton626115c2010-08-19 14:13:42 -0700[diff] [blame]1425void
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1426qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1427{
1428 uint32_t drv_active;
1429
1430 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1431 drv_active |= (1 << (ha->func_num * 4));
1432 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1433}
1434
1435void
1436qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1437{
1438 uint32_t drv_active;
1439
1440 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1441 drv_active &= ~(1 << (ha->func_num * 4));
1442 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1443}
1444
1445static inline int
1446qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1447{
Lalit Chandivade2232be02010-07-30 14:38:47 +0530[diff] [blame]1448 uint32_t drv_state, drv_active;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1449 int rval;
1450
Lalit Chandivade2232be02010-07-30 14:38:47 +0530[diff] [blame]1451 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1452 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1453 rval = drv_state & (1 << (ha->func_num * 4));
Lalit Chandivade2232be02010-07-30 14:38:47 +0530[diff] [blame]1454 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1455 rval = 1;
1456
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1457 return rval;
1458}
1459
1460static inline void
1461qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1462{
1463 uint32_t drv_state;
1464
1465 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1466 drv_state |= (1 << (ha->func_num * 4));
1467 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1468}
1469
1470static inline void
1471qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1472{
1473 uint32_t drv_state;
1474
1475 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1476 drv_state &= ~(1 << (ha->func_num * 4));
1477 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1478}
1479
1480static inline void
1481qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1482{
1483 uint32_t qsnt_state;
1484
1485 qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1486 qsnt_state |= (2 << (ha->func_num * 4));
1487 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1488}
1489
1490
1491static int
1492qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1493{
1494 int pcie_cap;
1495 uint16_t lnk;
1496
1497 /* scrub dma mask expansion register */
1498 qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1499
1500 /* Overwrite stale initialization register values */
1501 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1502 qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1503 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1504 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1505
1506 if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) {
1507 printk("%s: Error trying to start fw!\n", __func__);
1508 return QLA_ERROR;
1509 }
1510
1511 /* Handshake with the card before we register the devices. */
1512 if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1513 printk("%s: Error during card handshake!\n", __func__);
1514 return QLA_ERROR;
1515 }
1516
1517 /* Negotiated Link width */
1518 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
1519 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1520 ha->link_width = (lnk >> 4) & 0x3f;
1521
1522 /* Synchronize with Receive peg */
1523 return qla4_8xxx_rcvpeg_ready(ha);
1524}
1525
1526static int
1527qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1528{
1529 int rval = QLA_ERROR;
1530
1531 /*
1532 * FW Load priority:
1533 * 1) Operational firmware residing in flash.
1534 * 2) Fail
1535 */
1536
1537 ql4_printk(KERN_INFO, ha,
1538 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1539 rval = qla4_8xxx_get_flash_info(ha);
1540 if (rval != QLA_SUCCESS)
1541 return rval;
1542
1543 ql4_printk(KERN_INFO, ha,
1544 "FW: Attempting to load firmware from flash...\n");
1545 rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1546
Vikas Chaudharyf581a3f2010-10-06 22:47:48 -0700[diff] [blame]1547 if (rval != QLA_SUCCESS) {
1548 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1549 " FAILED...\n");
1550 return rval;
1551 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1552
1553 return rval;
1554}
1555
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]1556static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha)
1557{
1558 if (qla4_8xxx_rom_lock(ha)) {
1559 /* Someone else is holding the lock. */
1560 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1561 }
1562
1563 /*
1564 * Either we got the lock, or someone
1565 * else died while holding it.
1566 * In either case, unlock.
1567 */
1568 qla4_8xxx_rom_unlock(ha);
1569}
1570
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1571/**
1572 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
1573 * @ha: pointer to adapter structure
1574 *
1575 * Note: IDC lock must be held upon entry
1576 **/
1577static int
1578qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
1579{
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]1580 int rval = QLA_ERROR;
1581 int i, timeout;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1582 uint32_t old_count, count;
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]1583 int need_reset = 0, peg_stuck = 1;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1584
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]1585 need_reset = qla4_8xxx_need_reset(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1586
1587 old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1588
1589 for (i = 0; i < 10; i++) {
1590 timeout = msleep_interruptible(200);
1591 if (timeout) {
1592 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1593 QLA82XX_DEV_FAILED);
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]1594 return rval;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1595 }
1596
1597 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1598 if (count != old_count)
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]1599 peg_stuck = 0;
1600 }
1601
1602 if (need_reset) {
1603 /* We are trying to perform a recovery here. */
1604 if (peg_stuck)
1605 qla4_8xxx_rom_lock_recovery(ha);
1606 goto dev_initialize;
1607 } else {
1608 /* Start of day for this ha context. */
1609 if (peg_stuck) {
1610 /* Either we are the first or recovery in progress. */
1611 qla4_8xxx_rom_lock_recovery(ha);
1612 goto dev_initialize;
1613 } else {
1614 /* Firmware already running. */
1615 rval = QLA_SUCCESS;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1616 goto dev_ready;
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]1617 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1618 }
1619
1620dev_initialize:
1621 /* set to DEV_INITIALIZING */
1622 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
1623 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
1624
1625 /* Driver that sets device state to initializating sets IDC version */
1626 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
1627
1628 qla4_8xxx_idc_unlock(ha);
1629 rval = qla4_8xxx_try_start_fw(ha);
1630 qla4_8xxx_idc_lock(ha);
1631
1632 if (rval != QLA_SUCCESS) {
1633 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
1634 qla4_8xxx_clear_drv_active(ha);
1635 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
1636 return rval;
1637 }
1638
1639dev_ready:
1640 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
1641 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
1642
Shyam Sundarb25ee662010-10-06 22:50:51 -0700[diff] [blame^]1643 return rval;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1644}
1645
1646/**
1647 * qla4_8xxx_need_reset_handler - Code to start reset sequence
1648 * @ha: pointer to adapter structure
1649 *
1650 * Note: IDC lock must be held upon entry
1651 **/
1652static void
1653qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
1654{
1655 uint32_t dev_state, drv_state, drv_active;
1656 unsigned long reset_timeout;
1657
1658 ql4_printk(KERN_INFO, ha,
1659 "Performing ISP error recovery\n");
1660
1661 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
1662 qla4_8xxx_idc_unlock(ha);
1663 ha->isp_ops->disable_intrs(ha);
1664 qla4_8xxx_idc_lock(ha);
1665 }
1666
1667 qla4_8xxx_set_rst_ready(ha);
1668
1669 /* wait for 10 seconds for reset ack from all functions */
1670 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
1671
1672 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1673 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1674
1675 ql4_printk(KERN_INFO, ha,
1676 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1677 __func__, ha->host_no, drv_state, drv_active);
1678
1679 while (drv_state != drv_active) {
1680 if (time_after_eq(jiffies, reset_timeout)) {
1681 printk("%s: RESET TIMEOUT!\n", DRIVER_NAME);
1682 break;
1683 }
1684
1685 qla4_8xxx_idc_unlock(ha);
1686 msleep(1000);
1687 qla4_8xxx_idc_lock(ha);
1688
1689 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1690 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1691 }
1692
1693 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1694 ql4_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state,
1695 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1696
1697 /* Force to DEV_COLD unless someone else is starting a reset */
1698 if (dev_state != QLA82XX_DEV_INITIALIZING) {
1699 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
1700 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
1701 }
1702}
1703
1704/**
1705 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
1706 * @ha: pointer to adapter structure
1707 **/
1708void
1709qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
1710{
1711 qla4_8xxx_idc_lock(ha);
1712 qla4_8xxx_set_qsnt_ready(ha);
1713 qla4_8xxx_idc_unlock(ha);
1714}
1715
1716/**
1717 * qla4_8xxx_device_state_handler - Adapter state machine
1718 * @ha: pointer to host adapter structure.
1719 *
1720 * Note: IDC lock must be UNLOCKED upon entry
1721 **/
1722int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
1723{
1724 uint32_t dev_state;
1725 int rval = QLA_SUCCESS;
1726 unsigned long dev_init_timeout;
1727
1728 if (!test_bit(AF_INIT_DONE, &ha->flags))
1729 qla4_8xxx_set_drv_active(ha);
1730
1731 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1732 ql4_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state,
1733 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1734
1735 /* wait for 30 seconds for device to go ready */
1736 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
1737
1738 while (1) {
1739 qla4_8xxx_idc_lock(ha);
1740
1741 if (time_after_eq(jiffies, dev_init_timeout)) {
1742 ql4_printk(KERN_WARNING, ha, "Device init failed!\n");
1743 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1744 QLA82XX_DEV_FAILED);
1745 }
1746
1747 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1748 ql4_printk(KERN_INFO, ha,
1749 "2:Device state is 0x%x = %s\n", dev_state,
1750 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1751
1752 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1753 switch (dev_state) {
1754 case QLA82XX_DEV_READY:
1755 qla4_8xxx_idc_unlock(ha);
1756 goto exit;
1757 case QLA82XX_DEV_COLD:
1758 rval = qla4_8xxx_device_bootstrap(ha);
1759 qla4_8xxx_idc_unlock(ha);
1760 goto exit;
1761 case QLA82XX_DEV_INITIALIZING:
1762 qla4_8xxx_idc_unlock(ha);
1763 msleep(1000);
1764 break;
1765 case QLA82XX_DEV_NEED_RESET:
1766 if (!ql4xdontresethba) {
1767 qla4_8xxx_need_reset_handler(ha);
1768 /* Update timeout value after need
1769 * reset handler */
1770 dev_init_timeout = jiffies +
1771 (ha->nx_dev_init_timeout * HZ);
1772 }
1773 qla4_8xxx_idc_unlock(ha);
1774 break;
1775 case QLA82XX_DEV_NEED_QUIESCENT:
1776 qla4_8xxx_idc_unlock(ha);
1777 /* idc locked/unlocked in handler */
1778 qla4_8xxx_need_qsnt_handler(ha);
1779 qla4_8xxx_idc_lock(ha);
1780 /* fall thru needs idc_locked */
1781 case QLA82XX_DEV_QUIESCENT:
1782 qla4_8xxx_idc_unlock(ha);
1783 msleep(1000);
1784 break;
1785 case QLA82XX_DEV_FAILED:
1786 qla4_8xxx_idc_unlock(ha);
1787 qla4xxx_dead_adapter_cleanup(ha);
1788 rval = QLA_ERROR;
1789 goto exit;
1790 default:
1791 qla4_8xxx_idc_unlock(ha);
1792 qla4xxx_dead_adapter_cleanup(ha);
1793 rval = QLA_ERROR;
1794 goto exit;
1795 }
1796 }
1797exit:
1798 return rval;
1799}
1800
1801int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
1802{
1803 int retval;
1804 retval = qla4_8xxx_device_state_handler(ha);
1805
Vikas Chaudharyf581a3f2010-10-06 22:47:48 -0700[diff] [blame]1806 if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags))
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1807 retval = qla4xxx_request_irqs(ha);
Vikas Chaudharyf581a3f2010-10-06 22:47:48 -0700[diff] [blame]1808
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1809 return retval;
1810}
1811
1812/*****************************************************************************/
1813/* Flash Manipulation Routines */
1814/*****************************************************************************/
1815
1816#define OPTROM_BURST_SIZE 0x1000
1817#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
1818
1819#define FARX_DATA_FLAG BIT_31
1820#define FARX_ACCESS_FLASH_CONF 0x7FFD0000
1821#define FARX_ACCESS_FLASH_DATA 0x7FF00000
1822
1823static inline uint32_t
1824flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1825{
1826 return hw->flash_conf_off | faddr;
1827}
1828
1829static inline uint32_t
1830flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1831{
1832 return hw->flash_data_off | faddr;
1833}
1834
1835static uint32_t *
1836qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
1837 uint32_t faddr, uint32_t length)
1838{
1839 uint32_t i;
1840 uint32_t val;
1841 int loops = 0;
1842 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
1843 udelay(100);
1844 cond_resched();
1845 loops++;
1846 }
1847 if (loops >= 50000) {
1848 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
1849 return dwptr;
1850 }
1851
1852 /* Dword reads to flash. */
1853 for (i = 0; i < length/4; i++, faddr += 4) {
1854 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) {
1855 ql4_printk(KERN_WARNING, ha,
1856 "Do ROM fast read failed\n");
1857 goto done_read;
1858 }
1859 dwptr[i] = __constant_cpu_to_le32(val);
1860 }
1861
1862done_read:
1863 qla4_8xxx_rom_unlock(ha);
1864 return dwptr;
1865}
1866
1867/**
1868 * Address and length are byte address
1869 **/
1870static uint8_t *
1871qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1872 uint32_t offset, uint32_t length)
1873{
1874 qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length);
1875 return buf;
1876}
1877
1878static int
1879qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
1880{
1881 const char *loc, *locations[] = { "DEF", "PCI" };
1882
1883 /*
1884 * FLT-location structure resides after the last PCI region.
1885 */
1886
1887 /* Begin with sane defaults. */
1888 loc = locations[0];
1889 *start = FA_FLASH_LAYOUT_ADDR_82;
1890
1891 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
1892 return QLA_SUCCESS;
1893}
1894
1895static void
1896qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
1897{
1898 const char *loc, *locations[] = { "DEF", "FLT" };
1899 uint16_t *wptr;
1900 uint16_t cnt, chksum;
1901 uint32_t start;
1902 struct qla_flt_header *flt;
1903 struct qla_flt_region *region;
1904 struct ql82xx_hw_data *hw = &ha->hw;
1905
1906 hw->flt_region_flt = flt_addr;
1907 wptr = (uint16_t *)ha->request_ring;
1908 flt = (struct qla_flt_header *)ha->request_ring;
1909 region = (struct qla_flt_region *)&flt[1];
1910 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
1911 flt_addr << 2, OPTROM_BURST_SIZE);
1912 if (*wptr == __constant_cpu_to_le16(0xffff))
1913 goto no_flash_data;
1914 if (flt->version != __constant_cpu_to_le16(1)) {
1915 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
1916 "version=0x%x length=0x%x checksum=0x%x.\n",
1917 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1918 le16_to_cpu(flt->checksum)));
1919 goto no_flash_data;
1920 }
1921
1922 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
1923 for (chksum = 0; cnt; cnt--)
1924 chksum += le16_to_cpu(*wptr++);
1925 if (chksum) {
1926 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
1927 "version=0x%x length=0x%x checksum=0x%x.\n",
1928 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1929 chksum));
1930 goto no_flash_data;
1931 }
1932
1933 loc = locations[1];
1934 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
1935 for ( ; cnt; cnt--, region++) {
1936 /* Store addresses as DWORD offsets. */
1937 start = le32_to_cpu(region->start) >> 2;
1938
1939 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
1940 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
1941 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
1942
1943 switch (le32_to_cpu(region->code) & 0xff) {
1944 case FLT_REG_FDT:
1945 hw->flt_region_fdt = start;
1946 break;
1947 case FLT_REG_BOOT_CODE_82:
1948 hw->flt_region_boot = start;
1949 break;
1950 case FLT_REG_FW_82:
1951 hw->flt_region_fw = start;
1952 break;
1953 case FLT_REG_BOOTLOAD_82:
1954 hw->flt_region_bootload = start;
1955 break;
1956 }
1957 }
1958 goto done;
1959
1960no_flash_data:
1961 /* Use hardcoded defaults. */
1962 loc = locations[0];
1963
1964 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
1965 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
1966 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
1967 hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
1968done:
1969 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
1970 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
1971 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
1972 hw->flt_region_fw));
1973}
1974
1975static void
1976qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha)
1977{
1978#define FLASH_BLK_SIZE_4K 0x1000
1979#define FLASH_BLK_SIZE_32K 0x8000
1980#define FLASH_BLK_SIZE_64K 0x10000
1981 const char *loc, *locations[] = { "MID", "FDT" };
1982 uint16_t cnt, chksum;
1983 uint16_t *wptr;
1984 struct qla_fdt_layout *fdt;
Vikas Chaudhary3c3e2102010-08-09 05:14:07 -0700[diff] [blame]1985 uint16_t mid = 0;
1986 uint16_t fid = 0;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]1987 struct ql82xx_hw_data *hw = &ha->hw;
1988
1989 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
1990 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
1991
1992 wptr = (uint16_t *)ha->request_ring;
1993 fdt = (struct qla_fdt_layout *)ha->request_ring;
1994 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
1995 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
1996
1997 if (*wptr == __constant_cpu_to_le16(0xffff))
1998 goto no_flash_data;
1999
2000 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2001 fdt->sig[3] != 'D')
2002 goto no_flash_data;
2003
2004 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
2005 cnt++)
2006 chksum += le16_to_cpu(*wptr++);
2007
2008 if (chksum) {
2009 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
2010 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
2011 le16_to_cpu(fdt->version)));
2012 goto no_flash_data;
2013 }
2014
2015 loc = locations[1];
2016 mid = le16_to_cpu(fdt->man_id);
2017 fid = le16_to_cpu(fdt->id);
2018 hw->fdt_wrt_disable = fdt->wrt_disable_bits;
2019 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
2020 hw->fdt_block_size = le32_to_cpu(fdt->block_size);
2021
2022 if (fdt->unprotect_sec_cmd) {
2023 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
2024 fdt->unprotect_sec_cmd);
2025 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
2026 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
2027 flash_conf_addr(hw, 0x0336);
2028 }
2029 goto done;
2030
2031no_flash_data:
2032 loc = locations[0];
2033 hw->fdt_block_size = FLASH_BLK_SIZE_64K;
2034done:
2035 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2036 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2037 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2038 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2039 hw->fdt_block_size));
2040}
2041
2042static void
2043qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2044{
2045#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
2046 uint32_t *wptr;
2047
2048 if (!is_qla8022(ha))
2049 return;
2050 wptr = (uint32_t *)ha->request_ring;
2051 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2052 QLA82XX_IDC_PARAM_ADDR , 8);
2053
2054 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2055 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2056 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2057 } else {
2058 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2059 ha->nx_reset_timeout = le32_to_cpu(*wptr);
2060 }
2061
2062 DEBUG2(ql4_printk(KERN_DEBUG, ha,
2063 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
2064 DEBUG2(ql4_printk(KERN_DEBUG, ha,
2065 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
2066 return;
2067}
2068
2069int
2070qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2071{
2072 int ret;
2073 uint32_t flt_addr;
2074
2075 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2076 if (ret != QLA_SUCCESS)
2077 return ret;
2078
2079 qla4_8xxx_get_flt_info(ha, flt_addr);
2080 qla4_8xxx_get_fdt_info(ha);
2081 qla4_8xxx_get_idc_param(ha);
2082
2083 return QLA_SUCCESS;
2084}
2085
2086/**
2087 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2088 * @ha: pointer to host adapter structure.
2089 *
2090 * Remarks:
2091 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2092 * not be available after successful return. Driver must cleanup potential
2093 * outstanding I/O's after calling this funcion.
2094 **/
2095int
2096qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2097{
2098 int status;
2099 uint32_t mbox_cmd[MBOX_REG_COUNT];
2100 uint32_t mbox_sts[MBOX_REG_COUNT];
2101
2102 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2103 memset(&mbox_sts, 0, sizeof(mbox_sts));
2104
2105 mbox_cmd[0] = MBOX_CMD_STOP_FW;
2106 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
2107 &mbox_cmd[0], &mbox_sts[0]);
2108
2109 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2110 __func__, status));
2111 return status;
2112}
2113
2114/**
2115 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands.
2116 * @ha: pointer to host adapter structure.
2117 **/
2118int
2119qla4_8xxx_isp_reset(struct scsi_qla_host *ha)
2120{
2121 int rval;
2122 uint32_t dev_state;
2123
2124 qla4_8xxx_idc_lock(ha);
2125 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2126
2127 if (dev_state == QLA82XX_DEV_READY) {
2128 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2129 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2130 QLA82XX_DEV_NEED_RESET);
2131 } else
2132 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2133
2134 qla4_8xxx_idc_unlock(ha);
2135
2136 rval = qla4_8xxx_device_state_handler(ha);
2137
2138 qla4_8xxx_idc_lock(ha);
2139 qla4_8xxx_clear_rst_ready(ha);
2140 qla4_8xxx_idc_unlock(ha);
2141
Nilesh Javali21033632010-07-30 14:28:07 +0530[diff] [blame]2142 if (rval == QLA_SUCCESS)
2143 clear_bit(AF_FW_RECOVERY, &ha->flags);
2144
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]2145 return rval;
2146}
2147
2148/**
2149 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2150 * @ha: pointer to host adapter structure.
2151 *
2152 **/
2153int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
2154{
2155 uint32_t mbox_cmd[MBOX_REG_COUNT];
2156 uint32_t mbox_sts[MBOX_REG_COUNT];
2157 struct mbx_sys_info *sys_info;
2158 dma_addr_t sys_info_dma;
2159 int status = QLA_ERROR;
2160
2161 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
2162 &sys_info_dma, GFP_KERNEL);
2163 if (sys_info == NULL) {
2164 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
2165 ha->host_no, __func__));
2166 return status;
2167 }
2168
2169 memset(sys_info, 0, sizeof(*sys_info));
2170 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2171 memset(&mbox_sts, 0, sizeof(mbox_sts));
2172
2173 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
2174 mbox_cmd[1] = LSDW(sys_info_dma);
2175 mbox_cmd[2] = MSDW(sys_info_dma);
2176 mbox_cmd[4] = sizeof(*sys_info);
2177
2178 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
2179 &mbox_sts[0]) != QLA_SUCCESS) {
2180 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
2181 ha->host_no, __func__));
2182 goto exit_validate_mac82;
2183 }
2184
Vikas Chaudhary2ccdf0d2010-07-30 14:27:45 +0530[diff] [blame]2185 /* Make sure we receive the minimum required data to cache internally */
2186 if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530[diff] [blame]2187 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
2188 " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
2189 goto exit_validate_mac82;
2190
2191 }
2192
2193 /* Save M.A.C. address & serial_number */
2194 memcpy(ha->my_mac, &sys_info->mac_addr[0],
2195 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
2196 memcpy(ha->serial_number, &sys_info->serial_number,
2197 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
2198
2199 DEBUG2(printk("scsi%ld: %s: "
2200 "mac %02x:%02x:%02x:%02x:%02x:%02x "
2201 "serial %s\n", ha->host_no, __func__,
2202 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
2203 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
2204 ha->serial_number));
2205
2206 status = QLA_SUCCESS;
2207
2208exit_validate_mac82:
2209 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
2210 sys_info_dma);
2211 return status;
2212}
2213
2214/* Interrupt handling helpers. */
2215
2216static int
2217qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2218{
2219 uint32_t mbox_cmd[MBOX_REG_COUNT];
2220 uint32_t mbox_sts[MBOX_REG_COUNT];
2221
2222 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2223
2224 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2225 memset(&mbox_sts, 0, sizeof(mbox_sts));
2226 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2227 mbox_cmd[1] = INTR_ENABLE;
2228 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2229 &mbox_sts[0]) != QLA_SUCCESS) {
2230 DEBUG2(ql4_printk(KERN_INFO, ha,
2231 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2232 __func__, mbox_sts[0]));
2233 return QLA_ERROR;
2234 }
2235 return QLA_SUCCESS;
2236}
2237
2238static int
2239qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
2240{
2241 uint32_t mbox_cmd[MBOX_REG_COUNT];
2242 uint32_t mbox_sts[MBOX_REG_COUNT];
2243
2244 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2245
2246 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2247 memset(&mbox_sts, 0, sizeof(mbox_sts));
2248 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2249 mbox_cmd[1] = INTR_DISABLE;
2250 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2251 &mbox_sts[0]) != QLA_SUCCESS) {
2252 DEBUG2(ql4_printk(KERN_INFO, ha,
2253 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2254 __func__, mbox_sts[0]));
2255 return QLA_ERROR;
2256 }
2257
2258 return QLA_SUCCESS;
2259}
2260
2261void
2262qla4_8xxx_enable_intrs(struct scsi_qla_host *ha)
2263{
2264 qla4_8xxx_mbx_intr_enable(ha);
2265
2266 spin_lock_irq(&ha->hardware_lock);
2267 /* BIT 10 - reset */
2268 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2269 spin_unlock_irq(&ha->hardware_lock);
2270 set_bit(AF_INTERRUPTS_ON, &ha->flags);
2271}
2272
2273void
2274qla4_8xxx_disable_intrs(struct scsi_qla_host *ha)
2275{
2276 if (test_bit(AF_INTERRUPTS_ON, &ha->flags))
2277 qla4_8xxx_mbx_intr_disable(ha);
2278
2279 spin_lock_irq(&ha->hardware_lock);
2280 /* BIT 10 - set */
2281 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2282 spin_unlock_irq(&ha->hardware_lock);
2283 clear_bit(AF_INTERRUPTS_ON, &ha->flags);
2284}
2285
2286struct ql4_init_msix_entry {
2287 uint16_t entry;
2288 uint16_t index;
2289 const char *name;
2290 irq_handler_t handler;
2291};
2292
2293static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
2294 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
2295 "qla4xxx (default)",
2296 (irq_handler_t)qla4_8xxx_default_intr_handler },
2297 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
2298 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
2299};
2300
2301void
2302qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
2303{
2304 int i;
2305 struct ql4_msix_entry *qentry;
2306
2307 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2308 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2309 if (qentry->have_irq) {
2310 free_irq(qentry->msix_vector, ha);
2311 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2312 __func__, qla4_8xxx_msix_entries[i].name));
2313 }
2314 }
2315 pci_disable_msix(ha->pdev);
2316 clear_bit(AF_MSIX_ENABLED, &ha->flags);
2317}
2318
2319int
2320qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
2321{
2322 int i, ret;
2323 struct msix_entry entries[QLA_MSIX_ENTRIES];
2324 struct ql4_msix_entry *qentry;
2325
2326 for (i = 0; i < QLA_MSIX_ENTRIES; i++)
2327 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
2328
2329 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
2330 if (ret) {
2331 ql4_printk(KERN_WARNING, ha,
2332 "MSI-X: Failed to enable support -- %d/%d\n",
2333 QLA_MSIX_ENTRIES, ret);
2334 goto msix_out;
2335 }
2336 set_bit(AF_MSIX_ENABLED, &ha->flags);
2337
2338 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2339 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2340 qentry->msix_vector = entries[i].vector;
2341 qentry->msix_entry = entries[i].entry;
2342 qentry->have_irq = 0;
2343 ret = request_irq(qentry->msix_vector,
2344 qla4_8xxx_msix_entries[i].handler, 0,
2345 qla4_8xxx_msix_entries[i].name, ha);
2346 if (ret) {
2347 ql4_printk(KERN_WARNING, ha,
2348 "MSI-X: Unable to register handler -- %x/%d.\n",
2349 qla4_8xxx_msix_entries[i].index, ret);
2350 qla4_8xxx_disable_msix(ha);
2351 goto msix_out;
2352 }
2353 qentry->have_irq = 1;
2354 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2355 __func__, qla4_8xxx_msix_entries[i].name));
2356 }
2357msix_out:
2358 return ret;
2359}