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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02005 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Sergei Shtylyov59c8d042009-04-18 17:42:19 +02006 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
Alan Coxb39b01f2005-06-27 15:24:27 -070013 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080014 * HighPoint has its own drivers (open source except for the RAID part)
Justin P. Mattock631dd1a2010-10-18 11:03:14 +020015 * available from http://www.highpoint-tech.com/USA_new/service_support.htm
Sergei Shtylyov836c0062006-12-13 00:35:47 -080016 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
Alan Coxb39b01f2005-06-27 15:24:27 -070019 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
Alan Coxccd32e22008-11-02 21:40:08 +010055 * Alan Cox <alan@lxorguk.ukuu.org.uk>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080057 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010062 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -080066 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
Sergei Shtylyov26c068d2006-12-13 00:35:52 -080069 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
Sergei Shtylyov72931362007-09-11 22:28:35 +020070 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
Sergei Shtylyov33b18a62006-12-13 00:35:50 -080072 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -080074 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010076 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
Sergei Shtylyov90778572007-02-07 18:17:51 +010078 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +020080 * - optimize the UltraDMA filtering and the drive list lookup code
Sergei Shtylyovb4586712007-02-07 18:17:54 +010081 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010082 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +010086 * - rename all the register related variables consistently
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010087 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
Sergei Shtylyov866664d2008-01-25 22:17:05 +010089 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010090 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +010094 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010095 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
Sergei Shtylyov278978e2007-06-08 15:14:32 +0200109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
Sergei Shtylyov6273d262007-02-07 18:18:20 +0100111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200115 * - set the correct hwif->ultra_mask for each individual chip
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyovc018f1e2009-04-18 17:42:19 +0200117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 */
121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122#include <linux/types.h>
123#include <linux/module.h>
124#include <linux/kernel.h>
125#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126#include <linux/blkdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127#include <linux/interrupt.h>
128#include <linux/pci.h>
129#include <linux/init.h>
130#include <linux/ide.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +0900131#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
133#include <asm/uaccess.h>
134#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200136#define DRV_NAME "hpt366"
137
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138/* various tuning parameters */
Sergei Shtylyovc018f1e2009-04-18 17:42:19 +0200139#undef HPT_RESET_STATE_ENGINE
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800140#undef HPT_DELAY_INTERRUPT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142static const char *bad_ata100_5[] = {
143 "IBM-DTLA-307075",
144 "IBM-DTLA-307060",
145 "IBM-DTLA-307045",
146 "IBM-DTLA-307030",
147 "IBM-DTLA-307020",
148 "IBM-DTLA-307015",
149 "IBM-DTLA-305040",
150 "IBM-DTLA-305030",
151 "IBM-DTLA-305020",
152 "IC35L010AVER07-0",
153 "IC35L020AVER07-0",
154 "IC35L030AVER07-0",
155 "IC35L040AVER07-0",
156 "IC35L060AVER07-0",
157 "WDC AC310200R",
158 NULL
159};
160
161static const char *bad_ata66_4[] = {
162 "IBM-DTLA-307075",
163 "IBM-DTLA-307060",
164 "IBM-DTLA-307045",
165 "IBM-DTLA-307030",
166 "IBM-DTLA-307020",
167 "IBM-DTLA-307015",
168 "IBM-DTLA-305040",
169 "IBM-DTLA-305030",
170 "IBM-DTLA-305020",
171 "IC35L010AVER07-0",
172 "IC35L020AVER07-0",
173 "IC35L030AVER07-0",
174 "IC35L040AVER07-0",
175 "IC35L060AVER07-0",
176 "WDC AC310200R",
Sergei Shtylyov783353b2007-07-03 22:28:35 +0200177 "MAXTOR STM3320620A",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 NULL
179};
180
181static const char *bad_ata66_3[] = {
182 "WDC AC310200R",
183 NULL
184};
185
186static const char *bad_ata33[] = {
187 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
188 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
189 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
190 "Maxtor 90510D4",
191 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
192 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
193 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
194 NULL
195};
196
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800197static u8 xfer_speeds[] = {
198 XFER_UDMA_6,
199 XFER_UDMA_5,
200 XFER_UDMA_4,
201 XFER_UDMA_3,
202 XFER_UDMA_2,
203 XFER_UDMA_1,
204 XFER_UDMA_0,
205
206 XFER_MW_DMA_2,
207 XFER_MW_DMA_1,
208 XFER_MW_DMA_0,
209
210 XFER_PIO_4,
211 XFER_PIO_3,
212 XFER_PIO_2,
213 XFER_PIO_1,
214 XFER_PIO_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215};
216
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800217/* Key for bus clock timings
218 * 36x 37x
219 * bits bits
220 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
221 * cycles = value + 1
222 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
223 * cycles = value + 1
224 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
225 * register access.
226 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
227 * register access.
228 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
229 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
230 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
231 * MW DMA xfer.
232 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
233 * task file register access.
234 * 28 28 UDMA enable.
235 * 29 29 DMA enable.
236 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
237 * PIO xfer.
238 * 31 31 FIFO enable.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800241static u32 forty_base_hpt36x[] = {
242 /* XFER_UDMA_6 */ 0x900fd943,
243 /* XFER_UDMA_5 */ 0x900fd943,
244 /* XFER_UDMA_4 */ 0x900fd943,
245 /* XFER_UDMA_3 */ 0x900ad943,
246 /* XFER_UDMA_2 */ 0x900bd943,
247 /* XFER_UDMA_1 */ 0x9008d943,
248 /* XFER_UDMA_0 */ 0x9008d943,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800250 /* XFER_MW_DMA_2 */ 0xa008d943,
251 /* XFER_MW_DMA_1 */ 0xa010d955,
252 /* XFER_MW_DMA_0 */ 0xa010d9fc,
253
254 /* XFER_PIO_4 */ 0xc008d963,
255 /* XFER_PIO_3 */ 0xc010d974,
256 /* XFER_PIO_2 */ 0xc010d997,
257 /* XFER_PIO_1 */ 0xc010d9c7,
258 /* XFER_PIO_0 */ 0xc018d9d9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259};
260
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800261static u32 thirty_three_base_hpt36x[] = {
262 /* XFER_UDMA_6 */ 0x90c9a731,
263 /* XFER_UDMA_5 */ 0x90c9a731,
264 /* XFER_UDMA_4 */ 0x90c9a731,
265 /* XFER_UDMA_3 */ 0x90cfa731,
266 /* XFER_UDMA_2 */ 0x90caa731,
267 /* XFER_UDMA_1 */ 0x90cba731,
268 /* XFER_UDMA_0 */ 0x90c8a731,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800270 /* XFER_MW_DMA_2 */ 0xa0c8a731,
271 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
272 /* XFER_MW_DMA_0 */ 0xa0c8a797,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800274 /* XFER_PIO_4 */ 0xc0c8a731,
275 /* XFER_PIO_3 */ 0xc0c8a742,
276 /* XFER_PIO_2 */ 0xc0d0a753,
277 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
278 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279};
280
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800281static u32 twenty_five_base_hpt36x[] = {
282 /* XFER_UDMA_6 */ 0x90c98521,
283 /* XFER_UDMA_5 */ 0x90c98521,
284 /* XFER_UDMA_4 */ 0x90c98521,
285 /* XFER_UDMA_3 */ 0x90cf8521,
286 /* XFER_UDMA_2 */ 0x90cf8521,
287 /* XFER_UDMA_1 */ 0x90cb8521,
288 /* XFER_UDMA_0 */ 0x90cb8521,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800290 /* XFER_MW_DMA_2 */ 0xa0ca8521,
291 /* XFER_MW_DMA_1 */ 0xa0ca8532,
292 /* XFER_MW_DMA_0 */ 0xa0ca8575,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800294 /* XFER_PIO_4 */ 0xc0ca8521,
295 /* XFER_PIO_3 */ 0xc0ca8532,
296 /* XFER_PIO_2 */ 0xc0ca8542,
297 /* XFER_PIO_1 */ 0xc0d08572,
298 /* XFER_PIO_0 */ 0xc0d08585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299};
300
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100301/*
302 * The following are the new timing tables with PIO mode data/taskfile transfer
303 * overclocking fixed...
304 */
305
306/* This table is taken from the HPT370 data manual rev. 1.02 */
307static u32 thirty_three_base_hpt37x[] = {
308 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
309 /* XFER_UDMA_5 */ 0x16455031,
310 /* XFER_UDMA_4 */ 0x16455031,
311 /* XFER_UDMA_3 */ 0x166d5031,
312 /* XFER_UDMA_2 */ 0x16495031,
313 /* XFER_UDMA_1 */ 0x164d5033,
314 /* XFER_UDMA_0 */ 0x16515097,
315
316 /* XFER_MW_DMA_2 */ 0x26515031,
317 /* XFER_MW_DMA_1 */ 0x26515033,
318 /* XFER_MW_DMA_0 */ 0x26515097,
319
320 /* XFER_PIO_4 */ 0x06515021,
321 /* XFER_PIO_3 */ 0x06515022,
322 /* XFER_PIO_2 */ 0x06515033,
323 /* XFER_PIO_1 */ 0x06915065,
324 /* XFER_PIO_0 */ 0x06d1508a
325};
326
327static u32 fifty_base_hpt37x[] = {
328 /* XFER_UDMA_6 */ 0x1a861842,
329 /* XFER_UDMA_5 */ 0x1a861842,
330 /* XFER_UDMA_4 */ 0x1aae1842,
331 /* XFER_UDMA_3 */ 0x1a8e1842,
332 /* XFER_UDMA_2 */ 0x1a0e1842,
333 /* XFER_UDMA_1 */ 0x1a161854,
334 /* XFER_UDMA_0 */ 0x1a1a18ea,
335
336 /* XFER_MW_DMA_2 */ 0x2a821842,
337 /* XFER_MW_DMA_1 */ 0x2a821854,
338 /* XFER_MW_DMA_0 */ 0x2a8218ea,
339
340 /* XFER_PIO_4 */ 0x0a821842,
341 /* XFER_PIO_3 */ 0x0a821843,
342 /* XFER_PIO_2 */ 0x0a821855,
343 /* XFER_PIO_1 */ 0x0ac218a8,
344 /* XFER_PIO_0 */ 0x0b02190c
345};
346
347static u32 sixty_six_base_hpt37x[] = {
348 /* XFER_UDMA_6 */ 0x1c86fe62,
349 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
350 /* XFER_UDMA_4 */ 0x1c8afe62,
351 /* XFER_UDMA_3 */ 0x1c8efe62,
352 /* XFER_UDMA_2 */ 0x1c92fe62,
353 /* XFER_UDMA_1 */ 0x1c9afe62,
354 /* XFER_UDMA_0 */ 0x1c82fe62,
355
356 /* XFER_MW_DMA_2 */ 0x2c82fe62,
357 /* XFER_MW_DMA_1 */ 0x2c82fe66,
358 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
359
360 /* XFER_PIO_4 */ 0x0c82fe62,
361 /* XFER_PIO_3 */ 0x0c82fe84,
362 /* XFER_PIO_2 */ 0x0c82fea6,
363 /* XFER_PIO_1 */ 0x0d02ff26,
364 /* XFER_PIO_0 */ 0x0d42ff7f
365};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100367#define HPT371_ALLOW_ATA133_6 1
368#define HPT302_ALLOW_ATA133_6 1
369#define HPT372_ALLOW_ATA133_6 1
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100370#define HPT370_ALLOW_ATA100_5 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371#define HPT366_ALLOW_ATA66_4 1
372#define HPT366_ALLOW_ATA66_3 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100374/* Supported ATA clock frequencies */
375enum ata_clock {
376 ATA_CLOCK_25MHZ,
377 ATA_CLOCK_33MHZ,
378 ATA_CLOCK_40MHZ,
379 ATA_CLOCK_50MHZ,
380 ATA_CLOCK_66MHZ,
381 NUM_ATA_CLOCKS
Alan Coxb39b01f2005-06-27 15:24:27 -0700382};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100384struct hpt_timings {
385 u32 pio_mask;
386 u32 dma_mask;
387 u32 ultra_mask;
388 u32 *clock_table[NUM_ATA_CLOCKS];
389};
390
Alan Coxb39b01f2005-06-27 15:24:27 -0700391/*
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100392 * Hold all the HighPoint chip information in one place.
Alan Coxb39b01f2005-06-27 15:24:27 -0700393 */
394
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100395struct hpt_info {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200396 char *chip_name; /* Chip name */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100397 u8 chip_type; /* Chip type */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200398 u8 udma_mask; /* Allowed UltraDMA modes mask. */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100399 u8 dpll_clk; /* DPLL clock in MHz */
400 u8 pci_clk; /* PCI clock in MHz */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100401 struct hpt_timings *timings; /* Chipset timing data */
402 u8 clock; /* ATA clock selected */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100403};
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100404
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100405/* Supported HighPoint chips */
406enum {
407 HPT36x,
408 HPT370,
409 HPT370A,
410 HPT374,
411 HPT372,
412 HPT372A,
413 HPT302,
414 HPT371,
415 HPT372N,
416 HPT302N,
417 HPT371N
418};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100420static struct hpt_timings hpt36x_timings = {
421 .pio_mask = 0xc1f8ffff,
422 .dma_mask = 0x303800ff,
423 .ultra_mask = 0x30070000,
424 .clock_table = {
425 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
426 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
427 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
428 [ATA_CLOCK_50MHZ] = NULL,
429 [ATA_CLOCK_66MHZ] = NULL
430 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100431};
432
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100433static struct hpt_timings hpt37x_timings = {
434 .pio_mask = 0xcfc3ffff,
435 .dma_mask = 0x31c001ff,
436 .ultra_mask = 0x303c0000,
437 .clock_table = {
438 [ATA_CLOCK_25MHZ] = NULL,
439 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
440 [ATA_CLOCK_40MHZ] = NULL,
441 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
442 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
443 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100444};
445
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800446static const struct hpt_info hpt36x = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200447 .chip_name = "HPT36x",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100448 .chip_type = HPT36x,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200449 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100450 .dpll_clk = 0, /* no DPLL */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100451 .timings = &hpt36x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100452};
453
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800454static const struct hpt_info hpt370 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200455 .chip_name = "HPT370",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100456 .chip_type = HPT370,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200457 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100458 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100459 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100460};
461
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800462static const struct hpt_info hpt370a = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200463 .chip_name = "HPT370A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100464 .chip_type = HPT370A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200465 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100466 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100467 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100468};
469
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800470static const struct hpt_info hpt374 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200471 .chip_name = "HPT374",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100472 .chip_type = HPT374,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200473 .udma_mask = ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100474 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100475 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100476};
477
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800478static const struct hpt_info hpt372 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200479 .chip_name = "HPT372",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100480 .chip_type = HPT372,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200481 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100482 .dpll_clk = 55,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100483 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100484};
485
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800486static const struct hpt_info hpt372a = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200487 .chip_name = "HPT372A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100488 .chip_type = HPT372A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200489 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100490 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100491 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100492};
493
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800494static const struct hpt_info hpt302 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200495 .chip_name = "HPT302",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100496 .chip_type = HPT302,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200497 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100498 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100499 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100500};
501
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800502static const struct hpt_info hpt371 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200503 .chip_name = "HPT371",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100504 .chip_type = HPT371,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200505 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100506 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100507 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100508};
509
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800510static const struct hpt_info hpt372n = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200511 .chip_name = "HPT372N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100512 .chip_type = HPT372N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200513 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100514 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100515 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100516};
517
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800518static const struct hpt_info hpt302n = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200519 .chip_name = "HPT302N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100520 .chip_type = HPT302N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200521 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100522 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100523 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100524};
525
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800526static const struct hpt_info hpt371n = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200527 .chip_name = "HPT371N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100528 .chip_type = HPT371N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200529 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100530 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100531 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100532};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533
Andy Shevchenko9adb92542016-03-17 14:22:35 -0700534static bool check_in_drive_list(ide_drive_t *drive, const char **list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535{
Andy Shevchenko9adb92542016-03-17 14:22:35 -0700536 return match_string(list, -1, (char *)&drive->id[ATA_ID_PROD]) >= 0;
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100537}
Alan Coxb39b01f2005-06-27 15:24:27 -0700538
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200539static struct hpt_info *hpt3xx_get_info(struct device *dev)
540{
541 struct ide_host *host = dev_get_drvdata(dev);
542 struct hpt_info *info = (struct hpt_info *)host->host_priv;
543
544 return dev == host->dev[1] ? info + 1 : info;
545}
546
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547/*
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200548 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
549 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550 */
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200551
552static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100554 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200555 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200556 u8 mask = hwif->ultra_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200558 switch (info->chip_type) {
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200559 case HPT36x:
560 if (!HPT366_ALLOW_ATA66_4 ||
561 check_in_drive_list(drive, bad_ata66_4))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200562 mask = ATA_UDMA3;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100563
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200564 if (!HPT366_ALLOW_ATA66_3 ||
565 check_in_drive_list(drive, bad_ata66_3))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200566 mask = ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200567 break;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200568 case HPT370:
569 if (!HPT370_ALLOW_ATA100_5 ||
570 check_in_drive_list(drive, bad_ata100_5))
571 mask = ATA_UDMA4;
572 break;
573 case HPT370A:
574 if (!HPT370_ALLOW_ATA100_5 ||
575 check_in_drive_list(drive, bad_ata100_5))
576 return ATA_UDMA4;
577 case HPT372 :
578 case HPT372A:
579 case HPT372N:
580 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200581 if (ata_id_is_sata(drive->id))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200582 mask &= ~0x0e;
583 /* Fall thru */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200584 default:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200585 return mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 }
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200587
588 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589}
590
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200591static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
592{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100593 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200594 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200595
596 switch (info->chip_type) {
597 case HPT372 :
598 case HPT372A:
599 case HPT372N:
600 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200601 if (ata_id_is_sata(drive->id))
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200602 return 0x00;
603 /* Fall thru */
604 default:
605 return 0x07;
606 }
607}
608
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100609static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610{
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800611 int i;
612
613 /*
614 * Lookup the transfer mode table to get the index into
615 * the timing table.
616 *
617 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
618 */
619 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
620 if (xfer_speeds[i] == speed)
621 break;
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100622
623 return info->timings->clock_table[info->clock][i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624}
625
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800626static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627{
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +0200628 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200629 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100630 struct hpt_timings *t = info->timings;
631 u8 itr_addr = 0x40 + (drive->dn * 4);
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100632 u32 old_itr = 0;
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800633 const u8 speed = drive->dma_mode;
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100634 u32 new_itr = get_speed_setting(speed, info);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100635 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
636 (speed < XFER_UDMA_0 ? t->dma_mask :
637 t->ultra_mask);
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200638
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100639 pci_read_config_dword(dev, itr_addr, &old_itr);
640 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 /*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100642 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
643 * to avoid problems handling I/O errors later
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100645 new_itr &= ~0xc0000000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100647 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648}
649
Bartlomiej Zolnierkiewicze085b3c2010-01-19 01:44:41 -0800650static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651{
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800652 drive->dma_mode = drive->pio_mode;
653 hpt3xx_set_mode(hwif, drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654}
655
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100656static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100658 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100659 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200660 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661
Bartlomiej Zolnierkiewicz734affd2009-06-07 15:37:10 +0200662 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200663 return;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100664
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200665 if (info->chip_type >= HPT370) {
666 u8 scr1 = 0;
667
668 pci_read_config_byte(dev, 0x5a, &scr1);
669 if (((scr1 & 0x10) >> 4) != mask) {
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100670 if (mask)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200671 scr1 |= 0x10;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100672 else
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200673 scr1 &= ~0x10;
674 pci_write_config_byte(dev, 0x5a, scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 }
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200676 } else if (mask)
677 disable_irq(hwif->irq);
678 else
679 enable_irq(hwif->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680}
681
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682/*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100683 * This is specific to the HPT366 UDMA chipset
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684 * by HighPoint|Triones Technologies, Inc.
685 */
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200686static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100688 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100689 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100691 pci_read_config_byte(dev, 0x50, &mcr1);
692 pci_read_config_byte(dev, 0x52, &mcr3);
693 pci_read_config_byte(dev, 0x5a, &scr1);
694 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
Harvey Harrisoneb639632008-04-26 22:25:20 +0200695 drive->name, __func__, mcr1, mcr3, scr1);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100696 if (scr1 & 0x10)
697 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200698 ide_dma_lost_irq(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699}
700
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100701static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100703 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100704 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100705
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100706 pci_write_config_byte(dev, hwif->select_data, 0x37);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 udelay(10);
708}
709
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100710static void hpt370_irq_timeout(ide_drive_t *drive)
711{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100712 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100713 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100714 u16 bfifo = 0;
715 u8 dma_cmd;
716
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100717 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100718 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
719
720 /* get DMA command mode */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200721 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100722 /* stop DMA */
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200723 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100724 hpt370_clear_engine(drive);
725}
726
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200727static void hpt370_dma_start(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728{
729#ifdef HPT_RESET_STATE_ENGINE
730 hpt370_clear_engine(drive);
731#endif
732 ide_dma_start(drive);
733}
734
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200735static int hpt370_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100737 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200738 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200740 if (dma_stat & ATA_DMA_ACTIVE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 /* wait a little */
742 udelay(20);
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200743 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200744 if (dma_stat & ATA_DMA_ACTIVE)
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100745 hpt370_irq_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746 }
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200747 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748}
749
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750/* returns 1 if DMA IRQ issued, 0 otherwise */
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200751static int hpt374_dma_test_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100753 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100754 struct pci_dev *dev = to_pci_dev(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755 u16 bfifo = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100756 u8 dma_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100758 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759 if (bfifo & 0x1FF) {
760// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
761 return 0;
762 }
763
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200764 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 /* return 1 if INTR asserted */
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200766 if (dma_stat & ATA_DMA_INTR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767 return 1;
768
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 return 0;
770}
771
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200772static int hpt374_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100774 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100775 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100776 u8 mcr = 0, mcr_addr = hwif->select_data;
777 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100779 pci_read_config_byte(dev, 0x6a, &bwsr);
780 pci_read_config_byte(dev, mcr_addr, &mcr);
781 if (bwsr & mask)
782 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200783 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784}
785
786/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800787 * hpt3xxn_set_clock - perform clock switching dance
788 * @hwif: hwif to switch
789 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800791 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800793
794static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795{
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100796 unsigned long base = hwif->extra_base;
797 u8 scr2 = inb(base + 0x6b);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800798
799 if ((scr2 & 0x7f) == mode)
800 return;
801
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 /* Tristate the bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100803 outb(0x80, base + 0x63);
804 outb(0x80, base + 0x67);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800805
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806 /* Switch clock and reset channels */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100807 outb(mode, base + 0x6b);
808 outb(0xc0, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800809
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100810 /*
811 * Reset the state machines.
812 * NOTE: avoid accidentally enabling the disabled channels.
813 */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100814 outb(inb(base + 0x60) | 0x32, base + 0x60);
815 outb(inb(base + 0x64) | 0x32, base + 0x64);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800816
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 /* Complete reset */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100818 outb(0x00, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800819
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820 /* Reconnect channels to bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100821 outb(0x00, base + 0x63);
822 outb(0x00, base + 0x67);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823}
824
825/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800826 * hpt3xxn_rw_disk - prepare for I/O
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 * @drive: drive for command
828 * @rq: block request structure
829 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800830 * This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831 * We need it because of the clock switching.
832 */
833
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800834static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835{
Sergei Shtylyovbbe54d72010-09-27 11:01:32 -0700836 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837}
838
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100839/**
840 * hpt37x_calibrate_dpll - calibrate the DPLL
841 * @dev: PCI device
842 *
843 * Perform a calibration cycle on the DPLL.
844 * Returns 1 if this succeeds
845 */
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200846static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100848 u32 dpll = (f_high << 16) | f_low | 0x100;
849 u8 scr2;
850 int i;
Alan Coxb39b01f2005-06-27 15:24:27 -0700851
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100852 pci_write_config_dword(dev, 0x5c, dpll);
Alan Coxb39b01f2005-06-27 15:24:27 -0700853
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100854 /* Wait for oscillator ready */
855 for(i = 0; i < 0x5000; ++i) {
856 udelay(50);
857 pci_read_config_byte(dev, 0x5b, &scr2);
858 if (scr2 & 0x80)
Alan Coxb39b01f2005-06-27 15:24:27 -0700859 break;
860 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100861 /* See if it stays ready (we'll just bail out if it's not yet) */
862 for(i = 0; i < 0x1000; ++i) {
863 pci_read_config_byte(dev, 0x5b, &scr2);
864 /* DPLL destabilized? */
865 if(!(scr2 & 0x80))
866 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +0100867 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100868 /* Turn off tuning, we have the DPLL set */
869 pci_read_config_dword (dev, 0x5c, &dpll);
870 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
871 return 1;
Alan Coxb39b01f2005-06-27 15:24:27 -0700872}
873
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200874static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +0200875{
876 struct ide_host *host = pci_get_drvdata(dev);
877 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
878 u8 chip_type = info->chip_type;
879 u8 new_mcr, old_mcr = 0;
880
881 /*
882 * Disable the "fast interrupt" prediction. Don't hold off
883 * on interrupts. (== 0x01 despite what the docs say)
884 */
885 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
886
887 if (chip_type >= HPT374)
888 new_mcr = old_mcr & ~0x07;
889 else if (chip_type >= HPT370) {
890 new_mcr = old_mcr;
891 new_mcr &= ~0x02;
892#ifdef HPT_DELAY_INTERRUPT
893 new_mcr &= ~0x01;
894#else
895 new_mcr |= 0x01;
896#endif
897 } else /* HPT366 and HPT368 */
898 new_mcr = old_mcr & ~0x80;
899
900 if (new_mcr != old_mcr)
901 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
902}
903
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +0100904static int init_chipset_hpt366(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100906 unsigned long io_base = pci_resource_start(dev, 4);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200907 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
Bartlomiej Zolnierkiewicza326b022008-07-24 22:53:33 +0200908 const char *name = DRV_NAME;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100909 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200910 u8 chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100911 enum ata_clock clock;
912
Sergei Shtylyov72931362007-09-11 22:28:35 +0200913 chip_type = info->chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100914
Alan Coxb39b01f2005-06-27 15:24:27 -0700915 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
916 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
917 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
918 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100920 /*
921 * First, try to estimate the PCI clock frequency...
922 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200923 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100924 u8 scr1 = 0;
925 u16 f_cnt = 0;
926 u32 temp = 0;
Alan Coxb39b01f2005-06-27 15:24:27 -0700927
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100928 /* Interrupt force enable. */
929 pci_read_config_byte(dev, 0x5a, &scr1);
930 if (scr1 & 0x10)
931 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100932
933 /*
934 * HighPoint does this for HPT372A.
935 * NOTE: This register is only writeable via I/O space.
936 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200937 if (chip_type == HPT372A)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100938 outb(0x0e, io_base + 0x9c);
939
940 /*
941 * Default to PCI clock. Make sure MA15/16 are set to output
942 * to prevent drives having problems with 40-pin cables.
943 */
944 pci_write_config_byte(dev, 0x5b, 0x23);
945
946 /*
947 * We'll have to read f_CNT value in order to determine
948 * the PCI clock frequency according to the following ratio:
949 *
950 * f_CNT = Fpci * 192 / Fdpll
951 *
952 * First try reading the register in which the HighPoint BIOS
953 * saves f_CNT value before reprogramming the DPLL from its
954 * default setting (which differs for the various chips).
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100955 *
Sergei Shtylyov72931362007-09-11 22:28:35 +0200956 * NOTE: This register is only accessible via I/O space;
957 * HPT374 BIOS only saves it for the function 0, so we have to
958 * always read it from there -- no need to check the result of
959 * pci_get_slot() for the function 0 as the whole device has
960 * been already "pinned" (via function 1) in init_setup_hpt374()
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100961 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200962 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
963 struct pci_dev *dev1 = pci_get_slot(dev->bus,
964 dev->devfn - 1);
965 unsigned long io_base = pci_resource_start(dev1, 4);
966
967 temp = inl(io_base + 0x90);
968 pci_dev_put(dev1);
969 } else
970 temp = inl(io_base + 0x90);
971
972 /*
973 * In case the signature check fails, we'll have to
974 * resort to reading the f_CNT register itself in hopes
975 * that nobody has touched the DPLL yet...
976 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100977 if ((temp & 0xFFFFF000) != 0xABCDE000) {
978 int i;
979
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200980 printk(KERN_WARNING "%s %s: no clock data saved by "
981 "BIOS\n", name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100982
983 /* Calculate the average value of f_CNT. */
984 for (temp = i = 0; i < 128; i++) {
985 pci_read_config_word(dev, 0x78, &f_cnt);
986 temp += f_cnt & 0x1ff;
987 mdelay(1);
988 }
989 f_cnt = temp / 128;
990 } else
991 f_cnt = temp & 0x1ff;
992
993 dpll_clk = info->dpll_clk;
994 pci_clk = (f_cnt * dpll_clk) / 192;
995
996 /* Clamp PCI clock to bands. */
997 if (pci_clk < 40)
998 pci_clk = 33;
999 else if(pci_clk < 45)
1000 pci_clk = 40;
1001 else if(pci_clk < 55)
1002 pci_clk = 50;
1003 else
1004 pci_clk = 66;
1005
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001006 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1007 "assuming %d MHz PCI\n", name, pci_name(dev),
1008 dpll_clk, f_cnt, pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001009 } else {
1010 u32 itr1 = 0;
1011
1012 pci_read_config_dword(dev, 0x40, &itr1);
1013
1014 /* Detect PCI clock by looking at cmd_high_time. */
1015 switch((itr1 >> 8) & 0x07) {
1016 case 0x09:
1017 pci_clk = 40;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001018 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001019 case 0x05:
1020 pci_clk = 25;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001021 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001022 case 0x07:
1023 default:
1024 pci_clk = 33;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001025 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001026 }
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001027 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001029 /* Let's assume we'll use PCI clock for the ATA clock... */
1030 switch (pci_clk) {
1031 case 25:
1032 clock = ATA_CLOCK_25MHZ;
1033 break;
1034 case 33:
1035 default:
1036 clock = ATA_CLOCK_33MHZ;
1037 break;
1038 case 40:
1039 clock = ATA_CLOCK_40MHZ;
1040 break;
1041 case 50:
1042 clock = ATA_CLOCK_50MHZ;
1043 break;
1044 case 66:
1045 clock = ATA_CLOCK_66MHZ;
1046 break;
1047 }
1048
1049 /*
1050 * Only try the DPLL if we don't have a table for the PCI clock that
1051 * we are running at for HPT370/A, always use it for anything newer...
1052 *
1053 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1054 * We also don't like using the DPLL because this causes glitches
1055 * on PRST-/SRST- when the state engine gets reset...
1056 */
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001057 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001058 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1059 int adjust;
1060
1061 /*
1062 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1063 * supported/enabled, use 50 MHz DPLL clock otherwise...
1064 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001065 if (info->udma_mask == ATA_UDMA6) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001066 dpll_clk = 66;
1067 clock = ATA_CLOCK_66MHZ;
1068 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1069 dpll_clk = 50;
1070 clock = ATA_CLOCK_50MHZ;
1071 }
1072
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001073 if (info->timings->clock_table[clock] == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001074 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1075 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001076 return -EIO;
1077 }
1078
1079 /* Select the DPLL clock. */
1080 pci_write_config_byte(dev, 0x5b, 0x21);
1081
1082 /*
1083 * Adjust the DPLL based upon PCI clock, enable it,
1084 * and wait for stabilization...
1085 */
1086 f_low = (pci_clk * 48) / dpll_clk;
1087
1088 for (adjust = 0; adjust < 8; adjust++) {
1089 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1090 break;
1091
1092 /*
1093 * See if it'll settle at a fractionally different clock
1094 */
1095 if (adjust & 1)
1096 f_low -= adjust >> 1;
1097 else
1098 f_low += adjust >> 1;
1099 }
1100 if (adjust == 8) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001101 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1102 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001103 return -EIO;
1104 }
1105
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001106 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1107 name, pci_name(dev), dpll_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001108 } else {
1109 /* Mark the fact that we're not using the DPLL. */
1110 dpll_clk = 0;
1111
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001112 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1113 name, pci_name(dev), pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001114 }
1115
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001116 /* Store the clock frequencies. */
1117 info->dpll_clk = dpll_clk;
1118 info->pci_clk = pci_clk;
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001119 info->clock = clock;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001120
Sergei Shtylyov72931362007-09-11 22:28:35 +02001121 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001122 u8 mcr1, mcr4;
1123
1124 /*
1125 * Reset the state engines.
1126 * NOTE: Avoid accidentally enabling the disabled channels.
1127 */
1128 pci_read_config_byte (dev, 0x50, &mcr1);
1129 pci_read_config_byte (dev, 0x54, &mcr4);
1130 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1131 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1132 udelay(100);
1133 }
1134
1135 /*
1136 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1137 * the MISC. register to stretch the UltraDMA Tss timing.
1138 * NOTE: This register is only writeable via I/O space.
1139 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001140 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001141 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1142
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +02001143 hpt3xx_disable_fast_irq(dev, 0x50);
1144 hpt3xx_disable_fast_irq(dev, 0x54);
1145
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +01001146 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147}
1148
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +02001149static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001150{
1151 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001152 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001153 u8 chip_type = info->chip_type;
1154 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1155
1156 /*
1157 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1158 * address lines to access an external EEPROM. To read valid
1159 * cable detect state the pins must be enabled as inputs.
1160 */
1161 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1162 /*
1163 * HPT374 PCI function 1
1164 * - set bit 15 of reg 0x52 to enable TCBLID as input
1165 * - set bit 15 of reg 0x56 to enable FCBLID as input
1166 */
1167 u8 mcr_addr = hwif->select_data + 2;
1168 u16 mcr;
1169
1170 pci_read_config_word(dev, mcr_addr, &mcr);
Sergei Shtylyov5d3f1a42010-09-27 11:00:40 -07001171 pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
1172 /* Debounce, then read cable ID register */
1173 udelay(10);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001174 pci_read_config_byte(dev, 0x5a, &scr1);
1175 pci_write_config_word(dev, mcr_addr, mcr);
1176 } else if (chip_type >= HPT370) {
1177 /*
1178 * HPT370/372 and 374 pcifn 0
1179 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1180 */
1181 u8 scr2 = 0;
1182
1183 pci_read_config_byte(dev, 0x5b, &scr2);
Sergei Shtylyov5d3f1a42010-09-27 11:00:40 -07001184 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1185 /* Debounce, then read cable ID register */
1186 udelay(10);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001187 pci_read_config_byte(dev, 0x5a, &scr1);
Sergei Shtylyov5d3f1a42010-09-27 11:00:40 -07001188 pci_write_config_byte(dev, 0x5b, scr2);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001189 } else
1190 pci_read_config_byte(dev, 0x5a, &scr1);
1191
1192 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1193}
1194
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001195static void init_hwif_hpt366(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196{
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001197 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001198 u8 chip_type = info->chip_type;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001199
1200 /* Cache the channel's MISC. control registers' offset */
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001201 hwif->select_data = hwif->channel ? 0x54 : 0x50;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001202
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001203 /*
1204 * HPT3xxN chips have some complications:
1205 *
1206 * - on 33 MHz PCI we must clock switch
1207 * - on 66 MHz PCI we must NOT use the PCI clock
1208 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001209 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001210 /*
1211 * Clock is shared between the channels,
1212 * so we'll have to serialize them... :-(
1213 */
Bartlomiej Zolnierkiewicz702c0262008-12-29 20:27:36 +01001214 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001215 hwif->rw_disk = &hpt3xxn_rw_disk;
1216 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217}
1218
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001219static int init_dma_hpt366(ide_hwif_t *hwif,
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001220 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001222 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001223 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1224 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225
Bartlomiej Zolnierkiewiczebb00fb2008-07-23 19:55:51 +02001226 if (base == 0)
1227 return -1;
1228
1229 hwif->dma_base = base;
1230
1231 if (ide_pci_check_simplex(hwif, d) < 0)
1232 return -1;
1233
1234 if (ide_pci_set_master(dev, d->name) < 0)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001235 return -1;
1236
1237 dma_old = inb(base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238
1239 local_irq_save(flags);
1240
1241 dma_new = dma_old;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001242 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1243 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244
1245 if (masterdma & 0x30) dma_new |= 0x20;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001246 if ( slavedma & 0x30) dma_new |= 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247 if (dma_new != dma_old)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001248 outb(dma_new, base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249
1250 local_irq_restore(flags);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001251
1252 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1253 hwif->name, base, base + 7);
1254
1255 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1256
1257 if (ide_allocate_dma_engine(hwif))
1258 return -1;
1259
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001260 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261}
1262
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001263static void hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001265 if (dev2->irq != dev->irq) {
1266 /* FIXME: we need a core pci_set_interrupt() */
1267 dev2->irq = dev->irq;
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001268 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001269 "fixed\n", pci_name(dev2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001271}
1272
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001273static void hpt371_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001274{
Auke Kok44c10132007-06-08 15:46:36 -07001275 u8 mcr1 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001276
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001277 /*
1278 * HPT371 chips physically have only one channel, the secondary one,
1279 * but the primary channel registers do exist! Go figure...
1280 * So, we manually disable the non-existing channel here
1281 * (if the BIOS hasn't done this already).
1282 */
1283 pci_read_config_byte(dev, 0x50, &mcr1);
1284 if (mcr1 & 0x04)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001285 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001286}
1287
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001288static int hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001289{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001290 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001291
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001292 /*
1293 * Now we'll have to force both channels enabled if
1294 * at least one of them has been enabled by BIOS...
1295 */
1296 pci_read_config_byte(dev, 0x50, &mcr1);
1297 if (mcr1 & 0x30)
1298 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001299
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001300 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1301 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001302
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001303 if (pin1 != pin2 && dev->irq == dev2->irq) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001304 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001305 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001306 return 1;
1307 }
1308
1309 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001310}
1311
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001312#define IDE_HFLAGS_HPT3XX \
1313 (IDE_HFLAG_NO_ATAPI_DMA | \
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001314 IDE_HFLAG_OFF_BOARD)
1315
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001316static const struct ide_port_ops hpt3xx_port_ops = {
1317 .set_pio_mode = hpt3xx_set_pio_mode,
1318 .set_dma_mode = hpt3xx_set_mode,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001319 .maskproc = hpt3xx_maskproc,
1320 .mdma_filter = hpt3xx_mdma_filter,
1321 .udma_filter = hpt3xx_udma_filter,
1322 .cable_detect = hpt3xx_cable_detect,
1323};
1324
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001325static const struct ide_dma_ops hpt37x_dma_ops = {
1326 .dma_host_set = ide_dma_host_set,
1327 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001328 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001329 .dma_end = hpt374_dma_end,
1330 .dma_test_irq = hpt374_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001331 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001332 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001333 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001334};
1335
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001336static const struct ide_dma_ops hpt370_dma_ops = {
1337 .dma_host_set = ide_dma_host_set,
1338 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001339 .dma_start = hpt370_dma_start,
1340 .dma_end = hpt370_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001341 .dma_test_irq = ide_dma_test_irq,
1342 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001343 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Bartlomiej Zolnierkiewicz35c9b4d2009-03-31 20:15:19 +02001344 .dma_clear = hpt370_irq_timeout,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001345 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001346};
1347
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001348static const struct ide_dma_ops hpt36x_dma_ops = {
1349 .dma_host_set = ide_dma_host_set,
1350 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001351 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +02001352 .dma_end = ide_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001353 .dma_test_irq = ide_dma_test_irq,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001354 .dma_lost_irq = hpt366_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001355 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001356 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001357};
1358
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001359static const struct ide_port_info hpt366_chipsets[] = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001360 { /* 0: HPT36x */
1361 .name = DRV_NAME,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001362 .init_chipset = init_chipset_hpt366,
1363 .init_hwif = init_hwif_hpt366,
1364 .init_dma = init_dma_hpt366,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001365 /*
1366 * HPT36x chips have one channel per function and have
1367 * both channel enable bits located differently and visible
1368 * to both functions -- really stupid design decision... :-(
1369 * Bit 4 is for the primary channel, bit 5 for the secondary.
1370 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001371 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001372 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001373 .dma_ops = &hpt36x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001374 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001375 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001376 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001377 },
1378 { /* 1: HPT3xx */
1379 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380 .init_chipset = init_chipset_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001381 .init_hwif = init_hwif_hpt366,
1382 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001383 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001384 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001385 .dma_ops = &hpt37x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001386 .host_flags = IDE_HFLAGS_HPT3XX,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001387 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001388 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389 }
1390};
1391
1392/**
1393 * hpt366_init_one - called when an HPT366 is found
1394 * @dev: the hpt366 device
1395 * @id: the matching pci id
1396 *
1397 * Called when the PCI registration layer (or the IDE initialization)
1398 * finds a device matching our IDE device tables.
1399 */
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001400static int hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401{
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +02001402 const struct hpt_info *info = NULL;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001403 struct hpt_info *dyn_info;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001404 struct pci_dev *dev2 = NULL;
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +02001405 struct ide_port_info d;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001406 u8 idx = id->driver_data;
1407 u8 rev = dev->revision;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001408 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001410 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1411 return -ENODEV;
1412
1413 switch (idx) {
1414 case 0:
1415 if (rev < 3)
1416 info = &hpt36x;
1417 else {
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001418 switch (min_t(u8, rev, 6)) {
1419 case 3: info = &hpt370; break;
1420 case 4: info = &hpt370a; break;
1421 case 5: info = &hpt372; break;
1422 case 6: info = &hpt372n; break;
1423 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001424 idx++;
1425 }
1426 break;
1427 case 1:
1428 info = (rev > 1) ? &hpt372n : &hpt372a;
1429 break;
1430 case 2:
1431 info = (rev > 1) ? &hpt302n : &hpt302;
1432 break;
1433 case 3:
1434 hpt371_init(dev);
1435 info = (rev > 1) ? &hpt371n : &hpt371;
1436 break;
1437 case 4:
1438 info = &hpt374;
1439 break;
1440 case 5:
1441 info = &hpt372n;
1442 break;
1443 }
1444
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001445 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001446
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001447 d = hpt366_chipsets[min_t(u8, idx, 1)];
1448
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001449 d.udma_mask = info->udma_mask;
1450
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001451 /* fixup ->dma_ops for HPT370/HPT370A */
1452 if (info == &hpt370 || info == &hpt370a)
1453 d.dma_ops = &hpt370_dma_ops;
1454
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001455 if (info == &hpt36x || info == &hpt374)
1456 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1457
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001458 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1459 if (dyn_info == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001460 printk(KERN_ERR "%s %s: out of memory!\n",
1461 d.name, pci_name(dev));
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001462 pci_dev_put(dev2);
1463 return -ENOMEM;
1464 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001465
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001466 /*
1467 * Copy everything from a static "template" structure
1468 * to just allocated per-chip hpt_info structure.
1469 */
1470 memcpy(dyn_info, info, sizeof(*dyn_info));
1471
1472 if (dev2) {
1473 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001474
1475 if (info == &hpt374)
1476 hpt374_init(dev, dev2);
1477 else {
1478 if (hpt36x_init(dev, dev2))
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +02001479 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001480 }
1481
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001482 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1483 if (ret < 0) {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001484 pci_dev_put(dev2);
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001485 kfree(dyn_info);
1486 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001487 return ret;
1488 }
1489
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001490 ret = ide_pci_init_one(dev, &d, dyn_info);
1491 if (ret < 0)
1492 kfree(dyn_info);
1493
1494 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495}
1496
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001497static void hpt366_remove(struct pci_dev *dev)
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001498{
1499 struct ide_host *host = pci_get_drvdata(dev);
1500 struct ide_info *info = host->host_priv;
1501 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1502
1503 ide_pci_remove(dev);
1504 pci_dev_put(dev2);
1505 kfree(info);
1506}
1507
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001508static const struct pci_device_id hpt366_pci_tbl[] = {
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001509 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1510 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1511 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1512 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1513 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1514 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001515 { 0, },
1516};
1517MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1518
Bartlomiej Zolnierkiewicza9ab09e22008-10-13 21:39:41 +02001519static struct pci_driver hpt366_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001520 .name = "HPT366_IDE",
1521 .id_table = hpt366_pci_tbl,
1522 .probe = hpt366_init_one,
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001523 .remove = hpt366_remove,
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +02001524 .suspend = ide_pci_suspend,
1525 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526};
1527
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +01001528static int __init hpt366_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001529{
Bartlomiej Zolnierkiewicza9ab09e22008-10-13 21:39:41 +02001530 return ide_pci_register_driver(&hpt366_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531}
1532
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001533static void __exit hpt366_ide_exit(void)
1534{
Bartlomiej Zolnierkiewicza9ab09e22008-10-13 21:39:41 +02001535 pci_unregister_driver(&hpt366_pci_driver);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001536}
1537
Linus Torvalds1da177e2005-04-16 15:20:36 -07001538module_init(hpt366_ide_init);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001539module_exit(hpt366_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540
1541MODULE_AUTHOR("Andre Hedrick");
1542MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1543MODULE_LICENSE("GPL");