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Chunfeng Yundf2069a2016-10-19 10:28:23 +08001/*
2 * Copyright (C) 2016 MediaTek Inc.
3 *
4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clk.h>
18#include <linux/dma-mapping.h>
19#include <linux/iopoll.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080024#include <linux/pinctrl/consumer.h>
Chunfeng Yundf2069a2016-10-19 10:28:23 +080025#include <linux/platform_device.h>
26
27#include "mtu3.h"
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080028#include "mtu3_dr.h"
Chunfeng Yundf2069a2016-10-19 10:28:23 +080029
30/* u2-port0 should be powered on and enabled; */
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080031int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
Chunfeng Yundf2069a2016-10-19 10:28:23 +080032{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080033 void __iomem *ibase = ssusb->ippc_base;
Chunfeng Yundf2069a2016-10-19 10:28:23 +080034 u32 value, check_val;
35 int ret;
36
37 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
38 SSUSB_REF_RST_B_STS;
39
40 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
41 (check_val == (value & check_val)), 100, 20000);
42 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080043 dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +080044 return ret;
45 }
46
47 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
48 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
49 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080050 dev_err(ssusb->dev, "mac2 clock is not stable\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +080051 return ret;
52 }
53
54 return 0;
55}
56
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080057static int ssusb_phy_init(struct ssusb_mtk *ssusb)
58{
59 int i;
60 int ret;
61
62 for (i = 0; i < ssusb->num_phys; i++) {
63 ret = phy_init(ssusb->phys[i]);
64 if (ret)
65 goto exit_phy;
66 }
67 return 0;
68
69exit_phy:
70 for (; i > 0; i--)
71 phy_exit(ssusb->phys[i - 1]);
72
73 return ret;
74}
75
76static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
77{
78 int i;
79
80 for (i = 0; i < ssusb->num_phys; i++)
81 phy_exit(ssusb->phys[i]);
82
83 return 0;
84}
85
86static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
87{
88 int i;
89 int ret;
90
91 for (i = 0; i < ssusb->num_phys; i++) {
92 ret = phy_power_on(ssusb->phys[i]);
93 if (ret)
94 goto power_off_phy;
95 }
96 return 0;
97
98power_off_phy:
99 for (; i > 0; i--)
100 phy_power_off(ssusb->phys[i - 1]);
101
102 return ret;
103}
104
105static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
106{
107 unsigned int i;
108
109 for (i = 0; i < ssusb->num_phys; i++)
110 phy_power_off(ssusb->phys[i]);
111}
112
113static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800114{
115 int ret = 0;
116
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800117 ret = regulator_enable(ssusb->vusb33);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800118 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800119 dev_err(ssusb->dev, "failed to enable vusb33\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800120 goto vusb33_err;
121 }
122
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800123 ret = clk_prepare_enable(ssusb->sys_clk);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800124 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800125 dev_err(ssusb->dev, "failed to enable sys_clk\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800126 goto clk_err;
127 }
128
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800129 ret = ssusb_phy_init(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800130 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800131 dev_err(ssusb->dev, "failed to init phy\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800132 goto phy_init_err;
133 }
134
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800135 ret = ssusb_phy_power_on(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800136 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800137 dev_err(ssusb->dev, "failed to power on phy\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800138 goto phy_err;
139 }
140
141 return 0;
142
143phy_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800144 ssusb_phy_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800145
146phy_init_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800147 clk_disable_unprepare(ssusb->sys_clk);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800148
149clk_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800150 regulator_disable(ssusb->vusb33);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800151
152vusb33_err:
153
154 return ret;
155}
156
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800157static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800158{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800159 clk_disable_unprepare(ssusb->sys_clk);
160 regulator_disable(ssusb->vusb33);
161 ssusb_phy_power_off(ssusb);
162 ssusb_phy_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800163}
164
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800165static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800166{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800167 /* reset whole ip (xhci & u3d) */
168 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800169 udelay(1);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800170 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800171}
172
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800173static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800174{
175 struct device_node *node = pdev->dev.of_node;
176 struct device *dev = &pdev->dev;
177 struct resource *res;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800178 int i;
179 int ret;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800180
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800181 ssusb->num_phys = of_count_phandle_with_args(node,
182 "phys", "#phy-cells");
183 if (ssusb->num_phys > 0) {
184 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
185 sizeof(*ssusb->phys), GFP_KERNEL);
186 if (!ssusb->phys)
187 return -ENOMEM;
188 } else {
189 ssusb->num_phys = 0;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800190 }
191
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800192 for (i = 0; i < ssusb->num_phys; i++) {
193 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
194 if (IS_ERR(ssusb->phys[i])) {
195 dev_err(dev, "failed to get phy-%d\n", i);
196 return PTR_ERR(ssusb->phys[i]);
197 }
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800198 }
199
200 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800201 ssusb->ippc_base = devm_ioremap_resource(dev, res);
202 if (IS_ERR(ssusb->ippc_base)) {
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800203 dev_err(dev, "failed to map memory for ippc\n");
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800204 return PTR_ERR(ssusb->ippc_base);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800205 }
206
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800207 ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
208 if (IS_ERR(ssusb->vusb33)) {
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800209 dev_err(dev, "failed to get vusb33\n");
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800210 return PTR_ERR(ssusb->vusb33);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800211 }
212
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800213 ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
214 if (IS_ERR(ssusb->sys_clk)) {
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800215 dev_err(dev, "failed to get sys clock\n");
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800216 return PTR_ERR(ssusb->sys_clk);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800217 }
218
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800219 ssusb->dr_mode = usb_get_dr_mode(dev);
220 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
221 dev_err(dev, "dr_mode is error\n");
222 return -EINVAL;
223 }
224
225 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
226 return 0;
227
228 /* if host role is supported */
229 ret = ssusb_wakeup_of_property_parse(ssusb, node);
230 if (ret)
231 return ret;
232
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800233 return 0;
234}
235
236static int mtu3_probe(struct platform_device *pdev)
237{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800238 struct device_node *node = pdev->dev.of_node;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800239 struct device *dev = &pdev->dev;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800240 struct ssusb_mtk *ssusb;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800241 int ret = -ENOMEM;
242
243 /* all elements are set to ZERO as default value */
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800244 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
245 if (!ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800246 return -ENOMEM;
247
248 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
249 if (ret) {
250 dev_err(dev, "No suitable DMA config available\n");
251 return -ENOTSUPP;
252 }
253
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800254 platform_set_drvdata(pdev, ssusb);
255 ssusb->dev = dev;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800256
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800257 ret = get_ssusb_rscs(pdev, ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800258 if (ret)
259 return ret;
260
261 /* enable power domain */
262 pm_runtime_enable(dev);
263 pm_runtime_get_sync(dev);
264 device_enable_async_suspend(dev);
265
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800266 ret = ssusb_rscs_init(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800267 if (ret)
268 goto comm_init_err;
269
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800270 ssusb_ip_sw_reset(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800271
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800272 if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
273 ssusb->dr_mode = USB_DR_MODE_HOST;
274 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
275 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
276
277 /* default as host */
278 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
279
280 switch (ssusb->dr_mode) {
281 case USB_DR_MODE_PERIPHERAL:
282 ret = ssusb_gadget_init(ssusb);
283 if (ret) {
284 dev_err(dev, "failed to initialize gadget\n");
285 goto comm_exit;
286 }
287 break;
288 case USB_DR_MODE_HOST:
289 ret = ssusb_host_init(ssusb, node);
290 if (ret) {
291 dev_err(dev, "failed to initialize host\n");
292 goto comm_exit;
293 }
294 break;
295 default:
296 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
297 ret = -EINVAL;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800298 goto comm_exit;
299 }
300
301 return 0;
302
303comm_exit:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800304 ssusb_rscs_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800305
306comm_init_err:
307 pm_runtime_put_sync(dev);
308 pm_runtime_disable(dev);
309
310 return ret;
311}
312
313static int mtu3_remove(struct platform_device *pdev)
314{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800315 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800316
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800317 switch (ssusb->dr_mode) {
318 case USB_DR_MODE_PERIPHERAL:
319 ssusb_gadget_exit(ssusb);
320 break;
321 case USB_DR_MODE_HOST:
322 ssusb_host_exit(ssusb);
323 break;
324 default:
325 return -EINVAL;
326 }
327
328 ssusb_rscs_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800329 pm_runtime_put_sync(&pdev->dev);
330 pm_runtime_disable(&pdev->dev);
331
332 return 0;
333}
334
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800335/*
336 * when support dual-role mode, we reject suspend when
337 * it works as device mode;
338 */
339static int __maybe_unused mtu3_suspend(struct device *dev)
340{
341 struct platform_device *pdev = to_platform_device(dev);
342 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
343
344 dev_dbg(dev, "%s\n", __func__);
345
346 /* REVISIT: disconnect it for only device mode? */
347 if (!ssusb->is_host)
348 return 0;
349
350 ssusb_host_disable(ssusb, true);
351 ssusb_phy_power_off(ssusb);
352 clk_disable_unprepare(ssusb->sys_clk);
353 ssusb_wakeup_enable(ssusb);
354
355 return 0;
356}
357
358static int __maybe_unused mtu3_resume(struct device *dev)
359{
360 struct platform_device *pdev = to_platform_device(dev);
361 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
362
363 dev_dbg(dev, "%s\n", __func__);
364
365 if (!ssusb->is_host)
366 return 0;
367
368 ssusb_wakeup_disable(ssusb);
369 clk_prepare_enable(ssusb->sys_clk);
370 ssusb_phy_power_on(ssusb);
371 ssusb_host_enable(ssusb);
372
373 return 0;
374}
375
376static const struct dev_pm_ops mtu3_pm_ops = {
377 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
378};
379
380#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
381
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800382#ifdef CONFIG_OF
383
384static const struct of_device_id mtu3_of_match[] = {
385 {.compatible = "mediatek,mt8173-mtu3",},
386 {},
387};
388
389MODULE_DEVICE_TABLE(of, mtu3_of_match);
390
391#endif
392
393static struct platform_driver mtu3_driver = {
394 .probe = mtu3_probe,
395 .remove = mtu3_remove,
396 .driver = {
397 .name = MTU3_DRIVER_NAME,
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800398 .pm = DEV_PM_OPS,
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800399 .of_match_table = of_match_ptr(mtu3_of_match),
400 },
401};
402module_platform_driver(mtu3_driver);
403
404MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
405MODULE_LICENSE("GPL v2");
406MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");