blob: 69cd7cfa276bebf1016013748ee4ecab873ac04a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
Matt Carlsonb86fb2c2011-01-25 15:58:57 +00007 * Copyright (C) 2005-2011 Broadcom Corporation.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * Firmware is:
Michael Chan49cabf42005-06-06 15:15:17 -070010 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
19#include <linux/module.h>
20#include <linux/moduleparam.h>
Matt Carlson6867c842010-07-11 09:31:44 +000021#include <linux/stringify.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
Arnaldo Carvalho de Melo14c85022005-12-27 02:43:12 -020027#include <linux/in.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/init.h>
29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
Matt Carlson3110f5f52010-12-06 08:28:50 +000035#include <linux/mdio.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <linux/mii.h>
Matt Carlson158d7ab2008-05-29 01:37:54 -070037#include <linux/phy.h>
Matt Carlsona9daf362008-05-25 23:49:44 -070038#include <linux/brcmphy.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/if_vlan.h>
40#include <linux/ip.h>
41#include <linux/tcp.h>
42#include <linux/workqueue.h>
Michael Chan61487482005-09-05 17:53:19 -070043#include <linux/prefetch.h>
Tobias Klauserf9a5f7d2005-10-29 15:09:26 +020044#include <linux/dma-mapping.h>
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080045#include <linux/firmware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
47#include <net/checksum.h>
Arnaldo Carvalho de Meloc9bdd4b2007-03-12 20:09:15 -030048#include <net/ip.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
50#include <asm/system.h>
Javier Martinez Canillas27fd9de2011-03-26 16:42:31 +000051#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070052#include <asm/byteorder.h>
Javier Martinez Canillas27fd9de2011-03-26 16:42:31 +000053#include <linux/uaccess.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070054
David S. Miller49b6e95f2007-03-29 01:38:42 -070055#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070056#include <asm/idprom.h>
David S. Miller49b6e95f2007-03-29 01:38:42 -070057#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070058#endif
59
Matt Carlson63532392008-11-03 16:49:57 -080060#define BAR_0 0
61#define BAR_2 2
62
Linus Torvalds1da177e2005-04-16 15:20:36 -070063#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
Matt Carlson6867c842010-07-11 09:31:44 +000066#define TG3_MAJ_NUM 3
Matt Carlsonb86fb2c2011-01-25 15:58:57 +000067#define TG3_MIN_NUM 117
Matt Carlson6867c842010-07-11 09:31:44 +000068#define DRV_MODULE_VERSION \
69 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
Matt Carlsonb86fb2c2011-01-25 15:58:57 +000070#define DRV_MODULE_RELDATE "January 25, 2011"
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
72#define TG3_DEF_MAC_MODE 0
73#define TG3_DEF_RX_MODE 0
74#define TG3_DEF_TX_MODE 0
75#define TG3_DEF_MSG_ENABLE \
76 (NETIF_MSG_DRV | \
77 NETIF_MSG_PROBE | \
78 NETIF_MSG_LINK | \
79 NETIF_MSG_TIMER | \
80 NETIF_MSG_IFDOWN | \
81 NETIF_MSG_IFUP | \
82 NETIF_MSG_RX_ERR | \
83 NETIF_MSG_TX_ERR)
84
85/* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
87 */
88#define TG3_TX_TIMEOUT (5 * HZ)
89
90/* hardware minimum and maximum for a single frame's data payload */
91#define TG3_MIN_MTU 60
92#define TG3_MAX_MTU(tp) \
Matt Carlson8f666b02009-08-28 13:58:24 +000093 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
95/* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
98 */
Matt Carlson7cb32cf2010-09-30 10:34:36 +000099#define TG3_RX_STD_RING_SIZE(tp) \
Matt Carlsonde9f5232011-04-05 14:22:43 +0000100 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102#define TG3_DEF_RX_RING_PENDING 200
Matt Carlson7cb32cf2010-09-30 10:34:36 +0000103#define TG3_RX_JMB_RING_SIZE(tp) \
Matt Carlsonde9f5232011-04-05 14:22:43 +0000104 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106#define TG3_DEF_RX_JUMBO_RING_PENDING 100
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000107#define TG3_RSS_INDIR_TBL_SIZE 128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108
109/* Do not place this n-ring entries value into the tp struct itself,
110 * we really want to expose these constants to GCC so that modulo et
111 * al. operations are done with shifts and masks instead of with
112 * hw multiply/modulo instructions. Another solution would be to
113 * replace things like '% foo' with '& (foo - 1)'.
114 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115
116#define TG3_TX_RING_SIZE 512
117#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
Matt Carlson2c49a442010-09-30 10:34:35 +0000119#define TG3_RX_STD_RING_BYTES(tp) \
120 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121#define TG3_RX_JMB_RING_BYTES(tp) \
122 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123#define TG3_RX_RCB_RING_BYTES(tp) \
Matt Carlson7cb32cf2010-09-30 10:34:36 +0000124 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
Matt Carlson287be122009-08-28 13:58:46 +0000129#define TG3_DMA_BYTE_ENAB 64
130
131#define TG3_RX_STD_DMA_SZ 1536
132#define TG3_RX_JMB_DMA_SZ 9046
133
134#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135
136#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138
Matt Carlson2c49a442010-09-30 10:34:35 +0000139#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
Matt Carlson2b2cdb62009-11-13 13:03:48 +0000141
Matt Carlson2c49a442010-09-30 10:34:35 +0000142#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
Matt Carlson2b2cdb62009-11-13 13:03:48 +0000144
Matt Carlsond2757fc2010-04-12 06:58:27 +0000145/* Due to a hardware bug, the 5701 can only DMA to memory addresses
146 * that are at least dword aligned when used in PCIX mode. The driver
147 * works around this bug by double copying the packet. This workaround
148 * is built into the normal double copy length check for efficiency.
149 *
150 * However, the double copy is only necessary on those architectures
151 * where unaligned memory accesses are inefficient. For those architectures
152 * where unaligned memory accesses incur little penalty, we can reintegrate
153 * the 5701 in the normal rx path. Doing so saves a device structure
154 * dereference by hardcoding the double copy threshold in place.
155 */
156#define TG3_RX_COPY_THRESHOLD 256
157#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
159#else
160 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
161#endif
162
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163/* minimum number of free TX descriptors required to wake up TX process */
Matt Carlsonf3f3f272009-08-28 14:03:21 +0000164#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165
Matt Carlsonad829262008-11-21 17:16:16 -0800166#define TG3_RAW_IP_ALIGN 2
167
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000168#define TG3_FW_UPDATE_TIMEOUT_SEC 5
169
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -0800170#define FIRMWARE_TG3 "tigon/tg3.bin"
171#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
172#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
173
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174static char version[] __devinitdata =
Joe Perches05dbe002010-02-17 19:44:19 +0000175 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176
177MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
178MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
179MODULE_LICENSE("GPL");
180MODULE_VERSION(DRV_MODULE_VERSION);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -0800181MODULE_FIRMWARE(FIRMWARE_TG3);
182MODULE_FIRMWARE(FIRMWARE_TG3TSO);
183MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
184
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
186module_param(tg3_debug, int, 0);
187MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
188
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000189static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
Michael Chan126a3362006-09-27 16:03:07 -0700213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
Michael Chan126a3362006-09-27 16:03:07 -0700226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
Michael Chan676917d2006-12-07 00:20:22 -0800230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
Michael Chanb5d37722006-09-27 16:06:21 -0700238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
Matt Carlsond30cdd22007-10-07 23:28:35 -0700240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
Matt Carlson6c7af272007-10-21 16:12:02 -0700242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
Matt Carlson9936bcf2007-10-10 18:03:07 -0700243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
Matt Carlsonc88e6682008-11-03 16:49:18 -0800245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
Matt Carlson2befdce2009-08-28 12:28:45 +0000247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
Matt Carlson321d32a2008-11-21 17:22:19 -0800249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
Matt Carlson5e7ccf22009-08-25 10:08:42 +0000252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
Matt Carlson5001e2f2009-11-13 13:03:51 +0000253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
Matt Carlsonb0f75222010-01-20 16:58:11 +0000255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
Matt Carlson302b5002010-06-05 17:24:38 +0000261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
Matt Carlsonba1f3c72011-04-05 14:22:50 +0000262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700263 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
264 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
265 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
266 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
267 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
268 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
269 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
270 {}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271};
272
273MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
274
Andreas Mohr50da8592006-08-14 23:54:30 -0700275static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 const char string[ETH_GSTRING_LEN];
Matt Carlson48fa55a2011-04-13 11:05:06 +0000277} ethtool_stats_keys[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 { "rx_octets" },
279 { "rx_fragments" },
280 { "rx_ucast_packets" },
281 { "rx_mcast_packets" },
282 { "rx_bcast_packets" },
283 { "rx_fcs_errors" },
284 { "rx_align_errors" },
285 { "rx_xon_pause_rcvd" },
286 { "rx_xoff_pause_rcvd" },
287 { "rx_mac_ctrl_rcvd" },
288 { "rx_xoff_entered" },
289 { "rx_frame_too_long_errors" },
290 { "rx_jabbers" },
291 { "rx_undersize_packets" },
292 { "rx_in_length_errors" },
293 { "rx_out_length_errors" },
294 { "rx_64_or_less_octet_packets" },
295 { "rx_65_to_127_octet_packets" },
296 { "rx_128_to_255_octet_packets" },
297 { "rx_256_to_511_octet_packets" },
298 { "rx_512_to_1023_octet_packets" },
299 { "rx_1024_to_1522_octet_packets" },
300 { "rx_1523_to_2047_octet_packets" },
301 { "rx_2048_to_4095_octet_packets" },
302 { "rx_4096_to_8191_octet_packets" },
303 { "rx_8192_to_9022_octet_packets" },
304
305 { "tx_octets" },
306 { "tx_collisions" },
307
308 { "tx_xon_sent" },
309 { "tx_xoff_sent" },
310 { "tx_flow_control" },
311 { "tx_mac_errors" },
312 { "tx_single_collisions" },
313 { "tx_mult_collisions" },
314 { "tx_deferred" },
315 { "tx_excessive_collisions" },
316 { "tx_late_collisions" },
317 { "tx_collide_2times" },
318 { "tx_collide_3times" },
319 { "tx_collide_4times" },
320 { "tx_collide_5times" },
321 { "tx_collide_6times" },
322 { "tx_collide_7times" },
323 { "tx_collide_8times" },
324 { "tx_collide_9times" },
325 { "tx_collide_10times" },
326 { "tx_collide_11times" },
327 { "tx_collide_12times" },
328 { "tx_collide_13times" },
329 { "tx_collide_14times" },
330 { "tx_collide_15times" },
331 { "tx_ucast_packets" },
332 { "tx_mcast_packets" },
333 { "tx_bcast_packets" },
334 { "tx_carrier_sense_errors" },
335 { "tx_discards" },
336 { "tx_errors" },
337
338 { "dma_writeq_full" },
339 { "dma_write_prioq_full" },
340 { "rxbds_empty" },
341 { "rx_discards" },
Matt Carlson4d958472011-04-20 07:57:35 +0000342 { "mbuf_lwm_thresh_hit" },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 { "rx_errors" },
344 { "rx_threshold_hit" },
345
346 { "dma_readq_full" },
347 { "dma_read_prioq_full" },
348 { "tx_comp_queue_full" },
349
350 { "ring_set_send_prod_index" },
351 { "ring_status_update" },
352 { "nic_irqs" },
353 { "nic_avoided_irqs" },
354 { "nic_tx_threshold_hit" }
355};
356
Matt Carlson48fa55a2011-04-13 11:05:06 +0000357#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
358
359
Andreas Mohr50da8592006-08-14 23:54:30 -0700360static const struct {
Michael Chan4cafd3f2005-05-29 14:56:34 -0700361 const char string[ETH_GSTRING_LEN];
Matt Carlson48fa55a2011-04-13 11:05:06 +0000362} ethtool_test_keys[] = {
Michael Chan4cafd3f2005-05-29 14:56:34 -0700363 { "nvram test (online) " },
364 { "link test (online) " },
365 { "register test (offline)" },
366 { "memory test (offline)" },
367 { "loopback test (offline)" },
368 { "interrupt test (offline)" },
369};
370
Matt Carlson48fa55a2011-04-13 11:05:06 +0000371#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
372
373
Michael Chanb401e9e2005-12-19 16:27:04 -0800374static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
375{
376 writel(val, tp->regs + off);
377}
378
379static u32 tg3_read32(struct tg3 *tp, u32 off)
380{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000381 return readl(tp->regs + off);
Michael Chanb401e9e2005-12-19 16:27:04 -0800382}
383
Matt Carlson0d3031d2007-10-10 18:02:43 -0700384static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
385{
386 writel(val, tp->aperegs + off);
387}
388
389static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
390{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000391 return readl(tp->aperegs + off);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700392}
393
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
395{
Michael Chan68929142005-08-09 20:17:14 -0700396 unsigned long flags;
397
398 spin_lock_irqsave(&tp->indirect_lock, flags);
Michael Chan1ee582d2005-08-09 20:16:46 -0700399 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
400 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
Michael Chan68929142005-08-09 20:17:14 -0700401 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Michael Chan1ee582d2005-08-09 20:16:46 -0700402}
403
404static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
405{
406 writel(val, tp->regs + off);
407 readl(tp->regs + off);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408}
409
Michael Chan68929142005-08-09 20:17:14 -0700410static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
411{
412 unsigned long flags;
413 u32 val;
414
415 spin_lock_irqsave(&tp->indirect_lock, flags);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
417 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
418 spin_unlock_irqrestore(&tp->indirect_lock, flags);
419 return val;
420}
421
422static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
423{
424 unsigned long flags;
425
426 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
427 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
428 TG3_64BIT_REG_LOW, val);
429 return;
430 }
Matt Carlson66711e62009-11-13 13:03:49 +0000431 if (off == TG3_RX_STD_PROD_IDX_REG) {
Michael Chan68929142005-08-09 20:17:14 -0700432 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
433 TG3_64BIT_REG_LOW, val);
434 return;
435 }
436
437 spin_lock_irqsave(&tp->indirect_lock, flags);
438 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
439 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
440 spin_unlock_irqrestore(&tp->indirect_lock, flags);
441
442 /* In indirect mode when disabling interrupts, we also need
443 * to clear the interrupt bit in the GRC local ctrl register.
444 */
445 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
446 (val == 0x1)) {
447 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
448 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
449 }
450}
451
452static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
453{
454 unsigned long flags;
455 u32 val;
456
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
461 return val;
462}
463
Michael Chanb401e9e2005-12-19 16:27:04 -0800464/* usec_wait specifies the wait time in usec when writing to certain registers
465 * where it is unsafe to read back the register without some delay.
466 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
467 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
468 */
469static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470{
Michael Chanb401e9e2005-12-19 16:27:04 -0800471 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
472 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
473 /* Non-posted methods */
474 tp->write32(tp, off, val);
475 else {
476 /* Posted method */
477 tg3_write32(tp, off, val);
478 if (usec_wait)
479 udelay(usec_wait);
480 tp->read32(tp, off);
481 }
482 /* Wait again after the read for the posted method to guarantee that
483 * the wait time is met.
484 */
485 if (usec_wait)
486 udelay(usec_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487}
488
Michael Chan09ee9292005-08-09 20:17:00 -0700489static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
490{
491 tp->write32_mbox(tp, off, val);
Michael Chan68929142005-08-09 20:17:14 -0700492 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
493 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
494 tp->read32_mbox(tp, off);
Michael Chan09ee9292005-08-09 20:17:00 -0700495}
496
Michael Chan20094932005-08-09 20:16:32 -0700497static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498{
499 void __iomem *mbox = tp->regs + off;
500 writel(val, mbox);
501 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
502 writel(val, mbox);
503 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
504 readl(mbox);
505}
506
Michael Chanb5d37722006-09-27 16:06:21 -0700507static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
508{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000509 return readl(tp->regs + off + GRCMBOX_BASE);
Michael Chanb5d37722006-09-27 16:06:21 -0700510}
511
512static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
513{
514 writel(val, tp->regs + off + GRCMBOX_BASE);
515}
516
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000517#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
Michael Chan09ee9292005-08-09 20:17:00 -0700518#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000519#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
520#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
521#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
Michael Chan20094932005-08-09 20:16:32 -0700522
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000523#define tw32(reg, val) tp->write32(tp, reg, val)
524#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
525#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
526#define tr32(reg) tp->read32(tp, reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527
528static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
529{
Michael Chan68929142005-08-09 20:17:14 -0700530 unsigned long flags;
531
Michael Chanb5d37722006-09-27 16:06:21 -0700532 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
533 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
534 return;
535
Michael Chan68929142005-08-09 20:17:14 -0700536 spin_lock_irqsave(&tp->indirect_lock, flags);
Michael Chanbbadf502006-04-06 21:46:34 -0700537 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
538 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
539 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540
Michael Chanbbadf502006-04-06 21:46:34 -0700541 /* Always leave this as zero. */
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
543 } else {
544 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
545 tw32_f(TG3PCI_MEM_WIN_DATA, val);
546
547 /* Always leave this as zero. */
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
549 }
Michael Chan68929142005-08-09 20:17:14 -0700550 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551}
552
553static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
554{
Michael Chan68929142005-08-09 20:17:14 -0700555 unsigned long flags;
556
Michael Chanb5d37722006-09-27 16:06:21 -0700557 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
558 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
559 *val = 0;
560 return;
561 }
562
Michael Chan68929142005-08-09 20:17:14 -0700563 spin_lock_irqsave(&tp->indirect_lock, flags);
Michael Chanbbadf502006-04-06 21:46:34 -0700564 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
565 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
566 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567
Michael Chanbbadf502006-04-06 21:46:34 -0700568 /* Always leave this as zero. */
569 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
570 } else {
571 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
572 *val = tr32(TG3PCI_MEM_WIN_DATA);
573
574 /* Always leave this as zero. */
575 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
576 }
Michael Chan68929142005-08-09 20:17:14 -0700577 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578}
579
Matt Carlson0d3031d2007-10-10 18:02:43 -0700580static void tg3_ape_lock_init(struct tg3 *tp)
581{
582 int i;
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000583 u32 regbase;
584
585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
586 regbase = TG3_APE_LOCK_GRANT;
587 else
588 regbase = TG3_APE_PER_LOCK_GRANT;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700589
590 /* Make sure the driver hasn't any stale locks. */
591 for (i = 0; i < 8; i++)
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000592 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700593}
594
595static int tg3_ape_lock(struct tg3 *tp, int locknum)
596{
597 int i, off;
598 int ret = 0;
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000599 u32 status, req, gnt;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700600
601 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
602 return 0;
603
604 switch (locknum) {
Matt Carlson33f401a2010-04-05 10:19:27 +0000605 case TG3_APE_LOCK_GRC:
606 case TG3_APE_LOCK_MEM:
607 break;
608 default:
609 return -EINVAL;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700610 }
611
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
613 req = TG3_APE_LOCK_REQ;
614 gnt = TG3_APE_LOCK_GRANT;
615 } else {
616 req = TG3_APE_PER_LOCK_REQ;
617 gnt = TG3_APE_PER_LOCK_GRANT;
618 }
619
Matt Carlson0d3031d2007-10-10 18:02:43 -0700620 off = 4 * locknum;
621
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000622 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700623
624 /* Wait for up to 1 millisecond to acquire lock. */
625 for (i = 0; i < 100; i++) {
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000626 status = tg3_ape_read32(tp, gnt + off);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700627 if (status == APE_LOCK_GRANT_DRIVER)
628 break;
629 udelay(10);
630 }
631
632 if (status != APE_LOCK_GRANT_DRIVER) {
633 /* Revoke the lock request. */
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000634 tg3_ape_write32(tp, gnt + off,
Matt Carlson0d3031d2007-10-10 18:02:43 -0700635 APE_LOCK_GRANT_DRIVER);
636
637 ret = -EBUSY;
638 }
639
640 return ret;
641}
642
643static void tg3_ape_unlock(struct tg3 *tp, int locknum)
644{
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000645 u32 gnt;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700646
647 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
648 return;
649
650 switch (locknum) {
Matt Carlson33f401a2010-04-05 10:19:27 +0000651 case TG3_APE_LOCK_GRC:
652 case TG3_APE_LOCK_MEM:
653 break;
654 default:
655 return;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700656 }
657
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
659 gnt = TG3_APE_LOCK_GRANT;
660 else
661 gnt = TG3_APE_PER_LOCK_GRANT;
662
663 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700664}
665
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666static void tg3_disable_ints(struct tg3 *tp)
667{
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000668 int i;
669
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 tw32(TG3PCI_MISC_HOST_CTRL,
671 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000672 for (i = 0; i < tp->irq_max; i++)
673 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674}
675
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676static void tg3_enable_ints(struct tg3 *tp)
677{
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000678 int i;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000679
Michael Chanbbe832c2005-06-24 20:20:04 -0700680 tp->irq_sync = 0;
681 wmb();
682
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 tw32(TG3PCI_MISC_HOST_CTRL,
684 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000685
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000686 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000687 for (i = 0; i < tp->irq_cnt; i++) {
688 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000689
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000690 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
691 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
692 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
693
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000694 tp->coal_now |= tnapi->coal_now;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000695 }
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000696
697 /* Force an initial interrupt */
698 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
699 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
700 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
701 else
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000702 tw32(HOSTCC_MODE, tp->coal_now);
703
704 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705}
706
Matt Carlson17375d22009-08-28 14:02:18 +0000707static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
Michael Chan04237dd2005-04-25 15:17:17 -0700708{
Matt Carlson17375d22009-08-28 14:02:18 +0000709 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +0000710 struct tg3_hw_status *sblk = tnapi->hw_status;
Michael Chan04237dd2005-04-25 15:17:17 -0700711 unsigned int work_exists = 0;
712
713 /* check for phy events */
714 if (!(tp->tg3_flags &
715 (TG3_FLAG_USE_LINKCHG_REG |
716 TG3_FLAG_POLL_SERDES))) {
717 if (sblk->status & SD_STATUS_LINK_CHG)
718 work_exists = 1;
719 }
720 /* check for RX/TX work to do */
Matt Carlsonf3f3f272009-08-28 14:03:21 +0000721 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
Matt Carlson8d9d7cf2009-09-01 13:19:05 +0000722 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
Michael Chan04237dd2005-04-25 15:17:17 -0700723 work_exists = 1;
724
725 return work_exists;
726}
727
Matt Carlson17375d22009-08-28 14:02:18 +0000728/* tg3_int_reenable
Michael Chan04237dd2005-04-25 15:17:17 -0700729 * similar to tg3_enable_ints, but it accurately determines whether there
730 * is new work pending and can return without flushing the PIO write
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400731 * which reenables interrupts
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 */
Matt Carlson17375d22009-08-28 14:02:18 +0000733static void tg3_int_reenable(struct tg3_napi *tnapi)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734{
Matt Carlson17375d22009-08-28 14:02:18 +0000735 struct tg3 *tp = tnapi->tp;
736
Matt Carlson898a56f2009-08-28 14:02:40 +0000737 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738 mmiowb();
739
David S. Millerfac9b832005-05-18 22:46:34 -0700740 /* When doing tagged status, this work check is unnecessary.
741 * The last_tag we write above tells the chip which piece of
742 * work we've completed.
743 */
744 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
Matt Carlson17375d22009-08-28 14:02:18 +0000745 tg3_has_work(tnapi))
Michael Chan04237dd2005-04-25 15:17:17 -0700746 tw32(HOSTCC_MODE, tp->coalesce_mode |
Matt Carlsonfd2ce372009-09-01 12:51:13 +0000747 HOSTCC_MODE_ENABLE | tnapi->coal_now);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748}
749
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750static void tg3_switch_clocks(struct tg3 *tp)
751{
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000752 u32 clock_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753 u32 orig_clock_ctrl;
754
Matt Carlson795d01c2007-10-07 23:28:17 -0700755 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
756 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
Michael Chan4cf78e42005-07-25 12:29:19 -0700757 return;
758
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000759 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
760
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 orig_clock_ctrl = clock_ctrl;
762 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
763 CLOCK_CTRL_CLKRUN_OENABLE |
764 0x1f);
765 tp->pci_clock_ctrl = clock_ctrl;
766
767 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
768 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
Michael Chanb401e9e2005-12-19 16:27:04 -0800769 tw32_wait_f(TG3PCI_CLOCK_CTRL,
770 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771 }
772 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
Michael Chanb401e9e2005-12-19 16:27:04 -0800773 tw32_wait_f(TG3PCI_CLOCK_CTRL,
774 clock_ctrl |
775 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
776 40);
777 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778 clock_ctrl | (CLOCK_CTRL_ALTCLK),
779 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 }
Michael Chanb401e9e2005-12-19 16:27:04 -0800781 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782}
783
784#define PHY_BUSY_LOOPS 5000
785
786static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
787{
788 u32 frame_val;
789 unsigned int loops;
790 int ret;
791
792 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
793 tw32_f(MAC_MI_MODE,
794 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
795 udelay(80);
796 }
797
798 *val = 0x0;
799
Matt Carlson882e9792009-09-01 13:21:36 +0000800 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 MI_COM_PHY_ADDR_MASK);
802 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
803 MI_COM_REG_ADDR_MASK);
804 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400805
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806 tw32_f(MAC_MI_COM, frame_val);
807
808 loops = PHY_BUSY_LOOPS;
809 while (loops != 0) {
810 udelay(10);
811 frame_val = tr32(MAC_MI_COM);
812
813 if ((frame_val & MI_COM_BUSY) == 0) {
814 udelay(5);
815 frame_val = tr32(MAC_MI_COM);
816 break;
817 }
818 loops -= 1;
819 }
820
821 ret = -EBUSY;
822 if (loops != 0) {
823 *val = frame_val & MI_COM_DATA_MASK;
824 ret = 0;
825 }
826
827 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
828 tw32_f(MAC_MI_MODE, tp->mi_mode);
829 udelay(80);
830 }
831
832 return ret;
833}
834
835static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
836{
837 u32 frame_val;
838 unsigned int loops;
839 int ret;
840
Matt Carlsonf07e9af2010-08-02 11:26:07 +0000841 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
Michael Chanb5d37722006-09-27 16:06:21 -0700842 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
843 return 0;
844
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
846 tw32_f(MAC_MI_MODE,
847 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
848 udelay(80);
849 }
850
Matt Carlson882e9792009-09-01 13:21:36 +0000851 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 MI_COM_PHY_ADDR_MASK);
853 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
854 MI_COM_REG_ADDR_MASK);
855 frame_val |= (val & MI_COM_DATA_MASK);
856 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400857
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 tw32_f(MAC_MI_COM, frame_val);
859
860 loops = PHY_BUSY_LOOPS;
861 while (loops != 0) {
862 udelay(10);
863 frame_val = tr32(MAC_MI_COM);
864 if ((frame_val & MI_COM_BUSY) == 0) {
865 udelay(5);
866 frame_val = tr32(MAC_MI_COM);
867 break;
868 }
869 loops -= 1;
870 }
871
872 ret = -EBUSY;
873 if (loops != 0)
874 ret = 0;
875
876 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
877 tw32_f(MAC_MI_MODE, tp->mi_mode);
878 udelay(80);
879 }
880
881 return ret;
882}
883
Matt Carlsonb0988c12011-04-20 07:57:39 +0000884static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
885{
886 int err;
887
888 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
889 if (err)
890 goto done;
891
892 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
893 if (err)
894 goto done;
895
896 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
897 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
898 if (err)
899 goto done;
900
901 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
902
903done:
904 return err;
905}
906
907static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
908{
909 int err;
910
911 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
912 if (err)
913 goto done;
914
915 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
916 if (err)
917 goto done;
918
919 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
920 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
921 if (err)
922 goto done;
923
924 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
925
926done:
927 return err;
928}
929
930static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
931{
932 int err;
933
934 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
935 if (!err)
936 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
937
938 return err;
939}
940
941static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
942{
943 int err;
944
945 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
946 if (!err)
947 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
948
949 return err;
950}
951
Matt Carlson15ee95c2011-04-20 07:57:40 +0000952static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
953{
954 int err;
955
956 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
957 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
958 MII_TG3_AUXCTL_SHDWSEL_MISC);
959 if (!err)
960 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
961
962 return err;
963}
964
Matt Carlsonb4bd2922011-04-20 07:57:41 +0000965static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
966{
967 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
968 set |= MII_TG3_AUXCTL_MISC_WREN;
969
970 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
971}
972
Matt Carlson95e28692008-05-25 23:44:14 -0700973static int tg3_bmcr_reset(struct tg3 *tp)
974{
975 u32 phy_control;
976 int limit, err;
977
978 /* OK, reset it, and poll the BMCR_RESET bit until it
979 * clears or we time out.
980 */
981 phy_control = BMCR_RESET;
982 err = tg3_writephy(tp, MII_BMCR, phy_control);
983 if (err != 0)
984 return -EBUSY;
985
986 limit = 5000;
987 while (limit--) {
988 err = tg3_readphy(tp, MII_BMCR, &phy_control);
989 if (err != 0)
990 return -EBUSY;
991
992 if ((phy_control & BMCR_RESET) == 0) {
993 udelay(40);
994 break;
995 }
996 udelay(10);
997 }
Roel Kluind4675b52009-02-12 16:33:27 -0800998 if (limit < 0)
Matt Carlson95e28692008-05-25 23:44:14 -0700999 return -EBUSY;
1000
1001 return 0;
1002}
1003
Matt Carlson158d7ab2008-05-29 01:37:54 -07001004static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1005{
Francois Romieu3d165432009-01-19 16:56:50 -08001006 struct tg3 *tp = bp->priv;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001007 u32 val;
1008
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001009 spin_lock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001010
1011 if (tg3_readphy(tp, reg, &val))
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001012 val = -EIO;
1013
1014 spin_unlock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001015
1016 return val;
1017}
1018
1019static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1020{
Francois Romieu3d165432009-01-19 16:56:50 -08001021 struct tg3 *tp = bp->priv;
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001022 u32 ret = 0;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001023
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001024 spin_lock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001025
1026 if (tg3_writephy(tp, reg, val))
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001027 ret = -EIO;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001028
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001029 spin_unlock_bh(&tp->lock);
1030
1031 return ret;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001032}
1033
1034static int tg3_mdio_reset(struct mii_bus *bp)
1035{
1036 return 0;
1037}
1038
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001039static void tg3_mdio_config_5785(struct tg3 *tp)
Matt Carlsona9daf362008-05-25 23:49:44 -07001040{
1041 u32 val;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001042 struct phy_device *phydev;
Matt Carlsona9daf362008-05-25 23:49:44 -07001043
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001044 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001045 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
Matt Carlson6a443a02010-02-17 15:17:04 +00001046 case PHY_ID_BCM50610:
1047 case PHY_ID_BCM50610M:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001048 val = MAC_PHYCFG2_50610_LED_MODES;
1049 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001050 case PHY_ID_BCMAC131:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001051 val = MAC_PHYCFG2_AC131_LED_MODES;
1052 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001053 case PHY_ID_RTL8211C:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001054 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1055 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001056 case PHY_ID_RTL8201E:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001057 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1058 break;
1059 default:
Matt Carlsona9daf362008-05-25 23:49:44 -07001060 return;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001061 }
1062
1063 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1064 tw32(MAC_PHYCFG2, val);
1065
1066 val = tr32(MAC_PHYCFG1);
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001067 val &= ~(MAC_PHYCFG1_RGMII_INT |
1068 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1069 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001070 tw32(MAC_PHYCFG1, val);
1071
1072 return;
1073 }
1074
Matt Carlson14417062010-02-17 15:16:59 +00001075 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001076 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1077 MAC_PHYCFG2_FMODE_MASK_MASK |
1078 MAC_PHYCFG2_GMODE_MASK_MASK |
1079 MAC_PHYCFG2_ACT_MASK_MASK |
1080 MAC_PHYCFG2_QUAL_MASK_MASK |
1081 MAC_PHYCFG2_INBAND_ENABLE;
1082
1083 tw32(MAC_PHYCFG2, val);
Matt Carlsona9daf362008-05-25 23:49:44 -07001084
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001085 val = tr32(MAC_PHYCFG1);
1086 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1087 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
Matt Carlson14417062010-02-17 15:16:59 +00001088 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
Matt Carlsona9daf362008-05-25 23:49:44 -07001089 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1090 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1091 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1092 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1093 }
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001094 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1095 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1096 tw32(MAC_PHYCFG1, val);
Matt Carlsona9daf362008-05-25 23:49:44 -07001097
Matt Carlsona9daf362008-05-25 23:49:44 -07001098 val = tr32(MAC_EXT_RGMII_MODE);
1099 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1100 MAC_RGMII_MODE_RX_QUALITY |
1101 MAC_RGMII_MODE_RX_ACTIVITY |
1102 MAC_RGMII_MODE_RX_ENG_DET |
1103 MAC_RGMII_MODE_TX_ENABLE |
1104 MAC_RGMII_MODE_TX_LOWPWR |
1105 MAC_RGMII_MODE_TX_RESET);
Matt Carlson14417062010-02-17 15:16:59 +00001106 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
Matt Carlsona9daf362008-05-25 23:49:44 -07001107 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1108 val |= MAC_RGMII_MODE_RX_INT_B |
1109 MAC_RGMII_MODE_RX_QUALITY |
1110 MAC_RGMII_MODE_RX_ACTIVITY |
1111 MAC_RGMII_MODE_RX_ENG_DET;
1112 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113 val |= MAC_RGMII_MODE_TX_ENABLE |
1114 MAC_RGMII_MODE_TX_LOWPWR |
1115 MAC_RGMII_MODE_TX_RESET;
1116 }
1117 tw32(MAC_EXT_RGMII_MODE, val);
1118}
1119
Matt Carlson158d7ab2008-05-29 01:37:54 -07001120static void tg3_mdio_start(struct tg3 *tp)
1121{
Matt Carlson158d7ab2008-05-29 01:37:54 -07001122 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1123 tw32_f(MAC_MI_MODE, tp->mi_mode);
1124 udelay(80);
Matt Carlsona9daf362008-05-25 23:49:44 -07001125
Matt Carlson9ea48182010-02-17 15:17:01 +00001126 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1128 tg3_mdio_config_5785(tp);
1129}
1130
1131static int tg3_mdio_init(struct tg3 *tp)
1132{
1133 int i;
1134 u32 reg;
1135 struct phy_device *phydev;
1136
Matt Carlson0a58d662011-04-05 14:22:45 +00001137 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
Matt Carlson9c7df912010-06-05 17:24:36 +00001138 u32 is_serdes;
Matt Carlson882e9792009-09-01 13:21:36 +00001139
Matt Carlson9c7df912010-06-05 17:24:36 +00001140 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
Matt Carlson882e9792009-09-01 13:21:36 +00001141
Matt Carlsond1ec96a2010-01-12 10:11:38 +00001142 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1143 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1144 else
1145 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1146 TG3_CPMU_PHY_STRAP_IS_SERDES;
Matt Carlson882e9792009-09-01 13:21:36 +00001147 if (is_serdes)
1148 tp->phy_addr += 7;
1149 } else
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001150 tp->phy_addr = TG3_PHY_MII_ADDR;
Matt Carlson882e9792009-09-01 13:21:36 +00001151
Matt Carlson158d7ab2008-05-29 01:37:54 -07001152 tg3_mdio_start(tp);
1153
1154 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1155 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1156 return 0;
1157
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001158 tp->mdio_bus = mdiobus_alloc();
1159 if (tp->mdio_bus == NULL)
1160 return -ENOMEM;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001161
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001162 tp->mdio_bus->name = "tg3 mdio bus";
1163 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
Matt Carlson158d7ab2008-05-29 01:37:54 -07001164 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001165 tp->mdio_bus->priv = tp;
1166 tp->mdio_bus->parent = &tp->pdev->dev;
1167 tp->mdio_bus->read = &tg3_mdio_read;
1168 tp->mdio_bus->write = &tg3_mdio_write;
1169 tp->mdio_bus->reset = &tg3_mdio_reset;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001170 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001171 tp->mdio_bus->irq = &tp->mdio_irq[0];
Matt Carlson158d7ab2008-05-29 01:37:54 -07001172
1173 for (i = 0; i < PHY_MAX_ADDR; i++)
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001174 tp->mdio_bus->irq[i] = PHY_POLL;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001175
1176 /* The bus registration will look for all the PHYs on the mdio bus.
1177 * Unfortunately, it does not ensure the PHY is powered up before
1178 * accessing the PHY ID registers. A chip reset is the
1179 * quickest way to bring the device back to an operational state..
1180 */
1181 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1182 tg3_bmcr_reset(tp);
1183
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001184 i = mdiobus_register(tp->mdio_bus);
Matt Carlsona9daf362008-05-25 23:49:44 -07001185 if (i) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001186 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001187 mdiobus_free(tp->mdio_bus);
Matt Carlsona9daf362008-05-25 23:49:44 -07001188 return i;
1189 }
Matt Carlson158d7ab2008-05-29 01:37:54 -07001190
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001191 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsona9daf362008-05-25 23:49:44 -07001192
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001193 if (!phydev || !phydev->drv) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001194 dev_warn(&tp->pdev->dev, "No PHY devices\n");
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001195 mdiobus_unregister(tp->mdio_bus);
1196 mdiobus_free(tp->mdio_bus);
1197 return -ENODEV;
1198 }
1199
1200 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
Matt Carlson6a443a02010-02-17 15:17:04 +00001201 case PHY_ID_BCM57780:
Matt Carlson321d32a2008-11-21 17:22:19 -08001202 phydev->interface = PHY_INTERFACE_MODE_GMII;
Matt Carlsonc704dc22009-11-02 14:32:12 +00001203 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlson321d32a2008-11-21 17:22:19 -08001204 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001205 case PHY_ID_BCM50610:
1206 case PHY_ID_BCM50610M:
Matt Carlson32e5a8d2009-11-02 14:31:39 +00001207 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
Matt Carlsonc704dc22009-11-02 14:32:12 +00001208 PHY_BRCM_RX_REFCLK_UNUSED |
Matt Carlson52fae082009-11-02 14:32:38 +00001209 PHY_BRCM_DIS_TXCRXC_NOENRGY |
Matt Carlsonc704dc22009-11-02 14:32:12 +00001210 PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlson14417062010-02-17 15:16:59 +00001211 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
Matt Carlsona9daf362008-05-25 23:49:44 -07001212 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1213 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1214 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1215 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1216 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001217 /* fallthru */
Matt Carlson6a443a02010-02-17 15:17:04 +00001218 case PHY_ID_RTL8211C:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001219 phydev->interface = PHY_INTERFACE_MODE_RGMII;
Matt Carlsona9daf362008-05-25 23:49:44 -07001220 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001221 case PHY_ID_RTL8201E:
1222 case PHY_ID_BCMAC131:
Matt Carlsona9daf362008-05-25 23:49:44 -07001223 phydev->interface = PHY_INTERFACE_MODE_MII;
Matt Carlsoncdd4e09d2009-11-02 14:31:11 +00001224 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001225 tp->phy_flags |= TG3_PHYFLG_IS_FET;
Matt Carlsona9daf362008-05-25 23:49:44 -07001226 break;
1227 }
1228
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001229 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1230
1231 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1232 tg3_mdio_config_5785(tp);
Matt Carlsona9daf362008-05-25 23:49:44 -07001233
1234 return 0;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001235}
1236
1237static void tg3_mdio_fini(struct tg3 *tp)
1238{
1239 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1240 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001241 mdiobus_unregister(tp->mdio_bus);
1242 mdiobus_free(tp->mdio_bus);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001243 }
1244}
1245
Matt Carlson95e28692008-05-25 23:44:14 -07001246/* tp->lock is held. */
Matt Carlson4ba526c2008-08-15 14:10:04 -07001247static inline void tg3_generate_fw_event(struct tg3 *tp)
1248{
1249 u32 val;
1250
1251 val = tr32(GRC_RX_CPU_EVENT);
1252 val |= GRC_RX_CPU_DRIVER_EVENT;
1253 tw32_f(GRC_RX_CPU_EVENT, val);
1254
1255 tp->last_event_jiffies = jiffies;
1256}
1257
1258#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1259
1260/* tp->lock is held. */
Matt Carlson95e28692008-05-25 23:44:14 -07001261static void tg3_wait_for_event_ack(struct tg3 *tp)
1262{
1263 int i;
Matt Carlson4ba526c2008-08-15 14:10:04 -07001264 unsigned int delay_cnt;
1265 long time_remain;
Matt Carlson95e28692008-05-25 23:44:14 -07001266
Matt Carlson4ba526c2008-08-15 14:10:04 -07001267 /* If enough time has passed, no wait is necessary. */
1268 time_remain = (long)(tp->last_event_jiffies + 1 +
1269 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1270 (long)jiffies;
1271 if (time_remain < 0)
1272 return;
1273
1274 /* Check if we can shorten the wait time. */
1275 delay_cnt = jiffies_to_usecs(time_remain);
1276 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1277 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1278 delay_cnt = (delay_cnt >> 3) + 1;
1279
1280 for (i = 0; i < delay_cnt; i++) {
Matt Carlson95e28692008-05-25 23:44:14 -07001281 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1282 break;
Matt Carlson4ba526c2008-08-15 14:10:04 -07001283 udelay(8);
Matt Carlson95e28692008-05-25 23:44:14 -07001284 }
1285}
1286
1287/* tp->lock is held. */
1288static void tg3_ump_link_report(struct tg3 *tp)
1289{
1290 u32 reg;
1291 u32 val;
1292
1293 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1294 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1295 return;
1296
1297 tg3_wait_for_event_ack(tp);
1298
1299 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1300
1301 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1302
1303 val = 0;
1304 if (!tg3_readphy(tp, MII_BMCR, &reg))
1305 val = reg << 16;
1306 if (!tg3_readphy(tp, MII_BMSR, &reg))
1307 val |= (reg & 0xffff);
1308 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1309
1310 val = 0;
1311 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1312 val = reg << 16;
1313 if (!tg3_readphy(tp, MII_LPA, &reg))
1314 val |= (reg & 0xffff);
1315 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1316
1317 val = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001318 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
Matt Carlson95e28692008-05-25 23:44:14 -07001319 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1320 val = reg << 16;
1321 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1322 val |= (reg & 0xffff);
1323 }
1324 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1325
1326 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1327 val = reg << 16;
1328 else
1329 val = 0;
1330 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1331
Matt Carlson4ba526c2008-08-15 14:10:04 -07001332 tg3_generate_fw_event(tp);
Matt Carlson95e28692008-05-25 23:44:14 -07001333}
1334
1335static void tg3_link_report(struct tg3 *tp)
1336{
1337 if (!netif_carrier_ok(tp->dev)) {
Joe Perches05dbe002010-02-17 19:44:19 +00001338 netif_info(tp, link, tp->dev, "Link is down\n");
Matt Carlson95e28692008-05-25 23:44:14 -07001339 tg3_ump_link_report(tp);
1340 } else if (netif_msg_link(tp)) {
Joe Perches05dbe002010-02-17 19:44:19 +00001341 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1342 (tp->link_config.active_speed == SPEED_1000 ?
1343 1000 :
1344 (tp->link_config.active_speed == SPEED_100 ?
1345 100 : 10)),
1346 (tp->link_config.active_duplex == DUPLEX_FULL ?
1347 "full" : "half"));
Matt Carlson95e28692008-05-25 23:44:14 -07001348
Joe Perches05dbe002010-02-17 19:44:19 +00001349 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1350 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1351 "on" : "off",
1352 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1353 "on" : "off");
Matt Carlson95e28692008-05-25 23:44:14 -07001354 tg3_ump_link_report(tp);
1355 }
1356}
1357
1358static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1359{
1360 u16 miireg;
1361
Steve Glendinninge18ce342008-12-16 02:00:00 -08001362 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
Matt Carlson95e28692008-05-25 23:44:14 -07001363 miireg = ADVERTISE_PAUSE_CAP;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001364 else if (flow_ctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001365 miireg = ADVERTISE_PAUSE_ASYM;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001366 else if (flow_ctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001367 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1368 else
1369 miireg = 0;
1370
1371 return miireg;
1372}
1373
1374static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1375{
1376 u16 miireg;
1377
Steve Glendinninge18ce342008-12-16 02:00:00 -08001378 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
Matt Carlson95e28692008-05-25 23:44:14 -07001379 miireg = ADVERTISE_1000XPAUSE;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001380 else if (flow_ctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001381 miireg = ADVERTISE_1000XPSE_ASYM;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001382 else if (flow_ctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001383 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1384 else
1385 miireg = 0;
1386
1387 return miireg;
1388}
1389
Matt Carlson95e28692008-05-25 23:44:14 -07001390static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1391{
1392 u8 cap = 0;
1393
1394 if (lcladv & ADVERTISE_1000XPAUSE) {
1395 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1396 if (rmtadv & LPA_1000XPAUSE)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001397 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001398 else if (rmtadv & LPA_1000XPAUSE_ASYM)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001399 cap = FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001400 } else {
1401 if (rmtadv & LPA_1000XPAUSE)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001402 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001403 }
1404 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1405 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
Steve Glendinninge18ce342008-12-16 02:00:00 -08001406 cap = FLOW_CTRL_TX;
Matt Carlson95e28692008-05-25 23:44:14 -07001407 }
1408
1409 return cap;
1410}
1411
Matt Carlsonf51f3562008-05-25 23:45:08 -07001412static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
Matt Carlson95e28692008-05-25 23:44:14 -07001413{
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001414 u8 autoneg;
Matt Carlsonf51f3562008-05-25 23:45:08 -07001415 u8 flowctrl = 0;
Matt Carlson95e28692008-05-25 23:44:14 -07001416 u32 old_rx_mode = tp->rx_mode;
1417 u32 old_tx_mode = tp->tx_mode;
1418
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001419 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001420 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001421 else
1422 autoneg = tp->link_config.autoneg;
1423
1424 if (autoneg == AUTONEG_ENABLE &&
Matt Carlson95e28692008-05-25 23:44:14 -07001425 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001426 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Matt Carlsonf51f3562008-05-25 23:45:08 -07001427 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
Matt Carlson95e28692008-05-25 23:44:14 -07001428 else
Steve Glendinningbc02ff92008-12-16 02:00:48 -08001429 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
Matt Carlsonf51f3562008-05-25 23:45:08 -07001430 } else
1431 flowctrl = tp->link_config.flowctrl;
Matt Carlson95e28692008-05-25 23:44:14 -07001432
Matt Carlsonf51f3562008-05-25 23:45:08 -07001433 tp->link_config.active_flowctrl = flowctrl;
Matt Carlson95e28692008-05-25 23:44:14 -07001434
Steve Glendinninge18ce342008-12-16 02:00:00 -08001435 if (flowctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001436 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1437 else
1438 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1439
Matt Carlsonf51f3562008-05-25 23:45:08 -07001440 if (old_rx_mode != tp->rx_mode)
Matt Carlson95e28692008-05-25 23:44:14 -07001441 tw32_f(MAC_RX_MODE, tp->rx_mode);
Matt Carlson95e28692008-05-25 23:44:14 -07001442
Steve Glendinninge18ce342008-12-16 02:00:00 -08001443 if (flowctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001444 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1445 else
1446 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1447
Matt Carlsonf51f3562008-05-25 23:45:08 -07001448 if (old_tx_mode != tp->tx_mode)
Matt Carlson95e28692008-05-25 23:44:14 -07001449 tw32_f(MAC_TX_MODE, tp->tx_mode);
Matt Carlson95e28692008-05-25 23:44:14 -07001450}
1451
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001452static void tg3_adjust_link(struct net_device *dev)
1453{
1454 u8 oldflowctrl, linkmesg = 0;
1455 u32 mac_mode, lcl_adv, rmt_adv;
1456 struct tg3 *tp = netdev_priv(dev);
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001457 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001458
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001459 spin_lock_bh(&tp->lock);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001460
1461 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1462 MAC_MODE_HALF_DUPLEX);
1463
1464 oldflowctrl = tp->link_config.active_flowctrl;
1465
1466 if (phydev->link) {
1467 lcl_adv = 0;
1468 rmt_adv = 0;
1469
1470 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1471 mac_mode |= MAC_MODE_PORT_MODE_MII;
Matt Carlsonc3df0742009-11-02 14:27:02 +00001472 else if (phydev->speed == SPEED_1000 ||
1473 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001474 mac_mode |= MAC_MODE_PORT_MODE_GMII;
Matt Carlsonc3df0742009-11-02 14:27:02 +00001475 else
1476 mac_mode |= MAC_MODE_PORT_MODE_MII;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001477
1478 if (phydev->duplex == DUPLEX_HALF)
1479 mac_mode |= MAC_MODE_HALF_DUPLEX;
1480 else {
1481 lcl_adv = tg3_advert_flowctrl_1000T(
1482 tp->link_config.flowctrl);
1483
1484 if (phydev->pause)
1485 rmt_adv = LPA_PAUSE_CAP;
1486 if (phydev->asym_pause)
1487 rmt_adv |= LPA_PAUSE_ASYM;
1488 }
1489
1490 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1491 } else
1492 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1493
1494 if (mac_mode != tp->mac_mode) {
1495 tp->mac_mode = mac_mode;
1496 tw32_f(MAC_MODE, tp->mac_mode);
1497 udelay(40);
1498 }
1499
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1501 if (phydev->speed == SPEED_10)
1502 tw32(MAC_MI_STAT,
1503 MAC_MI_STAT_10MBPS_MODE |
1504 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1505 else
1506 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1507 }
1508
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001509 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1510 tw32(MAC_TX_LENGTHS,
1511 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1512 (6 << TX_LENGTHS_IPG_SHIFT) |
1513 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1514 else
1515 tw32(MAC_TX_LENGTHS,
1516 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1517 (6 << TX_LENGTHS_IPG_SHIFT) |
1518 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1519
1520 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1521 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1522 phydev->speed != tp->link_config.active_speed ||
1523 phydev->duplex != tp->link_config.active_duplex ||
1524 oldflowctrl != tp->link_config.active_flowctrl)
Matt Carlsonc6cdf432010-04-05 10:19:26 +00001525 linkmesg = 1;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001526
1527 tp->link_config.active_speed = phydev->speed;
1528 tp->link_config.active_duplex = phydev->duplex;
1529
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001530 spin_unlock_bh(&tp->lock);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001531
1532 if (linkmesg)
1533 tg3_link_report(tp);
1534}
1535
1536static int tg3_phy_init(struct tg3 *tp)
1537{
1538 struct phy_device *phydev;
1539
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001540 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001541 return 0;
1542
1543 /* Bring the PHY back to a known state. */
1544 tg3_bmcr_reset(tp);
1545
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001546 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001547
1548 /* Attach the MAC to the PHY. */
Kay Sieversfb28ad352008-11-10 13:55:14 -08001549 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
Matt Carlsona9daf362008-05-25 23:49:44 -07001550 phydev->dev_flags, phydev->interface);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001551 if (IS_ERR(phydev)) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001552 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001553 return PTR_ERR(phydev);
1554 }
1555
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001556 /* Mask with MAC supported features. */
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001557 switch (phydev->interface) {
1558 case PHY_INTERFACE_MODE_GMII:
1559 case PHY_INTERFACE_MODE_RGMII:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001560 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Matt Carlson321d32a2008-11-21 17:22:19 -08001561 phydev->supported &= (PHY_GBIT_FEATURES |
1562 SUPPORTED_Pause |
1563 SUPPORTED_Asym_Pause);
1564 break;
1565 }
1566 /* fallthru */
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001567 case PHY_INTERFACE_MODE_MII:
1568 phydev->supported &= (PHY_BASIC_FEATURES |
1569 SUPPORTED_Pause |
1570 SUPPORTED_Asym_Pause);
1571 break;
1572 default:
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001573 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001574 return -EINVAL;
1575 }
1576
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001577 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001578
1579 phydev->advertising = phydev->supported;
1580
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001581 return 0;
1582}
1583
1584static void tg3_phy_start(struct tg3 *tp)
1585{
1586 struct phy_device *phydev;
1587
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001588 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001589 return;
1590
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001591 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001592
Matt Carlson80096062010-08-02 11:26:06 +00001593 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1594 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001595 phydev->speed = tp->link_config.orig_speed;
1596 phydev->duplex = tp->link_config.orig_duplex;
1597 phydev->autoneg = tp->link_config.orig_autoneg;
1598 phydev->advertising = tp->link_config.orig_advertising;
1599 }
1600
1601 phy_start(phydev);
1602
1603 phy_start_aneg(phydev);
1604}
1605
1606static void tg3_phy_stop(struct tg3 *tp)
1607{
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001608 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001609 return;
1610
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001611 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001612}
1613
1614static void tg3_phy_fini(struct tg3 *tp)
1615{
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001616 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001617 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001618 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001619 }
1620}
1621
Matt Carlson7f97a4b2009-08-25 10:10:03 +00001622static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1623{
1624 u32 phytest;
1625
1626 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1627 u32 phy;
1628
1629 tg3_writephy(tp, MII_TG3_FET_TEST,
1630 phytest | MII_TG3_FET_SHADOW_EN);
1631 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1632 if (enable)
1633 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1634 else
1635 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1636 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1637 }
1638 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1639 }
1640}
1641
Matt Carlson6833c042008-11-21 17:18:59 -08001642static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1643{
1644 u32 reg;
1645
Matt Carlsonecf14102010-01-20 16:58:05 +00001646 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
Matt Carlson0a58d662011-04-05 14:22:45 +00001647 ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001648 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
Matt Carlson6833c042008-11-21 17:18:59 -08001649 return;
1650
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001651 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson7f97a4b2009-08-25 10:10:03 +00001652 tg3_phy_fet_toggle_apd(tp, enable);
1653 return;
1654 }
1655
Matt Carlson6833c042008-11-21 17:18:59 -08001656 reg = MII_TG3_MISC_SHDW_WREN |
1657 MII_TG3_MISC_SHDW_SCR5_SEL |
1658 MII_TG3_MISC_SHDW_SCR5_LPED |
1659 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1660 MII_TG3_MISC_SHDW_SCR5_SDTL |
1661 MII_TG3_MISC_SHDW_SCR5_C125OE;
1662 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1663 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1664
1665 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1666
1667
1668 reg = MII_TG3_MISC_SHDW_WREN |
1669 MII_TG3_MISC_SHDW_APD_SEL |
1670 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1671 if (enable)
1672 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1673
1674 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1675}
1676
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001677static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1678{
1679 u32 phy;
1680
1681 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001682 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001683 return;
1684
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001685 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001686 u32 ephy;
1687
Matt Carlson535ef6e2009-08-25 10:09:36 +00001688 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1689 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1690
1691 tg3_writephy(tp, MII_TG3_FET_TEST,
1692 ephy | MII_TG3_FET_SHADOW_EN);
1693 if (!tg3_readphy(tp, reg, &phy)) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001694 if (enable)
Matt Carlson535ef6e2009-08-25 10:09:36 +00001695 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001696 else
Matt Carlson535ef6e2009-08-25 10:09:36 +00001697 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1698 tg3_writephy(tp, reg, phy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001699 }
Matt Carlson535ef6e2009-08-25 10:09:36 +00001700 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001701 }
1702 } else {
Matt Carlson15ee95c2011-04-20 07:57:40 +00001703 int ret;
1704
1705 ret = tg3_phy_auxctl_read(tp,
1706 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
1707 if (!ret) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001708 if (enable)
1709 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1710 else
1711 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
Matt Carlsonb4bd2922011-04-20 07:57:41 +00001712 tg3_phy_auxctl_write(tp,
1713 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001714 }
1715 }
1716}
1717
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718static void tg3_phy_set_wirespeed(struct tg3 *tp)
1719{
Matt Carlson15ee95c2011-04-20 07:57:40 +00001720 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721 u32 val;
1722
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001723 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724 return;
1725
Matt Carlson15ee95c2011-04-20 07:57:40 +00001726 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
1727 if (!ret)
Matt Carlsonb4bd2922011-04-20 07:57:41 +00001728 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
1729 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001730}
1731
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001732static void tg3_phy_apply_otp(struct tg3 *tp)
1733{
1734 u32 otp, phy;
1735
1736 if (!tp->phy_otp)
1737 return;
1738
1739 otp = tp->phy_otp;
1740
1741 /* Enable SM_DSP clock and tx 6dB coding. */
1742 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1743 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1744 MII_TG3_AUXCTL_ACTL_TX_6DB;
1745 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1746
1747 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1748 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1749 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1750
1751 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1752 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1753 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1754
1755 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1756 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1757 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1758
1759 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1760 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1761
1762 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1763 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1764
1765 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1766 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1767 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1768
1769 /* Turn off SM_DSP clock. */
1770 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1771 MII_TG3_AUXCTL_ACTL_TX_6DB;
1772 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1773}
1774
Matt Carlson52b02d02010-10-14 10:37:41 +00001775static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1776{
1777 u32 val;
1778
1779 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1780 return;
1781
1782 tp->setlpicnt = 0;
1783
1784 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1785 current_link_up == 1 &&
Matt Carlsona6b68da2010-12-06 08:28:52 +00001786 tp->link_config.active_duplex == DUPLEX_FULL &&
1787 (tp->link_config.active_speed == SPEED_100 ||
1788 tp->link_config.active_speed == SPEED_1000)) {
Matt Carlson52b02d02010-10-14 10:37:41 +00001789 u32 eeectl;
1790
1791 if (tp->link_config.active_speed == SPEED_1000)
1792 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1793 else
1794 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1795
1796 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1797
Matt Carlson3110f5f52010-12-06 08:28:50 +00001798 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1799 TG3_CL45_D7_EEERES_STAT, &val);
Matt Carlson52b02d02010-10-14 10:37:41 +00001800
Matt Carlson21a00ab2011-01-25 15:58:55 +00001801 switch (val) {
1802 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1803 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1804 case ASIC_REV_5717:
1805 case ASIC_REV_5719:
1806 case ASIC_REV_57765:
1807 /* Enable SM_DSP clock and tx 6dB coding. */
1808 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1809 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1810 MII_TG3_AUXCTL_ACTL_TX_6DB;
1811 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1812
1813 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1814
1815 /* Turn off SM_DSP clock. */
1816 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1817 MII_TG3_AUXCTL_ACTL_TX_6DB;
1818 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1819 }
1820 /* Fallthrough */
1821 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
Matt Carlson52b02d02010-10-14 10:37:41 +00001822 tp->setlpicnt = 2;
Matt Carlson21a00ab2011-01-25 15:58:55 +00001823 }
Matt Carlson52b02d02010-10-14 10:37:41 +00001824 }
1825
1826 if (!tp->setlpicnt) {
1827 val = tr32(TG3_CPMU_EEE_MODE);
1828 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1829 }
1830}
1831
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832static int tg3_wait_macro_done(struct tg3 *tp)
1833{
1834 int limit = 100;
1835
1836 while (limit--) {
1837 u32 tmp32;
1838
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001839 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001840 if ((tmp32 & 0x1000) == 0)
1841 break;
1842 }
1843 }
Roel Kluind4675b52009-02-12 16:33:27 -08001844 if (limit < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845 return -EBUSY;
1846
1847 return 0;
1848}
1849
1850static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1851{
1852 static const u32 test_pat[4][6] = {
1853 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1854 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1855 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1856 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1857 };
1858 int chan;
1859
1860 for (chan = 0; chan < 4; chan++) {
1861 int i;
1862
1863 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1864 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001865 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866
1867 for (i = 0; i < 6; i++)
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1869 test_pat[chan][i]);
1870
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001871 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872 if (tg3_wait_macro_done(tp)) {
1873 *resetp = 1;
1874 return -EBUSY;
1875 }
1876
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1878 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001879 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880 if (tg3_wait_macro_done(tp)) {
1881 *resetp = 1;
1882 return -EBUSY;
1883 }
1884
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001885 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886 if (tg3_wait_macro_done(tp)) {
1887 *resetp = 1;
1888 return -EBUSY;
1889 }
1890
1891 for (i = 0; i < 6; i += 2) {
1892 u32 low, high;
1893
1894 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1895 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1896 tg3_wait_macro_done(tp)) {
1897 *resetp = 1;
1898 return -EBUSY;
1899 }
1900 low &= 0x7fff;
1901 high &= 0x000f;
1902 if (low != test_pat[chan][i] ||
1903 high != test_pat[chan][i+1]) {
1904 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1905 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1906 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1907
1908 return -EBUSY;
1909 }
1910 }
1911 }
1912
1913 return 0;
1914}
1915
1916static int tg3_phy_reset_chanpat(struct tg3 *tp)
1917{
1918 int chan;
1919
1920 for (chan = 0; chan < 4; chan++) {
1921 int i;
1922
1923 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1924 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001925 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926 for (i = 0; i < 6; i++)
1927 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001928 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929 if (tg3_wait_macro_done(tp))
1930 return -EBUSY;
1931 }
1932
1933 return 0;
1934}
1935
1936static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1937{
1938 u32 reg32, phy9_orig;
1939 int retries, do_phy_reset, err;
1940
1941 retries = 10;
1942 do_phy_reset = 1;
1943 do {
1944 if (do_phy_reset) {
1945 err = tg3_bmcr_reset(tp);
1946 if (err)
1947 return err;
1948 do_phy_reset = 0;
1949 }
1950
1951 /* Disable transmitter and interrupt. */
1952 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1953 continue;
1954
1955 reg32 |= 0x3000;
1956 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1957
1958 /* Set full-duplex, 1000 mbps. */
1959 tg3_writephy(tp, MII_BMCR,
1960 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1961
1962 /* Set to master mode. */
1963 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1964 continue;
1965
1966 tg3_writephy(tp, MII_TG3_CTRL,
1967 (MII_TG3_CTRL_AS_MASTER |
1968 MII_TG3_CTRL_ENABLE_AS_MASTER));
1969
1970 /* Enable SM_DSP_CLOCK and 6dB. */
1971 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972
1973 /* Block the PHY control access. */
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00001974 tg3_phydsp_write(tp, 0x8005, 0x0800);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001975
1976 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1977 if (!err)
1978 break;
1979 } while (--retries);
1980
1981 err = tg3_phy_reset_chanpat(tp);
1982 if (err)
1983 return err;
1984
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00001985 tg3_phydsp_write(tp, 0x8005, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001986
1987 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001988 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989
1990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1992 /* Set Extended packet length bit for jumbo frames */
1993 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
Matt Carlson859a588792010-04-05 10:19:28 +00001994 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001995 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1996 }
1997
1998 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1999
2000 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2001 reg32 &= ~0x3000;
2002 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2003 } else if (!err)
2004 err = -EBUSY;
2005
2006 return err;
2007}
2008
2009/* This will reset the tigon3 PHY if there is no valid
2010 * link unless the FORCE argument is non-zero.
2011 */
2012static int tg3_phy_reset(struct tg3 *tp)
2013{
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002014 u32 val, cpmuctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002015 int err;
2016
Michael Chan60189dd2006-12-17 17:08:07 -08002017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan60189dd2006-12-17 17:08:07 -08002018 val = tr32(GRC_MISC_CFG);
2019 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2020 udelay(40);
2021 }
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002022 err = tg3_readphy(tp, MII_BMSR, &val);
2023 err |= tg3_readphy(tp, MII_BMSR, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002024 if (err != 0)
2025 return -EBUSY;
2026
Michael Chanc8e1e822006-04-29 18:55:17 -07002027 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2028 netif_carrier_off(tp->dev);
2029 tg3_link_report(tp);
2030 }
2031
Linus Torvalds1da177e2005-04-16 15:20:36 -07002032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2035 err = tg3_phy_reset_5703_4_5(tp);
2036 if (err)
2037 return err;
2038 goto out;
2039 }
2040
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002041 cpmuctrl = 0;
2042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2043 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2044 cpmuctrl = tr32(TG3_CPMU_CTRL);
2045 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2046 tw32(TG3_CPMU_CTRL,
2047 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2048 }
2049
Linus Torvalds1da177e2005-04-16 15:20:36 -07002050 err = tg3_bmcr_reset(tp);
2051 if (err)
2052 return err;
2053
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002054 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002055 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2056 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002057
2058 tw32(TG3_CPMU_CTRL, cpmuctrl);
2059 }
2060
Matt Carlsonbcb37f62008-11-03 16:52:09 -08002061 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2062 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
Matt Carlsonce057f02007-11-12 21:08:03 -08002063 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2064 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2065 CPMU_LSPD_1000MB_MACCLK_12_5) {
2066 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2067 udelay(40);
2068 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2069 }
2070 }
2071
Matt Carlson0a58d662011-04-05 14:22:45 +00002072 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002073 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
Matt Carlsonecf14102010-01-20 16:58:05 +00002074 return 0;
2075
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002076 tg3_phy_apply_otp(tp);
2077
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002078 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
Matt Carlson6833c042008-11-21 17:18:59 -08002079 tg3_phy_toggle_apd(tp, true);
2080 else
2081 tg3_phy_toggle_apd(tp, false);
2082
Linus Torvalds1da177e2005-04-16 15:20:36 -07002083out:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002084 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002085 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002086 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2087 tg3_phydsp_write(tp, 0x000a, 0x0323);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002088 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2089 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002090 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002091 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2092 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002093 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002094 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002095 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002096 tg3_phydsp_write(tp, 0x000a, 0x310b);
2097 tg3_phydsp_write(tp, 0x201f, 0x9506);
2098 tg3_phydsp_write(tp, 0x401f, 0x14e2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002099 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002100 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
Michael Chanc424cb22006-04-29 18:56:34 -07002101 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2102 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002103 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
Michael Chanc1d2a192007-01-08 19:57:20 -08002104 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2105 tg3_writephy(tp, MII_TG3_TEST1,
2106 MII_TG3_TEST1_TRIM_EN | 0x4);
2107 } else
2108 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
Michael Chanc424cb22006-04-29 18:56:34 -07002109 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2110 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002111 /* Set Extended packet length bit (bit 14) on all chips that */
2112 /* support jumbo frames */
Matt Carlson79eb6902010-02-17 15:17:03 +00002113 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002114 /* Cannot do read-modify-write on 5401 */
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002115 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
Matt Carlson8f666b02009-08-28 13:58:24 +00002116 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002117 /* Set bit 14 with read-modify-write to preserve other bits */
Matt Carlson15ee95c2011-04-20 07:57:40 +00002118 err = tg3_phy_auxctl_read(tp,
2119 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2120 if (!err)
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002121 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2122 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002123 }
2124
2125 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2126 * jumbo frames transmission.
2127 */
Matt Carlson8f666b02009-08-28 13:58:24 +00002128 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002129 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
Matt Carlsonc6cdf432010-04-05 10:19:26 +00002130 tg3_writephy(tp, MII_TG3_EXT_CTRL,
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002131 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002132 }
2133
Michael Chan715116a2006-09-27 16:09:25 -07002134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan715116a2006-09-27 16:09:25 -07002135 /* adjust output voltage */
Matt Carlson535ef6e2009-08-25 10:09:36 +00002136 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
Michael Chan715116a2006-09-27 16:09:25 -07002137 }
2138
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002139 tg3_phy_toggle_automdix(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002140 tg3_phy_set_wirespeed(tp);
2141 return 0;
2142}
2143
2144static void tg3_frob_aux_power(struct tg3 *tp)
2145{
Matt Carlson683644b2011-03-09 16:58:23 +00002146 bool need_vaux = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002147
Matt Carlson334355a2010-01-20 16:58:10 +00002148 /* The GPIOs do something completely different on 57765. */
2149 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
Matt Carlsona50d0792010-06-05 17:24:37 +00002150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
Matt Carlson334355a2010-01-20 16:58:10 +00002151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002152 return;
2153
Matt Carlson683644b2011-03-09 16:58:23 +00002154 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2155 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
Matt Carlsond78b59f2011-04-05 14:22:46 +00002156 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
Matt Carlson683644b2011-03-09 16:58:23 +00002158 tp->pdev_peer != tp->pdev) {
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002159 struct net_device *dev_peer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002160
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002161 dev_peer = pci_get_drvdata(tp->pdev_peer);
Matt Carlson683644b2011-03-09 16:58:23 +00002162
Michael Chanbc1c7562006-03-20 17:48:03 -08002163 /* remove_one() may have been run on the peer. */
Matt Carlson683644b2011-03-09 16:58:23 +00002164 if (dev_peer) {
2165 struct tg3 *tp_peer = netdev_priv(dev_peer);
2166
2167 if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2168 return;
2169
2170 if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2171 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2172 need_vaux = true;
2173 }
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002174 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002175
Matt Carlson683644b2011-03-09 16:58:23 +00002176 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2177 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2178 need_vaux = true;
2179
2180 if (need_vaux) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2182 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
Michael Chanb401e9e2005-12-19 16:27:04 -08002183 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2184 (GRC_LCLCTRL_GPIO_OE0 |
2185 GRC_LCLCTRL_GPIO_OE1 |
2186 GRC_LCLCTRL_GPIO_OE2 |
2187 GRC_LCLCTRL_GPIO_OUTPUT0 |
2188 GRC_LCLCTRL_GPIO_OUTPUT1),
2189 100);
Matt Carlson8d519ab2009-04-20 06:58:01 +00002190 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2191 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
Matt Carlson5f0c4a32008-06-09 15:41:12 -07002192 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2193 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2194 GRC_LCLCTRL_GPIO_OE1 |
2195 GRC_LCLCTRL_GPIO_OE2 |
2196 GRC_LCLCTRL_GPIO_OUTPUT0 |
2197 GRC_LCLCTRL_GPIO_OUTPUT1 |
2198 tp->grc_local_ctrl;
2199 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2200
2201 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2202 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2203
2204 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2205 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002206 } else {
2207 u32 no_gpio2;
Michael Chandc56b7d2005-12-19 16:26:28 -08002208 u32 grc_local_ctrl = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002209
Michael Chandc56b7d2005-12-19 16:26:28 -08002210 /* Workaround to prevent overdrawing Amps. */
2211 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2212 ASIC_REV_5714) {
2213 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
Michael Chanb401e9e2005-12-19 16:27:04 -08002214 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215 grc_local_ctrl, 100);
Michael Chandc56b7d2005-12-19 16:26:28 -08002216 }
2217
Linus Torvalds1da177e2005-04-16 15:20:36 -07002218 /* On 5753 and variants, GPIO2 cannot be used. */
2219 no_gpio2 = tp->nic_sram_data_cfg &
2220 NIC_SRAM_DATA_CFG_NO_GPIO2;
2221
Michael Chandc56b7d2005-12-19 16:26:28 -08002222 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
Linus Torvalds1da177e2005-04-16 15:20:36 -07002223 GRC_LCLCTRL_GPIO_OE1 |
2224 GRC_LCLCTRL_GPIO_OE2 |
2225 GRC_LCLCTRL_GPIO_OUTPUT1 |
2226 GRC_LCLCTRL_GPIO_OUTPUT2;
2227 if (no_gpio2) {
2228 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2229 GRC_LCLCTRL_GPIO_OUTPUT2);
2230 }
Michael Chanb401e9e2005-12-19 16:27:04 -08002231 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2232 grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002233
2234 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2235
Michael Chanb401e9e2005-12-19 16:27:04 -08002236 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2237 grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002238
2239 if (!no_gpio2) {
2240 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
Michael Chanb401e9e2005-12-19 16:27:04 -08002241 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2242 grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002243 }
2244 }
2245 } else {
2246 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2247 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
Michael Chanb401e9e2005-12-19 16:27:04 -08002248 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2249 (GRC_LCLCTRL_GPIO_OE1 |
2250 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002251
Michael Chanb401e9e2005-12-19 16:27:04 -08002252 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2253 GRC_LCLCTRL_GPIO_OE1, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002254
Michael Chanb401e9e2005-12-19 16:27:04 -08002255 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2256 (GRC_LCLCTRL_GPIO_OE1 |
2257 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002258 }
2259 }
2260}
2261
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002262static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2263{
2264 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2265 return 1;
Matt Carlson79eb6902010-02-17 15:17:03 +00002266 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002267 if (speed != SPEED_10)
2268 return 1;
2269 } else if (speed == SPEED_10)
2270 return 1;
2271
2272 return 0;
2273}
2274
Linus Torvalds1da177e2005-04-16 15:20:36 -07002275static int tg3_setup_phy(struct tg3 *, int);
2276
2277#define RESET_KIND_SHUTDOWN 0
2278#define RESET_KIND_INIT 1
2279#define RESET_KIND_SUSPEND 2
2280
2281static void tg3_write_sig_post_reset(struct tg3 *, int);
2282static int tg3_halt_cpu(struct tg3 *, u32);
2283
Matt Carlson0a459aa2008-11-03 16:54:15 -08002284static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
Michael Chan15c3b692006-03-22 01:06:52 -08002285{
Matt Carlsonce057f02007-11-12 21:08:03 -08002286 u32 val;
2287
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002288 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Michael Chan51297242007-02-13 12:17:57 -08002289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2290 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2291 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2292
2293 sg_dig_ctrl |=
2294 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2295 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2296 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2297 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002298 return;
Michael Chan51297242007-02-13 12:17:57 -08002299 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002300
Michael Chan60189dd2006-12-17 17:08:07 -08002301 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan60189dd2006-12-17 17:08:07 -08002302 tg3_bmcr_reset(tp);
2303 val = tr32(GRC_MISC_CFG);
2304 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2305 udelay(40);
2306 return;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002307 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson0e5f7842009-11-02 14:26:38 +00002308 u32 phytest;
2309 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2310 u32 phy;
2311
2312 tg3_writephy(tp, MII_ADVERTISE, 0);
2313 tg3_writephy(tp, MII_BMCR,
2314 BMCR_ANENABLE | BMCR_ANRESTART);
2315
2316 tg3_writephy(tp, MII_TG3_FET_TEST,
2317 phytest | MII_TG3_FET_SHADOW_EN);
2318 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2319 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2320 tg3_writephy(tp,
2321 MII_TG3_FET_SHDW_AUXMODE4,
2322 phy);
2323 }
2324 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2325 }
2326 return;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002327 } else if (do_low_power) {
Michael Chan715116a2006-09-27 16:09:25 -07002328 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2329 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
Matt Carlson0a459aa2008-11-03 16:54:15 -08002330
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002331 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2332 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2333 MII_TG3_AUXCTL_PCTL_VREG_11V;
2334 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
Michael Chan715116a2006-09-27 16:09:25 -07002335 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002336
Michael Chan15c3b692006-03-22 01:06:52 -08002337 /* The PHY should not be powered down on some chips because
2338 * of bugs.
2339 */
2340 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2341 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2342 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002343 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
Michael Chan15c3b692006-03-22 01:06:52 -08002344 return;
Matt Carlsonce057f02007-11-12 21:08:03 -08002345
Matt Carlsonbcb37f62008-11-03 16:52:09 -08002346 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2347 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
Matt Carlsonce057f02007-11-12 21:08:03 -08002348 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2349 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2350 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2351 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2352 }
2353
Michael Chan15c3b692006-03-22 01:06:52 -08002354 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2355}
2356
Matt Carlson3f007892008-11-03 16:51:36 -08002357/* tp->lock is held. */
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002358static int tg3_nvram_lock(struct tg3 *tp)
2359{
2360 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2361 int i;
2362
2363 if (tp->nvram_lock_cnt == 0) {
2364 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2365 for (i = 0; i < 8000; i++) {
2366 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2367 break;
2368 udelay(20);
2369 }
2370 if (i == 8000) {
2371 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2372 return -ENODEV;
2373 }
2374 }
2375 tp->nvram_lock_cnt++;
2376 }
2377 return 0;
2378}
2379
2380/* tp->lock is held. */
2381static void tg3_nvram_unlock(struct tg3 *tp)
2382{
2383 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2384 if (tp->nvram_lock_cnt > 0)
2385 tp->nvram_lock_cnt--;
2386 if (tp->nvram_lock_cnt == 0)
2387 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2388 }
2389}
2390
2391/* tp->lock is held. */
2392static void tg3_enable_nvram_access(struct tg3 *tp)
2393{
2394 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
Matt Carlsonf66a29b2009-11-13 13:03:36 +00002395 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002396 u32 nvaccess = tr32(NVRAM_ACCESS);
2397
2398 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2399 }
2400}
2401
2402/* tp->lock is held. */
2403static void tg3_disable_nvram_access(struct tg3 *tp)
2404{
2405 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
Matt Carlsonf66a29b2009-11-13 13:03:36 +00002406 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002407 u32 nvaccess = tr32(NVRAM_ACCESS);
2408
2409 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2410 }
2411}
2412
2413static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2414 u32 offset, u32 *val)
2415{
2416 u32 tmp;
2417 int i;
2418
2419 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2420 return -EINVAL;
2421
2422 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2423 EEPROM_ADDR_DEVID_MASK |
2424 EEPROM_ADDR_READ);
2425 tw32(GRC_EEPROM_ADDR,
2426 tmp |
2427 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2428 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2429 EEPROM_ADDR_ADDR_MASK) |
2430 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2431
2432 for (i = 0; i < 1000; i++) {
2433 tmp = tr32(GRC_EEPROM_ADDR);
2434
2435 if (tmp & EEPROM_ADDR_COMPLETE)
2436 break;
2437 msleep(1);
2438 }
2439 if (!(tmp & EEPROM_ADDR_COMPLETE))
2440 return -EBUSY;
2441
Matt Carlson62cedd12009-04-20 14:52:29 -07002442 tmp = tr32(GRC_EEPROM_DATA);
2443
2444 /*
2445 * The data will always be opposite the native endian
2446 * format. Perform a blind byteswap to compensate.
2447 */
2448 *val = swab32(tmp);
2449
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002450 return 0;
2451}
2452
2453#define NVRAM_CMD_TIMEOUT 10000
2454
2455static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2456{
2457 int i;
2458
2459 tw32(NVRAM_CMD, nvram_cmd);
2460 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2461 udelay(10);
2462 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2463 udelay(10);
2464 break;
2465 }
2466 }
2467
2468 if (i == NVRAM_CMD_TIMEOUT)
2469 return -EBUSY;
2470
2471 return 0;
2472}
2473
2474static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2475{
2476 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2477 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2478 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2479 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2480 (tp->nvram_jedecnum == JEDEC_ATMEL))
2481
2482 addr = ((addr / tp->nvram_pagesize) <<
2483 ATMEL_AT45DB0X1B_PAGE_POS) +
2484 (addr % tp->nvram_pagesize);
2485
2486 return addr;
2487}
2488
2489static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2490{
2491 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2492 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2493 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2494 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2495 (tp->nvram_jedecnum == JEDEC_ATMEL))
2496
2497 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2498 tp->nvram_pagesize) +
2499 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2500
2501 return addr;
2502}
2503
Matt Carlsone4f34112009-02-25 14:25:00 +00002504/* NOTE: Data read in from NVRAM is byteswapped according to
2505 * the byteswapping settings for all other register accesses.
2506 * tg3 devices are BE devices, so on a BE machine, the data
2507 * returned will be exactly as it is seen in NVRAM. On a LE
2508 * machine, the 32-bit value will be byteswapped.
2509 */
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002510static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2511{
2512 int ret;
2513
2514 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2515 return tg3_nvram_read_using_eeprom(tp, offset, val);
2516
2517 offset = tg3_nvram_phys_addr(tp, offset);
2518
2519 if (offset > NVRAM_ADDR_MSK)
2520 return -EINVAL;
2521
2522 ret = tg3_nvram_lock(tp);
2523 if (ret)
2524 return ret;
2525
2526 tg3_enable_nvram_access(tp);
2527
2528 tw32(NVRAM_ADDR, offset);
2529 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2530 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2531
2532 if (ret == 0)
Matt Carlsone4f34112009-02-25 14:25:00 +00002533 *val = tr32(NVRAM_RDDATA);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002534
2535 tg3_disable_nvram_access(tp);
2536
2537 tg3_nvram_unlock(tp);
2538
2539 return ret;
2540}
2541
Matt Carlsona9dc5292009-02-25 14:25:30 +00002542/* Ensures NVRAM data is in bytestream format. */
2543static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002544{
2545 u32 v;
Matt Carlsona9dc5292009-02-25 14:25:30 +00002546 int res = tg3_nvram_read(tp, offset, &v);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002547 if (!res)
Matt Carlsona9dc5292009-02-25 14:25:30 +00002548 *val = cpu_to_be32(v);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002549 return res;
2550}
2551
2552/* tp->lock is held. */
Matt Carlson3f007892008-11-03 16:51:36 -08002553static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2554{
2555 u32 addr_high, addr_low;
2556 int i;
2557
2558 addr_high = ((tp->dev->dev_addr[0] << 8) |
2559 tp->dev->dev_addr[1]);
2560 addr_low = ((tp->dev->dev_addr[2] << 24) |
2561 (tp->dev->dev_addr[3] << 16) |
2562 (tp->dev->dev_addr[4] << 8) |
2563 (tp->dev->dev_addr[5] << 0));
2564 for (i = 0; i < 4; i++) {
2565 if (i == 1 && skip_mac_1)
2566 continue;
2567 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2568 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2569 }
2570
2571 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2573 for (i = 0; i < 12; i++) {
2574 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2575 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2576 }
2577 }
2578
2579 addr_high = (tp->dev->dev_addr[0] +
2580 tp->dev->dev_addr[1] +
2581 tp->dev->dev_addr[2] +
2582 tp->dev->dev_addr[3] +
2583 tp->dev->dev_addr[4] +
2584 tp->dev->dev_addr[5]) &
2585 TX_BACKOFF_SEED_MASK;
2586 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2587}
2588
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00002589static void tg3_enable_register_access(struct tg3 *tp)
2590{
2591 /*
2592 * Make sure register accesses (indirect or otherwise) will function
2593 * correctly.
2594 */
2595 pci_write_config_dword(tp->pdev,
2596 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2597}
2598
2599static int tg3_power_up(struct tg3 *tp)
2600{
2601 tg3_enable_register_access(tp);
2602
2603 pci_set_power_state(tp->pdev, PCI_D0);
2604
2605 /* Switch out of Vaux if it is a NIC */
2606 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2607 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2608
2609 return 0;
2610}
2611
2612static int tg3_power_down_prepare(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002613{
2614 u32 misc_host_ctrl;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002615 bool device_should_wake, do_low_power;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002616
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00002617 tg3_enable_register_access(tp);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08002618
2619 /* Restore the CLKREQ setting. */
2620 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2621 u16 lnkctl;
2622
2623 pci_read_config_word(tp->pdev,
2624 tp->pcie_cap + PCI_EXP_LNKCTL,
2625 &lnkctl);
2626 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2627 pci_write_config_word(tp->pdev,
2628 tp->pcie_cap + PCI_EXP_LNKCTL,
2629 lnkctl);
2630 }
2631
Linus Torvalds1da177e2005-04-16 15:20:36 -07002632 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2633 tw32(TG3PCI_MISC_HOST_CTRL,
2634 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2635
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00002636 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002637 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2638
Matt Carlsondd477002008-05-25 23:45:58 -07002639 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson0a459aa2008-11-03 16:54:15 -08002640 do_low_power = false;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002641 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
Matt Carlson80096062010-08-02 11:26:06 +00002642 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002643 struct phy_device *phydev;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002644 u32 phyid, advertising;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002645
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00002646 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002647
Matt Carlson80096062010-08-02 11:26:06 +00002648 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002649
2650 tp->link_config.orig_speed = phydev->speed;
2651 tp->link_config.orig_duplex = phydev->duplex;
2652 tp->link_config.orig_autoneg = phydev->autoneg;
2653 tp->link_config.orig_advertising = phydev->advertising;
2654
2655 advertising = ADVERTISED_TP |
2656 ADVERTISED_Pause |
2657 ADVERTISED_Autoneg |
2658 ADVERTISED_10baseT_Half;
2659
2660 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002661 device_should_wake) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002662 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2663 advertising |=
2664 ADVERTISED_100baseT_Half |
2665 ADVERTISED_100baseT_Full |
2666 ADVERTISED_10baseT_Full;
2667 else
2668 advertising |= ADVERTISED_10baseT_Full;
2669 }
2670
2671 phydev->advertising = advertising;
2672
2673 phy_start_aneg(phydev);
Matt Carlson0a459aa2008-11-03 16:54:15 -08002674
2675 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
Matt Carlson6a443a02010-02-17 15:17:04 +00002676 if (phyid != PHY_ID_BCMAC131) {
2677 phyid &= PHY_BCM_OUI_MASK;
2678 if (phyid == PHY_BCM_OUI_1 ||
2679 phyid == PHY_BCM_OUI_2 ||
2680 phyid == PHY_BCM_OUI_3)
Matt Carlson0a459aa2008-11-03 16:54:15 -08002681 do_low_power = true;
2682 }
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002683 }
Matt Carlsondd477002008-05-25 23:45:58 -07002684 } else {
Matt Carlson20232762008-12-21 20:18:56 -08002685 do_low_power = true;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002686
Matt Carlson80096062010-08-02 11:26:06 +00002687 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2688 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsondd477002008-05-25 23:45:58 -07002689 tp->link_config.orig_speed = tp->link_config.speed;
2690 tp->link_config.orig_duplex = tp->link_config.duplex;
2691 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2692 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002693
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002694 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
Matt Carlsondd477002008-05-25 23:45:58 -07002695 tp->link_config.speed = SPEED_10;
2696 tp->link_config.duplex = DUPLEX_HALF;
2697 tp->link_config.autoneg = AUTONEG_ENABLE;
2698 tg3_setup_phy(tp, 0);
2699 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002700 }
2701
Michael Chanb5d37722006-09-27 16:06:21 -07002702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2703 u32 val;
2704
2705 val = tr32(GRC_VCPU_EXT_CTRL);
2706 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2707 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
Michael Chan6921d202005-12-13 21:15:53 -08002708 int i;
2709 u32 val;
2710
2711 for (i = 0; i < 200; i++) {
2712 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2713 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2714 break;
2715 msleep(1);
2716 }
2717 }
Gary Zambranoa85feb82007-05-05 11:52:19 -07002718 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2719 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2720 WOL_DRV_STATE_SHUTDOWN |
2721 WOL_DRV_WOL |
2722 WOL_SET_MAGIC_PKT);
Michael Chan6921d202005-12-13 21:15:53 -08002723
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002724 if (device_should_wake) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002725 u32 mac_mode;
2726
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002727 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002728 if (do_low_power &&
2729 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
2730 tg3_phy_auxctl_write(tp,
2731 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
2732 MII_TG3_AUXCTL_PCTL_WOL_EN |
2733 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2734 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
Matt Carlsondd477002008-05-25 23:45:58 -07002735 udelay(40);
2736 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002737
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002738 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chan3f7045c2006-09-27 16:02:29 -07002739 mac_mode = MAC_MODE_PORT_MODE_GMII;
2740 else
2741 mac_mode = MAC_MODE_PORT_MODE_MII;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002742
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002743 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2744 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2745 ASIC_REV_5700) {
2746 u32 speed = (tp->tg3_flags &
2747 TG3_FLAG_WOL_SPEED_100MB) ?
2748 SPEED_100 : SPEED_10;
2749 if (tg3_5700_link_polarity(tp, speed))
2750 mac_mode |= MAC_MODE_LINK_POLARITY;
2751 else
2752 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2753 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002754 } else {
2755 mac_mode = MAC_MODE_PORT_MODE_TBI;
2756 }
2757
John W. Linvillecbf46852005-04-21 17:01:29 -07002758 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002759 tw32(MAC_LED_CTRL, tp->led_ctrl);
2760
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002761 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2762 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2763 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2764 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2765 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2766 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002767
Matt Carlsond2394e6b2010-11-24 08:31:47 +00002768 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2769 mac_mode |= MAC_MODE_APE_TX_EN |
2770 MAC_MODE_APE_RX_EN |
2771 MAC_MODE_TDE_ENABLE;
Matt Carlson3bda1252008-08-15 14:08:22 -07002772
Linus Torvalds1da177e2005-04-16 15:20:36 -07002773 tw32_f(MAC_MODE, mac_mode);
2774 udelay(100);
2775
2776 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2777 udelay(10);
2778 }
2779
2780 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2781 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2782 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2783 u32 base_val;
2784
2785 base_val = tp->pci_clock_ctrl;
2786 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2787 CLOCK_CTRL_TXCLK_DISABLE);
2788
Michael Chanb401e9e2005-12-19 16:27:04 -08002789 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2790 CLOCK_CTRL_PWRDOWN_PLL133, 40);
Michael Chand7b0a852007-02-13 12:17:38 -08002791 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
Matt Carlson795d01c2007-10-07 23:28:17 -07002792 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
Michael Chand7b0a852007-02-13 12:17:38 -08002793 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
Michael Chan4cf78e42005-07-25 12:29:19 -07002794 /* do nothing */
Michael Chan85e94ce2005-04-21 17:05:28 -07002795 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07002796 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2797 u32 newbits1, newbits2;
2798
2799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2801 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2802 CLOCK_CTRL_TXCLK_DISABLE |
2803 CLOCK_CTRL_ALTCLK);
2804 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2805 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2806 newbits1 = CLOCK_CTRL_625_CORE;
2807 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2808 } else {
2809 newbits1 = CLOCK_CTRL_ALTCLK;
2810 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2811 }
2812
Michael Chanb401e9e2005-12-19 16:27:04 -08002813 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2814 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002815
Michael Chanb401e9e2005-12-19 16:27:04 -08002816 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2817 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002818
2819 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2820 u32 newbits3;
2821
2822 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2823 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2824 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2825 CLOCK_CTRL_TXCLK_DISABLE |
2826 CLOCK_CTRL_44MHZ_CORE);
2827 } else {
2828 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2829 }
2830
Michael Chanb401e9e2005-12-19 16:27:04 -08002831 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2832 tp->pci_clock_ctrl | newbits3, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002833 }
2834 }
2835
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002836 if (!(device_should_wake) &&
Matt Carlson22435842008-11-21 17:21:13 -08002837 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
Matt Carlson0a459aa2008-11-03 16:54:15 -08002838 tg3_power_down_phy(tp, do_low_power);
Michael Chan6921d202005-12-13 21:15:53 -08002839
Linus Torvalds1da177e2005-04-16 15:20:36 -07002840 tg3_frob_aux_power(tp);
2841
2842 /* Workaround for unstable PLL clock */
2843 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2844 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2845 u32 val = tr32(0x7d00);
2846
2847 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2848 tw32(0x7d00, val);
Michael Chan6921d202005-12-13 21:15:53 -08002849 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
Michael Chanec41c7d2006-01-17 02:40:55 -08002850 int err;
2851
2852 err = tg3_nvram_lock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002853 tg3_halt_cpu(tp, RX_CPU_BASE);
Michael Chanec41c7d2006-01-17 02:40:55 -08002854 if (!err)
2855 tg3_nvram_unlock(tp);
Michael Chan6921d202005-12-13 21:15:53 -08002856 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002857 }
2858
Michael Chanbbadf502006-04-06 21:46:34 -07002859 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2860
Linus Torvalds1da177e2005-04-16 15:20:36 -07002861 return 0;
2862}
2863
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00002864static void tg3_power_down(struct tg3 *tp)
2865{
2866 tg3_power_down_prepare(tp);
2867
2868 pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2869 pci_set_power_state(tp->pdev, PCI_D3hot);
2870}
2871
Linus Torvalds1da177e2005-04-16 15:20:36 -07002872static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2873{
2874 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2875 case MII_TG3_AUX_STAT_10HALF:
2876 *speed = SPEED_10;
2877 *duplex = DUPLEX_HALF;
2878 break;
2879
2880 case MII_TG3_AUX_STAT_10FULL:
2881 *speed = SPEED_10;
2882 *duplex = DUPLEX_FULL;
2883 break;
2884
2885 case MII_TG3_AUX_STAT_100HALF:
2886 *speed = SPEED_100;
2887 *duplex = DUPLEX_HALF;
2888 break;
2889
2890 case MII_TG3_AUX_STAT_100FULL:
2891 *speed = SPEED_100;
2892 *duplex = DUPLEX_FULL;
2893 break;
2894
2895 case MII_TG3_AUX_STAT_1000HALF:
2896 *speed = SPEED_1000;
2897 *duplex = DUPLEX_HALF;
2898 break;
2899
2900 case MII_TG3_AUX_STAT_1000FULL:
2901 *speed = SPEED_1000;
2902 *duplex = DUPLEX_FULL;
2903 break;
2904
2905 default:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002906 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Michael Chan715116a2006-09-27 16:09:25 -07002907 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2908 SPEED_10;
2909 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2910 DUPLEX_HALF;
2911 break;
2912 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002913 *speed = SPEED_INVALID;
2914 *duplex = DUPLEX_INVALID;
2915 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07002916 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002917}
2918
2919static void tg3_phy_copper_begin(struct tg3 *tp)
2920{
2921 u32 new_adv;
2922 int i;
2923
Matt Carlson80096062010-08-02 11:26:06 +00002924 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002925 /* Entering low power mode. Disable gigabit and
2926 * 100baseT advertisements.
2927 */
2928 tg3_writephy(tp, MII_TG3_CTRL, 0);
2929
2930 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2931 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2932 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2933 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2934
2935 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2936 } else if (tp->link_config.speed == SPEED_INVALID) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002937 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002938 tp->link_config.advertising &=
2939 ~(ADVERTISED_1000baseT_Half |
2940 ADVERTISED_1000baseT_Full);
2941
Matt Carlsonba4d07a2007-12-20 20:08:00 -08002942 new_adv = ADVERTISE_CSMA;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002943 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2944 new_adv |= ADVERTISE_10HALF;
2945 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2946 new_adv |= ADVERTISE_10FULL;
2947 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2948 new_adv |= ADVERTISE_100HALF;
2949 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2950 new_adv |= ADVERTISE_100FULL;
Matt Carlsonba4d07a2007-12-20 20:08:00 -08002951
2952 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2953
Linus Torvalds1da177e2005-04-16 15:20:36 -07002954 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2955
2956 if (tp->link_config.advertising &
2957 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2958 new_adv = 0;
2959 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2960 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2961 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2962 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002963 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07002964 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2965 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2966 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2967 MII_TG3_CTRL_ENABLE_AS_MASTER);
2968 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969 } else {
2970 tg3_writephy(tp, MII_TG3_CTRL, 0);
2971 }
2972 } else {
Matt Carlsonba4d07a2007-12-20 20:08:00 -08002973 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2974 new_adv |= ADVERTISE_CSMA;
2975
Linus Torvalds1da177e2005-04-16 15:20:36 -07002976 /* Asking for a specific link mode. */
2977 if (tp->link_config.speed == SPEED_1000) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002978 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2979
2980 if (tp->link_config.duplex == DUPLEX_FULL)
2981 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2982 else
2983 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2984 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2985 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2986 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2987 MII_TG3_CTRL_ENABLE_AS_MASTER);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002988 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002989 if (tp->link_config.speed == SPEED_100) {
2990 if (tp->link_config.duplex == DUPLEX_FULL)
2991 new_adv |= ADVERTISE_100FULL;
2992 else
2993 new_adv |= ADVERTISE_100HALF;
2994 } else {
2995 if (tp->link_config.duplex == DUPLEX_FULL)
2996 new_adv |= ADVERTISE_10FULL;
2997 else
2998 new_adv |= ADVERTISE_10HALF;
2999 }
3000 tg3_writephy(tp, MII_ADVERTISE, new_adv);
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003001
3002 new_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003003 }
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003004
3005 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003006 }
3007
Matt Carlson52b02d02010-10-14 10:37:41 +00003008 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
Matt Carlsona6b68da2010-12-06 08:28:52 +00003009 u32 val;
Matt Carlson52b02d02010-10-14 10:37:41 +00003010
3011 tw32(TG3_CPMU_EEE_MODE,
3012 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3013
3014 /* Enable SM_DSP clock and tx 6dB coding. */
3015 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3016 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
3017 MII_TG3_AUXCTL_ACTL_TX_6DB;
3018 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3019
Matt Carlson21a00ab2011-01-25 15:58:55 +00003020 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3021 case ASIC_REV_5717:
3022 case ASIC_REV_57765:
3023 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3024 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3025 MII_TG3_DSP_CH34TP2_HIBW01);
3026 /* Fall through */
3027 case ASIC_REV_5719:
3028 val = MII_TG3_DSP_TAP26_ALNOKO |
3029 MII_TG3_DSP_TAP26_RMRXSTO |
3030 MII_TG3_DSP_TAP26_OPCSINPT;
3031 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3032 }
Matt Carlson52b02d02010-10-14 10:37:41 +00003033
Matt Carlsona6b68da2010-12-06 08:28:52 +00003034 val = 0;
Matt Carlson52b02d02010-10-14 10:37:41 +00003035 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3036 /* Advertise 100-BaseTX EEE ability */
3037 if (tp->link_config.advertising &
Matt Carlson3110f5f52010-12-06 08:28:50 +00003038 ADVERTISED_100baseT_Full)
3039 val |= MDIO_AN_EEE_ADV_100TX;
Matt Carlson52b02d02010-10-14 10:37:41 +00003040 /* Advertise 1000-BaseT EEE ability */
3041 if (tp->link_config.advertising &
Matt Carlson3110f5f52010-12-06 08:28:50 +00003042 ADVERTISED_1000baseT_Full)
3043 val |= MDIO_AN_EEE_ADV_1000T;
Matt Carlson52b02d02010-10-14 10:37:41 +00003044 }
Matt Carlson3110f5f52010-12-06 08:28:50 +00003045 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
Matt Carlson52b02d02010-10-14 10:37:41 +00003046
3047 /* Turn off SM_DSP clock. */
3048 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3049 MII_TG3_AUXCTL_ACTL_TX_6DB;
3050 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3051 }
3052
Linus Torvalds1da177e2005-04-16 15:20:36 -07003053 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3054 tp->link_config.speed != SPEED_INVALID) {
3055 u32 bmcr, orig_bmcr;
3056
3057 tp->link_config.active_speed = tp->link_config.speed;
3058 tp->link_config.active_duplex = tp->link_config.duplex;
3059
3060 bmcr = 0;
3061 switch (tp->link_config.speed) {
3062 default:
3063 case SPEED_10:
3064 break;
3065
3066 case SPEED_100:
3067 bmcr |= BMCR_SPEED100;
3068 break;
3069
3070 case SPEED_1000:
3071 bmcr |= TG3_BMCR_SPEED1000;
3072 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07003073 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003074
3075 if (tp->link_config.duplex == DUPLEX_FULL)
3076 bmcr |= BMCR_FULLDPLX;
3077
3078 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3079 (bmcr != orig_bmcr)) {
3080 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3081 for (i = 0; i < 1500; i++) {
3082 u32 tmp;
3083
3084 udelay(10);
3085 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3086 tg3_readphy(tp, MII_BMSR, &tmp))
3087 continue;
3088 if (!(tmp & BMSR_LSTATUS)) {
3089 udelay(40);
3090 break;
3091 }
3092 }
3093 tg3_writephy(tp, MII_BMCR, bmcr);
3094 udelay(40);
3095 }
3096 } else {
3097 tg3_writephy(tp, MII_BMCR,
3098 BMCR_ANENABLE | BMCR_ANRESTART);
3099 }
3100}
3101
3102static int tg3_init_5401phy_dsp(struct tg3 *tp)
3103{
3104 int err;
3105
3106 /* Turn off tap power management. */
3107 /* Set Extended packet length bit */
Matt Carlsonb4bd2922011-04-20 07:57:41 +00003108 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003109
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00003110 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3111 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3112 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3113 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3114 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003115
3116 udelay(40);
3117
3118 return err;
3119}
3120
Michael Chan3600d912006-12-07 00:21:48 -08003121static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003122{
Michael Chan3600d912006-12-07 00:21:48 -08003123 u32 adv_reg, all_mask = 0;
3124
3125 if (mask & ADVERTISED_10baseT_Half)
3126 all_mask |= ADVERTISE_10HALF;
3127 if (mask & ADVERTISED_10baseT_Full)
3128 all_mask |= ADVERTISE_10FULL;
3129 if (mask & ADVERTISED_100baseT_Half)
3130 all_mask |= ADVERTISE_100HALF;
3131 if (mask & ADVERTISED_100baseT_Full)
3132 all_mask |= ADVERTISE_100FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003133
3134 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3135 return 0;
3136
Linus Torvalds1da177e2005-04-16 15:20:36 -07003137 if ((adv_reg & all_mask) != all_mask)
3138 return 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003139 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003140 u32 tg3_ctrl;
3141
Michael Chan3600d912006-12-07 00:21:48 -08003142 all_mask = 0;
3143 if (mask & ADVERTISED_1000baseT_Half)
3144 all_mask |= ADVERTISE_1000HALF;
3145 if (mask & ADVERTISED_1000baseT_Full)
3146 all_mask |= ADVERTISE_1000FULL;
3147
Linus Torvalds1da177e2005-04-16 15:20:36 -07003148 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3149 return 0;
3150
Linus Torvalds1da177e2005-04-16 15:20:36 -07003151 if ((tg3_ctrl & all_mask) != all_mask)
3152 return 0;
3153 }
3154 return 1;
3155}
3156
Matt Carlsonef167e22007-12-20 20:10:01 -08003157static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3158{
3159 u32 curadv, reqadv;
3160
3161 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3162 return 1;
3163
3164 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3165 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3166
3167 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3168 if (curadv != reqadv)
3169 return 0;
3170
3171 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3172 tg3_readphy(tp, MII_LPA, rmtadv);
3173 } else {
3174 /* Reprogram the advertisement register, even if it
3175 * does not affect the current link. If the link
3176 * gets renegotiated in the future, we can save an
3177 * additional renegotiation cycle by advertising
3178 * it correctly in the first place.
3179 */
3180 if (curadv != reqadv) {
3181 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3182 ADVERTISE_PAUSE_ASYM);
3183 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3184 }
3185 }
3186
3187 return 1;
3188}
3189
Linus Torvalds1da177e2005-04-16 15:20:36 -07003190static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3191{
3192 int current_link_up;
Matt Carlsonf833c4c2010-09-15 09:00:01 +00003193 u32 bmsr, val;
Matt Carlsonef167e22007-12-20 20:10:01 -08003194 u32 lcl_adv, rmt_adv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003195 u16 current_speed;
3196 u8 current_duplex;
3197 int i, err;
3198
3199 tw32(MAC_EVENT, 0);
3200
3201 tw32_f(MAC_STATUS,
3202 (MAC_STATUS_SYNC_CHANGED |
3203 MAC_STATUS_CFG_CHANGED |
3204 MAC_STATUS_MI_COMPLETION |
3205 MAC_STATUS_LNKSTATE_CHANGED));
3206 udelay(40);
3207
Matt Carlson8ef21422008-05-02 16:47:53 -07003208 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3209 tw32_f(MAC_MI_MODE,
3210 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3211 udelay(80);
3212 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003213
Matt Carlsonb4bd2922011-04-20 07:57:41 +00003214 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003215
3216 /* Some third-party PHYs need to be reset on link going
3217 * down.
3218 */
3219 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3222 netif_carrier_ok(tp->dev)) {
3223 tg3_readphy(tp, MII_BMSR, &bmsr);
3224 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3225 !(bmsr & BMSR_LSTATUS))
3226 force_reset = 1;
3227 }
3228 if (force_reset)
3229 tg3_phy_reset(tp);
3230
Matt Carlson79eb6902010-02-17 15:17:03 +00003231 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003232 tg3_readphy(tp, MII_BMSR, &bmsr);
3233 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3234 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3235 bmsr = 0;
3236
3237 if (!(bmsr & BMSR_LSTATUS)) {
3238 err = tg3_init_5401phy_dsp(tp);
3239 if (err)
3240 return err;
3241
3242 tg3_readphy(tp, MII_BMSR, &bmsr);
3243 for (i = 0; i < 1000; i++) {
3244 udelay(10);
3245 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3246 (bmsr & BMSR_LSTATUS)) {
3247 udelay(40);
3248 break;
3249 }
3250 }
3251
Matt Carlson79eb6902010-02-17 15:17:03 +00003252 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3253 TG3_PHY_REV_BCM5401_B0 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003254 !(bmsr & BMSR_LSTATUS) &&
3255 tp->link_config.active_speed == SPEED_1000) {
3256 err = tg3_phy_reset(tp);
3257 if (!err)
3258 err = tg3_init_5401phy_dsp(tp);
3259 if (err)
3260 return err;
3261 }
3262 }
3263 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3264 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3265 /* 5701 {A0,B0} CRC bug workaround */
3266 tg3_writephy(tp, 0x15, 0x0a75);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00003267 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3268 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3269 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003270 }
3271
3272 /* Clear pending interrupts... */
Matt Carlsonf833c4c2010-09-15 09:00:01 +00003273 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3274 tg3_readphy(tp, MII_TG3_ISTAT, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003275
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003276 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003277 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003278 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003279 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3280
3281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3282 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3283 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3284 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3285 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3286 else
3287 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3288 }
3289
3290 current_link_up = 0;
3291 current_speed = SPEED_INVALID;
3292 current_duplex = DUPLEX_INVALID;
3293
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003294 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
Matt Carlson15ee95c2011-04-20 07:57:40 +00003295 err = tg3_phy_auxctl_read(tp,
3296 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3297 &val);
3298 if (!err && !(val & (1 << 10))) {
Matt Carlsonb4bd2922011-04-20 07:57:41 +00003299 tg3_phy_auxctl_write(tp,
3300 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3301 val | (1 << 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003302 goto relink;
3303 }
3304 }
3305
3306 bmsr = 0;
3307 for (i = 0; i < 100; i++) {
3308 tg3_readphy(tp, MII_BMSR, &bmsr);
3309 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3310 (bmsr & BMSR_LSTATUS))
3311 break;
3312 udelay(40);
3313 }
3314
3315 if (bmsr & BMSR_LSTATUS) {
3316 u32 aux_stat, bmcr;
3317
3318 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3319 for (i = 0; i < 2000; i++) {
3320 udelay(10);
3321 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3322 aux_stat)
3323 break;
3324 }
3325
3326 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3327 &current_speed,
3328 &current_duplex);
3329
3330 bmcr = 0;
3331 for (i = 0; i < 200; i++) {
3332 tg3_readphy(tp, MII_BMCR, &bmcr);
3333 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3334 continue;
3335 if (bmcr && bmcr != 0x7fff)
3336 break;
3337 udelay(10);
3338 }
3339
Matt Carlsonef167e22007-12-20 20:10:01 -08003340 lcl_adv = 0;
3341 rmt_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003342
Matt Carlsonef167e22007-12-20 20:10:01 -08003343 tp->link_config.active_speed = current_speed;
3344 tp->link_config.active_duplex = current_duplex;
3345
3346 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3347 if ((bmcr & BMCR_ANENABLE) &&
3348 tg3_copper_is_advertising_all(tp,
3349 tp->link_config.advertising)) {
3350 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3351 &rmt_adv))
3352 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003353 }
3354 } else {
3355 if (!(bmcr & BMCR_ANENABLE) &&
3356 tp->link_config.speed == current_speed &&
Matt Carlsonef167e22007-12-20 20:10:01 -08003357 tp->link_config.duplex == current_duplex &&
3358 tp->link_config.flowctrl ==
3359 tp->link_config.active_flowctrl) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003360 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003361 }
3362 }
3363
Matt Carlsonef167e22007-12-20 20:10:01 -08003364 if (current_link_up == 1 &&
3365 tp->link_config.active_duplex == DUPLEX_FULL)
3366 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003367 }
3368
Linus Torvalds1da177e2005-04-16 15:20:36 -07003369relink:
Matt Carlson80096062010-08-02 11:26:06 +00003370 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003371 tg3_phy_copper_begin(tp);
3372
Matt Carlsonf833c4c2010-09-15 09:00:01 +00003373 tg3_readphy(tp, MII_BMSR, &bmsr);
3374 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3375 (bmsr & BMSR_LSTATUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003376 current_link_up = 1;
3377 }
3378
3379 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3380 if (current_link_up == 1) {
3381 if (tp->link_config.active_speed == SPEED_100 ||
3382 tp->link_config.active_speed == SPEED_10)
3383 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3384 else
3385 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003386 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
Matt Carlson7f97a4b2009-08-25 10:10:03 +00003387 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3388 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07003389 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3390
3391 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3392 if (tp->link_config.active_duplex == DUPLEX_HALF)
3393 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3394
Linus Torvalds1da177e2005-04-16 15:20:36 -07003395 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003396 if (current_link_up == 1 &&
3397 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003398 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003399 else
3400 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003401 }
3402
3403 /* ??? Without this setting Netgear GA302T PHY does not
3404 * ??? send/receive packets...
3405 */
Matt Carlson79eb6902010-02-17 15:17:03 +00003406 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003407 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3408 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3409 tw32_f(MAC_MI_MODE, tp->mi_mode);
3410 udelay(80);
3411 }
3412
3413 tw32_f(MAC_MODE, tp->mac_mode);
3414 udelay(40);
3415
Matt Carlson52b02d02010-10-14 10:37:41 +00003416 tg3_phy_eee_adjust(tp, current_link_up);
3417
Linus Torvalds1da177e2005-04-16 15:20:36 -07003418 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3419 /* Polled via timer. */
3420 tw32_f(MAC_EVENT, 0);
3421 } else {
3422 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3423 }
3424 udelay(40);
3425
3426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3427 current_link_up == 1 &&
3428 tp->link_config.active_speed == SPEED_1000 &&
3429 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3430 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3431 udelay(120);
3432 tw32_f(MAC_STATUS,
3433 (MAC_STATUS_SYNC_CHANGED |
3434 MAC_STATUS_CFG_CHANGED));
3435 udelay(40);
3436 tg3_write_mem(tp,
3437 NIC_SRAM_FIRMWARE_MBOX,
3438 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3439 }
3440
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003441 /* Prevent send BD corruption. */
3442 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3443 u16 oldlnkctl, newlnkctl;
3444
3445 pci_read_config_word(tp->pdev,
3446 tp->pcie_cap + PCI_EXP_LNKCTL,
3447 &oldlnkctl);
3448 if (tp->link_config.active_speed == SPEED_100 ||
3449 tp->link_config.active_speed == SPEED_10)
3450 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3451 else
3452 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3453 if (newlnkctl != oldlnkctl)
3454 pci_write_config_word(tp->pdev,
3455 tp->pcie_cap + PCI_EXP_LNKCTL,
3456 newlnkctl);
3457 }
3458
Linus Torvalds1da177e2005-04-16 15:20:36 -07003459 if (current_link_up != netif_carrier_ok(tp->dev)) {
3460 if (current_link_up)
3461 netif_carrier_on(tp->dev);
3462 else
3463 netif_carrier_off(tp->dev);
3464 tg3_link_report(tp);
3465 }
3466
3467 return 0;
3468}
3469
3470struct tg3_fiber_aneginfo {
3471 int state;
3472#define ANEG_STATE_UNKNOWN 0
3473#define ANEG_STATE_AN_ENABLE 1
3474#define ANEG_STATE_RESTART_INIT 2
3475#define ANEG_STATE_RESTART 3
3476#define ANEG_STATE_DISABLE_LINK_OK 4
3477#define ANEG_STATE_ABILITY_DETECT_INIT 5
3478#define ANEG_STATE_ABILITY_DETECT 6
3479#define ANEG_STATE_ACK_DETECT_INIT 7
3480#define ANEG_STATE_ACK_DETECT 8
3481#define ANEG_STATE_COMPLETE_ACK_INIT 9
3482#define ANEG_STATE_COMPLETE_ACK 10
3483#define ANEG_STATE_IDLE_DETECT_INIT 11
3484#define ANEG_STATE_IDLE_DETECT 12
3485#define ANEG_STATE_LINK_OK 13
3486#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3487#define ANEG_STATE_NEXT_PAGE_WAIT 15
3488
3489 u32 flags;
3490#define MR_AN_ENABLE 0x00000001
3491#define MR_RESTART_AN 0x00000002
3492#define MR_AN_COMPLETE 0x00000004
3493#define MR_PAGE_RX 0x00000008
3494#define MR_NP_LOADED 0x00000010
3495#define MR_TOGGLE_TX 0x00000020
3496#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3497#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3498#define MR_LP_ADV_SYM_PAUSE 0x00000100
3499#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3500#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3501#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3502#define MR_LP_ADV_NEXT_PAGE 0x00001000
3503#define MR_TOGGLE_RX 0x00002000
3504#define MR_NP_RX 0x00004000
3505
3506#define MR_LINK_OK 0x80000000
3507
3508 unsigned long link_time, cur_time;
3509
3510 u32 ability_match_cfg;
3511 int ability_match_count;
3512
3513 char ability_match, idle_match, ack_match;
3514
3515 u32 txconfig, rxconfig;
3516#define ANEG_CFG_NP 0x00000080
3517#define ANEG_CFG_ACK 0x00000040
3518#define ANEG_CFG_RF2 0x00000020
3519#define ANEG_CFG_RF1 0x00000010
3520#define ANEG_CFG_PS2 0x00000001
3521#define ANEG_CFG_PS1 0x00008000
3522#define ANEG_CFG_HD 0x00004000
3523#define ANEG_CFG_FD 0x00002000
3524#define ANEG_CFG_INVAL 0x00001f06
3525
3526};
3527#define ANEG_OK 0
3528#define ANEG_DONE 1
3529#define ANEG_TIMER_ENAB 2
3530#define ANEG_FAILED -1
3531
3532#define ANEG_STATE_SETTLE_TIME 10000
3533
3534static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3535 struct tg3_fiber_aneginfo *ap)
3536{
Matt Carlson5be73b42007-12-20 20:09:29 -08003537 u16 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003538 unsigned long delta;
3539 u32 rx_cfg_reg;
3540 int ret;
3541
3542 if (ap->state == ANEG_STATE_UNKNOWN) {
3543 ap->rxconfig = 0;
3544 ap->link_time = 0;
3545 ap->cur_time = 0;
3546 ap->ability_match_cfg = 0;
3547 ap->ability_match_count = 0;
3548 ap->ability_match = 0;
3549 ap->idle_match = 0;
3550 ap->ack_match = 0;
3551 }
3552 ap->cur_time++;
3553
3554 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3555 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3556
3557 if (rx_cfg_reg != ap->ability_match_cfg) {
3558 ap->ability_match_cfg = rx_cfg_reg;
3559 ap->ability_match = 0;
3560 ap->ability_match_count = 0;
3561 } else {
3562 if (++ap->ability_match_count > 1) {
3563 ap->ability_match = 1;
3564 ap->ability_match_cfg = rx_cfg_reg;
3565 }
3566 }
3567 if (rx_cfg_reg & ANEG_CFG_ACK)
3568 ap->ack_match = 1;
3569 else
3570 ap->ack_match = 0;
3571
3572 ap->idle_match = 0;
3573 } else {
3574 ap->idle_match = 1;
3575 ap->ability_match_cfg = 0;
3576 ap->ability_match_count = 0;
3577 ap->ability_match = 0;
3578 ap->ack_match = 0;
3579
3580 rx_cfg_reg = 0;
3581 }
3582
3583 ap->rxconfig = rx_cfg_reg;
3584 ret = ANEG_OK;
3585
Matt Carlson33f401a2010-04-05 10:19:27 +00003586 switch (ap->state) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003587 case ANEG_STATE_UNKNOWN:
3588 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3589 ap->state = ANEG_STATE_AN_ENABLE;
3590
3591 /* fallthru */
3592 case ANEG_STATE_AN_ENABLE:
3593 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3594 if (ap->flags & MR_AN_ENABLE) {
3595 ap->link_time = 0;
3596 ap->cur_time = 0;
3597 ap->ability_match_cfg = 0;
3598 ap->ability_match_count = 0;
3599 ap->ability_match = 0;
3600 ap->idle_match = 0;
3601 ap->ack_match = 0;
3602
3603 ap->state = ANEG_STATE_RESTART_INIT;
3604 } else {
3605 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3606 }
3607 break;
3608
3609 case ANEG_STATE_RESTART_INIT:
3610 ap->link_time = ap->cur_time;
3611 ap->flags &= ~(MR_NP_LOADED);
3612 ap->txconfig = 0;
3613 tw32(MAC_TX_AUTO_NEG, 0);
3614 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3615 tw32_f(MAC_MODE, tp->mac_mode);
3616 udelay(40);
3617
3618 ret = ANEG_TIMER_ENAB;
3619 ap->state = ANEG_STATE_RESTART;
3620
3621 /* fallthru */
3622 case ANEG_STATE_RESTART:
3623 delta = ap->cur_time - ap->link_time;
Matt Carlson859a588792010-04-05 10:19:28 +00003624 if (delta > ANEG_STATE_SETTLE_TIME)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003625 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
Matt Carlson859a588792010-04-05 10:19:28 +00003626 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07003627 ret = ANEG_TIMER_ENAB;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003628 break;
3629
3630 case ANEG_STATE_DISABLE_LINK_OK:
3631 ret = ANEG_DONE;
3632 break;
3633
3634 case ANEG_STATE_ABILITY_DETECT_INIT:
3635 ap->flags &= ~(MR_TOGGLE_TX);
Matt Carlson5be73b42007-12-20 20:09:29 -08003636 ap->txconfig = ANEG_CFG_FD;
3637 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3638 if (flowctrl & ADVERTISE_1000XPAUSE)
3639 ap->txconfig |= ANEG_CFG_PS1;
3640 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3641 ap->txconfig |= ANEG_CFG_PS2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003642 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3643 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3644 tw32_f(MAC_MODE, tp->mac_mode);
3645 udelay(40);
3646
3647 ap->state = ANEG_STATE_ABILITY_DETECT;
3648 break;
3649
3650 case ANEG_STATE_ABILITY_DETECT:
Matt Carlson859a588792010-04-05 10:19:28 +00003651 if (ap->ability_match != 0 && ap->rxconfig != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003652 ap->state = ANEG_STATE_ACK_DETECT_INIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003653 break;
3654
3655 case ANEG_STATE_ACK_DETECT_INIT:
3656 ap->txconfig |= ANEG_CFG_ACK;
3657 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3658 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3659 tw32_f(MAC_MODE, tp->mac_mode);
3660 udelay(40);
3661
3662 ap->state = ANEG_STATE_ACK_DETECT;
3663
3664 /* fallthru */
3665 case ANEG_STATE_ACK_DETECT:
3666 if (ap->ack_match != 0) {
3667 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3668 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3669 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3670 } else {
3671 ap->state = ANEG_STATE_AN_ENABLE;
3672 }
3673 } else if (ap->ability_match != 0 &&
3674 ap->rxconfig == 0) {
3675 ap->state = ANEG_STATE_AN_ENABLE;
3676 }
3677 break;
3678
3679 case ANEG_STATE_COMPLETE_ACK_INIT:
3680 if (ap->rxconfig & ANEG_CFG_INVAL) {
3681 ret = ANEG_FAILED;
3682 break;
3683 }
3684 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3685 MR_LP_ADV_HALF_DUPLEX |
3686 MR_LP_ADV_SYM_PAUSE |
3687 MR_LP_ADV_ASYM_PAUSE |
3688 MR_LP_ADV_REMOTE_FAULT1 |
3689 MR_LP_ADV_REMOTE_FAULT2 |
3690 MR_LP_ADV_NEXT_PAGE |
3691 MR_TOGGLE_RX |
3692 MR_NP_RX);
3693 if (ap->rxconfig & ANEG_CFG_FD)
3694 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3695 if (ap->rxconfig & ANEG_CFG_HD)
3696 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3697 if (ap->rxconfig & ANEG_CFG_PS1)
3698 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3699 if (ap->rxconfig & ANEG_CFG_PS2)
3700 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3701 if (ap->rxconfig & ANEG_CFG_RF1)
3702 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3703 if (ap->rxconfig & ANEG_CFG_RF2)
3704 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3705 if (ap->rxconfig & ANEG_CFG_NP)
3706 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3707
3708 ap->link_time = ap->cur_time;
3709
3710 ap->flags ^= (MR_TOGGLE_TX);
3711 if (ap->rxconfig & 0x0008)
3712 ap->flags |= MR_TOGGLE_RX;
3713 if (ap->rxconfig & ANEG_CFG_NP)
3714 ap->flags |= MR_NP_RX;
3715 ap->flags |= MR_PAGE_RX;
3716
3717 ap->state = ANEG_STATE_COMPLETE_ACK;
3718 ret = ANEG_TIMER_ENAB;
3719 break;
3720
3721 case ANEG_STATE_COMPLETE_ACK:
3722 if (ap->ability_match != 0 &&
3723 ap->rxconfig == 0) {
3724 ap->state = ANEG_STATE_AN_ENABLE;
3725 break;
3726 }
3727 delta = ap->cur_time - ap->link_time;
3728 if (delta > ANEG_STATE_SETTLE_TIME) {
3729 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3730 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3731 } else {
3732 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3733 !(ap->flags & MR_NP_RX)) {
3734 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3735 } else {
3736 ret = ANEG_FAILED;
3737 }
3738 }
3739 }
3740 break;
3741
3742 case ANEG_STATE_IDLE_DETECT_INIT:
3743 ap->link_time = ap->cur_time;
3744 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3745 tw32_f(MAC_MODE, tp->mac_mode);
3746 udelay(40);
3747
3748 ap->state = ANEG_STATE_IDLE_DETECT;
3749 ret = ANEG_TIMER_ENAB;
3750 break;
3751
3752 case ANEG_STATE_IDLE_DETECT:
3753 if (ap->ability_match != 0 &&
3754 ap->rxconfig == 0) {
3755 ap->state = ANEG_STATE_AN_ENABLE;
3756 break;
3757 }
3758 delta = ap->cur_time - ap->link_time;
3759 if (delta > ANEG_STATE_SETTLE_TIME) {
3760 /* XXX another gem from the Broadcom driver :( */
3761 ap->state = ANEG_STATE_LINK_OK;
3762 }
3763 break;
3764
3765 case ANEG_STATE_LINK_OK:
3766 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3767 ret = ANEG_DONE;
3768 break;
3769
3770 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3771 /* ??? unimplemented */
3772 break;
3773
3774 case ANEG_STATE_NEXT_PAGE_WAIT:
3775 /* ??? unimplemented */
3776 break;
3777
3778 default:
3779 ret = ANEG_FAILED;
3780 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07003781 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003782
3783 return ret;
3784}
3785
Matt Carlson5be73b42007-12-20 20:09:29 -08003786static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003787{
3788 int res = 0;
3789 struct tg3_fiber_aneginfo aninfo;
3790 int status = ANEG_FAILED;
3791 unsigned int tick;
3792 u32 tmp;
3793
3794 tw32_f(MAC_TX_AUTO_NEG, 0);
3795
3796 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3797 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3798 udelay(40);
3799
3800 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3801 udelay(40);
3802
3803 memset(&aninfo, 0, sizeof(aninfo));
3804 aninfo.flags |= MR_AN_ENABLE;
3805 aninfo.state = ANEG_STATE_UNKNOWN;
3806 aninfo.cur_time = 0;
3807 tick = 0;
3808 while (++tick < 195000) {
3809 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3810 if (status == ANEG_DONE || status == ANEG_FAILED)
3811 break;
3812
3813 udelay(1);
3814 }
3815
3816 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3817 tw32_f(MAC_MODE, tp->mac_mode);
3818 udelay(40);
3819
Matt Carlson5be73b42007-12-20 20:09:29 -08003820 *txflags = aninfo.txconfig;
3821 *rxflags = aninfo.flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003822
3823 if (status == ANEG_DONE &&
3824 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3825 MR_LP_ADV_FULL_DUPLEX)))
3826 res = 1;
3827
3828 return res;
3829}
3830
3831static void tg3_init_bcm8002(struct tg3 *tp)
3832{
3833 u32 mac_status = tr32(MAC_STATUS);
3834 int i;
3835
3836 /* Reset when initting first time or we have a link. */
3837 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3838 !(mac_status & MAC_STATUS_PCS_SYNCED))
3839 return;
3840
3841 /* Set PLL lock range. */
3842 tg3_writephy(tp, 0x16, 0x8007);
3843
3844 /* SW reset */
3845 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3846
3847 /* Wait for reset to complete. */
3848 /* XXX schedule_timeout() ... */
3849 for (i = 0; i < 500; i++)
3850 udelay(10);
3851
3852 /* Config mode; select PMA/Ch 1 regs. */
3853 tg3_writephy(tp, 0x10, 0x8411);
3854
3855 /* Enable auto-lock and comdet, select txclk for tx. */
3856 tg3_writephy(tp, 0x11, 0x0a10);
3857
3858 tg3_writephy(tp, 0x18, 0x00a0);
3859 tg3_writephy(tp, 0x16, 0x41ff);
3860
3861 /* Assert and deassert POR. */
3862 tg3_writephy(tp, 0x13, 0x0400);
3863 udelay(40);
3864 tg3_writephy(tp, 0x13, 0x0000);
3865
3866 tg3_writephy(tp, 0x11, 0x0a50);
3867 udelay(40);
3868 tg3_writephy(tp, 0x11, 0x0a10);
3869
3870 /* Wait for signal to stabilize */
3871 /* XXX schedule_timeout() ... */
3872 for (i = 0; i < 15000; i++)
3873 udelay(10);
3874
3875 /* Deselect the channel register so we can read the PHYID
3876 * later.
3877 */
3878 tg3_writephy(tp, 0x10, 0x8011);
3879}
3880
3881static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3882{
Matt Carlson82cd3d12007-12-20 20:09:00 -08003883 u16 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003884 u32 sg_dig_ctrl, sg_dig_status;
3885 u32 serdes_cfg, expected_sg_dig_ctrl;
3886 int workaround, port_a;
3887 int current_link_up;
3888
3889 serdes_cfg = 0;
3890 expected_sg_dig_ctrl = 0;
3891 workaround = 0;
3892 port_a = 1;
3893 current_link_up = 0;
3894
3895 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3896 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3897 workaround = 1;
3898 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3899 port_a = 0;
3900
3901 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3902 /* preserve bits 20-23 for voltage regulator */
3903 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3904 }
3905
3906 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3907
3908 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003909 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003910 if (workaround) {
3911 u32 val = serdes_cfg;
3912
3913 if (port_a)
3914 val |= 0xc010000;
3915 else
3916 val |= 0x4010000;
3917 tw32_f(MAC_SERDES_CFG, val);
3918 }
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003919
3920 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003921 }
3922 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3923 tg3_setup_flow_control(tp, 0, 0);
3924 current_link_up = 1;
3925 }
3926 goto out;
3927 }
3928
3929 /* Want auto-negotiation. */
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003930 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003931
Matt Carlson82cd3d12007-12-20 20:09:00 -08003932 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3933 if (flowctrl & ADVERTISE_1000XPAUSE)
3934 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3935 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3936 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003937
3938 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003939 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
Michael Chan3d3ebe72006-09-27 15:59:15 -07003940 tp->serdes_counter &&
3941 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3942 MAC_STATUS_RCVD_CFG)) ==
3943 MAC_STATUS_PCS_SYNCED)) {
3944 tp->serdes_counter--;
3945 current_link_up = 1;
3946 goto out;
3947 }
3948restart_autoneg:
Linus Torvalds1da177e2005-04-16 15:20:36 -07003949 if (workaround)
3950 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003951 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003952 udelay(5);
3953 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3954
Michael Chan3d3ebe72006-09-27 15:59:15 -07003955 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003956 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003957 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3958 MAC_STATUS_SIGNAL_DET)) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07003959 sg_dig_status = tr32(SG_DIG_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003960 mac_status = tr32(MAC_STATUS);
3961
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003962 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003963 (mac_status & MAC_STATUS_PCS_SYNCED)) {
Matt Carlson82cd3d12007-12-20 20:09:00 -08003964 u32 local_adv = 0, remote_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003965
Matt Carlson82cd3d12007-12-20 20:09:00 -08003966 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3967 local_adv |= ADVERTISE_1000XPAUSE;
3968 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3969 local_adv |= ADVERTISE_1000XPSE_ASYM;
3970
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003971 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
Matt Carlson82cd3d12007-12-20 20:09:00 -08003972 remote_adv |= LPA_1000XPAUSE;
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003973 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
Matt Carlson82cd3d12007-12-20 20:09:00 -08003974 remote_adv |= LPA_1000XPAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003975
3976 tg3_setup_flow_control(tp, local_adv, remote_adv);
3977 current_link_up = 1;
Michael Chan3d3ebe72006-09-27 15:59:15 -07003978 tp->serdes_counter = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003979 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003980 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07003981 if (tp->serdes_counter)
3982 tp->serdes_counter--;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003983 else {
3984 if (workaround) {
3985 u32 val = serdes_cfg;
3986
3987 if (port_a)
3988 val |= 0xc010000;
3989 else
3990 val |= 0x4010000;
3991
3992 tw32_f(MAC_SERDES_CFG, val);
3993 }
3994
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003995 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003996 udelay(40);
3997
3998 /* Link parallel detection - link is up */
3999 /* only if we have PCS_SYNC and not */
4000 /* receiving config code words */
4001 mac_status = tr32(MAC_STATUS);
4002 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4003 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4004 tg3_setup_flow_control(tp, 0, 0);
4005 current_link_up = 1;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004006 tp->phy_flags |=
4007 TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan3d3ebe72006-09-27 15:59:15 -07004008 tp->serdes_counter =
4009 SERDES_PARALLEL_DET_TIMEOUT;
4010 } else
4011 goto restart_autoneg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004012 }
4013 }
Michael Chan3d3ebe72006-09-27 15:59:15 -07004014 } else {
4015 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004016 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004017 }
4018
4019out:
4020 return current_link_up;
4021}
4022
4023static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4024{
4025 int current_link_up = 0;
4026
Michael Chan5cf64b8a2007-05-05 12:11:21 -07004027 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004028 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004029
4030 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
Matt Carlson5be73b42007-12-20 20:09:29 -08004031 u32 txflags, rxflags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004032 int i;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004033
Matt Carlson5be73b42007-12-20 20:09:29 -08004034 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4035 u32 local_adv = 0, remote_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004036
Matt Carlson5be73b42007-12-20 20:09:29 -08004037 if (txflags & ANEG_CFG_PS1)
4038 local_adv |= ADVERTISE_1000XPAUSE;
4039 if (txflags & ANEG_CFG_PS2)
4040 local_adv |= ADVERTISE_1000XPSE_ASYM;
4041
4042 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4043 remote_adv |= LPA_1000XPAUSE;
4044 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4045 remote_adv |= LPA_1000XPAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004046
4047 tg3_setup_flow_control(tp, local_adv, remote_adv);
4048
Linus Torvalds1da177e2005-04-16 15:20:36 -07004049 current_link_up = 1;
4050 }
4051 for (i = 0; i < 30; i++) {
4052 udelay(20);
4053 tw32_f(MAC_STATUS,
4054 (MAC_STATUS_SYNC_CHANGED |
4055 MAC_STATUS_CFG_CHANGED));
4056 udelay(40);
4057 if ((tr32(MAC_STATUS) &
4058 (MAC_STATUS_SYNC_CHANGED |
4059 MAC_STATUS_CFG_CHANGED)) == 0)
4060 break;
4061 }
4062
4063 mac_status = tr32(MAC_STATUS);
4064 if (current_link_up == 0 &&
4065 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4066 !(mac_status & MAC_STATUS_RCVD_CFG))
4067 current_link_up = 1;
4068 } else {
Matt Carlson5be73b42007-12-20 20:09:29 -08004069 tg3_setup_flow_control(tp, 0, 0);
4070
Linus Torvalds1da177e2005-04-16 15:20:36 -07004071 /* Forcing 1000FD link up. */
4072 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004073
4074 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4075 udelay(40);
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07004076
4077 tw32_f(MAC_MODE, tp->mac_mode);
4078 udelay(40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004079 }
4080
4081out:
4082 return current_link_up;
4083}
4084
4085static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4086{
4087 u32 orig_pause_cfg;
4088 u16 orig_active_speed;
4089 u8 orig_active_duplex;
4090 u32 mac_status;
4091 int current_link_up;
4092 int i;
4093
Matt Carlson8d018622007-12-20 20:05:44 -08004094 orig_pause_cfg = tp->link_config.active_flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004095 orig_active_speed = tp->link_config.active_speed;
4096 orig_active_duplex = tp->link_config.active_duplex;
4097
4098 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4099 netif_carrier_ok(tp->dev) &&
4100 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4101 mac_status = tr32(MAC_STATUS);
4102 mac_status &= (MAC_STATUS_PCS_SYNCED |
4103 MAC_STATUS_SIGNAL_DET |
4104 MAC_STATUS_CFG_CHANGED |
4105 MAC_STATUS_RCVD_CFG);
4106 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4107 MAC_STATUS_SIGNAL_DET)) {
4108 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4109 MAC_STATUS_CFG_CHANGED));
4110 return 0;
4111 }
4112 }
4113
4114 tw32_f(MAC_TX_AUTO_NEG, 0);
4115
4116 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4117 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4118 tw32_f(MAC_MODE, tp->mac_mode);
4119 udelay(40);
4120
Matt Carlson79eb6902010-02-17 15:17:03 +00004121 if (tp->phy_id == TG3_PHY_ID_BCM8002)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004122 tg3_init_bcm8002(tp);
4123
4124 /* Enable link change event even when serdes polling. */
4125 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4126 udelay(40);
4127
4128 current_link_up = 0;
4129 mac_status = tr32(MAC_STATUS);
4130
4131 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4132 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4133 else
4134 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4135
Matt Carlson898a56f2009-08-28 14:02:40 +00004136 tp->napi[0].hw_status->status =
Linus Torvalds1da177e2005-04-16 15:20:36 -07004137 (SD_STATUS_UPDATED |
Matt Carlson898a56f2009-08-28 14:02:40 +00004138 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004139
4140 for (i = 0; i < 100; i++) {
4141 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4142 MAC_STATUS_CFG_CHANGED));
4143 udelay(5);
4144 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
Michael Chan3d3ebe72006-09-27 15:59:15 -07004145 MAC_STATUS_CFG_CHANGED |
4146 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004147 break;
4148 }
4149
4150 mac_status = tr32(MAC_STATUS);
4151 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4152 current_link_up = 0;
Michael Chan3d3ebe72006-09-27 15:59:15 -07004153 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4154 tp->serdes_counter == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004155 tw32_f(MAC_MODE, (tp->mac_mode |
4156 MAC_MODE_SEND_CONFIGS));
4157 udelay(1);
4158 tw32_f(MAC_MODE, tp->mac_mode);
4159 }
4160 }
4161
4162 if (current_link_up == 1) {
4163 tp->link_config.active_speed = SPEED_1000;
4164 tp->link_config.active_duplex = DUPLEX_FULL;
4165 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4166 LED_CTRL_LNKLED_OVERRIDE |
4167 LED_CTRL_1000MBPS_ON));
4168 } else {
4169 tp->link_config.active_speed = SPEED_INVALID;
4170 tp->link_config.active_duplex = DUPLEX_INVALID;
4171 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4172 LED_CTRL_LNKLED_OVERRIDE |
4173 LED_CTRL_TRAFFIC_OVERRIDE));
4174 }
4175
4176 if (current_link_up != netif_carrier_ok(tp->dev)) {
4177 if (current_link_up)
4178 netif_carrier_on(tp->dev);
4179 else
4180 netif_carrier_off(tp->dev);
4181 tg3_link_report(tp);
4182 } else {
Matt Carlson8d018622007-12-20 20:05:44 -08004183 u32 now_pause_cfg = tp->link_config.active_flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004184 if (orig_pause_cfg != now_pause_cfg ||
4185 orig_active_speed != tp->link_config.active_speed ||
4186 orig_active_duplex != tp->link_config.active_duplex)
4187 tg3_link_report(tp);
4188 }
4189
4190 return 0;
4191}
4192
Michael Chan747e8f82005-07-25 12:33:22 -07004193static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4194{
4195 int current_link_up, err = 0;
4196 u32 bmsr, bmcr;
4197 u16 current_speed;
4198 u8 current_duplex;
Matt Carlsonef167e22007-12-20 20:10:01 -08004199 u32 local_adv, remote_adv;
Michael Chan747e8f82005-07-25 12:33:22 -07004200
4201 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4202 tw32_f(MAC_MODE, tp->mac_mode);
4203 udelay(40);
4204
4205 tw32(MAC_EVENT, 0);
4206
4207 tw32_f(MAC_STATUS,
4208 (MAC_STATUS_SYNC_CHANGED |
4209 MAC_STATUS_CFG_CHANGED |
4210 MAC_STATUS_MI_COMPLETION |
4211 MAC_STATUS_LNKSTATE_CHANGED));
4212 udelay(40);
4213
4214 if (force_reset)
4215 tg3_phy_reset(tp);
4216
4217 current_link_up = 0;
4218 current_speed = SPEED_INVALID;
4219 current_duplex = DUPLEX_INVALID;
4220
4221 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4222 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
Michael Chand4d2c552006-03-20 17:47:20 -08004223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4224 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4225 bmsr |= BMSR_LSTATUS;
4226 else
4227 bmsr &= ~BMSR_LSTATUS;
4228 }
Michael Chan747e8f82005-07-25 12:33:22 -07004229
4230 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4231
4232 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004233 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
Michael Chan747e8f82005-07-25 12:33:22 -07004234 /* do nothing, just check for link up at the end */
4235 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4236 u32 adv, new_adv;
4237
4238 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4239 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4240 ADVERTISE_1000XPAUSE |
4241 ADVERTISE_1000XPSE_ASYM |
4242 ADVERTISE_SLCT);
4243
Matt Carlsonba4d07a2007-12-20 20:08:00 -08004244 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
Michael Chan747e8f82005-07-25 12:33:22 -07004245
4246 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4247 new_adv |= ADVERTISE_1000XHALF;
4248 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4249 new_adv |= ADVERTISE_1000XFULL;
4250
4251 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4252 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4253 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4254 tg3_writephy(tp, MII_BMCR, bmcr);
4255
4256 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
Michael Chan3d3ebe72006-09-27 15:59:15 -07004257 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004258 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004259
4260 return err;
4261 }
4262 } else {
4263 u32 new_bmcr;
4264
4265 bmcr &= ~BMCR_SPEED1000;
4266 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4267
4268 if (tp->link_config.duplex == DUPLEX_FULL)
4269 new_bmcr |= BMCR_FULLDPLX;
4270
4271 if (new_bmcr != bmcr) {
4272 /* BMCR_SPEED1000 is a reserved bit that needs
4273 * to be set on write.
4274 */
4275 new_bmcr |= BMCR_SPEED1000;
4276
4277 /* Force a linkdown */
4278 if (netif_carrier_ok(tp->dev)) {
4279 u32 adv;
4280
4281 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4282 adv &= ~(ADVERTISE_1000XFULL |
4283 ADVERTISE_1000XHALF |
4284 ADVERTISE_SLCT);
4285 tg3_writephy(tp, MII_ADVERTISE, adv);
4286 tg3_writephy(tp, MII_BMCR, bmcr |
4287 BMCR_ANRESTART |
4288 BMCR_ANENABLE);
4289 udelay(10);
4290 netif_carrier_off(tp->dev);
4291 }
4292 tg3_writephy(tp, MII_BMCR, new_bmcr);
4293 bmcr = new_bmcr;
4294 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4295 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
Michael Chand4d2c552006-03-20 17:47:20 -08004296 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4297 ASIC_REV_5714) {
4298 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4299 bmsr |= BMSR_LSTATUS;
4300 else
4301 bmsr &= ~BMSR_LSTATUS;
4302 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004303 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004304 }
4305 }
4306
4307 if (bmsr & BMSR_LSTATUS) {
4308 current_speed = SPEED_1000;
4309 current_link_up = 1;
4310 if (bmcr & BMCR_FULLDPLX)
4311 current_duplex = DUPLEX_FULL;
4312 else
4313 current_duplex = DUPLEX_HALF;
4314
Matt Carlsonef167e22007-12-20 20:10:01 -08004315 local_adv = 0;
4316 remote_adv = 0;
4317
Michael Chan747e8f82005-07-25 12:33:22 -07004318 if (bmcr & BMCR_ANENABLE) {
Matt Carlsonef167e22007-12-20 20:10:01 -08004319 u32 common;
Michael Chan747e8f82005-07-25 12:33:22 -07004320
4321 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4322 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4323 common = local_adv & remote_adv;
4324 if (common & (ADVERTISE_1000XHALF |
4325 ADVERTISE_1000XFULL)) {
4326 if (common & ADVERTISE_1000XFULL)
4327 current_duplex = DUPLEX_FULL;
4328 else
4329 current_duplex = DUPLEX_HALF;
Matt Carlson57d8b882010-06-05 17:24:35 +00004330 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4331 /* Link is up via parallel detect */
Matt Carlson859a588792010-04-05 10:19:28 +00004332 } else {
Michael Chan747e8f82005-07-25 12:33:22 -07004333 current_link_up = 0;
Matt Carlson859a588792010-04-05 10:19:28 +00004334 }
Michael Chan747e8f82005-07-25 12:33:22 -07004335 }
4336 }
4337
Matt Carlsonef167e22007-12-20 20:10:01 -08004338 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4339 tg3_setup_flow_control(tp, local_adv, remote_adv);
4340
Michael Chan747e8f82005-07-25 12:33:22 -07004341 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4342 if (tp->link_config.active_duplex == DUPLEX_HALF)
4343 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4344
4345 tw32_f(MAC_MODE, tp->mac_mode);
4346 udelay(40);
4347
4348 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4349
4350 tp->link_config.active_speed = current_speed;
4351 tp->link_config.active_duplex = current_duplex;
4352
4353 if (current_link_up != netif_carrier_ok(tp->dev)) {
4354 if (current_link_up)
4355 netif_carrier_on(tp->dev);
4356 else {
4357 netif_carrier_off(tp->dev);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004358 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004359 }
4360 tg3_link_report(tp);
4361 }
4362 return err;
4363}
4364
4365static void tg3_serdes_parallel_detect(struct tg3 *tp)
4366{
Michael Chan3d3ebe72006-09-27 15:59:15 -07004367 if (tp->serdes_counter) {
Michael Chan747e8f82005-07-25 12:33:22 -07004368 /* Give autoneg time to complete. */
Michael Chan3d3ebe72006-09-27 15:59:15 -07004369 tp->serdes_counter--;
Michael Chan747e8f82005-07-25 12:33:22 -07004370 return;
4371 }
Matt Carlsonc6cdf432010-04-05 10:19:26 +00004372
Michael Chan747e8f82005-07-25 12:33:22 -07004373 if (!netif_carrier_ok(tp->dev) &&
4374 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4375 u32 bmcr;
4376
4377 tg3_readphy(tp, MII_BMCR, &bmcr);
4378 if (bmcr & BMCR_ANENABLE) {
4379 u32 phy1, phy2;
4380
4381 /* Select shadow register 0x1f */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00004382 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4383 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
Michael Chan747e8f82005-07-25 12:33:22 -07004384
4385 /* Select expansion interrupt status register */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00004386 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4387 MII_TG3_DSP_EXP1_INT_STAT);
4388 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4389 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
Michael Chan747e8f82005-07-25 12:33:22 -07004390
4391 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4392 /* We have signal detect and not receiving
4393 * config code words, link is up by parallel
4394 * detection.
4395 */
4396
4397 bmcr &= ~BMCR_ANENABLE;
4398 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4399 tg3_writephy(tp, MII_BMCR, bmcr);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004400 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004401 }
4402 }
Matt Carlson859a588792010-04-05 10:19:28 +00004403 } else if (netif_carrier_ok(tp->dev) &&
4404 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004405 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
Michael Chan747e8f82005-07-25 12:33:22 -07004406 u32 phy2;
4407
4408 /* Select expansion interrupt status register */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00004409 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4410 MII_TG3_DSP_EXP1_INT_STAT);
4411 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
Michael Chan747e8f82005-07-25 12:33:22 -07004412 if (phy2 & 0x20) {
4413 u32 bmcr;
4414
4415 /* Config code words received, turn on autoneg. */
4416 tg3_readphy(tp, MII_BMCR, &bmcr);
4417 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4418
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004419 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004420
4421 }
4422 }
4423}
4424
Linus Torvalds1da177e2005-04-16 15:20:36 -07004425static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4426{
Matt Carlsonf2096f92011-04-05 14:22:48 +00004427 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004428 int err;
4429
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004430 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004431 err = tg3_setup_fiber_phy(tp, force_reset);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004432 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chan747e8f82005-07-25 12:33:22 -07004433 err = tg3_setup_fiber_mii_phy(tp, force_reset);
Matt Carlson859a588792010-04-05 10:19:28 +00004434 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004435 err = tg3_setup_copper_phy(tp, force_reset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004436
Matt Carlsonbcb37f62008-11-03 16:52:09 -08004437 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
Matt Carlsonf2096f92011-04-05 14:22:48 +00004438 u32 scale;
Matt Carlsonaa6c91f2007-11-12 21:18:04 -08004439
4440 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4441 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4442 scale = 65;
4443 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4444 scale = 6;
4445 else
4446 scale = 12;
4447
4448 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4449 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4450 tw32(GRC_MISC_CFG, val);
4451 }
4452
Matt Carlsonf2096f92011-04-05 14:22:48 +00004453 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4454 (6 << TX_LENGTHS_IPG_SHIFT);
4455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4456 val |= tr32(MAC_TX_LENGTHS) &
4457 (TX_LENGTHS_JMB_FRM_LEN_MSK |
4458 TX_LENGTHS_CNT_DWN_VAL_MSK);
4459
Linus Torvalds1da177e2005-04-16 15:20:36 -07004460 if (tp->link_config.active_speed == SPEED_1000 &&
4461 tp->link_config.active_duplex == DUPLEX_HALF)
Matt Carlsonf2096f92011-04-05 14:22:48 +00004462 tw32(MAC_TX_LENGTHS, val |
4463 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004464 else
Matt Carlsonf2096f92011-04-05 14:22:48 +00004465 tw32(MAC_TX_LENGTHS, val |
4466 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004467
4468 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4469 if (netif_carrier_ok(tp->dev)) {
4470 tw32(HOSTCC_STAT_COAL_TICKS,
David S. Miller15f98502005-05-18 22:49:26 -07004471 tp->coal.stats_block_coalesce_usecs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004472 } else {
4473 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4474 }
4475 }
4476
Matt Carlson8ed5d972007-05-07 00:25:49 -07004477 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
Matt Carlsonf2096f92011-04-05 14:22:48 +00004478 val = tr32(PCIE_PWR_MGMT_THRESH);
Matt Carlson8ed5d972007-05-07 00:25:49 -07004479 if (!netif_carrier_ok(tp->dev))
4480 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4481 tp->pwrmgmt_thresh;
4482 else
4483 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4484 tw32(PCIE_PWR_MGMT_THRESH, val);
4485 }
4486
Linus Torvalds1da177e2005-04-16 15:20:36 -07004487 return err;
4488}
4489
Matt Carlson66cfd1b2010-09-30 10:34:30 +00004490static inline int tg3_irq_sync(struct tg3 *tp)
4491{
4492 return tp->irq_sync;
4493}
4494
Matt Carlson97bd8e42011-04-13 11:05:04 +00004495static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4496{
4497 int i;
4498
4499 dst = (u32 *)((u8 *)dst + off);
4500 for (i = 0; i < len; i += sizeof(u32))
4501 *dst++ = tr32(off + i);
4502}
4503
4504static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4505{
4506 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4507 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4508 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4509 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4510 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4511 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4512 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4513 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4514 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4515 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4516 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4517 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4518 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4519 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4520 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4521 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4522 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4523 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4524 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4525
4526 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)
4527 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4528
4529 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4530 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4531 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4532 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4533 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4534 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4535 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4536 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4537
4538 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4539 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4540 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4541 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4542 }
4543
4544 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4545 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4546 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4547 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4548 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4549
4550 if (tp->tg3_flags & TG3_FLAG_NVRAM)
4551 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4552}
4553
4554static void tg3_dump_state(struct tg3 *tp)
4555{
4556 int i;
4557 u32 *regs;
4558
4559 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4560 if (!regs) {
4561 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4562 return;
4563 }
4564
4565 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4566 /* Read up to but not including private PCI registers */
4567 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4568 regs[i / sizeof(u32)] = tr32(i);
4569 } else
4570 tg3_dump_legacy_regs(tp, regs);
4571
4572 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4573 if (!regs[i + 0] && !regs[i + 1] &&
4574 !regs[i + 2] && !regs[i + 3])
4575 continue;
4576
4577 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4578 i * 4,
4579 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4580 }
4581
4582 kfree(regs);
4583
4584 for (i = 0; i < tp->irq_cnt; i++) {
4585 struct tg3_napi *tnapi = &tp->napi[i];
4586
4587 /* SW status block */
4588 netdev_err(tp->dev,
4589 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4590 i,
4591 tnapi->hw_status->status,
4592 tnapi->hw_status->status_tag,
4593 tnapi->hw_status->rx_jumbo_consumer,
4594 tnapi->hw_status->rx_consumer,
4595 tnapi->hw_status->rx_mini_consumer,
4596 tnapi->hw_status->idx[0].rx_producer,
4597 tnapi->hw_status->idx[0].tx_consumer);
4598
4599 netdev_err(tp->dev,
4600 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4601 i,
4602 tnapi->last_tag, tnapi->last_irq_tag,
4603 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4604 tnapi->rx_rcb_ptr,
4605 tnapi->prodring.rx_std_prod_idx,
4606 tnapi->prodring.rx_std_cons_idx,
4607 tnapi->prodring.rx_jmb_prod_idx,
4608 tnapi->prodring.rx_jmb_cons_idx);
4609 }
4610}
4611
Michael Chandf3e6542006-05-26 17:48:07 -07004612/* This is called whenever we suspect that the system chipset is re-
4613 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4614 * is bogus tx completions. We try to recover by setting the
4615 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4616 * in the workqueue.
4617 */
4618static void tg3_tx_recover(struct tg3 *tp)
4619{
4620 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4621 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4622
Matt Carlson5129c3a2010-04-05 10:19:23 +00004623 netdev_warn(tp->dev,
4624 "The system may be re-ordering memory-mapped I/O "
4625 "cycles to the network device, attempting to recover. "
4626 "Please report the problem to the driver maintainer "
4627 "and include system chipset information.\n");
Michael Chandf3e6542006-05-26 17:48:07 -07004628
4629 spin_lock(&tp->lock);
Michael Chandf3e6542006-05-26 17:48:07 -07004630 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
Michael Chandf3e6542006-05-26 17:48:07 -07004631 spin_unlock(&tp->lock);
4632}
4633
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004634static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
Michael Chan1b2a7202006-08-07 21:46:02 -07004635{
Matt Carlsonf65aac12010-08-02 11:26:03 +00004636 /* Tell compiler to fetch tx indices from memory. */
4637 barrier();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004638 return tnapi->tx_pending -
4639 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
Michael Chan1b2a7202006-08-07 21:46:02 -07004640}
4641
Linus Torvalds1da177e2005-04-16 15:20:36 -07004642/* Tigon3 never reports partial packet sends. So we do not
4643 * need special logic to handle SKBs that have not had all
4644 * of their frags sent yet, like SunGEM does.
4645 */
Matt Carlson17375d22009-08-28 14:02:18 +00004646static void tg3_tx(struct tg3_napi *tnapi)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004647{
Matt Carlson17375d22009-08-28 14:02:18 +00004648 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00004649 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004650 u32 sw_idx = tnapi->tx_cons;
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004651 struct netdev_queue *txq;
4652 int index = tnapi - tp->napi;
4653
Matt Carlson19cfaec2009-12-03 08:36:20 +00004654 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004655 index--;
4656
4657 txq = netdev_get_tx_queue(tp->dev, index);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004658
4659 while (sw_idx != hw_idx) {
Alexander Duyckf4188d82009-12-02 16:48:38 +00004660 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004661 struct sk_buff *skb = ri->skb;
Michael Chandf3e6542006-05-26 17:48:07 -07004662 int i, tx_bug = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004663
Michael Chandf3e6542006-05-26 17:48:07 -07004664 if (unlikely(skb == NULL)) {
4665 tg3_tx_recover(tp);
4666 return;
4667 }
4668
Alexander Duyckf4188d82009-12-02 16:48:38 +00004669 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004670 dma_unmap_addr(ri, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00004671 skb_headlen(skb),
4672 PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004673
4674 ri->skb = NULL;
4675
4676 sw_idx = NEXT_TX(sw_idx);
4677
4678 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004679 ri = &tnapi->tx_buffers[sw_idx];
Michael Chandf3e6542006-05-26 17:48:07 -07004680 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4681 tx_bug = 1;
Alexander Duyckf4188d82009-12-02 16:48:38 +00004682
4683 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004684 dma_unmap_addr(ri, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00004685 skb_shinfo(skb)->frags[i].size,
4686 PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004687 sw_idx = NEXT_TX(sw_idx);
4688 }
4689
David S. Millerf47c11e2005-06-24 20:18:35 -07004690 dev_kfree_skb(skb);
Michael Chandf3e6542006-05-26 17:48:07 -07004691
4692 if (unlikely(tx_bug)) {
4693 tg3_tx_recover(tp);
4694 return;
4695 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004696 }
4697
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004698 tnapi->tx_cons = sw_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004699
Michael Chan1b2a7202006-08-07 21:46:02 -07004700 /* Need to make the tx_cons update visible to tg3_start_xmit()
4701 * before checking for netif_queue_stopped(). Without the
4702 * memory barrier, there is a small possibility that tg3_start_xmit()
4703 * will miss it and cause the queue to be stopped forever.
4704 */
4705 smp_mb();
4706
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004707 if (unlikely(netif_tx_queue_stopped(txq) &&
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004708 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004709 __netif_tx_lock(txq, smp_processor_id());
4710 if (netif_tx_queue_stopped(txq) &&
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004711 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004712 netif_tx_wake_queue(txq);
4713 __netif_tx_unlock(txq);
Michael Chan51b91462005-09-01 17:41:28 -07004714 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004715}
4716
Matt Carlson2b2cdb62009-11-13 13:03:48 +00004717static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4718{
4719 if (!ri->skb)
4720 return;
4721
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004722 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
Matt Carlson2b2cdb62009-11-13 13:03:48 +00004723 map_sz, PCI_DMA_FROMDEVICE);
4724 dev_kfree_skb_any(ri->skb);
4725 ri->skb = NULL;
4726}
4727
Linus Torvalds1da177e2005-04-16 15:20:36 -07004728/* Returns size of skb allocated or < 0 on error.
4729 *
4730 * We only need to fill in the address because the other members
4731 * of the RX descriptor are invariant, see tg3_init_rings.
4732 *
4733 * Note the purposeful assymetry of cpu vs. chip accesses. For
4734 * posting buffers we only dirty the first cache line of the RX
4735 * descriptor (containing the address). Whereas for the RX status
4736 * buffers the cpu only reads the last cacheline of the RX descriptor
4737 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4738 */
Matt Carlson86b21e52009-11-13 13:03:45 +00004739static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
Matt Carlsona3896162009-11-13 13:03:44 +00004740 u32 opaque_key, u32 dest_idx_unmasked)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004741{
4742 struct tg3_rx_buffer_desc *desc;
Matt Carlsonf94e2902010-10-14 10:37:42 +00004743 struct ring_info *map;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004744 struct sk_buff *skb;
4745 dma_addr_t mapping;
4746 int skb_size, dest_idx;
4747
Linus Torvalds1da177e2005-04-16 15:20:36 -07004748 switch (opaque_key) {
4749 case RXD_OPAQUE_RING_STD:
Matt Carlson2c49a442010-09-30 10:34:35 +00004750 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
Matt Carlson21f581a2009-08-28 14:00:25 +00004751 desc = &tpr->rx_std[dest_idx];
4752 map = &tpr->rx_std_buffers[dest_idx];
Matt Carlson287be122009-08-28 13:58:46 +00004753 skb_size = tp->rx_pkt_map_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004754 break;
4755
4756 case RXD_OPAQUE_RING_JUMBO:
Matt Carlson2c49a442010-09-30 10:34:35 +00004757 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
Matt Carlson79ed5ac2009-08-28 14:00:55 +00004758 desc = &tpr->rx_jmb[dest_idx].std;
Matt Carlson21f581a2009-08-28 14:00:25 +00004759 map = &tpr->rx_jmb_buffers[dest_idx];
Matt Carlson287be122009-08-28 13:58:46 +00004760 skb_size = TG3_RX_JMB_MAP_SZ;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004761 break;
4762
4763 default:
4764 return -EINVAL;
Stephen Hemminger855e1112008-04-16 16:37:28 -07004765 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004766
4767 /* Do not overwrite any of the map or rp information
4768 * until we are sure we can commit to a new buffer.
4769 *
4770 * Callers depend upon this behavior and assume that
4771 * we leave everything unchanged if we fail.
4772 */
Matt Carlson287be122009-08-28 13:58:46 +00004773 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004774 if (skb == NULL)
4775 return -ENOMEM;
4776
Linus Torvalds1da177e2005-04-16 15:20:36 -07004777 skb_reserve(skb, tp->rx_offset);
4778
Matt Carlson287be122009-08-28 13:58:46 +00004779 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004780 PCI_DMA_FROMDEVICE);
Matt Carlsona21771d2009-11-02 14:25:31 +00004781 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4782 dev_kfree_skb(skb);
4783 return -EIO;
4784 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004785
4786 map->skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004787 dma_unmap_addr_set(map, mapping, mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004788
Linus Torvalds1da177e2005-04-16 15:20:36 -07004789 desc->addr_hi = ((u64)mapping >> 32);
4790 desc->addr_lo = ((u64)mapping & 0xffffffff);
4791
4792 return skb_size;
4793}
4794
4795/* We only need to move over in the address because the other
4796 * members of the RX descriptor are invariant. See notes above
4797 * tg3_alloc_rx_skb for full details.
4798 */
Matt Carlsona3896162009-11-13 13:03:44 +00004799static void tg3_recycle_rx(struct tg3_napi *tnapi,
4800 struct tg3_rx_prodring_set *dpr,
4801 u32 opaque_key, int src_idx,
4802 u32 dest_idx_unmasked)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004803{
Matt Carlson17375d22009-08-28 14:02:18 +00004804 struct tg3 *tp = tnapi->tp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004805 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4806 struct ring_info *src_map, *dest_map;
Matt Carlson8fea32b2010-09-15 08:59:58 +00004807 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
Matt Carlsonc6cdf432010-04-05 10:19:26 +00004808 int dest_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004809
4810 switch (opaque_key) {
4811 case RXD_OPAQUE_RING_STD:
Matt Carlson2c49a442010-09-30 10:34:35 +00004812 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
Matt Carlsona3896162009-11-13 13:03:44 +00004813 dest_desc = &dpr->rx_std[dest_idx];
4814 dest_map = &dpr->rx_std_buffers[dest_idx];
4815 src_desc = &spr->rx_std[src_idx];
4816 src_map = &spr->rx_std_buffers[src_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004817 break;
4818
4819 case RXD_OPAQUE_RING_JUMBO:
Matt Carlson2c49a442010-09-30 10:34:35 +00004820 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
Matt Carlsona3896162009-11-13 13:03:44 +00004821 dest_desc = &dpr->rx_jmb[dest_idx].std;
4822 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4823 src_desc = &spr->rx_jmb[src_idx].std;
4824 src_map = &spr->rx_jmb_buffers[src_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004825 break;
4826
4827 default:
4828 return;
Stephen Hemminger855e1112008-04-16 16:37:28 -07004829 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004830
4831 dest_map->skb = src_map->skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004832 dma_unmap_addr_set(dest_map, mapping,
4833 dma_unmap_addr(src_map, mapping));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004834 dest_desc->addr_hi = src_desc->addr_hi;
4835 dest_desc->addr_lo = src_desc->addr_lo;
Matt Carlsone92967b2010-02-12 14:47:06 +00004836
4837 /* Ensure that the update to the skb happens after the physical
4838 * addresses have been transferred to the new BD location.
4839 */
4840 smp_wmb();
4841
Linus Torvalds1da177e2005-04-16 15:20:36 -07004842 src_map->skb = NULL;
4843}
4844
Linus Torvalds1da177e2005-04-16 15:20:36 -07004845/* The RX ring scheme is composed of multiple rings which post fresh
4846 * buffers to the chip, and one special ring the chip uses to report
4847 * status back to the host.
4848 *
4849 * The special ring reports the status of received packets to the
4850 * host. The chip does not write into the original descriptor the
4851 * RX buffer was obtained from. The chip simply takes the original
4852 * descriptor as provided by the host, updates the status and length
4853 * field, then writes this into the next status ring entry.
4854 *
4855 * Each ring the host uses to post buffers to the chip is described
4856 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4857 * it is first placed into the on-chip ram. When the packet's length
4858 * is known, it walks down the TG3_BDINFO entries to select the ring.
4859 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4860 * which is within the range of the new packet's length is chosen.
4861 *
4862 * The "separate ring for rx status" scheme may sound queer, but it makes
4863 * sense from a cache coherency perspective. If only the host writes
4864 * to the buffer post rings, and only the chip writes to the rx status
4865 * rings, then cache lines never move beyond shared-modified state.
4866 * If both the host and chip were to write into the same ring, cache line
4867 * eviction could occur since both entities want it in an exclusive state.
4868 */
Matt Carlson17375d22009-08-28 14:02:18 +00004869static int tg3_rx(struct tg3_napi *tnapi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004870{
Matt Carlson17375d22009-08-28 14:02:18 +00004871 struct tg3 *tp = tnapi->tp;
Michael Chanf92905d2006-06-29 20:14:29 -07004872 u32 work_mask, rx_std_posted = 0;
Matt Carlson43619352009-11-13 13:03:47 +00004873 u32 std_prod_idx, jmb_prod_idx;
Matt Carlson72334482009-08-28 14:03:01 +00004874 u32 sw_idx = tnapi->rx_rcb_ptr;
Michael Chan483ba502005-04-25 15:14:03 -07004875 u16 hw_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004876 int received;
Matt Carlson8fea32b2010-09-15 08:59:58 +00004877 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004878
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00004879 hw_idx = *(tnapi->rx_rcb_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004880 /*
4881 * We need to order the read of hw_idx and the read of
4882 * the opaque cookie.
4883 */
4884 rmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07004885 work_mask = 0;
4886 received = 0;
Matt Carlson43619352009-11-13 13:03:47 +00004887 std_prod_idx = tpr->rx_std_prod_idx;
4888 jmb_prod_idx = tpr->rx_jmb_prod_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004889 while (sw_idx != hw_idx && budget > 0) {
Matt Carlsonafc081f2009-11-13 13:03:43 +00004890 struct ring_info *ri;
Matt Carlson72334482009-08-28 14:03:01 +00004891 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004892 unsigned int len;
4893 struct sk_buff *skb;
4894 dma_addr_t dma_addr;
4895 u32 opaque_key, desc_idx, *post_ptr;
4896
4897 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4898 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4899 if (opaque_key == RXD_OPAQUE_RING_STD) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00004900 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004901 dma_addr = dma_unmap_addr(ri, mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00004902 skb = ri->skb;
Matt Carlson43619352009-11-13 13:03:47 +00004903 post_ptr = &std_prod_idx;
Michael Chanf92905d2006-06-29 20:14:29 -07004904 rx_std_posted++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004905 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00004906 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004907 dma_addr = dma_unmap_addr(ri, mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00004908 skb = ri->skb;
Matt Carlson43619352009-11-13 13:03:47 +00004909 post_ptr = &jmb_prod_idx;
Matt Carlson21f581a2009-08-28 14:00:25 +00004910 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004911 goto next_pkt_nopost;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004912
4913 work_mask |= opaque_key;
4914
4915 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4916 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4917 drop_it:
Matt Carlsona3896162009-11-13 13:03:44 +00004918 tg3_recycle_rx(tnapi, tpr, opaque_key,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004919 desc_idx, *post_ptr);
4920 drop_it_no_recycle:
4921 /* Other statistics kept track of by card. */
Eric Dumazetb0057c52010-10-10 19:55:52 +00004922 tp->rx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004923 goto next_pkt;
4924 }
4925
Matt Carlsonad829262008-11-21 17:16:16 -08004926 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4927 ETH_FCS_LEN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004928
Matt Carlsond2757fc2010-04-12 06:58:27 +00004929 if (len > TG3_RX_COPY_THRESH(tp)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004930 int skb_size;
4931
Matt Carlson86b21e52009-11-13 13:03:45 +00004932 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
Matt Carlsonafc081f2009-11-13 13:03:43 +00004933 *post_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004934 if (skb_size < 0)
4935 goto drop_it;
4936
Matt Carlson287be122009-08-28 13:58:46 +00004937 pci_unmap_single(tp->pdev, dma_addr, skb_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004938 PCI_DMA_FROMDEVICE);
4939
Matt Carlson61e800c2010-02-17 15:16:54 +00004940 /* Ensure that the update to the skb happens
4941 * after the usage of the old DMA mapping.
4942 */
4943 smp_wmb();
4944
4945 ri->skb = NULL;
4946
Linus Torvalds1da177e2005-04-16 15:20:36 -07004947 skb_put(skb, len);
4948 } else {
4949 struct sk_buff *copy_skb;
4950
Matt Carlsona3896162009-11-13 13:03:44 +00004951 tg3_recycle_rx(tnapi, tpr, opaque_key,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004952 desc_idx, *post_ptr);
4953
Matt Carlsonbf933c82011-01-25 15:58:49 +00004954 copy_skb = netdev_alloc_skb(tp->dev, len +
Matt Carlson9dc7a112010-04-12 06:58:28 +00004955 TG3_RAW_IP_ALIGN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004956 if (copy_skb == NULL)
4957 goto drop_it_no_recycle;
4958
Matt Carlsonbf933c82011-01-25 15:58:49 +00004959 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004960 skb_put(copy_skb, len);
4961 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -03004962 skb_copy_from_linear_data(skb, copy_skb->data, len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004963 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4964
4965 /* We'll reuse the original ring buffer. */
4966 skb = copy_skb;
4967 }
4968
Michał Mirosławdc668912011-04-07 03:35:07 +00004969 if ((tp->dev->features & NETIF_F_RXCSUM) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004970 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4971 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4972 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4973 skb->ip_summed = CHECKSUM_UNNECESSARY;
4974 else
Eric Dumazetbc8acf22010-09-02 13:07:41 -07004975 skb_checksum_none_assert(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004976
4977 skb->protocol = eth_type_trans(skb, tp->dev);
Matt Carlsonf7b493e2009-02-25 14:21:52 +00004978
4979 if (len > (tp->dev->mtu + ETH_HLEN) &&
4980 skb->protocol != htons(ETH_P_8021Q)) {
4981 dev_kfree_skb(skb);
Eric Dumazetb0057c52010-10-10 19:55:52 +00004982 goto drop_it_no_recycle;
Matt Carlsonf7b493e2009-02-25 14:21:52 +00004983 }
4984
Matt Carlson9dc7a112010-04-12 06:58:28 +00004985 if (desc->type_flags & RXD_FLAG_VLAN &&
Matt Carlsonbf933c82011-01-25 15:58:49 +00004986 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4987 __vlan_hwaccel_put_tag(skb,
4988 desc->err_vlan & RXD_VLAN_MASK);
Matt Carlson9dc7a112010-04-12 06:58:28 +00004989
Matt Carlsonbf933c82011-01-25 15:58:49 +00004990 napi_gro_receive(&tnapi->napi, skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004991
Linus Torvalds1da177e2005-04-16 15:20:36 -07004992 received++;
4993 budget--;
4994
4995next_pkt:
4996 (*post_ptr)++;
Michael Chanf92905d2006-06-29 20:14:29 -07004997
4998 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00004999 tpr->rx_std_prod_idx = std_prod_idx &
5000 tp->rx_std_ring_mask;
Matt Carlson86cfe4f2010-01-12 10:11:37 +00005001 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5002 tpr->rx_std_prod_idx);
Michael Chanf92905d2006-06-29 20:14:29 -07005003 work_mask &= ~RXD_OPAQUE_RING_STD;
5004 rx_std_posted = 0;
5005 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005006next_pkt_nopost:
Michael Chan483ba502005-04-25 15:14:03 -07005007 sw_idx++;
Matt Carlson7cb32cf2010-09-30 10:34:36 +00005008 sw_idx &= tp->rx_ret_ring_mask;
Michael Chan52f6d692005-04-25 15:14:32 -07005009
5010 /* Refresh hw_idx to see if there is new work */
5011 if (sw_idx == hw_idx) {
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00005012 hw_idx = *(tnapi->rx_rcb_prod_idx);
Michael Chan52f6d692005-04-25 15:14:32 -07005013 rmb();
5014 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005015 }
5016
5017 /* ACK the status ring. */
Matt Carlson72334482009-08-28 14:03:01 +00005018 tnapi->rx_rcb_ptr = sw_idx;
5019 tw32_rx_mbox(tnapi->consmbox, sw_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005020
5021 /* Refill RX ring(s). */
Matt Carlsone4af1af2010-02-12 14:47:05 +00005022 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005023 if (work_mask & RXD_OPAQUE_RING_STD) {
Matt Carlson2c49a442010-09-30 10:34:35 +00005024 tpr->rx_std_prod_idx = std_prod_idx &
5025 tp->rx_std_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005026 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5027 tpr->rx_std_prod_idx);
5028 }
5029 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
Matt Carlson2c49a442010-09-30 10:34:35 +00005030 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5031 tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005032 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5033 tpr->rx_jmb_prod_idx);
5034 }
5035 mmiowb();
5036 } else if (work_mask) {
5037 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5038 * updated before the producer indices can be updated.
5039 */
5040 smp_wmb();
5041
Matt Carlson2c49a442010-09-30 10:34:35 +00005042 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5043 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005044
Matt Carlsone4af1af2010-02-12 14:47:05 +00005045 if (tnapi != &tp->napi[1])
5046 napi_schedule(&tp->napi[1].napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005047 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005048
5049 return received;
5050}
5051
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005052static void tg3_poll_link(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005053{
Linus Torvalds1da177e2005-04-16 15:20:36 -07005054 /* handle link change and other phy events */
5055 if (!(tp->tg3_flags &
5056 (TG3_FLAG_USE_LINKCHG_REG |
5057 TG3_FLAG_POLL_SERDES))) {
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005058 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5059
Linus Torvalds1da177e2005-04-16 15:20:36 -07005060 if (sblk->status & SD_STATUS_LINK_CHG) {
5061 sblk->status = SD_STATUS_UPDATED |
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005062 (sblk->status & ~SD_STATUS_LINK_CHG);
David S. Millerf47c11e2005-06-24 20:18:35 -07005063 spin_lock(&tp->lock);
Matt Carlsondd477002008-05-25 23:45:58 -07005064 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
5065 tw32_f(MAC_STATUS,
5066 (MAC_STATUS_SYNC_CHANGED |
5067 MAC_STATUS_CFG_CHANGED |
5068 MAC_STATUS_MI_COMPLETION |
5069 MAC_STATUS_LNKSTATE_CHANGED));
5070 udelay(40);
5071 } else
5072 tg3_setup_phy(tp, 0);
David S. Millerf47c11e2005-06-24 20:18:35 -07005073 spin_unlock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005074 }
5075 }
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005076}
5077
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005078static int tg3_rx_prodring_xfer(struct tg3 *tp,
5079 struct tg3_rx_prodring_set *dpr,
5080 struct tg3_rx_prodring_set *spr)
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005081{
5082 u32 si, di, cpycnt, src_prod_idx;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005083 int i, err = 0;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005084
5085 while (1) {
5086 src_prod_idx = spr->rx_std_prod_idx;
5087
5088 /* Make sure updates to the rx_std_buffers[] entries and the
5089 * standard producer index are seen in the correct order.
5090 */
5091 smp_rmb();
5092
5093 if (spr->rx_std_cons_idx == src_prod_idx)
5094 break;
5095
5096 if (spr->rx_std_cons_idx < src_prod_idx)
5097 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5098 else
Matt Carlson2c49a442010-09-30 10:34:35 +00005099 cpycnt = tp->rx_std_ring_mask + 1 -
5100 spr->rx_std_cons_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005101
Matt Carlson2c49a442010-09-30 10:34:35 +00005102 cpycnt = min(cpycnt,
5103 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005104
5105 si = spr->rx_std_cons_idx;
5106 di = dpr->rx_std_prod_idx;
5107
Matt Carlsone92967b2010-02-12 14:47:06 +00005108 for (i = di; i < di + cpycnt; i++) {
5109 if (dpr->rx_std_buffers[i].skb) {
5110 cpycnt = i - di;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005111 err = -ENOSPC;
Matt Carlsone92967b2010-02-12 14:47:06 +00005112 break;
5113 }
5114 }
5115
5116 if (!cpycnt)
5117 break;
5118
5119 /* Ensure that updates to the rx_std_buffers ring and the
5120 * shadowed hardware producer ring from tg3_recycle_skb() are
5121 * ordered correctly WRT the skb check above.
5122 */
5123 smp_rmb();
5124
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005125 memcpy(&dpr->rx_std_buffers[di],
5126 &spr->rx_std_buffers[si],
5127 cpycnt * sizeof(struct ring_info));
5128
5129 for (i = 0; i < cpycnt; i++, di++, si++) {
5130 struct tg3_rx_buffer_desc *sbd, *dbd;
5131 sbd = &spr->rx_std[si];
5132 dbd = &dpr->rx_std[di];
5133 dbd->addr_hi = sbd->addr_hi;
5134 dbd->addr_lo = sbd->addr_lo;
5135 }
5136
Matt Carlson2c49a442010-09-30 10:34:35 +00005137 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5138 tp->rx_std_ring_mask;
5139 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5140 tp->rx_std_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005141 }
5142
5143 while (1) {
5144 src_prod_idx = spr->rx_jmb_prod_idx;
5145
5146 /* Make sure updates to the rx_jmb_buffers[] entries and
5147 * the jumbo producer index are seen in the correct order.
5148 */
5149 smp_rmb();
5150
5151 if (spr->rx_jmb_cons_idx == src_prod_idx)
5152 break;
5153
5154 if (spr->rx_jmb_cons_idx < src_prod_idx)
5155 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5156 else
Matt Carlson2c49a442010-09-30 10:34:35 +00005157 cpycnt = tp->rx_jmb_ring_mask + 1 -
5158 spr->rx_jmb_cons_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005159
5160 cpycnt = min(cpycnt,
Matt Carlson2c49a442010-09-30 10:34:35 +00005161 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005162
5163 si = spr->rx_jmb_cons_idx;
5164 di = dpr->rx_jmb_prod_idx;
5165
Matt Carlsone92967b2010-02-12 14:47:06 +00005166 for (i = di; i < di + cpycnt; i++) {
5167 if (dpr->rx_jmb_buffers[i].skb) {
5168 cpycnt = i - di;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005169 err = -ENOSPC;
Matt Carlsone92967b2010-02-12 14:47:06 +00005170 break;
5171 }
5172 }
5173
5174 if (!cpycnt)
5175 break;
5176
5177 /* Ensure that updates to the rx_jmb_buffers ring and the
5178 * shadowed hardware producer ring from tg3_recycle_skb() are
5179 * ordered correctly WRT the skb check above.
5180 */
5181 smp_rmb();
5182
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005183 memcpy(&dpr->rx_jmb_buffers[di],
5184 &spr->rx_jmb_buffers[si],
5185 cpycnt * sizeof(struct ring_info));
5186
5187 for (i = 0; i < cpycnt; i++, di++, si++) {
5188 struct tg3_rx_buffer_desc *sbd, *dbd;
5189 sbd = &spr->rx_jmb[si].std;
5190 dbd = &dpr->rx_jmb[di].std;
5191 dbd->addr_hi = sbd->addr_hi;
5192 dbd->addr_lo = sbd->addr_lo;
5193 }
5194
Matt Carlson2c49a442010-09-30 10:34:35 +00005195 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5196 tp->rx_jmb_ring_mask;
5197 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5198 tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005199 }
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005200
5201 return err;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005202}
5203
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005204static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5205{
5206 struct tg3 *tp = tnapi->tp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005207
5208 /* run TX completion thread */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005209 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
Matt Carlson17375d22009-08-28 14:02:18 +00005210 tg3_tx(tnapi);
David S. Miller6f535762007-10-11 18:08:29 -07005211 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
Michael Chan4fd7ab52007-10-12 01:39:50 -07005212 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005213 }
5214
Linus Torvalds1da177e2005-04-16 15:20:36 -07005215 /* run RX thread, within the bounds set by NAPI.
5216 * All RX "locking" is done by ensuring outside
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005217 * code synchronizes with tg3->napi.poll()
Linus Torvalds1da177e2005-04-16 15:20:36 -07005218 */
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00005219 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
Matt Carlson17375d22009-08-28 14:02:18 +00005220 work_done += tg3_rx(tnapi, budget - work_done);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005221
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005222 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00005223 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005224 int i, err = 0;
Matt Carlsone4af1af2010-02-12 14:47:05 +00005225 u32 std_prod_idx = dpr->rx_std_prod_idx;
5226 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005227
Matt Carlsone4af1af2010-02-12 14:47:05 +00005228 for (i = 1; i < tp->irq_cnt; i++)
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005229 err |= tg3_rx_prodring_xfer(tp, dpr,
Matt Carlson8fea32b2010-09-15 08:59:58 +00005230 &tp->napi[i].prodring);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005231
5232 wmb();
5233
Matt Carlsone4af1af2010-02-12 14:47:05 +00005234 if (std_prod_idx != dpr->rx_std_prod_idx)
5235 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5236 dpr->rx_std_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005237
Matt Carlsone4af1af2010-02-12 14:47:05 +00005238 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5239 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5240 dpr->rx_jmb_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005241
5242 mmiowb();
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005243
5244 if (err)
5245 tw32_f(HOSTCC_MODE, tp->coal_now);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005246 }
5247
David S. Miller6f535762007-10-11 18:08:29 -07005248 return work_done;
5249}
David S. Millerf7383c22005-05-18 22:50:53 -07005250
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005251static int tg3_poll_msix(struct napi_struct *napi, int budget)
5252{
5253 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5254 struct tg3 *tp = tnapi->tp;
5255 int work_done = 0;
5256 struct tg3_hw_status *sblk = tnapi->hw_status;
5257
5258 while (1) {
5259 work_done = tg3_poll_work(tnapi, work_done, budget);
5260
5261 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5262 goto tx_recovery;
5263
5264 if (unlikely(work_done >= budget))
5265 break;
5266
Matt Carlsonc6cdf432010-04-05 10:19:26 +00005267 /* tp->last_tag is used in tg3_int_reenable() below
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005268 * to tell the hw how much work has been processed,
5269 * so we must read it before checking for more work.
5270 */
5271 tnapi->last_tag = sblk->status_tag;
5272 tnapi->last_irq_tag = tnapi->last_tag;
5273 rmb();
5274
5275 /* check for RX/TX work to do */
Matt Carlson6d40db72010-04-05 10:19:20 +00005276 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5277 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005278 napi_complete(napi);
5279 /* Reenable interrupts. */
5280 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5281 mmiowb();
5282 break;
5283 }
5284 }
5285
5286 return work_done;
5287
5288tx_recovery:
5289 /* work_done is guaranteed to be less than budget. */
5290 napi_complete(napi);
5291 schedule_work(&tp->reset_task);
5292 return work_done;
5293}
5294
Matt Carlsone64de4e2011-04-13 11:05:05 +00005295static void tg3_process_error(struct tg3 *tp)
5296{
5297 u32 val;
5298 bool real_error = false;
5299
5300 if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED)
5301 return;
5302
5303 /* Check Flow Attention register */
5304 val = tr32(HOSTCC_FLOW_ATTN);
5305 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5306 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
5307 real_error = true;
5308 }
5309
5310 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5311 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
5312 real_error = true;
5313 }
5314
5315 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5316 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
5317 real_error = true;
5318 }
5319
5320 if (!real_error)
5321 return;
5322
5323 tg3_dump_state(tp);
5324
5325 tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED;
5326 schedule_work(&tp->reset_task);
5327}
5328
David S. Miller6f535762007-10-11 18:08:29 -07005329static int tg3_poll(struct napi_struct *napi, int budget)
5330{
Matt Carlson8ef04422009-08-28 14:01:37 +00005331 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5332 struct tg3 *tp = tnapi->tp;
David S. Miller6f535762007-10-11 18:08:29 -07005333 int work_done = 0;
Matt Carlson898a56f2009-08-28 14:02:40 +00005334 struct tg3_hw_status *sblk = tnapi->hw_status;
David S. Miller6f535762007-10-11 18:08:29 -07005335
5336 while (1) {
Matt Carlsone64de4e2011-04-13 11:05:05 +00005337 if (sblk->status & SD_STATUS_ERROR)
5338 tg3_process_error(tp);
5339
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005340 tg3_poll_link(tp);
5341
Matt Carlson17375d22009-08-28 14:02:18 +00005342 work_done = tg3_poll_work(tnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07005343
5344 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5345 goto tx_recovery;
5346
5347 if (unlikely(work_done >= budget))
5348 break;
5349
Michael Chan4fd7ab52007-10-12 01:39:50 -07005350 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
Matt Carlson17375d22009-08-28 14:02:18 +00005351 /* tp->last_tag is used in tg3_int_reenable() below
Michael Chan4fd7ab52007-10-12 01:39:50 -07005352 * to tell the hw how much work has been processed,
5353 * so we must read it before checking for more work.
5354 */
Matt Carlson898a56f2009-08-28 14:02:40 +00005355 tnapi->last_tag = sblk->status_tag;
5356 tnapi->last_irq_tag = tnapi->last_tag;
Michael Chan4fd7ab52007-10-12 01:39:50 -07005357 rmb();
5358 } else
5359 sblk->status &= ~SD_STATUS_UPDATED;
5360
Matt Carlson17375d22009-08-28 14:02:18 +00005361 if (likely(!tg3_has_work(tnapi))) {
Ben Hutchings288379f2009-01-19 16:43:59 -08005362 napi_complete(napi);
Matt Carlson17375d22009-08-28 14:02:18 +00005363 tg3_int_reenable(tnapi);
David S. Miller6f535762007-10-11 18:08:29 -07005364 break;
5365 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005366 }
5367
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005368 return work_done;
David S. Miller6f535762007-10-11 18:08:29 -07005369
5370tx_recovery:
Michael Chan4fd7ab52007-10-12 01:39:50 -07005371 /* work_done is guaranteed to be less than budget. */
Ben Hutchings288379f2009-01-19 16:43:59 -08005372 napi_complete(napi);
David S. Miller6f535762007-10-11 18:08:29 -07005373 schedule_work(&tp->reset_task);
Michael Chan4fd7ab52007-10-12 01:39:50 -07005374 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005375}
5376
Matt Carlson66cfd1b2010-09-30 10:34:30 +00005377static void tg3_napi_disable(struct tg3 *tp)
5378{
5379 int i;
5380
5381 for (i = tp->irq_cnt - 1; i >= 0; i--)
5382 napi_disable(&tp->napi[i].napi);
5383}
5384
5385static void tg3_napi_enable(struct tg3 *tp)
5386{
5387 int i;
5388
5389 for (i = 0; i < tp->irq_cnt; i++)
5390 napi_enable(&tp->napi[i].napi);
5391}
5392
5393static void tg3_napi_init(struct tg3 *tp)
5394{
5395 int i;
5396
5397 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5398 for (i = 1; i < tp->irq_cnt; i++)
5399 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5400}
5401
5402static void tg3_napi_fini(struct tg3 *tp)
5403{
5404 int i;
5405
5406 for (i = 0; i < tp->irq_cnt; i++)
5407 netif_napi_del(&tp->napi[i].napi);
5408}
5409
5410static inline void tg3_netif_stop(struct tg3 *tp)
5411{
5412 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5413 tg3_napi_disable(tp);
5414 netif_tx_disable(tp->dev);
5415}
5416
5417static inline void tg3_netif_start(struct tg3 *tp)
5418{
5419 /* NOTE: unconditional netif_tx_wake_all_queues is only
5420 * appropriate so long as all callers are assured to
5421 * have free tx slots (such as after tg3_init_hw)
5422 */
5423 netif_tx_wake_all_queues(tp->dev);
5424
5425 tg3_napi_enable(tp);
5426 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5427 tg3_enable_ints(tp);
5428}
5429
David S. Millerf47c11e2005-06-24 20:18:35 -07005430static void tg3_irq_quiesce(struct tg3 *tp)
5431{
Matt Carlson4f125f42009-09-01 12:55:02 +00005432 int i;
5433
David S. Millerf47c11e2005-06-24 20:18:35 -07005434 BUG_ON(tp->irq_sync);
5435
5436 tp->irq_sync = 1;
5437 smp_mb();
5438
Matt Carlson4f125f42009-09-01 12:55:02 +00005439 for (i = 0; i < tp->irq_cnt; i++)
5440 synchronize_irq(tp->napi[i].irq_vec);
David S. Millerf47c11e2005-06-24 20:18:35 -07005441}
5442
David S. Millerf47c11e2005-06-24 20:18:35 -07005443/* Fully shutdown all tg3 driver activity elsewhere in the system.
5444 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5445 * with as well. Most of the time, this is not necessary except when
5446 * shutting down the device.
5447 */
5448static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5449{
Michael Chan46966542007-07-11 19:47:19 -07005450 spin_lock_bh(&tp->lock);
David S. Millerf47c11e2005-06-24 20:18:35 -07005451 if (irq_sync)
5452 tg3_irq_quiesce(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07005453}
5454
5455static inline void tg3_full_unlock(struct tg3 *tp)
5456{
David S. Millerf47c11e2005-06-24 20:18:35 -07005457 spin_unlock_bh(&tp->lock);
5458}
5459
Michael Chanfcfa0a32006-03-20 22:28:41 -08005460/* One-shot MSI handler - Chip automatically disables interrupt
5461 * after sending MSI so driver doesn't have to do it.
5462 */
David Howells7d12e782006-10-05 14:55:46 +01005463static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
Michael Chanfcfa0a32006-03-20 22:28:41 -08005464{
Matt Carlson09943a12009-08-28 14:01:57 +00005465 struct tg3_napi *tnapi = dev_id;
5466 struct tg3 *tp = tnapi->tp;
Michael Chanfcfa0a32006-03-20 22:28:41 -08005467
Matt Carlson898a56f2009-08-28 14:02:40 +00005468 prefetch(tnapi->hw_status);
Matt Carlson0c1d0e22009-09-01 13:16:33 +00005469 if (tnapi->rx_rcb)
5470 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Michael Chanfcfa0a32006-03-20 22:28:41 -08005471
5472 if (likely(!tg3_irq_sync(tp)))
Matt Carlson09943a12009-08-28 14:01:57 +00005473 napi_schedule(&tnapi->napi);
Michael Chanfcfa0a32006-03-20 22:28:41 -08005474
5475 return IRQ_HANDLED;
5476}
5477
Michael Chan88b06bc22005-04-21 17:13:25 -07005478/* MSI ISR - No need to check for interrupt sharing and no need to
5479 * flush status block and interrupt mailbox. PCI ordering rules
5480 * guarantee that MSI will arrive after the status block.
5481 */
David Howells7d12e782006-10-05 14:55:46 +01005482static irqreturn_t tg3_msi(int irq, void *dev_id)
Michael Chan88b06bc22005-04-21 17:13:25 -07005483{
Matt Carlson09943a12009-08-28 14:01:57 +00005484 struct tg3_napi *tnapi = dev_id;
5485 struct tg3 *tp = tnapi->tp;
Michael Chan88b06bc22005-04-21 17:13:25 -07005486
Matt Carlson898a56f2009-08-28 14:02:40 +00005487 prefetch(tnapi->hw_status);
Matt Carlson0c1d0e22009-09-01 13:16:33 +00005488 if (tnapi->rx_rcb)
5489 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Michael Chan88b06bc22005-04-21 17:13:25 -07005490 /*
David S. Millerfac9b832005-05-18 22:46:34 -07005491 * Writing any value to intr-mbox-0 clears PCI INTA# and
Michael Chan88b06bc22005-04-21 17:13:25 -07005492 * chip-internal interrupt pending events.
David S. Millerfac9b832005-05-18 22:46:34 -07005493 * Writing non-zero to intr-mbox-0 additional tells the
Michael Chan88b06bc22005-04-21 17:13:25 -07005494 * NIC to stop sending us irqs, engaging "in-intr-handler"
5495 * event coalescing.
5496 */
5497 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Michael Chan61487482005-09-05 17:53:19 -07005498 if (likely(!tg3_irq_sync(tp)))
Matt Carlson09943a12009-08-28 14:01:57 +00005499 napi_schedule(&tnapi->napi);
Michael Chan61487482005-09-05 17:53:19 -07005500
Michael Chan88b06bc22005-04-21 17:13:25 -07005501 return IRQ_RETVAL(1);
5502}
5503
David Howells7d12e782006-10-05 14:55:46 +01005504static irqreturn_t tg3_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005505{
Matt Carlson09943a12009-08-28 14:01:57 +00005506 struct tg3_napi *tnapi = dev_id;
5507 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00005508 struct tg3_hw_status *sblk = tnapi->hw_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005509 unsigned int handled = 1;
5510
Linus Torvalds1da177e2005-04-16 15:20:36 -07005511 /* In INTx mode, it is possible for the interrupt to arrive at
5512 * the CPU before the status block posted prior to the interrupt.
5513 * Reading the PCI State register will confirm whether the
5514 * interrupt is ours and will flush the status block.
5515 */
Michael Chand18edcb2007-03-24 20:57:11 -07005516 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5517 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5518 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5519 handled = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07005520 goto out;
David S. Millerfac9b832005-05-18 22:46:34 -07005521 }
Michael Chand18edcb2007-03-24 20:57:11 -07005522 }
5523
5524 /*
5525 * Writing any value to intr-mbox-0 clears PCI INTA# and
5526 * chip-internal interrupt pending events.
5527 * Writing non-zero to intr-mbox-0 additional tells the
5528 * NIC to stop sending us irqs, engaging "in-intr-handler"
5529 * event coalescing.
Michael Chanc04cb342007-05-07 00:26:15 -07005530 *
5531 * Flush the mailbox to de-assert the IRQ immediately to prevent
5532 * spurious interrupts. The flush impacts performance but
5533 * excessive spurious interrupts can be worse in some cases.
Michael Chand18edcb2007-03-24 20:57:11 -07005534 */
Michael Chanc04cb342007-05-07 00:26:15 -07005535 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Michael Chand18edcb2007-03-24 20:57:11 -07005536 if (tg3_irq_sync(tp))
5537 goto out;
5538 sblk->status &= ~SD_STATUS_UPDATED;
Matt Carlson17375d22009-08-28 14:02:18 +00005539 if (likely(tg3_has_work(tnapi))) {
Matt Carlson72334482009-08-28 14:03:01 +00005540 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Matt Carlson09943a12009-08-28 14:01:57 +00005541 napi_schedule(&tnapi->napi);
Michael Chand18edcb2007-03-24 20:57:11 -07005542 } else {
5543 /* No work, shared interrupt perhaps? re-enable
5544 * interrupts, and flush that PCI write
5545 */
5546 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5547 0x00000000);
David S. Millerfac9b832005-05-18 22:46:34 -07005548 }
David S. Millerf47c11e2005-06-24 20:18:35 -07005549out:
David S. Millerfac9b832005-05-18 22:46:34 -07005550 return IRQ_RETVAL(handled);
5551}
5552
David Howells7d12e782006-10-05 14:55:46 +01005553static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
David S. Millerfac9b832005-05-18 22:46:34 -07005554{
Matt Carlson09943a12009-08-28 14:01:57 +00005555 struct tg3_napi *tnapi = dev_id;
5556 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00005557 struct tg3_hw_status *sblk = tnapi->hw_status;
David S. Millerfac9b832005-05-18 22:46:34 -07005558 unsigned int handled = 1;
5559
David S. Millerfac9b832005-05-18 22:46:34 -07005560 /* In INTx mode, it is possible for the interrupt to arrive at
5561 * the CPU before the status block posted prior to the interrupt.
5562 * Reading the PCI State register will confirm whether the
5563 * interrupt is ours and will flush the status block.
5564 */
Matt Carlson898a56f2009-08-28 14:02:40 +00005565 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
Michael Chand18edcb2007-03-24 20:57:11 -07005566 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5567 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5568 handled = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07005569 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005570 }
Michael Chand18edcb2007-03-24 20:57:11 -07005571 }
5572
5573 /*
5574 * writing any value to intr-mbox-0 clears PCI INTA# and
5575 * chip-internal interrupt pending events.
5576 * writing non-zero to intr-mbox-0 additional tells the
5577 * NIC to stop sending us irqs, engaging "in-intr-handler"
5578 * event coalescing.
Michael Chanc04cb342007-05-07 00:26:15 -07005579 *
5580 * Flush the mailbox to de-assert the IRQ immediately to prevent
5581 * spurious interrupts. The flush impacts performance but
5582 * excessive spurious interrupts can be worse in some cases.
Michael Chand18edcb2007-03-24 20:57:11 -07005583 */
Michael Chanc04cb342007-05-07 00:26:15 -07005584 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Matt Carlson624f8e52009-04-20 06:55:01 +00005585
5586 /*
5587 * In a shared interrupt configuration, sometimes other devices'
5588 * interrupts will scream. We record the current status tag here
5589 * so that the above check can report that the screaming interrupts
5590 * are unhandled. Eventually they will be silenced.
5591 */
Matt Carlson898a56f2009-08-28 14:02:40 +00005592 tnapi->last_irq_tag = sblk->status_tag;
Matt Carlson624f8e52009-04-20 06:55:01 +00005593
Michael Chand18edcb2007-03-24 20:57:11 -07005594 if (tg3_irq_sync(tp))
5595 goto out;
Matt Carlson624f8e52009-04-20 06:55:01 +00005596
Matt Carlson72334482009-08-28 14:03:01 +00005597 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Matt Carlson624f8e52009-04-20 06:55:01 +00005598
Matt Carlson09943a12009-08-28 14:01:57 +00005599 napi_schedule(&tnapi->napi);
Matt Carlson624f8e52009-04-20 06:55:01 +00005600
David S. Millerf47c11e2005-06-24 20:18:35 -07005601out:
Linus Torvalds1da177e2005-04-16 15:20:36 -07005602 return IRQ_RETVAL(handled);
5603}
5604
Michael Chan79381092005-04-21 17:13:59 -07005605/* ISR for interrupt test */
David Howells7d12e782006-10-05 14:55:46 +01005606static irqreturn_t tg3_test_isr(int irq, void *dev_id)
Michael Chan79381092005-04-21 17:13:59 -07005607{
Matt Carlson09943a12009-08-28 14:01:57 +00005608 struct tg3_napi *tnapi = dev_id;
5609 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00005610 struct tg3_hw_status *sblk = tnapi->hw_status;
Michael Chan79381092005-04-21 17:13:59 -07005611
Michael Chanf9804dd2005-09-27 12:13:10 -07005612 if ((sblk->status & SD_STATUS_UPDATED) ||
5613 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
Michael Chanb16250e2006-09-27 16:10:14 -07005614 tg3_disable_ints(tp);
Michael Chan79381092005-04-21 17:13:59 -07005615 return IRQ_RETVAL(1);
5616 }
5617 return IRQ_RETVAL(0);
5618}
5619
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07005620static int tg3_init_hw(struct tg3 *, int);
Michael Chan944d9802005-05-29 14:57:48 -07005621static int tg3_halt(struct tg3 *, int, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005622
Michael Chanb9ec6c12006-07-25 16:37:27 -07005623/* Restart hardware after configuration changes, self-test, etc.
5624 * Invoked with tp->lock held.
5625 */
5626static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
Eric Dumazet78c61462008-04-24 23:33:06 -07005627 __releases(tp->lock)
5628 __acquires(tp->lock)
Michael Chanb9ec6c12006-07-25 16:37:27 -07005629{
5630 int err;
5631
5632 err = tg3_init_hw(tp, reset_phy);
5633 if (err) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00005634 netdev_err(tp->dev,
5635 "Failed to re-initialize device, aborting\n");
Michael Chanb9ec6c12006-07-25 16:37:27 -07005636 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5637 tg3_full_unlock(tp);
5638 del_timer_sync(&tp->timer);
5639 tp->irq_sync = 0;
Matt Carlsonfed97812009-09-01 13:10:19 +00005640 tg3_napi_enable(tp);
Michael Chanb9ec6c12006-07-25 16:37:27 -07005641 dev_close(tp->dev);
5642 tg3_full_lock(tp, 0);
5643 }
5644 return err;
5645}
5646
Linus Torvalds1da177e2005-04-16 15:20:36 -07005647#ifdef CONFIG_NET_POLL_CONTROLLER
5648static void tg3_poll_controller(struct net_device *dev)
5649{
Matt Carlson4f125f42009-09-01 12:55:02 +00005650 int i;
Michael Chan88b06bc22005-04-21 17:13:25 -07005651 struct tg3 *tp = netdev_priv(dev);
5652
Matt Carlson4f125f42009-09-01 12:55:02 +00005653 for (i = 0; i < tp->irq_cnt; i++)
Louis Rillingfe234f02010-03-09 06:14:41 +00005654 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005655}
5656#endif
5657
David Howellsc4028952006-11-22 14:57:56 +00005658static void tg3_reset_task(struct work_struct *work)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005659{
David Howellsc4028952006-11-22 14:57:56 +00005660 struct tg3 *tp = container_of(work, struct tg3, reset_task);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07005661 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005662 unsigned int restart_timer;
5663
Michael Chan7faa0062006-02-02 17:29:28 -08005664 tg3_full_lock(tp, 0);
Michael Chan7faa0062006-02-02 17:29:28 -08005665
5666 if (!netif_running(tp->dev)) {
Michael Chan7faa0062006-02-02 17:29:28 -08005667 tg3_full_unlock(tp);
5668 return;
5669 }
5670
5671 tg3_full_unlock(tp);
5672
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07005673 tg3_phy_stop(tp);
5674
Linus Torvalds1da177e2005-04-16 15:20:36 -07005675 tg3_netif_stop(tp);
5676
David S. Millerf47c11e2005-06-24 20:18:35 -07005677 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005678
5679 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5680 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5681
Michael Chandf3e6542006-05-26 17:48:07 -07005682 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5683 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5684 tp->write32_rx_mbox = tg3_write_flush_reg32;
5685 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5686 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5687 }
5688
Michael Chan944d9802005-05-29 14:57:48 -07005689 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07005690 err = tg3_init_hw(tp, 1);
5691 if (err)
Michael Chanb9ec6c12006-07-25 16:37:27 -07005692 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005693
5694 tg3_netif_start(tp);
5695
Linus Torvalds1da177e2005-04-16 15:20:36 -07005696 if (restart_timer)
5697 mod_timer(&tp->timer, jiffies + 1);
Michael Chan7faa0062006-02-02 17:29:28 -08005698
Michael Chanb9ec6c12006-07-25 16:37:27 -07005699out:
Michael Chan7faa0062006-02-02 17:29:28 -08005700 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07005701
5702 if (!err)
5703 tg3_phy_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005704}
5705
5706static void tg3_tx_timeout(struct net_device *dev)
5707{
5708 struct tg3 *tp = netdev_priv(dev);
5709
Michael Chanb0408752007-02-13 12:18:30 -08005710 if (netif_msg_tx_err(tp)) {
Joe Perches05dbe002010-02-17 19:44:19 +00005711 netdev_err(dev, "transmit timed out, resetting\n");
Matt Carlson97bd8e42011-04-13 11:05:04 +00005712 tg3_dump_state(tp);
Michael Chanb0408752007-02-13 12:18:30 -08005713 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005714
5715 schedule_work(&tp->reset_task);
5716}
5717
Michael Chanc58ec932005-09-17 00:46:27 -07005718/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5719static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5720{
5721 u32 base = (u32) mapping & 0xffffffff;
5722
Eric Dumazet807540b2010-09-23 05:40:09 +00005723 return (base > 0xffffdcc0) && (base + len + 8 < base);
Michael Chanc58ec932005-09-17 00:46:27 -07005724}
5725
Michael Chan72f2afb2006-03-06 19:28:35 -08005726/* Test for DMA addresses > 40-bit */
5727static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5728 int len)
5729{
5730#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
Michael Chan6728a8e2006-03-27 23:16:49 -08005731 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
Eric Dumazet807540b2010-09-23 05:40:09 +00005732 return ((u64) mapping + len) > DMA_BIT_MASK(40);
Michael Chan72f2afb2006-03-06 19:28:35 -08005733 return 0;
5734#else
5735 return 0;
5736#endif
5737}
5738
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005739static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005740
Michael Chan72f2afb2006-03-06 19:28:35 -08005741/* Workaround 4GB and 40-bit hardware DMA bugs. */
Matt Carlson24f4efd2009-11-13 13:03:35 +00005742static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5743 struct sk_buff *skb, u32 last_plus_one,
5744 u32 *start, u32 base_flags, u32 mss)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005745{
Matt Carlson24f4efd2009-11-13 13:03:35 +00005746 struct tg3 *tp = tnapi->tp;
Matt Carlson41588ba2008-04-19 18:12:33 -07005747 struct sk_buff *new_skb;
Michael Chanc58ec932005-09-17 00:46:27 -07005748 dma_addr_t new_addr = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005749 u32 entry = *start;
Michael Chanc58ec932005-09-17 00:46:27 -07005750 int i, ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005751
Matt Carlson41588ba2008-04-19 18:12:33 -07005752 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5753 new_skb = skb_copy(skb, GFP_ATOMIC);
5754 else {
5755 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5756
5757 new_skb = skb_copy_expand(skb,
5758 skb_headroom(skb) + more_headroom,
5759 skb_tailroom(skb), GFP_ATOMIC);
5760 }
5761
Linus Torvalds1da177e2005-04-16 15:20:36 -07005762 if (!new_skb) {
Michael Chanc58ec932005-09-17 00:46:27 -07005763 ret = -1;
5764 } else {
5765 /* New SKB is guaranteed to be linear. */
5766 entry = *start;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005767 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5768 PCI_DMA_TODEVICE);
5769 /* Make sure the mapping succeeded */
5770 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5771 ret = -1;
5772 dev_kfree_skb(new_skb);
5773 new_skb = NULL;
David S. Miller90079ce2008-09-11 04:52:51 -07005774
Michael Chanc58ec932005-09-17 00:46:27 -07005775 /* Make sure new skb does not cross any 4G boundaries.
5776 * Drop the packet if it does.
5777 */
Alexander Duyckf4188d82009-12-02 16:48:38 +00005778 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5779 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5780 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5781 PCI_DMA_TODEVICE);
Michael Chanc58ec932005-09-17 00:46:27 -07005782 ret = -1;
5783 dev_kfree_skb(new_skb);
5784 new_skb = NULL;
5785 } else {
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005786 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
Michael Chanc58ec932005-09-17 00:46:27 -07005787 base_flags, 1 | (mss << 1));
5788 *start = NEXT_TX(entry);
5789 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005790 }
5791
Linus Torvalds1da177e2005-04-16 15:20:36 -07005792 /* Now clean up the sw ring entries. */
5793 i = 0;
5794 while (entry != last_plus_one) {
Alexander Duyckf4188d82009-12-02 16:48:38 +00005795 int len;
5796
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005797 if (i == 0)
Alexander Duyckf4188d82009-12-02 16:48:38 +00005798 len = skb_headlen(skb);
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005799 else
Alexander Duyckf4188d82009-12-02 16:48:38 +00005800 len = skb_shinfo(skb)->frags[i-1].size;
5801
5802 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005803 dma_unmap_addr(&tnapi->tx_buffers[entry],
Alexander Duyckf4188d82009-12-02 16:48:38 +00005804 mapping),
5805 len, PCI_DMA_TODEVICE);
5806 if (i == 0) {
5807 tnapi->tx_buffers[entry].skb = new_skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005808 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
Alexander Duyckf4188d82009-12-02 16:48:38 +00005809 new_addr);
5810 } else {
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005811 tnapi->tx_buffers[entry].skb = NULL;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005812 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005813 entry = NEXT_TX(entry);
5814 i++;
5815 }
5816
5817 dev_kfree_skb(skb);
5818
Michael Chanc58ec932005-09-17 00:46:27 -07005819 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005820}
5821
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005822static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005823 dma_addr_t mapping, int len, u32 flags,
5824 u32 mss_and_is_end)
5825{
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005826 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005827 int is_end = (mss_and_is_end & 0x1);
5828 u32 mss = (mss_and_is_end >> 1);
5829 u32 vlan_tag = 0;
5830
5831 if (is_end)
5832 flags |= TXD_FLAG_END;
5833 if (flags & TXD_FLAG_VLAN) {
5834 vlan_tag = flags >> 16;
5835 flags &= 0xffff;
5836 }
5837 vlan_tag |= (mss << TXD_MSS_SHIFT);
5838
5839 txd->addr_hi = ((u64) mapping >> 32);
5840 txd->addr_lo = ((u64) mapping & 0xffffffff);
5841 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5842 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5843}
5844
Michael Chan5a6f3072006-03-20 22:28:05 -08005845/* hard_start_xmit for devices that don't have any bugs and
Matt Carlsone849cdc2009-11-13 13:03:38 +00005846 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
Michael Chan5a6f3072006-03-20 22:28:05 -08005847 */
Stephen Hemminger613573252009-08-31 19:50:58 +00005848static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5849 struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005850{
5851 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005852 u32 len, entry, base_flags, mss;
David S. Miller90079ce2008-09-11 04:52:51 -07005853 dma_addr_t mapping;
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005854 struct tg3_napi *tnapi;
5855 struct netdev_queue *txq;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005856 unsigned int i, last;
5857
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005858 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5859 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
Matt Carlson19cfaec2009-12-03 08:36:20 +00005860 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005861 tnapi++;
Michael Chan5a6f3072006-03-20 22:28:05 -08005862
Michael Chan00b70502006-06-17 21:58:45 -07005863 /* We are running in BH disabled context with netif_tx_lock
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005864 * and TX reclaim runs via tp->napi.poll inside of a software
Michael Chan5a6f3072006-03-20 22:28:05 -08005865 * interrupt. Furthermore, IRQ processing runs lockless so we have
5866 * no IRQ context deadlocks to worry about either. Rejoice!
5867 */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005868 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005869 if (!netif_tx_queue_stopped(txq)) {
5870 netif_tx_stop_queue(txq);
Michael Chan5a6f3072006-03-20 22:28:05 -08005871
5872 /* This is a hard error, log it. */
Matt Carlson5129c3a2010-04-05 10:19:23 +00005873 netdev_err(dev,
5874 "BUG! Tx Ring full when queue awake!\n");
Michael Chan5a6f3072006-03-20 22:28:05 -08005875 }
Michael Chan5a6f3072006-03-20 22:28:05 -08005876 return NETDEV_TX_BUSY;
5877 }
5878
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005879 entry = tnapi->tx_prod;
Michael Chan5a6f3072006-03-20 22:28:05 -08005880 base_flags = 0;
Matt Carlsonbe98da62010-07-11 09:31:46 +00005881 mss = skb_shinfo(skb)->gso_size;
5882 if (mss) {
Michael Chan5a6f3072006-03-20 22:28:05 -08005883 int tcp_opt_len, ip_tcp_len;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005884 u32 hdrlen;
Michael Chan5a6f3072006-03-20 22:28:05 -08005885
5886 if (skb_header_cloned(skb) &&
5887 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5888 dev_kfree_skb(skb);
5889 goto out_unlock;
5890 }
5891
Matt Carlson02e96082010-09-15 08:59:59 +00005892 if (skb_is_gso_v6(skb)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005893 hdrlen = skb_headlen(skb) - ETH_HLEN;
Matt Carlson02e96082010-09-15 08:59:59 +00005894 } else {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005895 struct iphdr *iph = ip_hdr(skb);
5896
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07005897 tcp_opt_len = tcp_optlen(skb);
Arnaldo Carvalho de Meloc9bdd4b2007-03-12 20:09:15 -03005898 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
Michael Chanb0026622006-07-03 19:42:14 -07005899
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005900 iph->check = 0;
5901 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005902 hdrlen = ip_tcp_len + tcp_opt_len;
Michael Chanb0026622006-07-03 19:42:14 -07005903 }
Michael Chan5a6f3072006-03-20 22:28:05 -08005904
Matt Carlsone849cdc2009-11-13 13:03:38 +00005905 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005906 mss |= (hdrlen & 0xc) << 12;
5907 if (hdrlen & 0x10)
5908 base_flags |= 0x00000010;
5909 base_flags |= (hdrlen & 0x3e0) << 5;
5910 } else
5911 mss |= hdrlen << 9;
5912
Michael Chan5a6f3072006-03-20 22:28:05 -08005913 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5914 TXD_FLAG_CPU_POST_DMA);
5915
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07005916 tcp_hdr(skb)->check = 0;
Michael Chan5a6f3072006-03-20 22:28:05 -08005917
Matt Carlson859a588792010-04-05 10:19:28 +00005918 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
Michael Chan5a6f3072006-03-20 22:28:05 -08005919 base_flags |= TXD_FLAG_TCPUDP_CSUM;
Matt Carlson859a588792010-04-05 10:19:28 +00005920 }
5921
Jesse Grosseab6d182010-10-20 13:56:03 +00005922 if (vlan_tx_tag_present(skb))
Michael Chan5a6f3072006-03-20 22:28:05 -08005923 base_flags |= (TXD_FLAG_VLAN |
5924 (vlan_tx_tag_get(skb) << 16));
Michael Chan5a6f3072006-03-20 22:28:05 -08005925
Alexander Duyckf4188d82009-12-02 16:48:38 +00005926 len = skb_headlen(skb);
5927
5928 /* Queue skb data, a.k.a. the main skb fragment. */
5929 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5930 if (pci_dma_mapping_error(tp->pdev, mapping)) {
David S. Miller90079ce2008-09-11 04:52:51 -07005931 dev_kfree_skb(skb);
5932 goto out_unlock;
5933 }
5934
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005935 tnapi->tx_buffers[entry].skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005936 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005937
Matt Carlsonb703df62009-12-03 08:36:21 +00005938 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
Matt Carlson8fc2f992010-12-06 08:28:49 +00005939 !mss && skb->len > VLAN_ETH_FRAME_LEN)
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005940 base_flags |= TXD_FLAG_JMB_PKT;
5941
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005942 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
Michael Chan5a6f3072006-03-20 22:28:05 -08005943 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5944
5945 entry = NEXT_TX(entry);
5946
5947 /* Now loop through additional data fragments, and queue them. */
5948 if (skb_shinfo(skb)->nr_frags > 0) {
Michael Chan5a6f3072006-03-20 22:28:05 -08005949 last = skb_shinfo(skb)->nr_frags - 1;
5950 for (i = 0; i <= last; i++) {
5951 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5952
5953 len = frag->size;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005954 mapping = pci_map_page(tp->pdev,
5955 frag->page,
5956 frag->page_offset,
5957 len, PCI_DMA_TODEVICE);
5958 if (pci_dma_mapping_error(tp->pdev, mapping))
5959 goto dma_error;
5960
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005961 tnapi->tx_buffers[entry].skb = NULL;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005962 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
Alexander Duyckf4188d82009-12-02 16:48:38 +00005963 mapping);
Michael Chan5a6f3072006-03-20 22:28:05 -08005964
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005965 tg3_set_txd(tnapi, entry, mapping, len,
Michael Chan5a6f3072006-03-20 22:28:05 -08005966 base_flags, (i == last) | (mss << 1));
5967
5968 entry = NEXT_TX(entry);
5969 }
5970 }
5971
5972 /* Packets are ready, update Tx producer idx local and on card. */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005973 tw32_tx_mbox(tnapi->prodmbox, entry);
Michael Chan5a6f3072006-03-20 22:28:05 -08005974
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005975 tnapi->tx_prod = entry;
5976 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005977 netif_tx_stop_queue(txq);
Matt Carlsonf65aac12010-08-02 11:26:03 +00005978
5979 /* netif_tx_stop_queue() must be done before checking
5980 * checking tx index in tg3_tx_avail() below, because in
5981 * tg3_tx(), we update tx index before checking for
5982 * netif_tx_queue_stopped().
5983 */
5984 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005985 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005986 netif_tx_wake_queue(txq);
Michael Chan5a6f3072006-03-20 22:28:05 -08005987 }
5988
5989out_unlock:
Eric Dumazetcdd0db02009-05-28 00:00:41 +00005990 mmiowb();
Michael Chan5a6f3072006-03-20 22:28:05 -08005991
5992 return NETDEV_TX_OK;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005993
5994dma_error:
5995 last = i;
5996 entry = tnapi->tx_prod;
5997 tnapi->tx_buffers[entry].skb = NULL;
5998 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005999 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00006000 skb_headlen(skb),
6001 PCI_DMA_TODEVICE);
6002 for (i = 0; i <= last; i++) {
6003 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6004 entry = NEXT_TX(entry);
6005
6006 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006007 dma_unmap_addr(&tnapi->tx_buffers[entry],
Alexander Duyckf4188d82009-12-02 16:48:38 +00006008 mapping),
6009 frag->size, PCI_DMA_TODEVICE);
6010 }
6011
6012 dev_kfree_skb(skb);
6013 return NETDEV_TX_OK;
Michael Chan5a6f3072006-03-20 22:28:05 -08006014}
6015
Stephen Hemminger613573252009-08-31 19:50:58 +00006016static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
6017 struct net_device *);
Michael Chan52c0fd82006-06-29 20:15:54 -07006018
6019/* Use GSO to workaround a rare TSO bug that may be triggered when the
6020 * TSO header is greater than 80 bytes.
6021 */
6022static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6023{
6024 struct sk_buff *segs, *nskb;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006025 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
Michael Chan52c0fd82006-06-29 20:15:54 -07006026
6027 /* Estimate the number of fragments in the worst case */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006028 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
Michael Chan52c0fd82006-06-29 20:15:54 -07006029 netif_stop_queue(tp->dev);
Matt Carlsonf65aac12010-08-02 11:26:03 +00006030
6031 /* netif_tx_stop_queue() must be done before checking
6032 * checking tx index in tg3_tx_avail() below, because in
6033 * tg3_tx(), we update tx index before checking for
6034 * netif_tx_queue_stopped().
6035 */
6036 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006037 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
Michael Chan7f62ad52007-02-20 23:25:40 -08006038 return NETDEV_TX_BUSY;
6039
6040 netif_wake_queue(tp->dev);
Michael Chan52c0fd82006-06-29 20:15:54 -07006041 }
6042
6043 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
Hirofumi Nakagawa801678c2008-04-29 01:03:09 -07006044 if (IS_ERR(segs))
Michael Chan52c0fd82006-06-29 20:15:54 -07006045 goto tg3_tso_bug_end;
6046
6047 do {
6048 nskb = segs;
6049 segs = segs->next;
6050 nskb->next = NULL;
6051 tg3_start_xmit_dma_bug(nskb, tp->dev);
6052 } while (segs);
6053
6054tg3_tso_bug_end:
6055 dev_kfree_skb(skb);
6056
6057 return NETDEV_TX_OK;
6058}
Michael Chan52c0fd82006-06-29 20:15:54 -07006059
Michael Chan5a6f3072006-03-20 22:28:05 -08006060/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6061 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
6062 */
Stephen Hemminger613573252009-08-31 19:50:58 +00006063static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6064 struct net_device *dev)
Michael Chan5a6f3072006-03-20 22:28:05 -08006065{
6066 struct tg3 *tp = netdev_priv(dev);
Michael Chan5a6f3072006-03-20 22:28:05 -08006067 u32 len, entry, base_flags, mss;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006068 int would_hit_hwbug;
David S. Miller90079ce2008-09-11 04:52:51 -07006069 dma_addr_t mapping;
Matt Carlson24f4efd2009-11-13 13:03:35 +00006070 struct tg3_napi *tnapi;
6071 struct netdev_queue *txq;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006072 unsigned int i, last;
6073
Matt Carlson24f4efd2009-11-13 13:03:35 +00006074 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6075 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
Matt Carlson19cfaec2009-12-03 08:36:20 +00006076 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
Matt Carlson24f4efd2009-11-13 13:03:35 +00006077 tnapi++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006078
Michael Chan00b70502006-06-17 21:58:45 -07006079 /* We are running in BH disabled context with netif_tx_lock
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006080 * and TX reclaim runs via tp->napi.poll inside of a software
David S. Millerf47c11e2005-06-24 20:18:35 -07006081 * interrupt. Furthermore, IRQ processing runs lockless so we have
6082 * no IRQ context deadlocks to worry about either. Rejoice!
Linus Torvalds1da177e2005-04-16 15:20:36 -07006083 */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006084 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
Matt Carlson24f4efd2009-11-13 13:03:35 +00006085 if (!netif_tx_queue_stopped(txq)) {
6086 netif_tx_stop_queue(txq);
Stephen Hemminger1f064a82005-12-06 17:36:44 -08006087
6088 /* This is a hard error, log it. */
Matt Carlson5129c3a2010-04-05 10:19:23 +00006089 netdev_err(dev,
6090 "BUG! Tx Ring full when queue awake!\n");
Stephen Hemminger1f064a82005-12-06 17:36:44 -08006091 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006092 return NETDEV_TX_BUSY;
6093 }
6094
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006095 entry = tnapi->tx_prod;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006096 base_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07006097 if (skb->ip_summed == CHECKSUM_PARTIAL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006098 base_flags |= TXD_FLAG_TCPUDP_CSUM;
Matt Carlson24f4efd2009-11-13 13:03:35 +00006099
Matt Carlsonbe98da62010-07-11 09:31:46 +00006100 mss = skb_shinfo(skb)->gso_size;
6101 if (mss) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006102 struct iphdr *iph;
Matt Carlson34195c32010-07-11 09:31:42 +00006103 u32 tcp_opt_len, hdr_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006104
6105 if (skb_header_cloned(skb) &&
6106 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6107 dev_kfree_skb(skb);
6108 goto out_unlock;
6109 }
6110
Matt Carlson34195c32010-07-11 09:31:42 +00006111 iph = ip_hdr(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07006112 tcp_opt_len = tcp_optlen(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006113
Matt Carlson02e96082010-09-15 08:59:59 +00006114 if (skb_is_gso_v6(skb)) {
Matt Carlson34195c32010-07-11 09:31:42 +00006115 hdr_len = skb_headlen(skb) - ETH_HLEN;
6116 } else {
6117 u32 ip_tcp_len;
6118
6119 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6120 hdr_len = ip_tcp_len + tcp_opt_len;
6121
6122 iph->check = 0;
6123 iph->tot_len = htons(mss + hdr_len);
6124 }
6125
Michael Chan52c0fd82006-06-29 20:15:54 -07006126 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
Michael Chan7f62ad52007-02-20 23:25:40 -08006127 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
Matt Carlsonde6f31e2010-04-12 06:58:30 +00006128 return tg3_tso_bug(tp, skb);
Michael Chan52c0fd82006-06-29 20:15:54 -07006129
Linus Torvalds1da177e2005-04-16 15:20:36 -07006130 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6131 TXD_FLAG_CPU_POST_DMA);
6132
Linus Torvalds1da177e2005-04-16 15:20:36 -07006133 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07006134 tcp_hdr(skb)->check = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006135 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07006136 } else
6137 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6138 iph->daddr, 0,
6139 IPPROTO_TCP,
6140 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006141
Matt Carlson615774f2009-11-13 13:03:39 +00006142 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
6143 mss |= (hdr_len & 0xc) << 12;
6144 if (hdr_len & 0x10)
6145 base_flags |= 0x00000010;
6146 base_flags |= (hdr_len & 0x3e0) << 5;
6147 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
Matt Carlson92c6b8d2009-11-02 14:23:27 +00006148 mss |= hdr_len << 9;
6149 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
6150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006151 if (tcp_opt_len || iph->ihl > 5) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006152 int tsflags;
6153
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006154 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006155 mss |= (tsflags << 11);
6156 }
6157 } else {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006158 if (tcp_opt_len || iph->ihl > 5) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006159 int tsflags;
6160
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006161 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006162 base_flags |= tsflags << 12;
6163 }
6164 }
6165 }
Matt Carlsonbf933c82011-01-25 15:58:49 +00006166
Jesse Grosseab6d182010-10-20 13:56:03 +00006167 if (vlan_tx_tag_present(skb))
Linus Torvalds1da177e2005-04-16 15:20:36 -07006168 base_flags |= (TXD_FLAG_VLAN |
6169 (vlan_tx_tag_get(skb) << 16));
Linus Torvalds1da177e2005-04-16 15:20:36 -07006170
Matt Carlsonb703df62009-12-03 08:36:21 +00006171 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
Matt Carlson8fc2f992010-12-06 08:28:49 +00006172 !mss && skb->len > VLAN_ETH_FRAME_LEN)
Matt Carlson615774f2009-11-13 13:03:39 +00006173 base_flags |= TXD_FLAG_JMB_PKT;
6174
Alexander Duyckf4188d82009-12-02 16:48:38 +00006175 len = skb_headlen(skb);
6176
6177 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6178 if (pci_dma_mapping_error(tp->pdev, mapping)) {
David S. Miller90079ce2008-09-11 04:52:51 -07006179 dev_kfree_skb(skb);
6180 goto out_unlock;
6181 }
6182
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006183 tnapi->tx_buffers[entry].skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006184 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006185
6186 would_hit_hwbug = 0;
6187
Matt Carlson92c6b8d2009-11-02 14:23:27 +00006188 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6189 would_hit_hwbug = 1;
6190
Matt Carlson0e1406d2009-11-02 12:33:33 +00006191 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6192 tg3_4g_overflow_test(mapping, len))
Matt Carlson41588ba2008-04-19 18:12:33 -07006193 would_hit_hwbug = 1;
Matt Carlson0e1406d2009-11-02 12:33:33 +00006194
6195 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6196 tg3_40bit_overflow_test(tp, mapping, len))
6197 would_hit_hwbug = 1;
6198
6199 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
Michael Chanc58ec932005-09-17 00:46:27 -07006200 would_hit_hwbug = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006201
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006202 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006203 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6204
6205 entry = NEXT_TX(entry);
6206
6207 /* Now loop through additional data fragments, and queue them. */
6208 if (skb_shinfo(skb)->nr_frags > 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006209 last = skb_shinfo(skb)->nr_frags - 1;
6210 for (i = 0; i <= last; i++) {
6211 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6212
6213 len = frag->size;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006214 mapping = pci_map_page(tp->pdev,
6215 frag->page,
6216 frag->page_offset,
6217 len, PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006218
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006219 tnapi->tx_buffers[entry].skb = NULL;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006220 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
Alexander Duyckf4188d82009-12-02 16:48:38 +00006221 mapping);
6222 if (pci_dma_mapping_error(tp->pdev, mapping))
6223 goto dma_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006224
Matt Carlson92c6b8d2009-11-02 14:23:27 +00006225 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6226 len <= 8)
6227 would_hit_hwbug = 1;
6228
Matt Carlson0e1406d2009-11-02 12:33:33 +00006229 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6230 tg3_4g_overflow_test(mapping, len))
Michael Chanc58ec932005-09-17 00:46:27 -07006231 would_hit_hwbug = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006232
Matt Carlson0e1406d2009-11-02 12:33:33 +00006233 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6234 tg3_40bit_overflow_test(tp, mapping, len))
Michael Chan72f2afb2006-03-06 19:28:35 -08006235 would_hit_hwbug = 1;
6236
Linus Torvalds1da177e2005-04-16 15:20:36 -07006237 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006238 tg3_set_txd(tnapi, entry, mapping, len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006239 base_flags, (i == last)|(mss << 1));
6240 else
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006241 tg3_set_txd(tnapi, entry, mapping, len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006242 base_flags, (i == last));
6243
6244 entry = NEXT_TX(entry);
6245 }
6246 }
6247
6248 if (would_hit_hwbug) {
6249 u32 last_plus_one = entry;
6250 u32 start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006251
Michael Chanc58ec932005-09-17 00:46:27 -07006252 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6253 start &= (TG3_TX_RING_SIZE - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006254
6255 /* If the workaround fails due to memory/mapping
6256 * failure, silently drop this packet.
6257 */
Matt Carlson24f4efd2009-11-13 13:03:35 +00006258 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
Michael Chanc58ec932005-09-17 00:46:27 -07006259 &start, base_flags, mss))
Linus Torvalds1da177e2005-04-16 15:20:36 -07006260 goto out_unlock;
6261
6262 entry = start;
6263 }
6264
6265 /* Packets are ready, update Tx producer idx local and on card. */
Matt Carlson24f4efd2009-11-13 13:03:35 +00006266 tw32_tx_mbox(tnapi->prodmbox, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006267
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006268 tnapi->tx_prod = entry;
6269 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
Matt Carlson24f4efd2009-11-13 13:03:35 +00006270 netif_tx_stop_queue(txq);
Matt Carlsonf65aac12010-08-02 11:26:03 +00006271
6272 /* netif_tx_stop_queue() must be done before checking
6273 * checking tx index in tg3_tx_avail() below, because in
6274 * tg3_tx(), we update tx index before checking for
6275 * netif_tx_queue_stopped().
6276 */
6277 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006278 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
Matt Carlson24f4efd2009-11-13 13:03:35 +00006279 netif_tx_wake_queue(txq);
Michael Chan51b91462005-09-01 17:41:28 -07006280 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006281
6282out_unlock:
Eric Dumazetcdd0db02009-05-28 00:00:41 +00006283 mmiowb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07006284
6285 return NETDEV_TX_OK;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006286
6287dma_error:
6288 last = i;
6289 entry = tnapi->tx_prod;
6290 tnapi->tx_buffers[entry].skb = NULL;
6291 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006292 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00006293 skb_headlen(skb),
6294 PCI_DMA_TODEVICE);
6295 for (i = 0; i <= last; i++) {
6296 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6297 entry = NEXT_TX(entry);
6298
6299 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006300 dma_unmap_addr(&tnapi->tx_buffers[entry],
Alexander Duyckf4188d82009-12-02 16:48:38 +00006301 mapping),
6302 frag->size, PCI_DMA_TODEVICE);
6303 }
6304
6305 dev_kfree_skb(skb);
6306 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006307}
6308
Michał Mirosławdc668912011-04-07 03:35:07 +00006309static u32 tg3_fix_features(struct net_device *dev, u32 features)
6310{
6311 struct tg3 *tp = netdev_priv(dev);
6312
6313 if (dev->mtu > ETH_DATA_LEN && (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6314 features &= ~NETIF_F_ALL_TSO;
6315
6316 return features;
6317}
6318
Linus Torvalds1da177e2005-04-16 15:20:36 -07006319static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6320 int new_mtu)
6321{
6322 dev->mtu = new_mtu;
6323
Michael Chanef7f5ec2005-07-25 12:32:25 -07006324 if (new_mtu > ETH_DATA_LEN) {
Michael Chana4e2b342005-10-26 15:46:52 -07006325 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
Michał Mirosławdc668912011-04-07 03:35:07 +00006326 netdev_update_features(dev);
Michael Chanef7f5ec2005-07-25 12:32:25 -07006327 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
Matt Carlson859a588792010-04-05 10:19:28 +00006328 } else {
Michael Chanef7f5ec2005-07-25 12:32:25 -07006329 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
Matt Carlson859a588792010-04-05 10:19:28 +00006330 }
Michael Chanef7f5ec2005-07-25 12:32:25 -07006331 } else {
Michał Mirosławdc668912011-04-07 03:35:07 +00006332 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
Michael Chanef7f5ec2005-07-25 12:32:25 -07006333 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
Michał Mirosławdc668912011-04-07 03:35:07 +00006334 netdev_update_features(dev);
6335 }
Michael Chan0f893dc2005-07-25 12:30:38 -07006336 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
Michael Chanef7f5ec2005-07-25 12:32:25 -07006337 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006338}
6339
6340static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6341{
6342 struct tg3 *tp = netdev_priv(dev);
Michael Chanb9ec6c12006-07-25 16:37:27 -07006343 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006344
6345 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6346 return -EINVAL;
6347
6348 if (!netif_running(dev)) {
6349 /* We'll just catch it later when the
6350 * device is up'd.
6351 */
6352 tg3_set_mtu(dev, tp, new_mtu);
6353 return 0;
6354 }
6355
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07006356 tg3_phy_stop(tp);
6357
Linus Torvalds1da177e2005-04-16 15:20:36 -07006358 tg3_netif_stop(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07006359
6360 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006361
Michael Chan944d9802005-05-29 14:57:48 -07006362 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006363
6364 tg3_set_mtu(dev, tp, new_mtu);
6365
Michael Chanb9ec6c12006-07-25 16:37:27 -07006366 err = tg3_restart_hw(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006367
Michael Chanb9ec6c12006-07-25 16:37:27 -07006368 if (!err)
6369 tg3_netif_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006370
David S. Millerf47c11e2005-06-24 20:18:35 -07006371 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006372
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07006373 if (!err)
6374 tg3_phy_start(tp);
6375
Michael Chanb9ec6c12006-07-25 16:37:27 -07006376 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006377}
6378
Matt Carlson21f581a2009-08-28 14:00:25 +00006379static void tg3_rx_prodring_free(struct tg3 *tp,
6380 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006381{
Linus Torvalds1da177e2005-04-16 15:20:36 -07006382 int i;
6383
Matt Carlson8fea32b2010-09-15 08:59:58 +00006384 if (tpr != &tp->napi[0].prodring) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006385 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
Matt Carlson2c49a442010-09-30 10:34:35 +00006386 i = (i + 1) & tp->rx_std_ring_mask)
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006387 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6388 tp->rx_pkt_map_sz);
6389
6390 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6391 for (i = tpr->rx_jmb_cons_idx;
6392 i != tpr->rx_jmb_prod_idx;
Matt Carlson2c49a442010-09-30 10:34:35 +00006393 i = (i + 1) & tp->rx_jmb_ring_mask) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006394 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6395 TG3_RX_JMB_MAP_SZ);
6396 }
6397 }
6398
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006399 return;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006400 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006401
Matt Carlson2c49a442010-09-30 10:34:35 +00006402 for (i = 0; i <= tp->rx_std_ring_mask; i++)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006403 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6404 tp->rx_pkt_map_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006405
Matt Carlson48035722010-10-14 10:37:43 +00006406 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6407 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00006408 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006409 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6410 TG3_RX_JMB_MAP_SZ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006411 }
6412}
6413
Matt Carlsonc6cdf432010-04-05 10:19:26 +00006414/* Initialize rx rings for packet processing.
Linus Torvalds1da177e2005-04-16 15:20:36 -07006415 *
6416 * The chip has been shut down and the driver detached from
6417 * the networking, so no interrupts or new tx packets will
6418 * end up in the driver. tp->{tx,}lock are held and thus
6419 * we may not sleep.
6420 */
Matt Carlson21f581a2009-08-28 14:00:25 +00006421static int tg3_rx_prodring_alloc(struct tg3 *tp,
6422 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006423{
Matt Carlson287be122009-08-28 13:58:46 +00006424 u32 i, rx_pkt_dma_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006425
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006426 tpr->rx_std_cons_idx = 0;
6427 tpr->rx_std_prod_idx = 0;
6428 tpr->rx_jmb_cons_idx = 0;
6429 tpr->rx_jmb_prod_idx = 0;
6430
Matt Carlson8fea32b2010-09-15 08:59:58 +00006431 if (tpr != &tp->napi[0].prodring) {
Matt Carlson2c49a442010-09-30 10:34:35 +00006432 memset(&tpr->rx_std_buffers[0], 0,
6433 TG3_RX_STD_BUFF_RING_SIZE(tp));
Matt Carlson48035722010-10-14 10:37:43 +00006434 if (tpr->rx_jmb_buffers)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006435 memset(&tpr->rx_jmb_buffers[0], 0,
Matt Carlson2c49a442010-09-30 10:34:35 +00006436 TG3_RX_JMB_BUFF_RING_SIZE(tp));
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006437 goto done;
6438 }
6439
Linus Torvalds1da177e2005-04-16 15:20:36 -07006440 /* Zero out all descriptors. */
Matt Carlson2c49a442010-09-30 10:34:35 +00006441 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
Linus Torvalds1da177e2005-04-16 15:20:36 -07006442
Matt Carlson287be122009-08-28 13:58:46 +00006443 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
Michael Chana4e2b342005-10-26 15:46:52 -07006444 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
Matt Carlson287be122009-08-28 13:58:46 +00006445 tp->dev->mtu > ETH_DATA_LEN)
6446 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6447 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
Michael Chan7e72aad2005-07-25 12:31:17 -07006448
Linus Torvalds1da177e2005-04-16 15:20:36 -07006449 /* Initialize invariants of the rings, we only set this
6450 * stuff once. This works because the card does not
6451 * write into the rx buffer posting rings.
6452 */
Matt Carlson2c49a442010-09-30 10:34:35 +00006453 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006454 struct tg3_rx_buffer_desc *rxd;
6455
Matt Carlson21f581a2009-08-28 14:00:25 +00006456 rxd = &tpr->rx_std[i];
Matt Carlson287be122009-08-28 13:58:46 +00006457 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006458 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6459 rxd->opaque = (RXD_OPAQUE_RING_STD |
6460 (i << RXD_OPAQUE_INDEX_SHIFT));
6461 }
6462
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006463 /* Now allocate fresh SKBs for each rx ring. */
6464 for (i = 0; i < tp->rx_pending; i++) {
Matt Carlson86b21e52009-11-13 13:03:45 +00006465 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00006466 netdev_warn(tp->dev,
6467 "Using a smaller RX standard ring. Only "
6468 "%d out of %d buffers were allocated "
6469 "successfully\n", i, tp->rx_pending);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006470 if (i == 0)
6471 goto initfail;
6472 tp->rx_pending = i;
6473 break;
6474 }
6475 }
6476
Matt Carlson48035722010-10-14 10:37:43 +00006477 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6478 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006479 goto done;
6480
Matt Carlson2c49a442010-09-30 10:34:35 +00006481 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006482
Matt Carlson0d86df82010-02-17 15:17:00 +00006483 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6484 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006485
Matt Carlson2c49a442010-09-30 10:34:35 +00006486 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
Matt Carlson0d86df82010-02-17 15:17:00 +00006487 struct tg3_rx_buffer_desc *rxd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006488
Matt Carlson0d86df82010-02-17 15:17:00 +00006489 rxd = &tpr->rx_jmb[i].std;
6490 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6491 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6492 RXD_FLAG_JUMBO;
6493 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6494 (i << RXD_OPAQUE_INDEX_SHIFT));
6495 }
6496
6497 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6498 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00006499 netdev_warn(tp->dev,
6500 "Using a smaller RX jumbo ring. Only %d "
6501 "out of %d buffers were allocated "
6502 "successfully\n", i, tp->rx_jumbo_pending);
Matt Carlson0d86df82010-02-17 15:17:00 +00006503 if (i == 0)
6504 goto initfail;
6505 tp->rx_jumbo_pending = i;
6506 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006507 }
6508 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006509
6510done:
Michael Chan32d8c572006-07-25 16:38:29 -07006511 return 0;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006512
6513initfail:
Matt Carlson21f581a2009-08-28 14:00:25 +00006514 tg3_rx_prodring_free(tp, tpr);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006515 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006516}
6517
Matt Carlson21f581a2009-08-28 14:00:25 +00006518static void tg3_rx_prodring_fini(struct tg3 *tp,
6519 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006520{
Matt Carlson21f581a2009-08-28 14:00:25 +00006521 kfree(tpr->rx_std_buffers);
6522 tpr->rx_std_buffers = NULL;
6523 kfree(tpr->rx_jmb_buffers);
6524 tpr->rx_jmb_buffers = NULL;
6525 if (tpr->rx_std) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00006526 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6527 tpr->rx_std, tpr->rx_std_mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00006528 tpr->rx_std = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006529 }
Matt Carlson21f581a2009-08-28 14:00:25 +00006530 if (tpr->rx_jmb) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00006531 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6532 tpr->rx_jmb, tpr->rx_jmb_mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00006533 tpr->rx_jmb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006534 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006535}
6536
Matt Carlson21f581a2009-08-28 14:00:25 +00006537static int tg3_rx_prodring_init(struct tg3 *tp,
6538 struct tg3_rx_prodring_set *tpr)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006539{
Matt Carlson2c49a442010-09-30 10:34:35 +00006540 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6541 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00006542 if (!tpr->rx_std_buffers)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006543 return -ENOMEM;
6544
Matt Carlson4bae65c2010-11-24 08:31:52 +00006545 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6546 TG3_RX_STD_RING_BYTES(tp),
6547 &tpr->rx_std_mapping,
6548 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00006549 if (!tpr->rx_std)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006550 goto err_out;
6551
Matt Carlson48035722010-10-14 10:37:43 +00006552 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6553 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00006554 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
Matt Carlson21f581a2009-08-28 14:00:25 +00006555 GFP_KERNEL);
6556 if (!tpr->rx_jmb_buffers)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006557 goto err_out;
6558
Matt Carlson4bae65c2010-11-24 08:31:52 +00006559 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6560 TG3_RX_JMB_RING_BYTES(tp),
6561 &tpr->rx_jmb_mapping,
6562 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00006563 if (!tpr->rx_jmb)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006564 goto err_out;
6565 }
6566
6567 return 0;
6568
6569err_out:
Matt Carlson21f581a2009-08-28 14:00:25 +00006570 tg3_rx_prodring_fini(tp, tpr);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006571 return -ENOMEM;
6572}
6573
6574/* Free up pending packets in all rx/tx rings.
6575 *
6576 * The chip has been shut down and the driver detached from
6577 * the networking, so no interrupts or new tx packets will
6578 * end up in the driver. tp->{tx,}lock is not held and we are not
6579 * in an interrupt context and thus may sleep.
6580 */
6581static void tg3_free_rings(struct tg3 *tp)
6582{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006583 int i, j;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006584
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006585 for (j = 0; j < tp->irq_cnt; j++) {
6586 struct tg3_napi *tnapi = &tp->napi[j];
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006587
Matt Carlson8fea32b2010-09-15 08:59:58 +00006588 tg3_rx_prodring_free(tp, &tnapi->prodring);
Matt Carlsonb28f6422010-06-05 17:24:32 +00006589
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006590 if (!tnapi->tx_buffers)
6591 continue;
6592
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006593 for (i = 0; i < TG3_TX_RING_SIZE; ) {
Alexander Duyckf4188d82009-12-02 16:48:38 +00006594 struct ring_info *txp;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006595 struct sk_buff *skb;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006596 unsigned int k;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006597
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006598 txp = &tnapi->tx_buffers[i];
6599 skb = txp->skb;
6600
6601 if (skb == NULL) {
6602 i++;
6603 continue;
6604 }
6605
Alexander Duyckf4188d82009-12-02 16:48:38 +00006606 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006607 dma_unmap_addr(txp, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00006608 skb_headlen(skb),
6609 PCI_DMA_TODEVICE);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006610 txp->skb = NULL;
6611
Alexander Duyckf4188d82009-12-02 16:48:38 +00006612 i++;
6613
6614 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6615 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6616 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006617 dma_unmap_addr(txp, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00006618 skb_shinfo(skb)->frags[k].size,
6619 PCI_DMA_TODEVICE);
6620 i++;
6621 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006622
6623 dev_kfree_skb_any(skb);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006624 }
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006625 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006626}
6627
6628/* Initialize tx/rx rings for packet processing.
6629 *
6630 * The chip has been shut down and the driver detached from
6631 * the networking, so no interrupts or new tx packets will
6632 * end up in the driver. tp->{tx,}lock are held and thus
6633 * we may not sleep.
6634 */
6635static int tg3_init_rings(struct tg3 *tp)
6636{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006637 int i;
Matt Carlson72334482009-08-28 14:03:01 +00006638
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006639 /* Free up all the SKBs. */
6640 tg3_free_rings(tp);
6641
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006642 for (i = 0; i < tp->irq_cnt; i++) {
6643 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006644
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006645 tnapi->last_tag = 0;
6646 tnapi->last_irq_tag = 0;
6647 tnapi->hw_status->status = 0;
6648 tnapi->hw_status->status_tag = 0;
6649 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6650
6651 tnapi->tx_prod = 0;
6652 tnapi->tx_cons = 0;
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006653 if (tnapi->tx_ring)
6654 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006655
6656 tnapi->rx_rcb_ptr = 0;
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006657 if (tnapi->rx_rcb)
6658 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006659
Matt Carlson8fea32b2010-09-15 08:59:58 +00006660 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
Matt Carlsone4af1af2010-02-12 14:47:05 +00006661 tg3_free_rings(tp);
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006662 return -ENOMEM;
Matt Carlsone4af1af2010-02-12 14:47:05 +00006663 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006664 }
Matt Carlson72334482009-08-28 14:03:01 +00006665
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006666 return 0;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006667}
6668
6669/*
6670 * Must not be invoked with interrupt sources disabled and
6671 * the hardware shutdown down.
6672 */
6673static void tg3_free_consistent(struct tg3 *tp)
6674{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006675 int i;
Matt Carlson898a56f2009-08-28 14:02:40 +00006676
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006677 for (i = 0; i < tp->irq_cnt; i++) {
6678 struct tg3_napi *tnapi = &tp->napi[i];
6679
6680 if (tnapi->tx_ring) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00006681 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006682 tnapi->tx_ring, tnapi->tx_desc_mapping);
6683 tnapi->tx_ring = NULL;
6684 }
6685
6686 kfree(tnapi->tx_buffers);
6687 tnapi->tx_buffers = NULL;
6688
6689 if (tnapi->rx_rcb) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00006690 dma_free_coherent(&tp->pdev->dev,
6691 TG3_RX_RCB_RING_BYTES(tp),
6692 tnapi->rx_rcb,
6693 tnapi->rx_rcb_mapping);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006694 tnapi->rx_rcb = NULL;
6695 }
6696
Matt Carlson8fea32b2010-09-15 08:59:58 +00006697 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6698
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006699 if (tnapi->hw_status) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00006700 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6701 tnapi->hw_status,
6702 tnapi->status_mapping);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006703 tnapi->hw_status = NULL;
6704 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006705 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006706
Linus Torvalds1da177e2005-04-16 15:20:36 -07006707 if (tp->hw_stats) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00006708 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6709 tp->hw_stats, tp->stats_mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006710 tp->hw_stats = NULL;
6711 }
6712}
6713
6714/*
6715 * Must not be invoked with interrupt sources disabled and
6716 * the hardware shutdown down. Can sleep.
6717 */
6718static int tg3_alloc_consistent(struct tg3 *tp)
6719{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006720 int i;
Matt Carlson898a56f2009-08-28 14:02:40 +00006721
Matt Carlson4bae65c2010-11-24 08:31:52 +00006722 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6723 sizeof(struct tg3_hw_stats),
6724 &tp->stats_mapping,
6725 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006726 if (!tp->hw_stats)
6727 goto err_out;
6728
Linus Torvalds1da177e2005-04-16 15:20:36 -07006729 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6730
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006731 for (i = 0; i < tp->irq_cnt; i++) {
6732 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00006733 struct tg3_hw_status *sblk;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006734
Matt Carlson4bae65c2010-11-24 08:31:52 +00006735 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6736 TG3_HW_STATUS_SIZE,
6737 &tnapi->status_mapping,
6738 GFP_KERNEL);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006739 if (!tnapi->hw_status)
6740 goto err_out;
6741
6742 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00006743 sblk = tnapi->hw_status;
6744
Matt Carlson8fea32b2010-09-15 08:59:58 +00006745 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6746 goto err_out;
6747
Matt Carlson19cfaec2009-12-03 08:36:20 +00006748 /* If multivector TSS is enabled, vector 0 does not handle
6749 * tx interrupts. Don't allocate any resources for it.
6750 */
6751 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6752 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6753 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6754 TG3_TX_RING_SIZE,
6755 GFP_KERNEL);
6756 if (!tnapi->tx_buffers)
6757 goto err_out;
6758
Matt Carlson4bae65c2010-11-24 08:31:52 +00006759 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6760 TG3_TX_RING_BYTES,
6761 &tnapi->tx_desc_mapping,
6762 GFP_KERNEL);
Matt Carlson19cfaec2009-12-03 08:36:20 +00006763 if (!tnapi->tx_ring)
6764 goto err_out;
6765 }
6766
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00006767 /*
6768 * When RSS is enabled, the status block format changes
6769 * slightly. The "rx_jumbo_consumer", "reserved",
6770 * and "rx_mini_consumer" members get mapped to the
6771 * other three rx return ring producer indexes.
6772 */
6773 switch (i) {
6774 default:
6775 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6776 break;
6777 case 2:
6778 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6779 break;
6780 case 3:
6781 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6782 break;
6783 case 4:
6784 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6785 break;
6786 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006787
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006788 /*
6789 * If multivector RSS is enabled, vector 0 does not handle
6790 * rx or tx interrupts. Don't allocate any resources for it.
6791 */
6792 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6793 continue;
6794
Matt Carlson4bae65c2010-11-24 08:31:52 +00006795 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6796 TG3_RX_RCB_RING_BYTES(tp),
6797 &tnapi->rx_rcb_mapping,
6798 GFP_KERNEL);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006799 if (!tnapi->rx_rcb)
6800 goto err_out;
6801
6802 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006803 }
6804
Linus Torvalds1da177e2005-04-16 15:20:36 -07006805 return 0;
6806
6807err_out:
6808 tg3_free_consistent(tp);
6809 return -ENOMEM;
6810}
6811
6812#define MAX_WAIT_CNT 1000
6813
6814/* To stop a block, clear the enable bit and poll till it
6815 * clears. tp->lock is held.
6816 */
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006817static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006818{
6819 unsigned int i;
6820 u32 val;
6821
6822 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6823 switch (ofs) {
6824 case RCVLSC_MODE:
6825 case DMAC_MODE:
6826 case MBFREE_MODE:
6827 case BUFMGR_MODE:
6828 case MEMARB_MODE:
6829 /* We can't enable/disable these bits of the
6830 * 5705/5750, just say success.
6831 */
6832 return 0;
6833
6834 default:
6835 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07006836 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006837 }
6838
6839 val = tr32(ofs);
6840 val &= ~enable_bit;
6841 tw32_f(ofs, val);
6842
6843 for (i = 0; i < MAX_WAIT_CNT; i++) {
6844 udelay(100);
6845 val = tr32(ofs);
6846 if ((val & enable_bit) == 0)
6847 break;
6848 }
6849
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006850 if (i == MAX_WAIT_CNT && !silent) {
Matt Carlson2445e462010-04-05 10:19:21 +00006851 dev_err(&tp->pdev->dev,
6852 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6853 ofs, enable_bit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006854 return -ENODEV;
6855 }
6856
6857 return 0;
6858}
6859
6860/* tp->lock is held. */
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006861static int tg3_abort_hw(struct tg3 *tp, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006862{
6863 int i, err;
6864
6865 tg3_disable_ints(tp);
6866
6867 tp->rx_mode &= ~RX_MODE_ENABLE;
6868 tw32_f(MAC_RX_MODE, tp->rx_mode);
6869 udelay(10);
6870
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006871 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6872 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6873 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6874 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6875 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6876 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006877
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006878 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6879 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6880 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6881 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6882 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6883 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6884 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006885
6886 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6887 tw32_f(MAC_MODE, tp->mac_mode);
6888 udelay(40);
6889
6890 tp->tx_mode &= ~TX_MODE_ENABLE;
6891 tw32_f(MAC_TX_MODE, tp->tx_mode);
6892
6893 for (i = 0; i < MAX_WAIT_CNT; i++) {
6894 udelay(100);
6895 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6896 break;
6897 }
6898 if (i >= MAX_WAIT_CNT) {
Matt Carlsonab96b242010-04-05 10:19:22 +00006899 dev_err(&tp->pdev->dev,
6900 "%s timed out, TX_MODE_ENABLE will not clear "
6901 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
Michael Chane6de8ad2005-05-05 14:42:41 -07006902 err |= -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006903 }
6904
Michael Chane6de8ad2005-05-05 14:42:41 -07006905 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006906 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6907 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006908
6909 tw32(FTQ_RESET, 0xffffffff);
6910 tw32(FTQ_RESET, 0x00000000);
6911
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006912 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6913 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006914
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006915 for (i = 0; i < tp->irq_cnt; i++) {
6916 struct tg3_napi *tnapi = &tp->napi[i];
6917 if (tnapi->hw_status)
6918 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6919 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006920 if (tp->hw_stats)
6921 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6922
Linus Torvalds1da177e2005-04-16 15:20:36 -07006923 return err;
6924}
6925
Matt Carlson0d3031d2007-10-10 18:02:43 -07006926static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6927{
6928 int i;
6929 u32 apedata;
6930
Matt Carlsondc6d0742010-09-15 08:59:55 +00006931 /* NCSI does not support APE events */
6932 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6933 return;
6934
Matt Carlson0d3031d2007-10-10 18:02:43 -07006935 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6936 if (apedata != APE_SEG_SIG_MAGIC)
6937 return;
6938
6939 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
Matt Carlson731fd792008-08-15 14:07:51 -07006940 if (!(apedata & APE_FW_STATUS_READY))
Matt Carlson0d3031d2007-10-10 18:02:43 -07006941 return;
6942
6943 /* Wait for up to 1 millisecond for APE to service previous event. */
6944 for (i = 0; i < 10; i++) {
6945 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6946 return;
6947
6948 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6949
6950 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6951 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6952 event | APE_EVENT_STATUS_EVENT_PENDING);
6953
6954 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6955
6956 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6957 break;
6958
6959 udelay(100);
6960 }
6961
6962 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6963 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6964}
6965
6966static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6967{
6968 u32 event;
6969 u32 apedata;
6970
6971 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6972 return;
6973
6974 switch (kind) {
Matt Carlson33f401a2010-04-05 10:19:27 +00006975 case RESET_KIND_INIT:
6976 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6977 APE_HOST_SEG_SIG_MAGIC);
6978 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6979 APE_HOST_SEG_LEN_MAGIC);
6980 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6981 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6982 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
Matt Carlson6867c842010-07-11 09:31:44 +00006983 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
Matt Carlson33f401a2010-04-05 10:19:27 +00006984 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6985 APE_HOST_BEHAV_NO_PHYLOCK);
Matt Carlsondc6d0742010-09-15 08:59:55 +00006986 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6987 TG3_APE_HOST_DRVR_STATE_START);
Matt Carlson0d3031d2007-10-10 18:02:43 -07006988
Matt Carlson33f401a2010-04-05 10:19:27 +00006989 event = APE_EVENT_STATUS_STATE_START;
6990 break;
6991 case RESET_KIND_SHUTDOWN:
6992 /* With the interface we are currently using,
6993 * APE does not track driver state. Wiping
6994 * out the HOST SEGMENT SIGNATURE forces
6995 * the APE to assume OS absent status.
6996 */
6997 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
Matt Carlsonb2aee152008-11-03 16:51:11 -08006998
Matt Carlsondc6d0742010-09-15 08:59:55 +00006999 if (device_may_wakeup(&tp->pdev->dev) &&
7000 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
7001 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
7002 TG3_APE_HOST_WOL_SPEED_AUTO);
7003 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
7004 } else
7005 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
7006
7007 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
7008
Matt Carlson33f401a2010-04-05 10:19:27 +00007009 event = APE_EVENT_STATUS_STATE_UNLOAD;
7010 break;
7011 case RESET_KIND_SUSPEND:
7012 event = APE_EVENT_STATUS_STATE_SUSPEND;
7013 break;
7014 default:
7015 return;
Matt Carlson0d3031d2007-10-10 18:02:43 -07007016 }
7017
7018 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
7019
7020 tg3_ape_send_event(tp, event);
7021}
7022
Michael Chane6af3012005-04-21 17:12:05 -07007023/* tp->lock is held. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07007024static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
7025{
David S. Millerf49639e2006-06-09 11:58:36 -07007026 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
7027 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007028
7029 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
7030 switch (kind) {
7031 case RESET_KIND_INIT:
7032 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7033 DRV_STATE_START);
7034 break;
7035
7036 case RESET_KIND_SHUTDOWN:
7037 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7038 DRV_STATE_UNLOAD);
7039 break;
7040
7041 case RESET_KIND_SUSPEND:
7042 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7043 DRV_STATE_SUSPEND);
7044 break;
7045
7046 default:
7047 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07007048 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007049 }
Matt Carlson0d3031d2007-10-10 18:02:43 -07007050
7051 if (kind == RESET_KIND_INIT ||
7052 kind == RESET_KIND_SUSPEND)
7053 tg3_ape_driver_state_change(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007054}
7055
7056/* tp->lock is held. */
7057static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
7058{
7059 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
7060 switch (kind) {
7061 case RESET_KIND_INIT:
7062 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7063 DRV_STATE_START_DONE);
7064 break;
7065
7066 case RESET_KIND_SHUTDOWN:
7067 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7068 DRV_STATE_UNLOAD_DONE);
7069 break;
7070
7071 default:
7072 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07007073 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007074 }
Matt Carlson0d3031d2007-10-10 18:02:43 -07007075
7076 if (kind == RESET_KIND_SHUTDOWN)
7077 tg3_ape_driver_state_change(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007078}
7079
7080/* tp->lock is held. */
7081static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
7082{
7083 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7084 switch (kind) {
7085 case RESET_KIND_INIT:
7086 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7087 DRV_STATE_START);
7088 break;
7089
7090 case RESET_KIND_SHUTDOWN:
7091 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7092 DRV_STATE_UNLOAD);
7093 break;
7094
7095 case RESET_KIND_SUSPEND:
7096 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7097 DRV_STATE_SUSPEND);
7098 break;
7099
7100 default:
7101 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07007102 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007103 }
7104}
7105
Michael Chan7a6f4362006-09-27 16:03:31 -07007106static int tg3_poll_fw(struct tg3 *tp)
7107{
7108 int i;
7109 u32 val;
7110
Michael Chanb5d37722006-09-27 16:06:21 -07007111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Gary Zambrano0ccead12006-11-14 16:34:00 -08007112 /* Wait up to 20ms for init done. */
7113 for (i = 0; i < 200; i++) {
Michael Chanb5d37722006-09-27 16:06:21 -07007114 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
7115 return 0;
Gary Zambrano0ccead12006-11-14 16:34:00 -08007116 udelay(100);
Michael Chanb5d37722006-09-27 16:06:21 -07007117 }
7118 return -ENODEV;
7119 }
7120
Michael Chan7a6f4362006-09-27 16:03:31 -07007121 /* Wait for firmware initialization to complete. */
7122 for (i = 0; i < 100000; i++) {
7123 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
7124 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
7125 break;
7126 udelay(10);
7127 }
7128
7129 /* Chip might not be fitted with firmware. Some Sun onboard
7130 * parts are configured like that. So don't signal the timeout
7131 * of the above loop as an error, but do report the lack of
7132 * running firmware once.
7133 */
7134 if (i >= 100000 &&
7135 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
7136 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
7137
Joe Perches05dbe002010-02-17 19:44:19 +00007138 netdev_info(tp->dev, "No firmware running\n");
Michael Chan7a6f4362006-09-27 16:03:31 -07007139 }
7140
Matt Carlson6b10c162010-02-12 14:47:08 +00007141 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7142 /* The 57765 A0 needs a little more
7143 * time to do some important work.
7144 */
7145 mdelay(10);
7146 }
7147
Michael Chan7a6f4362006-09-27 16:03:31 -07007148 return 0;
7149}
7150
Michael Chanee6a99b2007-07-18 21:49:10 -07007151/* Save PCI command register before chip reset */
7152static void tg3_save_pci_state(struct tg3 *tp)
7153{
Matt Carlson8a6eac92007-10-21 16:17:55 -07007154 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
Michael Chanee6a99b2007-07-18 21:49:10 -07007155}
7156
7157/* Restore PCI state after chip reset */
7158static void tg3_restore_pci_state(struct tg3 *tp)
7159{
7160 u32 val;
7161
7162 /* Re-enable indirect register accesses. */
7163 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7164 tp->misc_host_ctrl);
7165
7166 /* Set MAX PCI retry to zero. */
7167 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7168 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7169 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
7170 val |= PCISTATE_RETRY_SAME_DMA;
Matt Carlson0d3031d2007-10-10 18:02:43 -07007171 /* Allow reads and writes to the APE register and memory space. */
7172 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7173 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00007174 PCISTATE_ALLOW_APE_SHMEM_WR |
7175 PCISTATE_ALLOW_APE_PSPACE_WR;
Michael Chanee6a99b2007-07-18 21:49:10 -07007176 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7177
Matt Carlson8a6eac92007-10-21 16:17:55 -07007178 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
Michael Chanee6a99b2007-07-18 21:49:10 -07007179
Matt Carlsonfcb389d2008-11-03 16:55:44 -08007180 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7181 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
Matt Carlsoncf790032010-11-24 08:31:48 +00007182 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
Matt Carlsonfcb389d2008-11-03 16:55:44 -08007183 else {
7184 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7185 tp->pci_cacheline_sz);
7186 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7187 tp->pci_lat_timer);
7188 }
Michael Chan114342f2007-10-15 02:12:26 -07007189 }
Matt Carlson5f5c51e2007-11-12 21:19:37 -08007190
Michael Chanee6a99b2007-07-18 21:49:10 -07007191 /* Make sure PCI-X relaxed ordering bit is clear. */
Matt Carlson52f44902008-11-21 17:17:04 -08007192 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
Matt Carlson9974a352007-10-07 23:27:28 -07007193 u16 pcix_cmd;
7194
7195 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7196 &pcix_cmd);
7197 pcix_cmd &= ~PCI_X_CMD_ERO;
7198 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7199 pcix_cmd);
7200 }
Michael Chanee6a99b2007-07-18 21:49:10 -07007201
7202 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
Michael Chanee6a99b2007-07-18 21:49:10 -07007203
7204 /* Chip reset on 5780 will reset MSI enable bit,
7205 * so need to restore it.
7206 */
7207 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7208 u16 ctrl;
7209
7210 pci_read_config_word(tp->pdev,
7211 tp->msi_cap + PCI_MSI_FLAGS,
7212 &ctrl);
7213 pci_write_config_word(tp->pdev,
7214 tp->msi_cap + PCI_MSI_FLAGS,
7215 ctrl | PCI_MSI_FLAGS_ENABLE);
7216 val = tr32(MSGINT_MODE);
7217 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7218 }
7219 }
7220}
7221
Linus Torvalds1da177e2005-04-16 15:20:36 -07007222static void tg3_stop_fw(struct tg3 *);
7223
7224/* tp->lock is held. */
7225static int tg3_chip_reset(struct tg3 *tp)
7226{
7227 u32 val;
Michael Chan1ee582d2005-08-09 20:16:46 -07007228 void (*write_op)(struct tg3 *, u32, u32);
Matt Carlson4f125f42009-09-01 12:55:02 +00007229 int i, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007230
David S. Millerf49639e2006-06-09 11:58:36 -07007231 tg3_nvram_lock(tp);
7232
Matt Carlson77b483f2008-08-15 14:07:24 -07007233 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7234
David S. Millerf49639e2006-06-09 11:58:36 -07007235 /* No matching tg3_nvram_unlock() after this because
7236 * chip reset below will undo the nvram lock.
7237 */
7238 tp->nvram_lock_cnt = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007239
Michael Chanee6a99b2007-07-18 21:49:10 -07007240 /* GRC_MISC_CFG core clock reset will clear the memory
7241 * enable bit in PCI register 4 and the MSI enable bit
7242 * on some chips, so we save relevant registers here.
7243 */
7244 tg3_save_pci_state(tp);
7245
Michael Chand9ab5ad12006-03-20 22:27:35 -08007246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
Matt Carlson321d32a2008-11-21 17:22:19 -08007247 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
Michael Chand9ab5ad12006-03-20 22:27:35 -08007248 tw32(GRC_FASTBOOT_PC, 0);
7249
Linus Torvalds1da177e2005-04-16 15:20:36 -07007250 /*
7251 * We must avoid the readl() that normally takes place.
7252 * It locks machines, causes machine checks, and other
7253 * fun things. So, temporarily disable the 5701
7254 * hardware workaround, while we do the reset.
7255 */
Michael Chan1ee582d2005-08-09 20:16:46 -07007256 write_op = tp->write32;
7257 if (write_op == tg3_write_flush_reg32)
7258 tp->write32 = tg3_write32;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007259
Michael Chand18edcb2007-03-24 20:57:11 -07007260 /* Prevent the irq handler from reading or writing PCI registers
7261 * during chip reset when the memory enable bit in the PCI command
7262 * register may be cleared. The chip does not generate interrupt
7263 * at this time, but the irq handler may still be called due to irq
7264 * sharing or irqpoll.
7265 */
7266 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007267 for (i = 0; i < tp->irq_cnt; i++) {
7268 struct tg3_napi *tnapi = &tp->napi[i];
7269 if (tnapi->hw_status) {
7270 tnapi->hw_status->status = 0;
7271 tnapi->hw_status->status_tag = 0;
7272 }
7273 tnapi->last_tag = 0;
7274 tnapi->last_irq_tag = 0;
Michael Chanb8fa2f32007-04-06 17:35:37 -07007275 }
Michael Chand18edcb2007-03-24 20:57:11 -07007276 smp_mb();
Matt Carlson4f125f42009-09-01 12:55:02 +00007277
7278 for (i = 0; i < tp->irq_cnt; i++)
7279 synchronize_irq(tp->napi[i].irq_vec);
Michael Chand18edcb2007-03-24 20:57:11 -07007280
Matt Carlson255ca312009-08-25 10:07:27 +00007281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7282 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7283 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7284 }
7285
Linus Torvalds1da177e2005-04-16 15:20:36 -07007286 /* do the reset */
7287 val = GRC_MISC_CFG_CORECLK_RESET;
7288
7289 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
Matt Carlson88075d92010-08-02 11:25:58 +00007290 /* Force PCIe 1.0a mode */
7291 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Matt Carlson1407deb2011-04-05 14:22:44 +00007292 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
Matt Carlson88075d92010-08-02 11:25:58 +00007293 tr32(TG3_PCIE_PHY_TSTCTL) ==
7294 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7295 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7296
Linus Torvalds1da177e2005-04-16 15:20:36 -07007297 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7298 tw32(GRC_MISC_CFG, (1 << 29));
7299 val |= (1 << 29);
7300 }
7301 }
7302
Michael Chanb5d37722006-09-27 16:06:21 -07007303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7304 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7305 tw32(GRC_VCPU_EXT_CTRL,
7306 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7307 }
7308
Matt Carlsonf37500d2010-08-02 11:25:59 +00007309 /* Manage gphy power for all CPMU absent PCIe devices. */
7310 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7311 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
Linus Torvalds1da177e2005-04-16 15:20:36 -07007312 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
Matt Carlsonf37500d2010-08-02 11:25:59 +00007313
Linus Torvalds1da177e2005-04-16 15:20:36 -07007314 tw32(GRC_MISC_CFG, val);
7315
Michael Chan1ee582d2005-08-09 20:16:46 -07007316 /* restore 5701 hardware bug workaround write method */
7317 tp->write32 = write_op;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007318
7319 /* Unfortunately, we have to delay before the PCI read back.
7320 * Some 575X chips even will not respond to a PCI cfg access
7321 * when the reset command is given to the chip.
7322 *
7323 * How do these hardware designers expect things to work
7324 * properly if the PCI write is posted for a long period
7325 * of time? It is always necessary to have some method by
7326 * which a register read back can occur to push the write
7327 * out which does the reset.
7328 *
7329 * For most tg3 variants the trick below was working.
7330 * Ho hum...
7331 */
7332 udelay(120);
7333
7334 /* Flush PCI posted writes. The normal MMIO registers
7335 * are inaccessible at this time so this is the only
7336 * way to make this reliably (actually, this is no longer
7337 * the case, see above). I tried to use indirect
7338 * register read/write but this upset some 5701 variants.
7339 */
7340 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7341
7342 udelay(120);
7343
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007344 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
Matt Carlsone7126992009-08-25 10:08:16 +00007345 u16 val16;
7346
Linus Torvalds1da177e2005-04-16 15:20:36 -07007347 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7348 int i;
7349 u32 cfg_val;
7350
7351 /* Wait for link training to complete. */
7352 for (i = 0; i < 5000; i++)
7353 udelay(100);
7354
7355 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7356 pci_write_config_dword(tp->pdev, 0xc4,
7357 cfg_val | (1 << 15));
7358 }
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007359
Matt Carlsone7126992009-08-25 10:08:16 +00007360 /* Clear the "no snoop" and "relaxed ordering" bits. */
7361 pci_read_config_word(tp->pdev,
7362 tp->pcie_cap + PCI_EXP_DEVCTL,
7363 &val16);
7364 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7365 PCI_EXP_DEVCTL_NOSNOOP_EN);
7366 /*
7367 * Older PCIe devices only support the 128 byte
7368 * MPS setting. Enforce the restriction.
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007369 */
Matt Carlson6de34cb2010-08-02 11:25:55 +00007370 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
Matt Carlsone7126992009-08-25 10:08:16 +00007371 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007372 pci_write_config_word(tp->pdev,
7373 tp->pcie_cap + PCI_EXP_DEVCTL,
Matt Carlsone7126992009-08-25 10:08:16 +00007374 val16);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007375
Matt Carlsoncf790032010-11-24 08:31:48 +00007376 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007377
7378 /* Clear error status */
7379 pci_write_config_word(tp->pdev,
7380 tp->pcie_cap + PCI_EXP_DEVSTA,
7381 PCI_EXP_DEVSTA_CED |
7382 PCI_EXP_DEVSTA_NFED |
7383 PCI_EXP_DEVSTA_FED |
7384 PCI_EXP_DEVSTA_URD);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007385 }
7386
Michael Chanee6a99b2007-07-18 21:49:10 -07007387 tg3_restore_pci_state(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007388
Matt Carlsone64de4e2011-04-13 11:05:05 +00007389 tp->tg3_flags &= ~(TG3_FLAG_CHIP_RESETTING |
7390 TG3_FLAG_ERROR_PROCESSED);
Michael Chand18edcb2007-03-24 20:57:11 -07007391
Michael Chanee6a99b2007-07-18 21:49:10 -07007392 val = 0;
7393 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
Michael Chan4cf78e42005-07-25 12:29:19 -07007394 val = tr32(MEMARB_MODE);
Michael Chanee6a99b2007-07-18 21:49:10 -07007395 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007396
7397 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7398 tg3_stop_fw(tp);
7399 tw32(0x5000, 0x400);
7400 }
7401
7402 tw32(GRC_MODE, tp->grc_mode);
7403
7404 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
Andy Gospodarekab0049b2007-09-06 20:42:14 +01007405 val = tr32(0xc4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007406
7407 tw32(0xc4, val | (1 << 15));
7408 }
7409
7410 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7412 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7413 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7414 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7415 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7416 }
7417
Matt Carlsond2394e6b2010-11-24 08:31:47 +00007418 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7419 tp->mac_mode = MAC_MODE_APE_TX_EN |
7420 MAC_MODE_APE_RX_EN |
7421 MAC_MODE_TDE_ENABLE;
7422
Matt Carlsonf07e9af2010-08-02 11:26:07 +00007423 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Matt Carlsond2394e6b2010-11-24 08:31:47 +00007424 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7425 val = tp->mac_mode;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00007426 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
Matt Carlsond2394e6b2010-11-24 08:31:47 +00007427 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7428 val = tp->mac_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007429 } else
Matt Carlsond2394e6b2010-11-24 08:31:47 +00007430 val = 0;
7431
7432 tw32_f(MAC_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007433 udelay(40);
7434
Matt Carlson77b483f2008-08-15 14:07:24 -07007435 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7436
Michael Chan7a6f4362006-09-27 16:03:31 -07007437 err = tg3_poll_fw(tp);
7438 if (err)
7439 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007440
Matt Carlson0a9140c2009-08-28 12:27:50 +00007441 tg3_mdio_start(tp);
7442
Linus Torvalds1da177e2005-04-16 15:20:36 -07007443 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00007444 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7445 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Matt Carlson1407deb2011-04-05 14:22:44 +00007446 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
Andy Gospodarekab0049b2007-09-06 20:42:14 +01007447 val = tr32(0x7c00);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007448
7449 tw32(0x7c00, val | (1 << 25));
7450 }
7451
Matt Carlsond78b59f2011-04-05 14:22:46 +00007452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7453 val = tr32(TG3_CPMU_CLCK_ORIDE);
7454 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7455 }
7456
Linus Torvalds1da177e2005-04-16 15:20:36 -07007457 /* Reprobe ASF enable state. */
7458 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7459 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7460 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7461 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7462 u32 nic_cfg;
7463
7464 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7465 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7466 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
Matt Carlson4ba526c2008-08-15 14:10:04 -07007467 tp->last_event_jiffies = jiffies;
John W. Linvillecbf46852005-04-21 17:01:29 -07007468 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007469 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7470 }
7471 }
7472
7473 return 0;
7474}
7475
7476/* tp->lock is held. */
7477static void tg3_stop_fw(struct tg3 *tp)
7478{
Matt Carlson0d3031d2007-10-10 18:02:43 -07007479 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7480 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
Matt Carlson7c5026a2008-05-02 16:49:29 -07007481 /* Wait for RX cpu to ACK the previous event. */
7482 tg3_wait_for_event_ack(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007483
7484 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
Matt Carlson4ba526c2008-08-15 14:10:04 -07007485
7486 tg3_generate_fw_event(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007487
Matt Carlson7c5026a2008-05-02 16:49:29 -07007488 /* Wait for RX cpu to ACK this event. */
7489 tg3_wait_for_event_ack(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007490 }
7491}
7492
7493/* tp->lock is held. */
Michael Chan944d9802005-05-29 14:57:48 -07007494static int tg3_halt(struct tg3 *tp, int kind, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007495{
7496 int err;
7497
7498 tg3_stop_fw(tp);
7499
Michael Chan944d9802005-05-29 14:57:48 -07007500 tg3_write_sig_pre_reset(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007501
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007502 tg3_abort_hw(tp, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007503 err = tg3_chip_reset(tp);
7504
Matt Carlsondaba2a62009-04-20 06:58:52 +00007505 __tg3_set_mac_addr(tp, 0);
7506
Michael Chan944d9802005-05-29 14:57:48 -07007507 tg3_write_sig_legacy(tp, kind);
7508 tg3_write_sig_post_reset(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007509
7510 if (err)
7511 return err;
7512
7513 return 0;
7514}
7515
Linus Torvalds1da177e2005-04-16 15:20:36 -07007516#define RX_CPU_SCRATCH_BASE 0x30000
7517#define RX_CPU_SCRATCH_SIZE 0x04000
7518#define TX_CPU_SCRATCH_BASE 0x34000
7519#define TX_CPU_SCRATCH_SIZE 0x04000
7520
7521/* tp->lock is held. */
7522static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7523{
7524 int i;
7525
Eric Sesterhenn5d9428d2006-04-02 13:52:48 +02007526 BUG_ON(offset == TX_CPU_BASE &&
7527 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007528
Michael Chanb5d37722006-09-27 16:06:21 -07007529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7530 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7531
7532 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7533 return 0;
7534 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007535 if (offset == RX_CPU_BASE) {
7536 for (i = 0; i < 10000; i++) {
7537 tw32(offset + CPU_STATE, 0xffffffff);
7538 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7539 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7540 break;
7541 }
7542
7543 tw32(offset + CPU_STATE, 0xffffffff);
7544 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7545 udelay(10);
7546 } else {
7547 for (i = 0; i < 10000; i++) {
7548 tw32(offset + CPU_STATE, 0xffffffff);
7549 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7550 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7551 break;
7552 }
7553 }
7554
7555 if (i >= 10000) {
Joe Perches05dbe002010-02-17 19:44:19 +00007556 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7557 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
Linus Torvalds1da177e2005-04-16 15:20:36 -07007558 return -ENODEV;
7559 }
Michael Chanec41c7d2006-01-17 02:40:55 -08007560
7561 /* Clear firmware's nvram arbitration. */
7562 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7563 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007564 return 0;
7565}
7566
7567struct fw_info {
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007568 unsigned int fw_base;
7569 unsigned int fw_len;
7570 const __be32 *fw_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007571};
7572
7573/* tp->lock is held. */
7574static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7575 int cpu_scratch_size, struct fw_info *info)
7576{
Michael Chanec41c7d2006-01-17 02:40:55 -08007577 int err, lock_err, i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007578 void (*write_op)(struct tg3 *, u32, u32);
7579
7580 if (cpu_base == TX_CPU_BASE &&
7581 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007582 netdev_err(tp->dev,
7583 "%s: Trying to load TX cpu firmware which is 5705\n",
Joe Perches05dbe002010-02-17 19:44:19 +00007584 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007585 return -EINVAL;
7586 }
7587
7588 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7589 write_op = tg3_write_mem;
7590 else
7591 write_op = tg3_write_indirect_reg32;
7592
Michael Chan1b628152005-05-29 14:59:49 -07007593 /* It is possible that bootcode is still loading at this point.
7594 * Get the nvram lock first before halting the cpu.
7595 */
Michael Chanec41c7d2006-01-17 02:40:55 -08007596 lock_err = tg3_nvram_lock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007597 err = tg3_halt_cpu(tp, cpu_base);
Michael Chanec41c7d2006-01-17 02:40:55 -08007598 if (!lock_err)
7599 tg3_nvram_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007600 if (err)
7601 goto out;
7602
7603 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7604 write_op(tp, cpu_scratch_base + i, 0);
7605 tw32(cpu_base + CPU_STATE, 0xffffffff);
7606 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007607 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007608 write_op(tp, (cpu_scratch_base +
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007609 (info->fw_base & 0xffff) +
Linus Torvalds1da177e2005-04-16 15:20:36 -07007610 (i * sizeof(u32))),
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007611 be32_to_cpu(info->fw_data[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007612
7613 err = 0;
7614
7615out:
Linus Torvalds1da177e2005-04-16 15:20:36 -07007616 return err;
7617}
7618
7619/* tp->lock is held. */
7620static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7621{
7622 struct fw_info info;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007623 const __be32 *fw_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007624 int err, i;
7625
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007626 fw_data = (void *)tp->fw->data;
7627
7628 /* Firmware blob starts with version numbers, followed by
7629 start address and length. We are setting complete length.
7630 length = end_address_of_bss - start_address_of_text.
7631 Remainder is the blob to be loaded contiguously
7632 from start address. */
7633
7634 info.fw_base = be32_to_cpu(fw_data[1]);
7635 info.fw_len = tp->fw->size - 12;
7636 info.fw_data = &fw_data[3];
Linus Torvalds1da177e2005-04-16 15:20:36 -07007637
7638 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7639 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7640 &info);
7641 if (err)
7642 return err;
7643
7644 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7645 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7646 &info);
7647 if (err)
7648 return err;
7649
7650 /* Now startup only the RX cpu. */
7651 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007652 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007653
7654 for (i = 0; i < 5; i++) {
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007655 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007656 break;
7657 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7658 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007659 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007660 udelay(1000);
7661 }
7662 if (i >= 5) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007663 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7664 "should be %08x\n", __func__,
Joe Perches05dbe002010-02-17 19:44:19 +00007665 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007666 return -ENODEV;
7667 }
7668 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7669 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7670
7671 return 0;
7672}
7673
Linus Torvalds1da177e2005-04-16 15:20:36 -07007674/* 5705 needs a special version of the TSO firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07007675
7676/* tp->lock is held. */
7677static int tg3_load_tso_firmware(struct tg3 *tp)
7678{
7679 struct fw_info info;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007680 const __be32 *fw_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007681 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7682 int err, i;
7683
7684 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7685 return 0;
7686
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007687 fw_data = (void *)tp->fw->data;
7688
7689 /* Firmware blob starts with version numbers, followed by
7690 start address and length. We are setting complete length.
7691 length = end_address_of_bss - start_address_of_text.
7692 Remainder is the blob to be loaded contiguously
7693 from start address. */
7694
7695 info.fw_base = be32_to_cpu(fw_data[1]);
7696 cpu_scratch_size = tp->fw_len;
7697 info.fw_len = tp->fw->size - 12;
7698 info.fw_data = &fw_data[3];
7699
Linus Torvalds1da177e2005-04-16 15:20:36 -07007700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007701 cpu_base = RX_CPU_BASE;
7702 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007703 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007704 cpu_base = TX_CPU_BASE;
7705 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7706 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7707 }
7708
7709 err = tg3_load_firmware_cpu(tp, cpu_base,
7710 cpu_scratch_base, cpu_scratch_size,
7711 &info);
7712 if (err)
7713 return err;
7714
7715 /* Now startup the cpu. */
7716 tw32(cpu_base + CPU_STATE, 0xffffffff);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007717 tw32_f(cpu_base + CPU_PC, info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007718
7719 for (i = 0; i < 5; i++) {
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007720 if (tr32(cpu_base + CPU_PC) == info.fw_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007721 break;
7722 tw32(cpu_base + CPU_STATE, 0xffffffff);
7723 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007724 tw32_f(cpu_base + CPU_PC, info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007725 udelay(1000);
7726 }
7727 if (i >= 5) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007728 netdev_err(tp->dev,
7729 "%s fails to set CPU PC, is %08x should be %08x\n",
Joe Perches05dbe002010-02-17 19:44:19 +00007730 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007731 return -ENODEV;
7732 }
7733 tw32(cpu_base + CPU_STATE, 0xffffffff);
7734 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7735 return 0;
7736}
7737
Linus Torvalds1da177e2005-04-16 15:20:36 -07007738
Linus Torvalds1da177e2005-04-16 15:20:36 -07007739static int tg3_set_mac_addr(struct net_device *dev, void *p)
7740{
7741 struct tg3 *tp = netdev_priv(dev);
7742 struct sockaddr *addr = p;
Michael Chan986e0ae2007-05-05 12:10:20 -07007743 int err = 0, skip_mac_1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007744
Michael Chanf9804dd2005-09-27 12:13:10 -07007745 if (!is_valid_ether_addr(addr->sa_data))
7746 return -EINVAL;
7747
Linus Torvalds1da177e2005-04-16 15:20:36 -07007748 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7749
Michael Chane75f7c92006-03-20 21:33:26 -08007750 if (!netif_running(dev))
7751 return 0;
7752
Michael Chan58712ef2006-04-29 18:58:01 -07007753 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
Michael Chan986e0ae2007-05-05 12:10:20 -07007754 u32 addr0_high, addr0_low, addr1_high, addr1_low;
Michael Chan58712ef2006-04-29 18:58:01 -07007755
Michael Chan986e0ae2007-05-05 12:10:20 -07007756 addr0_high = tr32(MAC_ADDR_0_HIGH);
7757 addr0_low = tr32(MAC_ADDR_0_LOW);
7758 addr1_high = tr32(MAC_ADDR_1_HIGH);
7759 addr1_low = tr32(MAC_ADDR_1_LOW);
7760
7761 /* Skip MAC addr 1 if ASF is using it. */
7762 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7763 !(addr1_high == 0 && addr1_low == 0))
7764 skip_mac_1 = 1;
Michael Chan58712ef2006-04-29 18:58:01 -07007765 }
Michael Chan986e0ae2007-05-05 12:10:20 -07007766 spin_lock_bh(&tp->lock);
7767 __tg3_set_mac_addr(tp, skip_mac_1);
7768 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007769
Michael Chanb9ec6c12006-07-25 16:37:27 -07007770 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007771}
7772
7773/* tp->lock is held. */
7774static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7775 dma_addr_t mapping, u32 maxlen_flags,
7776 u32 nic_addr)
7777{
7778 tg3_write_mem(tp,
7779 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7780 ((u64) mapping >> 32));
7781 tg3_write_mem(tp,
7782 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7783 ((u64) mapping & 0xffffffff));
7784 tg3_write_mem(tp,
7785 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7786 maxlen_flags);
7787
7788 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7789 tg3_write_mem(tp,
7790 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7791 nic_addr);
7792}
7793
7794static void __tg3_set_rx_mode(struct net_device *);
Michael Chand244c892005-07-05 14:42:33 -07007795static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
David S. Miller15f98502005-05-18 22:49:26 -07007796{
Matt Carlsonb6080e12009-09-01 13:12:00 +00007797 int i;
7798
Matt Carlson19cfaec2009-12-03 08:36:20 +00007799 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
Matt Carlsonb6080e12009-09-01 13:12:00 +00007800 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7801 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7802 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007803 } else {
7804 tw32(HOSTCC_TXCOL_TICKS, 0);
7805 tw32(HOSTCC_TXMAX_FRAMES, 0);
7806 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
Matt Carlson19cfaec2009-12-03 08:36:20 +00007807 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007808
Matt Carlson20d73752010-07-11 09:31:41 +00007809 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
Matt Carlson19cfaec2009-12-03 08:36:20 +00007810 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7811 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7812 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7813 } else {
Matt Carlsonb6080e12009-09-01 13:12:00 +00007814 tw32(HOSTCC_RXCOL_TICKS, 0);
7815 tw32(HOSTCC_RXMAX_FRAMES, 0);
7816 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
David S. Miller15f98502005-05-18 22:49:26 -07007817 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007818
David S. Miller15f98502005-05-18 22:49:26 -07007819 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7820 u32 val = ec->stats_block_coalesce_usecs;
7821
Matt Carlsonb6080e12009-09-01 13:12:00 +00007822 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7823 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7824
David S. Miller15f98502005-05-18 22:49:26 -07007825 if (!netif_carrier_ok(tp->dev))
7826 val = 0;
7827
7828 tw32(HOSTCC_STAT_COAL_TICKS, val);
7829 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007830
7831 for (i = 0; i < tp->irq_cnt - 1; i++) {
7832 u32 reg;
7833
7834 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7835 tw32(reg, ec->rx_coalesce_usecs);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007836 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7837 tw32(reg, ec->rx_max_coalesced_frames);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007838 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7839 tw32(reg, ec->rx_max_coalesced_frames_irq);
Matt Carlson19cfaec2009-12-03 08:36:20 +00007840
7841 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7842 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7843 tw32(reg, ec->tx_coalesce_usecs);
7844 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7845 tw32(reg, ec->tx_max_coalesced_frames);
7846 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7847 tw32(reg, ec->tx_max_coalesced_frames_irq);
7848 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007849 }
7850
7851 for (; i < tp->irq_max - 1; i++) {
7852 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007853 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007854 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
Matt Carlson19cfaec2009-12-03 08:36:20 +00007855
7856 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7857 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7858 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7859 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7860 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007861 }
David S. Miller15f98502005-05-18 22:49:26 -07007862}
Linus Torvalds1da177e2005-04-16 15:20:36 -07007863
7864/* tp->lock is held. */
Matt Carlson2d31eca2009-09-01 12:53:31 +00007865static void tg3_rings_reset(struct tg3 *tp)
7866{
7867 int i;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007868 u32 stblk, txrcb, rxrcb, limit;
Matt Carlson2d31eca2009-09-01 12:53:31 +00007869 struct tg3_napi *tnapi = &tp->napi[0];
7870
7871 /* Disable all transmit rings but the first. */
7872 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7873 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
Matt Carlson0a58d662011-04-05 14:22:45 +00007874 else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
Matt Carlson3d377282010-10-14 10:37:39 +00007875 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
Matt Carlsonb703df62009-12-03 08:36:21 +00007876 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7877 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
Matt Carlson2d31eca2009-09-01 12:53:31 +00007878 else
7879 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7880
7881 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7882 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7883 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7884 BDINFO_FLAGS_DISABLED);
7885
7886
7887 /* Disable all receive return rings but the first. */
Matt Carlson0a58d662011-04-05 14:22:45 +00007888 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00007889 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7890 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
Matt Carlson2d31eca2009-09-01 12:53:31 +00007891 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
Matt Carlsonb703df62009-12-03 08:36:21 +00007892 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson2d31eca2009-09-01 12:53:31 +00007894 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7895 else
7896 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7897
7898 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7899 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7900 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7901 BDINFO_FLAGS_DISABLED);
7902
7903 /* Disable interrupts */
7904 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7905
7906 /* Zero mailbox registers. */
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007907 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
Matt Carlson6fd45cb2010-09-15 08:59:57 +00007908 for (i = 1; i < tp->irq_max; i++) {
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007909 tp->napi[i].tx_prod = 0;
7910 tp->napi[i].tx_cons = 0;
Matt Carlsonc2353a32010-01-20 16:58:08 +00007911 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7912 tw32_mailbox(tp->napi[i].prodmbox, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007913 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7914 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7915 }
Matt Carlsonc2353a32010-01-20 16:58:08 +00007916 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7917 tw32_mailbox(tp->napi[0].prodmbox, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007918 } else {
7919 tp->napi[0].tx_prod = 0;
7920 tp->napi[0].tx_cons = 0;
7921 tw32_mailbox(tp->napi[0].prodmbox, 0);
7922 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7923 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00007924
7925 /* Make sure the NIC-based send BD rings are disabled. */
7926 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7927 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7928 for (i = 0; i < 16; i++)
7929 tw32_tx_mbox(mbox + i * 8, 0);
7930 }
7931
7932 txrcb = NIC_SRAM_SEND_RCB;
7933 rxrcb = NIC_SRAM_RCV_RET_RCB;
7934
7935 /* Clear status block in ram. */
7936 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7937
7938 /* Set status block DMA address */
7939 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7940 ((u64) tnapi->status_mapping >> 32));
7941 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7942 ((u64) tnapi->status_mapping & 0xffffffff));
7943
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007944 if (tnapi->tx_ring) {
7945 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7946 (TG3_TX_RING_SIZE <<
7947 BDINFO_FLAGS_MAXLEN_SHIFT),
7948 NIC_SRAM_TX_BUFFER_DESC);
7949 txrcb += TG3_BDINFO_SIZE;
7950 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00007951
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007952 if (tnapi->rx_rcb) {
7953 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
Matt Carlson7cb32cf2010-09-30 10:34:36 +00007954 (tp->rx_ret_ring_mask + 1) <<
7955 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007956 rxrcb += TG3_BDINFO_SIZE;
7957 }
7958
7959 stblk = HOSTCC_STATBLCK_RING1;
7960
7961 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7962 u64 mapping = (u64)tnapi->status_mapping;
7963 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7964 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7965
7966 /* Clear status block in ram. */
7967 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7968
Matt Carlson19cfaec2009-12-03 08:36:20 +00007969 if (tnapi->tx_ring) {
7970 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7971 (TG3_TX_RING_SIZE <<
7972 BDINFO_FLAGS_MAXLEN_SHIFT),
7973 NIC_SRAM_TX_BUFFER_DESC);
7974 txrcb += TG3_BDINFO_SIZE;
7975 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007976
7977 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
Matt Carlson7cb32cf2010-09-30 10:34:36 +00007978 ((tp->rx_ret_ring_mask + 1) <<
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007979 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7980
7981 stblk += 8;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007982 rxrcb += TG3_BDINFO_SIZE;
7983 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00007984}
7985
Matt Carlsoneb07a942011-04-20 07:57:36 +00007986static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
7987{
7988 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
7989
7990 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS) ||
7991 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
7992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7994 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
7995 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
7997 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
7998 else
7999 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8000
8001 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8002 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8003
8004 val = min(nic_rep_thresh, host_rep_thresh);
8005 tw32(RCVBDI_STD_THRESH, val);
8006
8007 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
8008 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8009
8010 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
8011 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8012 return;
8013
8014 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8015 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8016 else
8017 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
8018
8019 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8020
8021 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8022 tw32(RCVBDI_JUMBO_THRESH, val);
8023
8024 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
8025 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8026}
8027
Matt Carlson2d31eca2009-09-01 12:53:31 +00008028/* tp->lock is held. */
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07008029static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07008030{
8031 u32 val, rdmac_mode;
8032 int i, err, limit;
Matt Carlson8fea32b2010-09-15 08:59:58 +00008033 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008034
8035 tg3_disable_ints(tp);
8036
8037 tg3_stop_fw(tp);
8038
8039 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8040
Matt Carlson859a588792010-04-05 10:19:28 +00008041 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
Michael Chane6de8ad2005-05-05 14:42:41 -07008042 tg3_abort_hw(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008043
Matt Carlson699c0192010-12-06 08:28:51 +00008044 /* Enable MAC control of LPI */
8045 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8046 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8047 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8048 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8049
8050 tw32_f(TG3_CPMU_EEE_CTRL,
8051 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8052
Matt Carlsona386b902010-12-06 08:28:53 +00008053 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8054 TG3_CPMU_EEEMD_LPI_IN_TX |
8055 TG3_CPMU_EEEMD_LPI_IN_RX |
8056 TG3_CPMU_EEEMD_EEE_ENABLE;
8057
8058 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8059 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8060
8061 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8062 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8063
8064 tw32_f(TG3_CPMU_EEE_MODE, val);
8065
8066 tw32_f(TG3_CPMU_EEE_DBTMR1,
8067 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8068 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8069
8070 tw32_f(TG3_CPMU_EEE_DBTMR2,
Matt Carlsond7f2ab22011-01-25 15:58:56 +00008071 TG3_CPMU_DBTMR2_APE_TX_2047US |
Matt Carlsona386b902010-12-06 08:28:53 +00008072 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
Matt Carlson699c0192010-12-06 08:28:51 +00008073 }
8074
Matt Carlson603f1172010-02-12 14:47:10 +00008075 if (reset_phy)
Michael Chand4d2c552006-03-20 17:47:20 -08008076 tg3_phy_reset(tp);
8077
Linus Torvalds1da177e2005-04-16 15:20:36 -07008078 err = tg3_chip_reset(tp);
8079 if (err)
8080 return err;
8081
8082 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8083
Matt Carlsonbcb37f62008-11-03 16:52:09 -08008084 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
Matt Carlsond30cdd22007-10-07 23:28:35 -07008085 val = tr32(TG3_CPMU_CTRL);
8086 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8087 tw32(TG3_CPMU_CTRL, val);
Matt Carlson9acb9612007-11-12 21:10:06 -08008088
8089 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8090 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8091 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8092 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8093
8094 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8095 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8096 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8097 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8098
8099 val = tr32(TG3_CPMU_HST_ACC);
8100 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8101 val |= CPMU_HST_ACC_MACCLK_6_25;
8102 tw32(TG3_CPMU_HST_ACC, val);
Matt Carlsond30cdd22007-10-07 23:28:35 -07008103 }
8104
Matt Carlson33466d92009-04-20 06:57:41 +00008105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8106 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8107 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8108 PCIE_PWR_MGMT_L1_THRESH_4MS;
8109 tw32(PCIE_PWR_MGMT_THRESH, val);
Matt Carlson521e6b92009-08-25 10:06:01 +00008110
8111 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8112 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8113
8114 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
Matt Carlson33466d92009-04-20 06:57:41 +00008115
Matt Carlsonf40386c2009-11-02 14:24:02 +00008116 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8117 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
Matt Carlson255ca312009-08-25 10:07:27 +00008118 }
8119
Matt Carlson614b0592010-01-20 16:58:02 +00008120 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
8121 u32 grc_mode = tr32(GRC_MODE);
8122
8123 /* Access the lower 1K of PL PCIE block registers. */
8124 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8125 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8126
8127 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8128 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8129 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8130
8131 tw32(GRC_MODE, grc_mode);
8132 }
8133
Matt Carlson5093eed2010-11-24 08:31:45 +00008134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8135 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8136 u32 grc_mode = tr32(GRC_MODE);
Matt Carlsoncea46462010-04-12 06:58:24 +00008137
Matt Carlson5093eed2010-11-24 08:31:45 +00008138 /* Access the lower 1K of PL PCIE block registers. */
8139 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8140 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
Matt Carlsoncea46462010-04-12 06:58:24 +00008141
Matt Carlson5093eed2010-11-24 08:31:45 +00008142 val = tr32(TG3_PCIE_TLDLPL_PORT +
8143 TG3_PCIE_PL_LO_PHYCTL5);
8144 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8145 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
Matt Carlsoncea46462010-04-12 06:58:24 +00008146
Matt Carlson5093eed2010-11-24 08:31:45 +00008147 tw32(GRC_MODE, grc_mode);
8148 }
Matt Carlsona977dbe2010-04-12 06:58:26 +00008149
8150 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8151 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8152 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8153 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
Matt Carlsoncea46462010-04-12 06:58:24 +00008154 }
8155
Linus Torvalds1da177e2005-04-16 15:20:36 -07008156 /* This works around an issue with Athlon chipsets on
8157 * B3 tigon3 silicon. This bit has no effect on any
8158 * other revision. But do not set this on PCI Express
Matt Carlson795d01c2007-10-07 23:28:17 -07008159 * chips and don't even touch the clocks if the CPMU is present.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008160 */
Matt Carlson795d01c2007-10-07 23:28:17 -07008161 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
8162 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8163 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8164 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8165 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008166
8167 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8168 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
8169 val = tr32(TG3PCI_PCISTATE);
8170 val |= PCISTATE_RETRY_SAME_DMA;
8171 tw32(TG3PCI_PCISTATE, val);
8172 }
8173
Matt Carlson0d3031d2007-10-10 18:02:43 -07008174 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
8175 /* Allow reads and writes to the
8176 * APE register and memory space.
8177 */
8178 val = tr32(TG3PCI_PCISTATE);
8179 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00008180 PCISTATE_ALLOW_APE_SHMEM_WR |
8181 PCISTATE_ALLOW_APE_PSPACE_WR;
Matt Carlson0d3031d2007-10-10 18:02:43 -07008182 tw32(TG3PCI_PCISTATE, val);
8183 }
8184
Linus Torvalds1da177e2005-04-16 15:20:36 -07008185 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8186 /* Enable some hw fixes. */
8187 val = tr32(TG3PCI_MSI_DATA);
8188 val |= (1 << 26) | (1 << 28) | (1 << 29);
8189 tw32(TG3PCI_MSI_DATA, val);
8190 }
8191
8192 /* Descriptor ring init may make accesses to the
8193 * NIC SRAM area to setup the TX descriptors, so we
8194 * can only do this after the hardware has been
8195 * successfully reset.
8196 */
Michael Chan32d8c572006-07-25 16:38:29 -07008197 err = tg3_init_rings(tp);
8198 if (err)
8199 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008200
Matt Carlson1407deb2011-04-05 14:22:44 +00008201 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
Matt Carlsoncbf9ca62009-11-13 13:03:40 +00008202 val = tr32(TG3PCI_DMA_RW_CTRL) &
8203 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
Matt Carlson1a319022010-04-12 06:58:25 +00008204 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8205 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
Matt Carlsoncbf9ca62009-11-13 13:03:40 +00008206 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8207 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8208 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
Matt Carlsond30cdd22007-10-07 23:28:35 -07008209 /* This value is determined during the probe time DMA
8210 * engine test, tg3_test_dma.
8211 */
8212 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8213 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008214
8215 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8216 GRC_MODE_4X_NIC_SEND_RINGS |
8217 GRC_MODE_NO_TX_PHDR_CSUM |
8218 GRC_MODE_NO_RX_PHDR_CSUM);
8219 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
Michael Chand2d746f2006-04-06 21:45:39 -07008220
8221 /* Pseudo-header checksum is done by hardware logic and not
8222 * the offload processers, so make the chip do the pseudo-
8223 * header checksums on receive. For transmit it is more
8224 * convenient to do the pseudo-header checksum in software
8225 * as Linux does that on transmit for us in all cases.
8226 */
8227 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008228
8229 tw32(GRC_MODE,
8230 tp->grc_mode |
8231 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8232
8233 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8234 val = tr32(GRC_MISC_CFG);
8235 val &= ~0xff;
8236 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8237 tw32(GRC_MISC_CFG, val);
8238
8239 /* Initialize MBUF/DESC pool. */
John W. Linvillecbf46852005-04-21 17:01:29 -07008240 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008241 /* Do nothing. */
8242 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8243 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8245 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8246 else
8247 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8248 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8249 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
Matt Carlson859a588792010-04-05 10:19:28 +00008250 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008251 int fw_len;
8252
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08008253 fw_len = tp->fw_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008254 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8255 tw32(BUFMGR_MB_POOL_ADDR,
8256 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8257 tw32(BUFMGR_MB_POOL_SIZE,
8258 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8259 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008260
Michael Chan0f893dc2005-07-25 12:30:38 -07008261 if (tp->dev->mtu <= ETH_DATA_LEN) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008262 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8263 tp->bufmgr_config.mbuf_read_dma_low_water);
8264 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8265 tp->bufmgr_config.mbuf_mac_rx_low_water);
8266 tw32(BUFMGR_MB_HIGH_WATER,
8267 tp->bufmgr_config.mbuf_high_water);
8268 } else {
8269 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8270 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8271 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8272 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8273 tw32(BUFMGR_MB_HIGH_WATER,
8274 tp->bufmgr_config.mbuf_high_water_jumbo);
8275 }
8276 tw32(BUFMGR_DMA_LOW_WATER,
8277 tp->bufmgr_config.dma_low_water);
8278 tw32(BUFMGR_DMA_HIGH_WATER,
8279 tp->bufmgr_config.dma_high_water);
8280
Matt Carlsond309a462010-09-30 10:34:31 +00008281 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8282 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8283 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
Matt Carlson4d958472011-04-20 07:57:35 +00008284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8285 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8286 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8287 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
Matt Carlsond309a462010-09-30 10:34:31 +00008288 tw32(BUFMGR_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008289 for (i = 0; i < 2000; i++) {
8290 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8291 break;
8292 udelay(10);
8293 }
8294 if (i >= 2000) {
Joe Perches05dbe002010-02-17 19:44:19 +00008295 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008296 return -ENODEV;
8297 }
8298
Matt Carlsoneb07a942011-04-20 07:57:36 +00008299 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8300 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
Michael Chanb5d37722006-09-27 16:06:21 -07008301
Matt Carlsoneb07a942011-04-20 07:57:36 +00008302 tg3_setup_rxbd_thresholds(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008303
8304 /* Initialize TG3_BDINFO's at:
8305 * RCVDBDI_STD_BD: standard eth size rx ring
8306 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8307 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8308 *
8309 * like so:
8310 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8311 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8312 * ring attribute flags
8313 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8314 *
8315 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8316 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8317 *
8318 * The size of each ring is fixed in the firmware, but the location is
8319 * configurable.
8320 */
8321 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
Matt Carlson21f581a2009-08-28 14:00:25 +00008322 ((u64) tpr->rx_std_mapping >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07008323 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
Matt Carlson21f581a2009-08-28 14:00:25 +00008324 ((u64) tpr->rx_std_mapping & 0xffffffff));
Matt Carlson0a58d662011-04-05 14:22:45 +00008325 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
Matt Carlson87668d32009-11-13 13:03:34 +00008326 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8327 NIC_SRAM_RX_BUFFER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008328
Matt Carlsonfdb72b32009-08-28 13:57:12 +00008329 /* Disable the mini ring */
8330 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008331 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8332 BDINFO_FLAGS_DISABLED);
8333
Matt Carlsonfdb72b32009-08-28 13:57:12 +00008334 /* Program the jumbo buffer descriptor ring control
8335 * blocks on those devices that have them.
8336 */
Matt Carlsonbb18bb92011-03-09 16:58:19 +00008337 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
Matt Carlson4d163b72011-01-25 15:58:48 +00008338 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8339 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008340
Michael Chan0f893dc2005-07-25 12:30:38 -07008341 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008342 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
Matt Carlson21f581a2009-08-28 14:00:25 +00008343 ((u64) tpr->rx_jmb_mapping >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07008344 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
Matt Carlson21f581a2009-08-28 14:00:25 +00008345 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
Matt Carlsonde9f5232011-04-05 14:22:43 +00008346 val = TG3_RX_JMB_RING_SIZE(tp) <<
8347 BDINFO_FLAGS_MAXLEN_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008348 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
Matt Carlsonde9f5232011-04-05 14:22:43 +00008349 val | BDINFO_FLAGS_USE_EXT_RECV);
Matt Carlsona50d0792010-06-05 17:24:37 +00008350 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson87668d32009-11-13 13:03:34 +00008352 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8353 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008354 } else {
8355 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8356 BDINFO_FLAGS_DISABLED);
8357 }
8358
Matt Carlson1407deb2011-04-05 14:22:44 +00008359 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlsonde9f5232011-04-05 14:22:43 +00008361 val = TG3_RX_STD_MAX_SIZE_5700;
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008362 else
Matt Carlsonde9f5232011-04-05 14:22:43 +00008363 val = TG3_RX_STD_MAX_SIZE_5717;
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008364 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8365 val |= (TG3_RX_STD_DMA_SZ << 2);
8366 } else
Matt Carlson04380d42010-04-12 06:58:29 +00008367 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
Matt Carlsonfdb72b32009-08-28 13:57:12 +00008368 } else
Matt Carlsonde9f5232011-04-05 14:22:43 +00008369 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
Matt Carlsonfdb72b32009-08-28 13:57:12 +00008370
8371 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008372
Matt Carlson411da642009-11-13 13:03:46 +00008373 tpr->rx_std_prod_idx = tp->rx_pending;
Matt Carlson66711e62009-11-13 13:03:49 +00008374 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008375
Matt Carlson411da642009-11-13 13:03:46 +00008376 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
Matt Carlson21f581a2009-08-28 14:00:25 +00008377 tp->rx_jumbo_pending : 0;
Matt Carlson66711e62009-11-13 13:03:49 +00008378 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008379
Matt Carlson2d31eca2009-09-01 12:53:31 +00008380 tg3_rings_reset(tp);
8381
Linus Torvalds1da177e2005-04-16 15:20:36 -07008382 /* Initialize MAC address and backoff seed. */
Michael Chan986e0ae2007-05-05 12:10:20 -07008383 __tg3_set_mac_addr(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008384
8385 /* MTU + ethernet header + FCS + optional VLAN tag */
Matt Carlsonf7b493e2009-02-25 14:21:52 +00008386 tw32(MAC_RX_MTU_SIZE,
8387 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008388
8389 /* The slot time is changed by tg3_setup_phy if we
8390 * run at gigabit with half duplex.
8391 */
Matt Carlsonf2096f92011-04-05 14:22:48 +00008392 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8393 (6 << TX_LENGTHS_IPG_SHIFT) |
8394 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8395
8396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8397 val |= tr32(MAC_TX_LENGTHS) &
8398 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8399 TX_LENGTHS_CNT_DWN_VAL_MSK);
8400
8401 tw32(MAC_TX_LENGTHS, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008402
8403 /* Receive rules. */
8404 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8405 tw32(RCVLPC_CONFIG, 0x0181);
8406
8407 /* Calculate RDMAC_MODE setting early, we need it to determine
8408 * the RCVLPC_STATE_ENABLE mask.
8409 */
8410 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8411 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8412 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8413 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8414 RDMAC_MODE_LNGREAD_ENAB);
Michael Chan85e94ce2005-04-21 17:05:28 -07008415
Matt Carlsondeabaac2010-11-24 08:31:50 +00008416 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
Matt Carlson0339e4e2010-02-12 14:47:09 +00008417 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8418
Matt Carlson57e69832008-05-25 23:48:31 -07008419 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson321d32a2008-11-21 17:22:19 -08008420 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8421 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlsond30cdd22007-10-07 23:28:35 -07008422 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8423 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8424 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8425
Matt Carlsonc5908932011-03-09 16:58:25 +00008426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8427 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008428 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
Matt Carlsonc13e3712007-05-05 11:50:04 -07008429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008430 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8431 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8432 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8433 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8434 }
8435 }
8436
Michael Chan85e94ce2005-04-21 17:05:28 -07008437 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8438 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8439
Linus Torvalds1da177e2005-04-16 15:20:36 -07008440 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
Matt Carlson027455a2008-12-21 20:19:30 -08008441 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8442
Matt Carlsone849cdc2009-11-13 13:03:38 +00008443 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlson027455a2008-12-21 20:19:30 -08008445 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8446 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008447
Matt Carlsonf2096f92011-04-05 14:22:48 +00008448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8449 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8450
Matt Carlson41a8a7e2010-09-15 08:59:53 +00008451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8452 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8453 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Matt Carlson1407deb2011-04-05 14:22:44 +00008455 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
Matt Carlson41a8a7e2010-09-15 08:59:53 +00008456 val = tr32(TG3_RDMA_RSRVCTRL_REG);
Matt Carlsond78b59f2011-04-05 14:22:46 +00008457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8458 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Matt Carlsonb4495ed2011-01-25 15:58:47 +00008459 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8460 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8461 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8462 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8463 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8464 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
Matt Carlsonb75cc0e2010-11-24 08:31:46 +00008465 }
Matt Carlson41a8a7e2010-09-15 08:59:53 +00008466 tw32(TG3_RDMA_RSRVCTRL_REG,
8467 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8468 }
8469
Matt Carlsond78b59f2011-04-05 14:22:46 +00008470 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8471 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Matt Carlsond309a462010-09-30 10:34:31 +00008472 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8473 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8474 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8475 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8476 }
8477
Linus Torvalds1da177e2005-04-16 15:20:36 -07008478 /* Receive/send statistics. */
Michael Chan16613942006-06-29 20:15:13 -07008479 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8480 val = tr32(RCVLPC_STATS_ENABLE);
8481 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8482 tw32(RCVLPC_STATS_ENABLE, val);
8483 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8484 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008485 val = tr32(RCVLPC_STATS_ENABLE);
8486 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8487 tw32(RCVLPC_STATS_ENABLE, val);
8488 } else {
8489 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8490 }
8491 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8492 tw32(SNDDATAI_STATSENAB, 0xffffff);
8493 tw32(SNDDATAI_STATSCTRL,
8494 (SNDDATAI_SCTRL_ENABLE |
8495 SNDDATAI_SCTRL_FASTUPD));
8496
8497 /* Setup host coalescing engine. */
8498 tw32(HOSTCC_MODE, 0);
8499 for (i = 0; i < 2000; i++) {
8500 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8501 break;
8502 udelay(10);
8503 }
8504
Michael Chand244c892005-07-05 14:42:33 -07008505 __tg3_set_coalesce(tp, &tp->coal);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008506
Linus Torvalds1da177e2005-04-16 15:20:36 -07008507 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8508 /* Status/statistics block address. See tg3_timer,
8509 * the tg3_periodic_fetch_stats call there, and
8510 * tg3_get_stats to see how this works for 5705/5750 chips.
8511 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07008512 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8513 ((u64) tp->stats_mapping >> 32));
8514 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8515 ((u64) tp->stats_mapping & 0xffffffff));
8516 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
Matt Carlson2d31eca2009-09-01 12:53:31 +00008517
Linus Torvalds1da177e2005-04-16 15:20:36 -07008518 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
Matt Carlson2d31eca2009-09-01 12:53:31 +00008519
8520 /* Clear statistics and status block memory areas */
8521 for (i = NIC_SRAM_STATS_BLK;
8522 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8523 i += sizeof(u32)) {
8524 tg3_write_mem(tp, i, 0);
8525 udelay(40);
8526 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008527 }
8528
8529 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8530
8531 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8532 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8533 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8534 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8535
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008536 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8537 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chanc94e3942005-09-27 12:12:42 -07008538 /* reset to prevent losing 1st rx packet intermittently */
8539 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8540 udelay(10);
8541 }
8542
Matt Carlson3bda1252008-08-15 14:08:22 -07008543 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
Matt Carlsond2394e6b2010-11-24 08:31:47 +00008544 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
Matt Carlson3bda1252008-08-15 14:08:22 -07008545 else
8546 tp->mac_mode = 0;
8547 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
Linus Torvalds1da177e2005-04-16 15:20:36 -07008548 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07008549 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008550 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07008551 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8552 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008553 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8554 udelay(40);
8555
Michael Chan314fba32005-04-21 17:07:04 -07008556 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
Michael Chan9d26e212006-12-07 00:21:14 -08008557 * If TG3_FLG2_IS_NIC is zero, we should read the
Michael Chan314fba32005-04-21 17:07:04 -07008558 * register to preserve the GPIO settings for LOMs. The GPIOs,
8559 * whether used as inputs or outputs, are set by boot code after
8560 * reset.
8561 */
Michael Chan9d26e212006-12-07 00:21:14 -08008562 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
Michael Chan314fba32005-04-21 17:07:04 -07008563 u32 gpio_mask;
8564
Michael Chan9d26e212006-12-07 00:21:14 -08008565 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8566 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8567 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
Michael Chan3e7d83b2005-04-21 17:10:36 -07008568
8569 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8570 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8571 GRC_LCLCTRL_GPIO_OUTPUT3;
8572
Michael Chanaf36e6b2006-03-23 01:28:06 -08008573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8574 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8575
Gary Zambranoaaf84462007-05-05 11:51:45 -07008576 tp->grc_local_ctrl &= ~gpio_mask;
Michael Chan314fba32005-04-21 17:07:04 -07008577 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8578
8579 /* GPIO1 must be driven high for eeprom write protect */
Michael Chan9d26e212006-12-07 00:21:14 -08008580 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8581 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8582 GRC_LCLCTRL_GPIO_OUTPUT1);
Michael Chan314fba32005-04-21 17:07:04 -07008583 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008584 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8585 udelay(100);
8586
Matt Carlson0583d522011-01-25 15:58:50 +00008587 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
8588 tp->irq_cnt > 1) {
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008589 val = tr32(MSGINT_MODE);
8590 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8591 tw32(MSGINT_MODE, val);
8592 }
8593
Linus Torvalds1da177e2005-04-16 15:20:36 -07008594 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8595 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8596 udelay(40);
8597 }
8598
8599 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8600 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8601 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8602 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8603 WDMAC_MODE_LNGREAD_ENAB);
8604
Matt Carlsonc5908932011-03-09 16:58:25 +00008605 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8606 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
Matt Carlson29ea0952009-08-25 10:07:54 +00008607 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07008608 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8609 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8610 /* nothing */
8611 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
Matt Carlsonc5908932011-03-09 16:58:25 +00008612 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008613 val |= WDMAC_MODE_RX_ACCEL;
8614 }
8615 }
8616
Michael Chand9ab5ad12006-03-20 22:27:35 -08008617 /* Enable host coalescing bug fix */
Matt Carlson321d32a2008-11-21 17:22:19 -08008618 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Matt Carlsonf51f3562008-05-25 23:45:08 -07008619 val |= WDMAC_MODE_STATUS_TAG_FIX;
Michael Chand9ab5ad12006-03-20 22:27:35 -08008620
Matt Carlson788a0352009-11-02 14:26:03 +00008621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8622 val |= WDMAC_MODE_BURST_ALL_DATA;
8623
Linus Torvalds1da177e2005-04-16 15:20:36 -07008624 tw32_f(WDMAC_MODE, val);
8625 udelay(40);
8626
Matt Carlson9974a352007-10-07 23:27:28 -07008627 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8628 u16 pcix_cmd;
8629
8630 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8631 &pcix_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
Matt Carlson9974a352007-10-07 23:27:28 -07008633 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8634 pcix_cmd |= PCI_X_CMD_READ_2K;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008635 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
Matt Carlson9974a352007-10-07 23:27:28 -07008636 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8637 pcix_cmd |= PCI_X_CMD_READ_2K;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008638 }
Matt Carlson9974a352007-10-07 23:27:28 -07008639 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8640 pcix_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008641 }
8642
8643 tw32_f(RDMAC_MODE, rdmac_mode);
8644 udelay(40);
8645
8646 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8647 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8648 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
Matt Carlson9936bcf2007-10-10 18:03:07 -07008649
8650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8651 tw32(SNDDATAC_MODE,
8652 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8653 else
8654 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8655
Linus Torvalds1da177e2005-04-16 15:20:36 -07008656 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8657 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008658 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
Matt Carlsonde9f5232011-04-05 14:22:43 +00008659 if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008660 val |= RCVDBDI_MODE_LRG_RING_SZ;
8661 tw32(RCVDBDI_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008662 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008663 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8664 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008665 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
Matt Carlson19cfaec2009-12-03 08:36:20 +00008666 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008667 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8668 tw32(SNDBDI_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008669 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8670
8671 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8672 err = tg3_load_5701_a0_firmware_fix(tp);
8673 if (err)
8674 return err;
8675 }
8676
Linus Torvalds1da177e2005-04-16 15:20:36 -07008677 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8678 err = tg3_load_tso_firmware(tp);
8679 if (err)
8680 return err;
8681 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008682
8683 tp->tx_mode = TX_MODE_ENABLE;
Matt Carlsonf2096f92011-04-05 14:22:48 +00008684
Matt Carlsonb1d05212010-06-05 17:24:31 +00008685 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8686 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8687 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
Matt Carlsonf2096f92011-04-05 14:22:48 +00008688
8689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8690 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8691 tp->tx_mode &= ~val;
8692 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8693 }
8694
Linus Torvalds1da177e2005-04-16 15:20:36 -07008695 tw32_f(MAC_TX_MODE, tp->tx_mode);
8696 udelay(100);
8697
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008698 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8699 u32 reg = MAC_RSS_INDIR_TBL_0;
8700 u8 *ent = (u8 *)&val;
8701
8702 /* Setup the indirection table */
8703 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8704 int idx = i % sizeof(val);
8705
Matt Carlson5efeeea2010-07-11 09:31:40 +00008706 ent[idx] = i % (tp->irq_cnt - 1);
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008707 if (idx == sizeof(val) - 1) {
8708 tw32(reg, val);
8709 reg += 4;
8710 }
8711 }
8712
8713 /* Setup the "secret" hash key. */
8714 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8715 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8716 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8717 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8718 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8719 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8720 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8721 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8722 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8723 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8724 }
8725
Linus Torvalds1da177e2005-04-16 15:20:36 -07008726 tp->rx_mode = RX_MODE_ENABLE;
Matt Carlson321d32a2008-11-21 17:22:19 -08008727 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Michael Chanaf36e6b2006-03-23 01:28:06 -08008728 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8729
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008730 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8731 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8732 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8733 RX_MODE_RSS_IPV6_HASH_EN |
8734 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8735 RX_MODE_RSS_IPV4_HASH_EN |
8736 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8737
Linus Torvalds1da177e2005-04-16 15:20:36 -07008738 tw32_f(MAC_RX_MODE, tp->rx_mode);
8739 udelay(10);
8740
Linus Torvalds1da177e2005-04-16 15:20:36 -07008741 tw32(MAC_LED_CTRL, tp->led_ctrl);
8742
8743 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008744 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008745 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8746 udelay(10);
8747 }
8748 tw32_f(MAC_RX_MODE, tp->rx_mode);
8749 udelay(10);
8750
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008751 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008752 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008753 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008754 /* Set drive transmission level to 1.2V */
8755 /* only if the signal pre-emphasis bit is not set */
8756 val = tr32(MAC_SERDES_CFG);
8757 val &= 0xfffff000;
8758 val |= 0x880;
8759 tw32(MAC_SERDES_CFG, val);
8760 }
8761 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8762 tw32(MAC_SERDES_CFG, 0x616000);
8763 }
8764
8765 /* Prevent chip from dropping frames when flow control
8766 * is enabled.
8767 */
Matt Carlson666bc832010-01-20 16:58:03 +00008768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8769 val = 1;
8770 else
8771 val = 2;
8772 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008773
8774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008775 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008776 /* Use hardware link auto-negotiation */
8777 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8778 }
8779
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008780 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
Michael Chand4d2c552006-03-20 17:47:20 -08008781 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8782 u32 tmp;
8783
8784 tmp = tr32(SERDES_RX_CTRL);
8785 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8786 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8787 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8788 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8789 }
8790
Matt Carlsondd477002008-05-25 23:45:58 -07008791 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
Matt Carlson80096062010-08-02 11:26:06 +00008792 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8793 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsondd477002008-05-25 23:45:58 -07008794 tp->link_config.speed = tp->link_config.orig_speed;
8795 tp->link_config.duplex = tp->link_config.orig_duplex;
8796 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8797 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008798
Matt Carlsondd477002008-05-25 23:45:58 -07008799 err = tg3_setup_phy(tp, 0);
8800 if (err)
8801 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008802
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008803 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8804 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
Matt Carlsondd477002008-05-25 23:45:58 -07008805 u32 tmp;
8806
8807 /* Clear CRC stats. */
8808 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8809 tg3_writephy(tp, MII_TG3_TEST1,
8810 tmp | MII_TG3_TEST1_CRC_EN);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00008811 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
Matt Carlsondd477002008-05-25 23:45:58 -07008812 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008813 }
8814 }
8815
8816 __tg3_set_rx_mode(tp->dev);
8817
8818 /* Initialize receive rules. */
8819 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8820 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8821 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8822 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8823
Michael Chan4cf78e42005-07-25 12:29:19 -07008824 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
Michael Chana4e2b342005-10-26 15:46:52 -07008825 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008826 limit = 8;
8827 else
8828 limit = 16;
8829 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8830 limit -= 4;
8831 switch (limit) {
8832 case 16:
8833 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8834 case 15:
8835 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8836 case 14:
8837 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8838 case 13:
8839 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8840 case 12:
8841 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8842 case 11:
8843 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8844 case 10:
8845 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8846 case 9:
8847 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8848 case 8:
8849 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8850 case 7:
8851 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8852 case 6:
8853 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8854 case 5:
8855 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8856 case 4:
8857 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8858 case 3:
8859 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8860 case 2:
8861 case 1:
8862
8863 default:
8864 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07008865 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008866
Matt Carlson9ce768e2007-10-11 19:49:11 -07008867 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8868 /* Write our heartbeat update interval to APE. */
8869 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8870 APE_HOST_HEARTBEAT_INT_DISABLE);
Matt Carlson0d3031d2007-10-10 18:02:43 -07008871
Linus Torvalds1da177e2005-04-16 15:20:36 -07008872 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8873
Linus Torvalds1da177e2005-04-16 15:20:36 -07008874 return 0;
8875}
8876
8877/* Called at device open time to get the chip ready for
8878 * packet processing. Invoked with tp->lock held.
8879 */
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07008880static int tg3_init_hw(struct tg3 *tp, int reset_phy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07008881{
Linus Torvalds1da177e2005-04-16 15:20:36 -07008882 tg3_switch_clocks(tp);
8883
8884 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8885
Matt Carlson2f751b62008-08-04 23:17:34 -07008886 return tg3_reset_hw(tp, reset_phy);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008887}
8888
8889#define TG3_STAT_ADD32(PSTAT, REG) \
8890do { u32 __val = tr32(REG); \
8891 (PSTAT)->low += __val; \
8892 if ((PSTAT)->low < __val) \
8893 (PSTAT)->high += 1; \
8894} while (0)
8895
8896static void tg3_periodic_fetch_stats(struct tg3 *tp)
8897{
8898 struct tg3_hw_stats *sp = tp->hw_stats;
8899
8900 if (!netif_carrier_ok(tp->dev))
8901 return;
8902
8903 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8904 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8905 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8906 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8907 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8908 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8909 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8910 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8911 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8912 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8913 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8914 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8915 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8916
8917 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8918 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8919 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8920 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8921 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8922 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8923 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8924 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8925 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8926 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8927 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8928 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8929 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8930 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
Michael Chan463d3052006-05-22 16:36:27 -07008931
8932 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
Matt Carlson4d958472011-04-20 07:57:35 +00008933 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
8934 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8935 } else {
8936 u32 val = tr32(HOSTCC_FLOW_ATTN);
8937 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
8938 if (val) {
8939 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
8940 sp->rx_discards.low += val;
8941 if (sp->rx_discards.low < val)
8942 sp->rx_discards.high += 1;
8943 }
8944 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
8945 }
Michael Chan463d3052006-05-22 16:36:27 -07008946 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008947}
8948
8949static void tg3_timer(unsigned long __opaque)
8950{
8951 struct tg3 *tp = (struct tg3 *) __opaque;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008952
Michael Chanf475f162006-03-27 23:20:14 -08008953 if (tp->irq_sync)
8954 goto restart_timer;
8955
David S. Millerf47c11e2005-06-24 20:18:35 -07008956 spin_lock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008957
David S. Millerfac9b832005-05-18 22:46:34 -07008958 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8959 /* All of this garbage is because when using non-tagged
8960 * IRQ status the mailbox/status_block protocol the chip
8961 * uses with the cpu is race prone.
8962 */
Matt Carlson898a56f2009-08-28 14:02:40 +00008963 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
David S. Millerfac9b832005-05-18 22:46:34 -07008964 tw32(GRC_LOCAL_CTRL,
8965 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8966 } else {
8967 tw32(HOSTCC_MODE, tp->coalesce_mode |
Matt Carlsonfd2ce372009-09-01 12:51:13 +00008968 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
David S. Millerfac9b832005-05-18 22:46:34 -07008969 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008970
David S. Millerfac9b832005-05-18 22:46:34 -07008971 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8972 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
David S. Millerf47c11e2005-06-24 20:18:35 -07008973 spin_unlock(&tp->lock);
David S. Millerfac9b832005-05-18 22:46:34 -07008974 schedule_work(&tp->reset_task);
8975 return;
8976 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008977 }
8978
Linus Torvalds1da177e2005-04-16 15:20:36 -07008979 /* This part only runs once per second. */
8980 if (!--tp->timer_counter) {
David S. Millerfac9b832005-05-18 22:46:34 -07008981 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8982 tg3_periodic_fetch_stats(tp);
8983
Matt Carlson52b02d02010-10-14 10:37:41 +00008984 if (tp->setlpicnt && !--tp->setlpicnt) {
8985 u32 val = tr32(TG3_CPMU_EEE_MODE);
8986 tw32(TG3_CPMU_EEE_MODE,
8987 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8988 }
8989
Linus Torvalds1da177e2005-04-16 15:20:36 -07008990 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8991 u32 mac_stat;
8992 int phy_event;
8993
8994 mac_stat = tr32(MAC_STATUS);
8995
8996 phy_event = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008997 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008998 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8999 phy_event = 1;
9000 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9001 phy_event = 1;
9002
9003 if (phy_event)
9004 tg3_setup_phy(tp, 0);
9005 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
9006 u32 mac_stat = tr32(MAC_STATUS);
9007 int need_setup = 0;
9008
9009 if (netif_carrier_ok(tp->dev) &&
9010 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9011 need_setup = 1;
9012 }
Matt Carlsonbe98da62010-07-11 09:31:46 +00009013 if (!netif_carrier_ok(tp->dev) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07009014 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9015 MAC_STATUS_SIGNAL_DET))) {
9016 need_setup = 1;
9017 }
9018 if (need_setup) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07009019 if (!tp->serdes_counter) {
9020 tw32_f(MAC_MODE,
9021 (tp->mac_mode &
9022 ~MAC_MODE_PORT_MODE_MASK));
9023 udelay(40);
9024 tw32_f(MAC_MODE, tp->mac_mode);
9025 udelay(40);
9026 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009027 tg3_setup_phy(tp, 0);
9028 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009029 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
Matt Carlson2138c002010-07-11 09:31:43 +00009030 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Michael Chan747e8f82005-07-25 12:33:22 -07009031 tg3_serdes_parallel_detect(tp);
Matt Carlson57d8b882010-06-05 17:24:35 +00009032 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009033
9034 tp->timer_counter = tp->timer_multiplier;
9035 }
9036
Michael Chan130b8e42006-09-27 16:00:40 -07009037 /* Heartbeat is only sent once every 2 seconds.
9038 *
9039 * The heartbeat is to tell the ASF firmware that the host
9040 * driver is still alive. In the event that the OS crashes,
9041 * ASF needs to reset the hardware to free up the FIFO space
9042 * that may be filled with rx packets destined for the host.
9043 * If the FIFO is full, ASF will no longer function properly.
9044 *
9045 * Unintended resets have been reported on real time kernels
9046 * where the timer doesn't run on time. Netpoll will also have
9047 * same problem.
9048 *
9049 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9050 * to check the ring condition when the heartbeat is expiring
9051 * before doing the reset. This will prevent most unintended
9052 * resets.
9053 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07009054 if (!--tp->asf_counter) {
Matt Carlsonbc7959b2008-08-15 14:08:55 -07009055 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
9056 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
Matt Carlson7c5026a2008-05-02 16:49:29 -07009057 tg3_wait_for_event_ack(tp);
9058
Michael Chanbbadf502006-04-06 21:46:34 -07009059 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
Michael Chan130b8e42006-09-27 16:00:40 -07009060 FWCMD_NICDRV_ALIVE3);
Michael Chanbbadf502006-04-06 21:46:34 -07009061 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
Matt Carlsonc6cdf432010-04-05 10:19:26 +00009062 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9063 TG3_FW_UPDATE_TIMEOUT_SEC);
Matt Carlson4ba526c2008-08-15 14:10:04 -07009064
9065 tg3_generate_fw_event(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009066 }
9067 tp->asf_counter = tp->asf_multiplier;
9068 }
9069
David S. Millerf47c11e2005-06-24 20:18:35 -07009070 spin_unlock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009071
Michael Chanf475f162006-03-27 23:20:14 -08009072restart_timer:
Linus Torvalds1da177e2005-04-16 15:20:36 -07009073 tp->timer.expires = jiffies + tp->timer_offset;
9074 add_timer(&tp->timer);
9075}
9076
Matt Carlson4f125f42009-09-01 12:55:02 +00009077static int tg3_request_irq(struct tg3 *tp, int irq_num)
Michael Chanfcfa0a32006-03-20 22:28:41 -08009078{
David Howells7d12e782006-10-05 14:55:46 +01009079 irq_handler_t fn;
Michael Chanfcfa0a32006-03-20 22:28:41 -08009080 unsigned long flags;
Matt Carlson4f125f42009-09-01 12:55:02 +00009081 char *name;
9082 struct tg3_napi *tnapi = &tp->napi[irq_num];
9083
9084 if (tp->irq_cnt == 1)
9085 name = tp->dev->name;
9086 else {
9087 name = &tnapi->irq_lbl[0];
9088 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9089 name[IFNAMSIZ-1] = 0;
9090 }
Michael Chanfcfa0a32006-03-20 22:28:41 -08009091
Matt Carlson679563f2009-09-01 12:55:46 +00009092 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
Michael Chanfcfa0a32006-03-20 22:28:41 -08009093 fn = tg3_msi;
9094 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
9095 fn = tg3_msi_1shot;
Javier Martinez Canillasab392d22011-03-28 16:27:31 +00009096 flags = 0;
Michael Chanfcfa0a32006-03-20 22:28:41 -08009097 } else {
9098 fn = tg3_interrupt;
9099 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9100 fn = tg3_interrupt_tagged;
Javier Martinez Canillasab392d22011-03-28 16:27:31 +00009101 flags = IRQF_SHARED;
Michael Chanfcfa0a32006-03-20 22:28:41 -08009102 }
Matt Carlson4f125f42009-09-01 12:55:02 +00009103
9104 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
Michael Chanfcfa0a32006-03-20 22:28:41 -08009105}
9106
Michael Chan79381092005-04-21 17:13:59 -07009107static int tg3_test_interrupt(struct tg3 *tp)
9108{
Matt Carlson09943a12009-08-28 14:01:57 +00009109 struct tg3_napi *tnapi = &tp->napi[0];
Michael Chan79381092005-04-21 17:13:59 -07009110 struct net_device *dev = tp->dev;
Michael Chanb16250e2006-09-27 16:10:14 -07009111 int err, i, intr_ok = 0;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009112 u32 val;
Michael Chan79381092005-04-21 17:13:59 -07009113
Michael Chand4bc3922005-05-29 14:59:20 -07009114 if (!netif_running(dev))
9115 return -ENODEV;
9116
Michael Chan79381092005-04-21 17:13:59 -07009117 tg3_disable_ints(tp);
9118
Matt Carlson4f125f42009-09-01 12:55:02 +00009119 free_irq(tnapi->irq_vec, tnapi);
Michael Chan79381092005-04-21 17:13:59 -07009120
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009121 /*
9122 * Turn off MSI one shot mode. Otherwise this test has no
9123 * observable way to know whether the interrupt was delivered.
9124 */
Matt Carlson1407deb2011-04-05 14:22:44 +00009125 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009126 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9127 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9128 tw32(MSGINT_MODE, val);
9129 }
9130
Matt Carlson4f125f42009-09-01 12:55:02 +00009131 err = request_irq(tnapi->irq_vec, tg3_test_isr,
Matt Carlson09943a12009-08-28 14:01:57 +00009132 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
Michael Chan79381092005-04-21 17:13:59 -07009133 if (err)
9134 return err;
9135
Matt Carlson898a56f2009-08-28 14:02:40 +00009136 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
Michael Chan79381092005-04-21 17:13:59 -07009137 tg3_enable_ints(tp);
9138
9139 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +00009140 tnapi->coal_now);
Michael Chan79381092005-04-21 17:13:59 -07009141
9142 for (i = 0; i < 5; i++) {
Michael Chanb16250e2006-09-27 16:10:14 -07009143 u32 int_mbox, misc_host_ctrl;
9144
Matt Carlson898a56f2009-08-28 14:02:40 +00009145 int_mbox = tr32_mailbox(tnapi->int_mbox);
Michael Chanb16250e2006-09-27 16:10:14 -07009146 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9147
9148 if ((int_mbox != 0) ||
9149 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9150 intr_ok = 1;
Michael Chan79381092005-04-21 17:13:59 -07009151 break;
Michael Chanb16250e2006-09-27 16:10:14 -07009152 }
9153
Michael Chan79381092005-04-21 17:13:59 -07009154 msleep(10);
9155 }
9156
9157 tg3_disable_ints(tp);
9158
Matt Carlson4f125f42009-09-01 12:55:02 +00009159 free_irq(tnapi->irq_vec, tnapi);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009160
Matt Carlson4f125f42009-09-01 12:55:02 +00009161 err = tg3_request_irq(tp, 0);
Michael Chan79381092005-04-21 17:13:59 -07009162
9163 if (err)
9164 return err;
9165
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009166 if (intr_ok) {
9167 /* Reenable MSI one shot mode. */
Matt Carlson1407deb2011-04-05 14:22:44 +00009168 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009169 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9170 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9171 tw32(MSGINT_MODE, val);
9172 }
Michael Chan79381092005-04-21 17:13:59 -07009173 return 0;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009174 }
Michael Chan79381092005-04-21 17:13:59 -07009175
9176 return -EIO;
9177}
9178
9179/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9180 * successfully restored
9181 */
9182static int tg3_test_msi(struct tg3 *tp)
9183{
Michael Chan79381092005-04-21 17:13:59 -07009184 int err;
9185 u16 pci_cmd;
9186
9187 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
9188 return 0;
9189
9190 /* Turn off SERR reporting in case MSI terminates with Master
9191 * Abort.
9192 */
9193 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9194 pci_write_config_word(tp->pdev, PCI_COMMAND,
9195 pci_cmd & ~PCI_COMMAND_SERR);
9196
9197 err = tg3_test_interrupt(tp);
9198
9199 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9200
9201 if (!err)
9202 return 0;
9203
9204 /* other failures */
9205 if (err != -EIO)
9206 return err;
9207
9208 /* MSI test failed, go back to INTx mode */
Matt Carlson5129c3a2010-04-05 10:19:23 +00009209 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9210 "to INTx mode. Please report this failure to the PCI "
9211 "maintainer and include system chipset information\n");
Michael Chan79381092005-04-21 17:13:59 -07009212
Matt Carlson4f125f42009-09-01 12:55:02 +00009213 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
Matt Carlson09943a12009-08-28 14:01:57 +00009214
Michael Chan79381092005-04-21 17:13:59 -07009215 pci_disable_msi(tp->pdev);
9216
9217 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
Andre Detschdc8bf1b2010-04-26 07:27:07 +00009218 tp->napi[0].irq_vec = tp->pdev->irq;
Michael Chan79381092005-04-21 17:13:59 -07009219
Matt Carlson4f125f42009-09-01 12:55:02 +00009220 err = tg3_request_irq(tp, 0);
Michael Chan79381092005-04-21 17:13:59 -07009221 if (err)
9222 return err;
9223
9224 /* Need to reset the chip because the MSI cycle may have terminated
9225 * with Master Abort.
9226 */
David S. Millerf47c11e2005-06-24 20:18:35 -07009227 tg3_full_lock(tp, 1);
Michael Chan79381092005-04-21 17:13:59 -07009228
Michael Chan944d9802005-05-29 14:57:48 -07009229 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07009230 err = tg3_init_hw(tp, 1);
Michael Chan79381092005-04-21 17:13:59 -07009231
David S. Millerf47c11e2005-06-24 20:18:35 -07009232 tg3_full_unlock(tp);
Michael Chan79381092005-04-21 17:13:59 -07009233
9234 if (err)
Matt Carlson4f125f42009-09-01 12:55:02 +00009235 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
Michael Chan79381092005-04-21 17:13:59 -07009236
9237 return err;
9238}
9239
Matt Carlson9e9fd122009-01-19 16:57:45 -08009240static int tg3_request_firmware(struct tg3 *tp)
9241{
9242 const __be32 *fw_data;
9243
9244 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
Joe Perches05dbe002010-02-17 19:44:19 +00009245 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9246 tp->fw_needed);
Matt Carlson9e9fd122009-01-19 16:57:45 -08009247 return -ENOENT;
9248 }
9249
9250 fw_data = (void *)tp->fw->data;
9251
9252 /* Firmware blob starts with version numbers, followed by
9253 * start address and _full_ length including BSS sections
9254 * (which must be longer than the actual data, of course
9255 */
9256
9257 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9258 if (tp->fw_len < (tp->fw->size - 12)) {
Joe Perches05dbe002010-02-17 19:44:19 +00009259 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9260 tp->fw_len, tp->fw_needed);
Matt Carlson9e9fd122009-01-19 16:57:45 -08009261 release_firmware(tp->fw);
9262 tp->fw = NULL;
9263 return -EINVAL;
9264 }
9265
9266 /* We no longer need firmware; we have it. */
9267 tp->fw_needed = NULL;
9268 return 0;
9269}
9270
Matt Carlson679563f2009-09-01 12:55:46 +00009271static bool tg3_enable_msix(struct tg3 *tp)
9272{
9273 int i, rc, cpus = num_online_cpus();
9274 struct msix_entry msix_ent[tp->irq_max];
9275
9276 if (cpus == 1)
9277 /* Just fallback to the simpler MSI mode. */
9278 return false;
9279
9280 /*
9281 * We want as many rx rings enabled as there are cpus.
9282 * The first MSIX vector only deals with link interrupts, etc,
9283 * so we add one to the number of vectors we are requesting.
9284 */
9285 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9286
9287 for (i = 0; i < tp->irq_max; i++) {
9288 msix_ent[i].entry = i;
9289 msix_ent[i].vector = 0;
9290 }
9291
9292 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
Matt Carlson2430b032010-06-05 17:24:34 +00009293 if (rc < 0) {
9294 return false;
9295 } else if (rc != 0) {
Matt Carlson679563f2009-09-01 12:55:46 +00009296 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9297 return false;
Joe Perches05dbe002010-02-17 19:44:19 +00009298 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9299 tp->irq_cnt, rc);
Matt Carlson679563f2009-09-01 12:55:46 +00009300 tp->irq_cnt = rc;
9301 }
9302
9303 for (i = 0; i < tp->irq_max; i++)
9304 tp->napi[i].irq_vec = msix_ent[i].vector;
9305
Ben Hutchings2ddaad32010-09-27 22:11:51 -07009306 netif_set_real_num_tx_queues(tp->dev, 1);
9307 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9308 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9309 pci_disable_msix(tp->pdev);
9310 return false;
9311 }
Matt Carlsonb92b9042010-11-24 08:31:51 +00009312
9313 if (tp->irq_cnt > 1) {
Matt Carlson2430b032010-06-05 17:24:34 +00009314 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
Matt Carlsond78b59f2011-04-05 14:22:46 +00009315
9316 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Matt Carlsonb92b9042010-11-24 08:31:51 +00009318 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9319 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9320 }
9321 }
Matt Carlson2430b032010-06-05 17:24:34 +00009322
Matt Carlson679563f2009-09-01 12:55:46 +00009323 return true;
9324}
9325
Matt Carlson07b01732009-08-28 14:01:15 +00009326static void tg3_ints_init(struct tg3 *tp)
9327{
Matt Carlson679563f2009-09-01 12:55:46 +00009328 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9329 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
Matt Carlson07b01732009-08-28 14:01:15 +00009330 /* All MSI supporting chips should support tagged
9331 * status. Assert that this is the case.
9332 */
Matt Carlson5129c3a2010-04-05 10:19:23 +00009333 netdev_warn(tp->dev,
9334 "MSI without TAGGED_STATUS? Not using MSI\n");
Matt Carlson679563f2009-09-01 12:55:46 +00009335 goto defcfg;
Matt Carlson07b01732009-08-28 14:01:15 +00009336 }
Matt Carlson4f125f42009-09-01 12:55:02 +00009337
Matt Carlson679563f2009-09-01 12:55:46 +00009338 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9339 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9340 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9341 pci_enable_msi(tp->pdev) == 0)
9342 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9343
9344 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9345 u32 msi_mode = tr32(MSGINT_MODE);
Matt Carlson0583d522011-01-25 15:58:50 +00009346 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
9347 tp->irq_cnt > 1)
Matt Carlsonbaf8a942009-09-01 13:13:00 +00009348 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
Matt Carlson679563f2009-09-01 12:55:46 +00009349 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9350 }
9351defcfg:
9352 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9353 tp->irq_cnt = 1;
9354 tp->napi[0].irq_vec = tp->pdev->irq;
Ben Hutchings2ddaad32010-09-27 22:11:51 -07009355 netif_set_real_num_tx_queues(tp->dev, 1);
Matt Carlson85407882010-10-06 13:40:58 -07009356 netif_set_real_num_rx_queues(tp->dev, 1);
Matt Carlson679563f2009-09-01 12:55:46 +00009357 }
Matt Carlson07b01732009-08-28 14:01:15 +00009358}
9359
9360static void tg3_ints_fini(struct tg3 *tp)
9361{
Matt Carlson679563f2009-09-01 12:55:46 +00009362 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9363 pci_disable_msix(tp->pdev);
9364 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9365 pci_disable_msi(tp->pdev);
9366 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
Matt Carlson774ee752010-08-02 11:25:56 +00009367 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
Matt Carlson07b01732009-08-28 14:01:15 +00009368}
9369
Linus Torvalds1da177e2005-04-16 15:20:36 -07009370static int tg3_open(struct net_device *dev)
9371{
9372 struct tg3 *tp = netdev_priv(dev);
Matt Carlson4f125f42009-09-01 12:55:02 +00009373 int i, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009374
Matt Carlson9e9fd122009-01-19 16:57:45 -08009375 if (tp->fw_needed) {
9376 err = tg3_request_firmware(tp);
9377 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9378 if (err)
9379 return err;
9380 } else if (err) {
Joe Perches05dbe002010-02-17 19:44:19 +00009381 netdev_warn(tp->dev, "TSO capability disabled\n");
Matt Carlson9e9fd122009-01-19 16:57:45 -08009382 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9383 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
Joe Perches05dbe002010-02-17 19:44:19 +00009384 netdev_notice(tp->dev, "TSO capability restored\n");
Matt Carlson9e9fd122009-01-19 16:57:45 -08009385 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9386 }
9387 }
9388
Michael Chanc49a1562006-12-17 17:07:29 -08009389 netif_carrier_off(tp->dev);
9390
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00009391 err = tg3_power_up(tp);
Matt Carlson2f751b62008-08-04 23:17:34 -07009392 if (err)
Michael Chanbc1c7562006-03-20 17:48:03 -08009393 return err;
Matt Carlson2f751b62008-08-04 23:17:34 -07009394
9395 tg3_full_lock(tp, 0);
Michael Chanbc1c7562006-03-20 17:48:03 -08009396
Linus Torvalds1da177e2005-04-16 15:20:36 -07009397 tg3_disable_ints(tp);
9398 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9399
David S. Millerf47c11e2005-06-24 20:18:35 -07009400 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009401
Matt Carlson679563f2009-09-01 12:55:46 +00009402 /*
9403 * Setup interrupts first so we know how
9404 * many NAPI resources to allocate
9405 */
9406 tg3_ints_init(tp);
9407
Linus Torvalds1da177e2005-04-16 15:20:36 -07009408 /* The placement of this call is tied
9409 * to the setup and use of Host TX descriptors.
9410 */
9411 err = tg3_alloc_consistent(tp);
9412 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +00009413 goto err_out1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009414
Matt Carlson66cfd1b2010-09-30 10:34:30 +00009415 tg3_napi_init(tp);
9416
Matt Carlsonfed97812009-09-01 13:10:19 +00009417 tg3_napi_enable(tp);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07009418
Matt Carlson4f125f42009-09-01 12:55:02 +00009419 for (i = 0; i < tp->irq_cnt; i++) {
9420 struct tg3_napi *tnapi = &tp->napi[i];
9421 err = tg3_request_irq(tp, i);
9422 if (err) {
9423 for (i--; i >= 0; i--)
9424 free_irq(tnapi->irq_vec, tnapi);
9425 break;
9426 }
9427 }
Matt Carlson07b01732009-08-28 14:01:15 +00009428
9429 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +00009430 goto err_out2;
Matt Carlson07b01732009-08-28 14:01:15 +00009431
David S. Millerf47c11e2005-06-24 20:18:35 -07009432 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009433
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07009434 err = tg3_init_hw(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009435 if (err) {
Michael Chan944d9802005-05-29 14:57:48 -07009436 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009437 tg3_free_rings(tp);
9438 } else {
David S. Millerfac9b832005-05-18 22:46:34 -07009439 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9440 tp->timer_offset = HZ;
9441 else
9442 tp->timer_offset = HZ / 10;
9443
9444 BUG_ON(tp->timer_offset > HZ);
9445 tp->timer_counter = tp->timer_multiplier =
9446 (HZ / tp->timer_offset);
9447 tp->asf_counter = tp->asf_multiplier =
Michael Chan28fbef72005-10-26 15:48:35 -07009448 ((HZ / tp->timer_offset) * 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009449
9450 init_timer(&tp->timer);
9451 tp->timer.expires = jiffies + tp->timer_offset;
9452 tp->timer.data = (unsigned long) tp;
9453 tp->timer.function = tg3_timer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009454 }
9455
David S. Millerf47c11e2005-06-24 20:18:35 -07009456 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009457
Matt Carlson07b01732009-08-28 14:01:15 +00009458 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +00009459 goto err_out3;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009460
Michael Chan79381092005-04-21 17:13:59 -07009461 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9462 err = tg3_test_msi(tp);
David S. Millerfac9b832005-05-18 22:46:34 -07009463
Michael Chan79381092005-04-21 17:13:59 -07009464 if (err) {
David S. Millerf47c11e2005-06-24 20:18:35 -07009465 tg3_full_lock(tp, 0);
Michael Chan944d9802005-05-29 14:57:48 -07009466 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chan79381092005-04-21 17:13:59 -07009467 tg3_free_rings(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07009468 tg3_full_unlock(tp);
Michael Chan79381092005-04-21 17:13:59 -07009469
Matt Carlson679563f2009-09-01 12:55:46 +00009470 goto err_out2;
Michael Chan79381092005-04-21 17:13:59 -07009471 }
Michael Chanfcfa0a32006-03-20 22:28:41 -08009472
Matt Carlson1407deb2011-04-05 14:22:44 +00009473 if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
Matt Carlsonc885e822010-08-02 11:25:57 +00009474 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009475 u32 val = tr32(PCIE_TRANSACTION_CFG);
Michael Chanfcfa0a32006-03-20 22:28:41 -08009476
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009477 tw32(PCIE_TRANSACTION_CFG,
9478 val | PCIE_TRANS_CFG_1SHOT_MSI);
Michael Chanfcfa0a32006-03-20 22:28:41 -08009479 }
Michael Chan79381092005-04-21 17:13:59 -07009480 }
9481
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009482 tg3_phy_start(tp);
9483
David S. Millerf47c11e2005-06-24 20:18:35 -07009484 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009485
Michael Chan79381092005-04-21 17:13:59 -07009486 add_timer(&tp->timer);
9487 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009488 tg3_enable_ints(tp);
9489
David S. Millerf47c11e2005-06-24 20:18:35 -07009490 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009491
Matt Carlsonfe5f5782009-09-01 13:09:39 +00009492 netif_tx_start_all_queues(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009493
9494 return 0;
Matt Carlson07b01732009-08-28 14:01:15 +00009495
Matt Carlson679563f2009-09-01 12:55:46 +00009496err_out3:
Matt Carlson4f125f42009-09-01 12:55:02 +00009497 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9498 struct tg3_napi *tnapi = &tp->napi[i];
9499 free_irq(tnapi->irq_vec, tnapi);
9500 }
Matt Carlson07b01732009-08-28 14:01:15 +00009501
Matt Carlson679563f2009-09-01 12:55:46 +00009502err_out2:
Matt Carlsonfed97812009-09-01 13:10:19 +00009503 tg3_napi_disable(tp);
Matt Carlson66cfd1b2010-09-30 10:34:30 +00009504 tg3_napi_fini(tp);
Matt Carlson07b01732009-08-28 14:01:15 +00009505 tg3_free_consistent(tp);
Matt Carlson679563f2009-09-01 12:55:46 +00009506
9507err_out1:
9508 tg3_ints_fini(tp);
Matt Carlson07b01732009-08-28 14:01:15 +00009509 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009510}
9511
Eric Dumazet511d2222010-07-07 20:44:24 +00009512static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9513 struct rtnl_link_stats64 *);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009514static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9515
9516static int tg3_close(struct net_device *dev)
9517{
Matt Carlson4f125f42009-09-01 12:55:02 +00009518 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009519 struct tg3 *tp = netdev_priv(dev);
9520
Matt Carlsonfed97812009-09-01 13:10:19 +00009521 tg3_napi_disable(tp);
Oleg Nesterov28e53bd2007-05-09 02:34:22 -07009522 cancel_work_sync(&tp->reset_task);
Michael Chan7faa0062006-02-02 17:29:28 -08009523
Matt Carlsonfe5f5782009-09-01 13:09:39 +00009524 netif_tx_stop_all_queues(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009525
9526 del_timer_sync(&tp->timer);
9527
Matt Carlson24bb4fb2009-10-05 17:55:29 +00009528 tg3_phy_stop(tp);
9529
David S. Millerf47c11e2005-06-24 20:18:35 -07009530 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009531
9532 tg3_disable_ints(tp);
9533
Michael Chan944d9802005-05-29 14:57:48 -07009534 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009535 tg3_free_rings(tp);
Michael Chan5cf64b8a2007-05-05 12:11:21 -07009536 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009537
David S. Millerf47c11e2005-06-24 20:18:35 -07009538 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009539
Matt Carlson4f125f42009-09-01 12:55:02 +00009540 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9541 struct tg3_napi *tnapi = &tp->napi[i];
9542 free_irq(tnapi->irq_vec, tnapi);
9543 }
Matt Carlson07b01732009-08-28 14:01:15 +00009544
9545 tg3_ints_fini(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009546
Eric Dumazet511d2222010-07-07 20:44:24 +00009547 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9548
Linus Torvalds1da177e2005-04-16 15:20:36 -07009549 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9550 sizeof(tp->estats_prev));
9551
Matt Carlson66cfd1b2010-09-30 10:34:30 +00009552 tg3_napi_fini(tp);
9553
Linus Torvalds1da177e2005-04-16 15:20:36 -07009554 tg3_free_consistent(tp);
9555
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00009556 tg3_power_down(tp);
Michael Chanbc1c7562006-03-20 17:48:03 -08009557
9558 netif_carrier_off(tp->dev);
9559
Linus Torvalds1da177e2005-04-16 15:20:36 -07009560 return 0;
9561}
9562
Eric Dumazet511d2222010-07-07 20:44:24 +00009563static inline u64 get_stat64(tg3_stat64_t *val)
Stefan Buehler816f8b82008-08-15 14:10:54 -07009564{
9565 return ((u64)val->high << 32) | ((u64)val->low);
9566}
9567
Eric Dumazet511d2222010-07-07 20:44:24 +00009568static u64 calc_crc_errors(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009569{
9570 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9571
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009572 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07009573 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009575 u32 val;
9576
David S. Millerf47c11e2005-06-24 20:18:35 -07009577 spin_lock_bh(&tp->lock);
Michael Chan569a5df2007-02-13 12:18:15 -08009578 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9579 tg3_writephy(tp, MII_TG3_TEST1,
9580 val | MII_TG3_TEST1_CRC_EN);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00009581 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009582 } else
9583 val = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07009584 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009585
9586 tp->phy_crc_errors += val;
9587
9588 return tp->phy_crc_errors;
9589 }
9590
9591 return get_stat64(&hw_stats->rx_fcs_errors);
9592}
9593
9594#define ESTAT_ADD(member) \
9595 estats->member = old_estats->member + \
Eric Dumazet511d2222010-07-07 20:44:24 +00009596 get_stat64(&hw_stats->member)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009597
9598static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9599{
9600 struct tg3_ethtool_stats *estats = &tp->estats;
9601 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9602 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9603
9604 if (!hw_stats)
9605 return old_estats;
9606
9607 ESTAT_ADD(rx_octets);
9608 ESTAT_ADD(rx_fragments);
9609 ESTAT_ADD(rx_ucast_packets);
9610 ESTAT_ADD(rx_mcast_packets);
9611 ESTAT_ADD(rx_bcast_packets);
9612 ESTAT_ADD(rx_fcs_errors);
9613 ESTAT_ADD(rx_align_errors);
9614 ESTAT_ADD(rx_xon_pause_rcvd);
9615 ESTAT_ADD(rx_xoff_pause_rcvd);
9616 ESTAT_ADD(rx_mac_ctrl_rcvd);
9617 ESTAT_ADD(rx_xoff_entered);
9618 ESTAT_ADD(rx_frame_too_long_errors);
9619 ESTAT_ADD(rx_jabbers);
9620 ESTAT_ADD(rx_undersize_packets);
9621 ESTAT_ADD(rx_in_length_errors);
9622 ESTAT_ADD(rx_out_length_errors);
9623 ESTAT_ADD(rx_64_or_less_octet_packets);
9624 ESTAT_ADD(rx_65_to_127_octet_packets);
9625 ESTAT_ADD(rx_128_to_255_octet_packets);
9626 ESTAT_ADD(rx_256_to_511_octet_packets);
9627 ESTAT_ADD(rx_512_to_1023_octet_packets);
9628 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9629 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9630 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9631 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9632 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9633
9634 ESTAT_ADD(tx_octets);
9635 ESTAT_ADD(tx_collisions);
9636 ESTAT_ADD(tx_xon_sent);
9637 ESTAT_ADD(tx_xoff_sent);
9638 ESTAT_ADD(tx_flow_control);
9639 ESTAT_ADD(tx_mac_errors);
9640 ESTAT_ADD(tx_single_collisions);
9641 ESTAT_ADD(tx_mult_collisions);
9642 ESTAT_ADD(tx_deferred);
9643 ESTAT_ADD(tx_excessive_collisions);
9644 ESTAT_ADD(tx_late_collisions);
9645 ESTAT_ADD(tx_collide_2times);
9646 ESTAT_ADD(tx_collide_3times);
9647 ESTAT_ADD(tx_collide_4times);
9648 ESTAT_ADD(tx_collide_5times);
9649 ESTAT_ADD(tx_collide_6times);
9650 ESTAT_ADD(tx_collide_7times);
9651 ESTAT_ADD(tx_collide_8times);
9652 ESTAT_ADD(tx_collide_9times);
9653 ESTAT_ADD(tx_collide_10times);
9654 ESTAT_ADD(tx_collide_11times);
9655 ESTAT_ADD(tx_collide_12times);
9656 ESTAT_ADD(tx_collide_13times);
9657 ESTAT_ADD(tx_collide_14times);
9658 ESTAT_ADD(tx_collide_15times);
9659 ESTAT_ADD(tx_ucast_packets);
9660 ESTAT_ADD(tx_mcast_packets);
9661 ESTAT_ADD(tx_bcast_packets);
9662 ESTAT_ADD(tx_carrier_sense_errors);
9663 ESTAT_ADD(tx_discards);
9664 ESTAT_ADD(tx_errors);
9665
9666 ESTAT_ADD(dma_writeq_full);
9667 ESTAT_ADD(dma_write_prioq_full);
9668 ESTAT_ADD(rxbds_empty);
9669 ESTAT_ADD(rx_discards);
9670 ESTAT_ADD(rx_errors);
9671 ESTAT_ADD(rx_threshold_hit);
9672
9673 ESTAT_ADD(dma_readq_full);
9674 ESTAT_ADD(dma_read_prioq_full);
9675 ESTAT_ADD(tx_comp_queue_full);
9676
9677 ESTAT_ADD(ring_set_send_prod_index);
9678 ESTAT_ADD(ring_status_update);
9679 ESTAT_ADD(nic_irqs);
9680 ESTAT_ADD(nic_avoided_irqs);
9681 ESTAT_ADD(nic_tx_threshold_hit);
9682
9683 return estats;
9684}
9685
Eric Dumazet511d2222010-07-07 20:44:24 +00009686static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9687 struct rtnl_link_stats64 *stats)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009688{
9689 struct tg3 *tp = netdev_priv(dev);
Eric Dumazet511d2222010-07-07 20:44:24 +00009690 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009691 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9692
9693 if (!hw_stats)
9694 return old_stats;
9695
9696 stats->rx_packets = old_stats->rx_packets +
9697 get_stat64(&hw_stats->rx_ucast_packets) +
9698 get_stat64(&hw_stats->rx_mcast_packets) +
9699 get_stat64(&hw_stats->rx_bcast_packets);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009700
Linus Torvalds1da177e2005-04-16 15:20:36 -07009701 stats->tx_packets = old_stats->tx_packets +
9702 get_stat64(&hw_stats->tx_ucast_packets) +
9703 get_stat64(&hw_stats->tx_mcast_packets) +
9704 get_stat64(&hw_stats->tx_bcast_packets);
9705
9706 stats->rx_bytes = old_stats->rx_bytes +
9707 get_stat64(&hw_stats->rx_octets);
9708 stats->tx_bytes = old_stats->tx_bytes +
9709 get_stat64(&hw_stats->tx_octets);
9710
9711 stats->rx_errors = old_stats->rx_errors +
John W. Linville4f63b872005-09-12 14:43:18 -07009712 get_stat64(&hw_stats->rx_errors);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009713 stats->tx_errors = old_stats->tx_errors +
9714 get_stat64(&hw_stats->tx_errors) +
9715 get_stat64(&hw_stats->tx_mac_errors) +
9716 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9717 get_stat64(&hw_stats->tx_discards);
9718
9719 stats->multicast = old_stats->multicast +
9720 get_stat64(&hw_stats->rx_mcast_packets);
9721 stats->collisions = old_stats->collisions +
9722 get_stat64(&hw_stats->tx_collisions);
9723
9724 stats->rx_length_errors = old_stats->rx_length_errors +
9725 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9726 get_stat64(&hw_stats->rx_undersize_packets);
9727
9728 stats->rx_over_errors = old_stats->rx_over_errors +
9729 get_stat64(&hw_stats->rxbds_empty);
9730 stats->rx_frame_errors = old_stats->rx_frame_errors +
9731 get_stat64(&hw_stats->rx_align_errors);
9732 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9733 get_stat64(&hw_stats->tx_discards);
9734 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9735 get_stat64(&hw_stats->tx_carrier_sense_errors);
9736
9737 stats->rx_crc_errors = old_stats->rx_crc_errors +
9738 calc_crc_errors(tp);
9739
John W. Linville4f63b872005-09-12 14:43:18 -07009740 stats->rx_missed_errors = old_stats->rx_missed_errors +
9741 get_stat64(&hw_stats->rx_discards);
9742
Eric Dumazetb0057c52010-10-10 19:55:52 +00009743 stats->rx_dropped = tp->rx_dropped;
9744
Linus Torvalds1da177e2005-04-16 15:20:36 -07009745 return stats;
9746}
9747
9748static inline u32 calc_crc(unsigned char *buf, int len)
9749{
9750 u32 reg;
9751 u32 tmp;
9752 int j, k;
9753
9754 reg = 0xffffffff;
9755
9756 for (j = 0; j < len; j++) {
9757 reg ^= buf[j];
9758
9759 for (k = 0; k < 8; k++) {
9760 tmp = reg & 0x01;
9761
9762 reg >>= 1;
9763
Matt Carlson859a588792010-04-05 10:19:28 +00009764 if (tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009765 reg ^= 0xedb88320;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009766 }
9767 }
9768
9769 return ~reg;
9770}
9771
9772static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9773{
9774 /* accept or reject all multicast frames */
9775 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9776 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9777 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9778 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9779}
9780
9781static void __tg3_set_rx_mode(struct net_device *dev)
9782{
9783 struct tg3 *tp = netdev_priv(dev);
9784 u32 rx_mode;
9785
9786 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9787 RX_MODE_KEEP_VLAN_TAG);
9788
Matt Carlsonbf933c82011-01-25 15:58:49 +00009789#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009790 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9791 * flag clear.
9792 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07009793 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9794 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9795#endif
9796
9797 if (dev->flags & IFF_PROMISC) {
9798 /* Promiscuous mode. */
9799 rx_mode |= RX_MODE_PROMISC;
9800 } else if (dev->flags & IFF_ALLMULTI) {
9801 /* Accept all multicast. */
Matt Carlsonde6f31e2010-04-12 06:58:30 +00009802 tg3_set_multi(tp, 1);
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00009803 } else if (netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009804 /* Reject all multicast. */
Matt Carlsonde6f31e2010-04-12 06:58:30 +00009805 tg3_set_multi(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009806 } else {
9807 /* Accept one or more multicast(s). */
Jiri Pirko22bedad32010-04-01 21:22:57 +00009808 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009809 u32 mc_filter[4] = { 0, };
9810 u32 regidx;
9811 u32 bit;
9812 u32 crc;
9813
Jiri Pirko22bedad32010-04-01 21:22:57 +00009814 netdev_for_each_mc_addr(ha, dev) {
9815 crc = calc_crc(ha->addr, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009816 bit = ~crc & 0x7f;
9817 regidx = (bit & 0x60) >> 5;
9818 bit &= 0x1f;
9819 mc_filter[regidx] |= (1 << bit);
9820 }
9821
9822 tw32(MAC_HASH_REG_0, mc_filter[0]);
9823 tw32(MAC_HASH_REG_1, mc_filter[1]);
9824 tw32(MAC_HASH_REG_2, mc_filter[2]);
9825 tw32(MAC_HASH_REG_3, mc_filter[3]);
9826 }
9827
9828 if (rx_mode != tp->rx_mode) {
9829 tp->rx_mode = rx_mode;
9830 tw32_f(MAC_RX_MODE, rx_mode);
9831 udelay(10);
9832 }
9833}
9834
9835static void tg3_set_rx_mode(struct net_device *dev)
9836{
9837 struct tg3 *tp = netdev_priv(dev);
9838
Michael Chane75f7c92006-03-20 21:33:26 -08009839 if (!netif_running(dev))
9840 return;
9841
David S. Millerf47c11e2005-06-24 20:18:35 -07009842 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009843 __tg3_set_rx_mode(dev);
David S. Millerf47c11e2005-06-24 20:18:35 -07009844 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009845}
9846
Linus Torvalds1da177e2005-04-16 15:20:36 -07009847static int tg3_get_regs_len(struct net_device *dev)
9848{
Matt Carlson97bd8e42011-04-13 11:05:04 +00009849 return TG3_REG_BLK_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009850}
9851
9852static void tg3_get_regs(struct net_device *dev,
9853 struct ethtool_regs *regs, void *_p)
9854{
Linus Torvalds1da177e2005-04-16 15:20:36 -07009855 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009856
9857 regs->version = 0;
9858
Matt Carlson97bd8e42011-04-13 11:05:04 +00009859 memset(_p, 0, TG3_REG_BLK_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009860
Matt Carlson80096062010-08-02 11:26:06 +00009861 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -08009862 return;
9863
David S. Millerf47c11e2005-06-24 20:18:35 -07009864 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009865
Matt Carlson97bd8e42011-04-13 11:05:04 +00009866 tg3_dump_legacy_regs(tp, (u32 *)_p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009867
David S. Millerf47c11e2005-06-24 20:18:35 -07009868 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009869}
9870
9871static int tg3_get_eeprom_len(struct net_device *dev)
9872{
9873 struct tg3 *tp = netdev_priv(dev);
9874
9875 return tp->nvram_size;
9876}
9877
Linus Torvalds1da177e2005-04-16 15:20:36 -07009878static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9879{
9880 struct tg3 *tp = netdev_priv(dev);
9881 int ret;
9882 u8 *pd;
Al Virob9fc7dc2007-12-17 22:59:57 -08009883 u32 i, offset, len, b_offset, b_count;
Matt Carlsona9dc5292009-02-25 14:25:30 +00009884 __be32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009885
Matt Carlsondf259d82009-04-20 06:57:14 +00009886 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9887 return -EINVAL;
9888
Matt Carlson80096062010-08-02 11:26:06 +00009889 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -08009890 return -EAGAIN;
9891
Linus Torvalds1da177e2005-04-16 15:20:36 -07009892 offset = eeprom->offset;
9893 len = eeprom->len;
9894 eeprom->len = 0;
9895
9896 eeprom->magic = TG3_EEPROM_MAGIC;
9897
9898 if (offset & 3) {
9899 /* adjustments to start on required 4 byte boundary */
9900 b_offset = offset & 3;
9901 b_count = 4 - b_offset;
9902 if (b_count > len) {
9903 /* i.e. offset=1 len=2 */
9904 b_count = len;
9905 }
Matt Carlsona9dc5292009-02-25 14:25:30 +00009906 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009907 if (ret)
9908 return ret;
Matt Carlsonbe98da62010-07-11 09:31:46 +00009909 memcpy(data, ((char *)&val) + b_offset, b_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009910 len -= b_count;
9911 offset += b_count;
Matt Carlsonc6cdf432010-04-05 10:19:26 +00009912 eeprom->len += b_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009913 }
9914
Lucas De Marchi25985ed2011-03-30 22:57:33 -03009915 /* read bytes up to the last 4 byte boundary */
Linus Torvalds1da177e2005-04-16 15:20:36 -07009916 pd = &data[eeprom->len];
9917 for (i = 0; i < (len - (len & 3)); i += 4) {
Matt Carlsona9dc5292009-02-25 14:25:30 +00009918 ret = tg3_nvram_read_be32(tp, offset + i, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009919 if (ret) {
9920 eeprom->len += i;
9921 return ret;
9922 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009923 memcpy(pd + i, &val, 4);
9924 }
9925 eeprom->len += i;
9926
9927 if (len & 3) {
9928 /* read last bytes not ending on 4 byte boundary */
9929 pd = &data[eeprom->len];
9930 b_count = len & 3;
9931 b_offset = offset + len - b_count;
Matt Carlsona9dc5292009-02-25 14:25:30 +00009932 ret = tg3_nvram_read_be32(tp, b_offset, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009933 if (ret)
9934 return ret;
Al Virob9fc7dc2007-12-17 22:59:57 -08009935 memcpy(pd, &val, b_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009936 eeprom->len += b_count;
9937 }
9938 return 0;
9939}
9940
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009941static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009942
9943static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9944{
9945 struct tg3 *tp = netdev_priv(dev);
9946 int ret;
Al Virob9fc7dc2007-12-17 22:59:57 -08009947 u32 offset, len, b_offset, odd_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009948 u8 *buf;
Matt Carlsona9dc5292009-02-25 14:25:30 +00009949 __be32 start, end;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009950
Matt Carlson80096062010-08-02 11:26:06 +00009951 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -08009952 return -EAGAIN;
9953
Matt Carlsondf259d82009-04-20 06:57:14 +00009954 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9955 eeprom->magic != TG3_EEPROM_MAGIC)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009956 return -EINVAL;
9957
9958 offset = eeprom->offset;
9959 len = eeprom->len;
9960
9961 if ((b_offset = (offset & 3))) {
9962 /* adjustments to start on required 4 byte boundary */
Matt Carlsona9dc5292009-02-25 14:25:30 +00009963 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009964 if (ret)
9965 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009966 len += b_offset;
9967 offset &= ~3;
Michael Chan1c8594b2005-04-21 17:12:46 -07009968 if (len < 4)
9969 len = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009970 }
9971
9972 odd_len = 0;
Michael Chan1c8594b2005-04-21 17:12:46 -07009973 if (len & 3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009974 /* adjustments to end on required 4 byte boundary */
9975 odd_len = 1;
9976 len = (len + 3) & ~3;
Matt Carlsona9dc5292009-02-25 14:25:30 +00009977 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009978 if (ret)
9979 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009980 }
9981
9982 buf = data;
9983 if (b_offset || odd_len) {
9984 buf = kmalloc(len, GFP_KERNEL);
Andy Gospodarekab0049b2007-09-06 20:42:14 +01009985 if (!buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009986 return -ENOMEM;
9987 if (b_offset)
9988 memcpy(buf, &start, 4);
9989 if (odd_len)
9990 memcpy(buf+len-4, &end, 4);
9991 memcpy(buf + b_offset, data, eeprom->len);
9992 }
9993
9994 ret = tg3_nvram_write_block(tp, offset, len, buf);
9995
9996 if (buf != data)
9997 kfree(buf);
9998
9999 return ret;
10000}
10001
10002static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10003{
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010004 struct tg3 *tp = netdev_priv(dev);
10005
10006 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010007 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010008 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010009 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010010 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10011 return phy_ethtool_gset(phydev, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010012 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010013
Linus Torvalds1da177e2005-04-16 15:20:36 -070010014 cmd->supported = (SUPPORTED_Autoneg);
10015
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010016 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010017 cmd->supported |= (SUPPORTED_1000baseT_Half |
10018 SUPPORTED_1000baseT_Full);
10019
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010020 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010021 cmd->supported |= (SUPPORTED_100baseT_Half |
10022 SUPPORTED_100baseT_Full |
10023 SUPPORTED_10baseT_Half |
10024 SUPPORTED_10baseT_Full |
Matt Carlson3bebab52007-11-12 21:22:40 -080010025 SUPPORTED_TP);
Karsten Keilef348142006-05-12 12:49:08 -070010026 cmd->port = PORT_TP;
10027 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010028 cmd->supported |= SUPPORTED_FIBRE;
Karsten Keilef348142006-05-12 12:49:08 -070010029 cmd->port = PORT_FIBRE;
10030 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010031
Linus Torvalds1da177e2005-04-16 15:20:36 -070010032 cmd->advertising = tp->link_config.advertising;
10033 if (netif_running(dev)) {
10034 cmd->speed = tp->link_config.active_speed;
10035 cmd->duplex = tp->link_config.active_duplex;
Matt Carlson64c22182010-10-14 10:37:44 +000010036 } else {
10037 cmd->speed = SPEED_INVALID;
10038 cmd->duplex = DUPLEX_INVALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010039 }
Matt Carlson882e9792009-09-01 13:21:36 +000010040 cmd->phy_address = tp->phy_addr;
Matt Carlson7e5856b2009-02-25 14:23:01 +000010041 cmd->transceiver = XCVR_INTERNAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010042 cmd->autoneg = tp->link_config.autoneg;
10043 cmd->maxtxpkt = 0;
10044 cmd->maxrxpkt = 0;
10045 return 0;
10046}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010047
Linus Torvalds1da177e2005-04-16 15:20:36 -070010048static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10049{
10050 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010051
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010052 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010053 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010054 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010055 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010056 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10057 return phy_ethtool_sset(phydev, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010058 }
10059
Matt Carlson7e5856b2009-02-25 14:23:01 +000010060 if (cmd->autoneg != AUTONEG_ENABLE &&
10061 cmd->autoneg != AUTONEG_DISABLE)
Michael Chan37ff2382005-10-26 15:49:51 -070010062 return -EINVAL;
Matt Carlson7e5856b2009-02-25 14:23:01 +000010063
10064 if (cmd->autoneg == AUTONEG_DISABLE &&
10065 cmd->duplex != DUPLEX_FULL &&
10066 cmd->duplex != DUPLEX_HALF)
Michael Chan37ff2382005-10-26 15:49:51 -070010067 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010068
Matt Carlson7e5856b2009-02-25 14:23:01 +000010069 if (cmd->autoneg == AUTONEG_ENABLE) {
10070 u32 mask = ADVERTISED_Autoneg |
10071 ADVERTISED_Pause |
10072 ADVERTISED_Asym_Pause;
10073
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010074 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Matt Carlson7e5856b2009-02-25 14:23:01 +000010075 mask |= ADVERTISED_1000baseT_Half |
10076 ADVERTISED_1000baseT_Full;
10077
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010078 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlson7e5856b2009-02-25 14:23:01 +000010079 mask |= ADVERTISED_100baseT_Half |
10080 ADVERTISED_100baseT_Full |
10081 ADVERTISED_10baseT_Half |
10082 ADVERTISED_10baseT_Full |
10083 ADVERTISED_TP;
10084 else
10085 mask |= ADVERTISED_FIBRE;
10086
10087 if (cmd->advertising & ~mask)
10088 return -EINVAL;
10089
10090 mask &= (ADVERTISED_1000baseT_Half |
10091 ADVERTISED_1000baseT_Full |
10092 ADVERTISED_100baseT_Half |
10093 ADVERTISED_100baseT_Full |
10094 ADVERTISED_10baseT_Half |
10095 ADVERTISED_10baseT_Full);
10096
10097 cmd->advertising &= mask;
10098 } else {
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010099 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
Matt Carlson7e5856b2009-02-25 14:23:01 +000010100 if (cmd->speed != SPEED_1000)
10101 return -EINVAL;
10102
10103 if (cmd->duplex != DUPLEX_FULL)
10104 return -EINVAL;
10105 } else {
10106 if (cmd->speed != SPEED_100 &&
10107 cmd->speed != SPEED_10)
10108 return -EINVAL;
10109 }
10110 }
10111
David S. Millerf47c11e2005-06-24 20:18:35 -070010112 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010113
10114 tp->link_config.autoneg = cmd->autoneg;
10115 if (cmd->autoneg == AUTONEG_ENABLE) {
Andy Gospodarek405d8e52007-10-08 01:08:47 -070010116 tp->link_config.advertising = (cmd->advertising |
10117 ADVERTISED_Autoneg);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010118 tp->link_config.speed = SPEED_INVALID;
10119 tp->link_config.duplex = DUPLEX_INVALID;
10120 } else {
10121 tp->link_config.advertising = 0;
10122 tp->link_config.speed = cmd->speed;
10123 tp->link_config.duplex = cmd->duplex;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010124 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010125
Michael Chan24fcad62006-12-17 17:06:46 -080010126 tp->link_config.orig_speed = tp->link_config.speed;
10127 tp->link_config.orig_duplex = tp->link_config.duplex;
10128 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10129
Linus Torvalds1da177e2005-04-16 15:20:36 -070010130 if (netif_running(dev))
10131 tg3_setup_phy(tp, 1);
10132
David S. Millerf47c11e2005-06-24 20:18:35 -070010133 tg3_full_unlock(tp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010134
Linus Torvalds1da177e2005-04-16 15:20:36 -070010135 return 0;
10136}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010137
Linus Torvalds1da177e2005-04-16 15:20:36 -070010138static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10139{
10140 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010141
Linus Torvalds1da177e2005-04-16 15:20:36 -070010142 strcpy(info->driver, DRV_MODULE_NAME);
10143 strcpy(info->version, DRV_MODULE_VERSION);
Michael Chanc4e65752006-03-20 22:29:32 -080010144 strcpy(info->fw_version, tp->fw_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010145 strcpy(info->bus_info, pci_name(tp->pdev));
10146}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010147
Linus Torvalds1da177e2005-04-16 15:20:36 -070010148static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10149{
10150 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010151
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070010152 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
10153 device_can_wakeup(&tp->pdev->dev))
Gary Zambranoa85feb82007-05-05 11:52:19 -070010154 wol->supported = WAKE_MAGIC;
10155 else
10156 wol->supported = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010157 wol->wolopts = 0;
Matt Carlson05ac4cb2008-11-03 16:53:46 -080010158 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
10159 device_can_wakeup(&tp->pdev->dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010160 wol->wolopts = WAKE_MAGIC;
10161 memset(&wol->sopass, 0, sizeof(wol->sopass));
10162}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010163
Linus Torvalds1da177e2005-04-16 15:20:36 -070010164static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10165{
10166 struct tg3 *tp = netdev_priv(dev);
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070010167 struct device *dp = &tp->pdev->dev;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010168
Linus Torvalds1da177e2005-04-16 15:20:36 -070010169 if (wol->wolopts & ~WAKE_MAGIC)
10170 return -EINVAL;
10171 if ((wol->wolopts & WAKE_MAGIC) &&
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070010172 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010173 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010174
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000010175 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10176
David S. Millerf47c11e2005-06-24 20:18:35 -070010177 spin_lock_bh(&tp->lock);
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000010178 if (device_may_wakeup(dp))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010179 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000010180 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070010181 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
David S. Millerf47c11e2005-06-24 20:18:35 -070010182 spin_unlock_bh(&tp->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010183
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000010184
Linus Torvalds1da177e2005-04-16 15:20:36 -070010185 return 0;
10186}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010187
Linus Torvalds1da177e2005-04-16 15:20:36 -070010188static u32 tg3_get_msglevel(struct net_device *dev)
10189{
10190 struct tg3 *tp = netdev_priv(dev);
10191 return tp->msg_enable;
10192}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010193
Linus Torvalds1da177e2005-04-16 15:20:36 -070010194static void tg3_set_msglevel(struct net_device *dev, u32 value)
10195{
10196 struct tg3 *tp = netdev_priv(dev);
10197 tp->msg_enable = value;
10198}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010199
Linus Torvalds1da177e2005-04-16 15:20:36 -070010200static int tg3_nway_reset(struct net_device *dev)
10201{
10202 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010203 int r;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010204
Linus Torvalds1da177e2005-04-16 15:20:36 -070010205 if (!netif_running(dev))
10206 return -EAGAIN;
10207
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010208 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Michael Chanc94e3942005-09-27 12:12:42 -070010209 return -EINVAL;
10210
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010211 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010212 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010213 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010214 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010215 } else {
10216 u32 bmcr;
10217
10218 spin_lock_bh(&tp->lock);
10219 r = -EINVAL;
10220 tg3_readphy(tp, MII_BMCR, &bmcr);
10221 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10222 ((bmcr & BMCR_ANENABLE) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010223 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010224 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10225 BMCR_ANENABLE);
10226 r = 0;
10227 }
10228 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010229 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010230
Linus Torvalds1da177e2005-04-16 15:20:36 -070010231 return r;
10232}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010233
Linus Torvalds1da177e2005-04-16 15:20:36 -070010234static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10235{
10236 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010237
Matt Carlson2c49a442010-09-30 10:34:35 +000010238 ering->rx_max_pending = tp->rx_std_ring_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010239 ering->rx_mini_max_pending = 0;
Michael Chan4f81c322006-03-20 21:33:42 -080010240 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
Matt Carlson2c49a442010-09-30 10:34:35 +000010241 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
Michael Chan4f81c322006-03-20 21:33:42 -080010242 else
10243 ering->rx_jumbo_max_pending = 0;
10244
10245 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010246
10247 ering->rx_pending = tp->rx_pending;
10248 ering->rx_mini_pending = 0;
Michael Chan4f81c322006-03-20 21:33:42 -080010249 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10250 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10251 else
10252 ering->rx_jumbo_pending = 0;
10253
Matt Carlsonf3f3f272009-08-28 14:03:21 +000010254 ering->tx_pending = tp->napi[0].tx_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010255}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010256
Linus Torvalds1da177e2005-04-16 15:20:36 -070010257static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10258{
10259 struct tg3 *tp = netdev_priv(dev);
Matt Carlson646c9ed2009-09-01 12:58:41 +000010260 int i, irq_sync = 0, err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010261
Matt Carlson2c49a442010-09-30 10:34:35 +000010262 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10263 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
Michael Chanbc3a9252006-10-18 20:55:18 -070010264 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10265 (ering->tx_pending <= MAX_SKB_FRAGS) ||
Michael Chan7f62ad52007-02-20 23:25:40 -080010266 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
Michael Chanbc3a9252006-10-18 20:55:18 -070010267 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010268 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010269
Michael Chanbbe832c2005-06-24 20:20:04 -070010270 if (netif_running(dev)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010271 tg3_phy_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010272 tg3_netif_stop(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070010273 irq_sync = 1;
10274 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070010275
Michael Chanbbe832c2005-06-24 20:20:04 -070010276 tg3_full_lock(tp, irq_sync);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010277
Linus Torvalds1da177e2005-04-16 15:20:36 -070010278 tp->rx_pending = ering->rx_pending;
10279
10280 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10281 tp->rx_pending > 63)
10282 tp->rx_pending = 63;
10283 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
Matt Carlson646c9ed2009-09-01 12:58:41 +000010284
Matt Carlson6fd45cb2010-09-15 08:59:57 +000010285 for (i = 0; i < tp->irq_max; i++)
Matt Carlson646c9ed2009-09-01 12:58:41 +000010286 tp->napi[i].tx_pending = ering->tx_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010287
10288 if (netif_running(dev)) {
Michael Chan944d9802005-05-29 14:57:48 -070010289 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chanb9ec6c12006-07-25 16:37:27 -070010290 err = tg3_restart_hw(tp, 1);
10291 if (!err)
10292 tg3_netif_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010293 }
10294
David S. Millerf47c11e2005-06-24 20:18:35 -070010295 tg3_full_unlock(tp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010296
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010297 if (irq_sync && !err)
10298 tg3_phy_start(tp);
10299
Michael Chanb9ec6c12006-07-25 16:37:27 -070010300 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010301}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010302
Linus Torvalds1da177e2005-04-16 15:20:36 -070010303static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10304{
10305 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010306
Linus Torvalds1da177e2005-04-16 15:20:36 -070010307 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
Matt Carlson8d018622007-12-20 20:05:44 -080010308
Steve Glendinninge18ce342008-12-16 02:00:00 -080010309 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
Matt Carlson8d018622007-12-20 20:05:44 -080010310 epause->rx_pause = 1;
10311 else
10312 epause->rx_pause = 0;
10313
Steve Glendinninge18ce342008-12-16 02:00:00 -080010314 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
Matt Carlson8d018622007-12-20 20:05:44 -080010315 epause->tx_pause = 1;
10316 else
10317 epause->tx_pause = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010318}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010319
Linus Torvalds1da177e2005-04-16 15:20:36 -070010320static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10321{
10322 struct tg3 *tp = netdev_priv(dev);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010323 int err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010324
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010325 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson27121682010-02-17 15:16:57 +000010326 u32 newadv;
10327 struct phy_device *phydev;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010328
Matt Carlson27121682010-02-17 15:16:57 +000010329 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010330
Matt Carlson27121682010-02-17 15:16:57 +000010331 if (!(phydev->supported & SUPPORTED_Pause) ||
10332 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
Nicolas Kaiser2259dca2010-10-07 23:29:27 +000010333 (epause->rx_pause != epause->tx_pause)))
Matt Carlson27121682010-02-17 15:16:57 +000010334 return -EINVAL;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010335
Matt Carlson27121682010-02-17 15:16:57 +000010336 tp->link_config.flowctrl = 0;
10337 if (epause->rx_pause) {
10338 tp->link_config.flowctrl |= FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010339
Matt Carlson27121682010-02-17 15:16:57 +000010340 if (epause->tx_pause) {
Steve Glendinninge18ce342008-12-16 02:00:00 -080010341 tp->link_config.flowctrl |= FLOW_CTRL_TX;
Matt Carlson27121682010-02-17 15:16:57 +000010342 newadv = ADVERTISED_Pause;
10343 } else
10344 newadv = ADVERTISED_Pause |
10345 ADVERTISED_Asym_Pause;
10346 } else if (epause->tx_pause) {
10347 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10348 newadv = ADVERTISED_Asym_Pause;
10349 } else
10350 newadv = 0;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010351
Matt Carlson27121682010-02-17 15:16:57 +000010352 if (epause->autoneg)
10353 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10354 else
10355 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10356
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010357 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson27121682010-02-17 15:16:57 +000010358 u32 oldadv = phydev->advertising &
10359 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10360 if (oldadv != newadv) {
10361 phydev->advertising &=
10362 ~(ADVERTISED_Pause |
10363 ADVERTISED_Asym_Pause);
10364 phydev->advertising |= newadv;
10365 if (phydev->autoneg) {
10366 /*
10367 * Always renegotiate the link to
10368 * inform our link partner of our
10369 * flow control settings, even if the
10370 * flow control is forced. Let
10371 * tg3_adjust_link() do the final
10372 * flow control setup.
10373 */
10374 return phy_start_aneg(phydev);
10375 }
10376 }
10377
10378 if (!epause->autoneg)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010379 tg3_setup_flow_control(tp, 0, 0);
Matt Carlson27121682010-02-17 15:16:57 +000010380 } else {
10381 tp->link_config.orig_advertising &=
10382 ~(ADVERTISED_Pause |
10383 ADVERTISED_Asym_Pause);
10384 tp->link_config.orig_advertising |= newadv;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010385 }
10386 } else {
10387 int irq_sync = 0;
10388
10389 if (netif_running(dev)) {
10390 tg3_netif_stop(tp);
10391 irq_sync = 1;
10392 }
10393
10394 tg3_full_lock(tp, irq_sync);
10395
10396 if (epause->autoneg)
10397 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10398 else
10399 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10400 if (epause->rx_pause)
Steve Glendinninge18ce342008-12-16 02:00:00 -080010401 tp->link_config.flowctrl |= FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010402 else
Steve Glendinninge18ce342008-12-16 02:00:00 -080010403 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010404 if (epause->tx_pause)
Steve Glendinninge18ce342008-12-16 02:00:00 -080010405 tp->link_config.flowctrl |= FLOW_CTRL_TX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010406 else
Steve Glendinninge18ce342008-12-16 02:00:00 -080010407 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010408
10409 if (netif_running(dev)) {
10410 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10411 err = tg3_restart_hw(tp, 1);
10412 if (!err)
10413 tg3_netif_start(tp);
10414 }
10415
10416 tg3_full_unlock(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070010417 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070010418
Michael Chanb9ec6c12006-07-25 16:37:27 -070010419 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010420}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010421
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010422static int tg3_get_sset_count(struct net_device *dev, int sset)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010423{
Jeff Garzikb9f2c042007-10-03 18:07:32 -070010424 switch (sset) {
10425 case ETH_SS_TEST:
10426 return TG3_NUM_TEST;
10427 case ETH_SS_STATS:
10428 return TG3_NUM_STATS;
10429 default:
10430 return -EOPNOTSUPP;
10431 }
Michael Chan4cafd3f2005-05-29 14:56:34 -070010432}
10433
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010434static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010435{
10436 switch (stringset) {
10437 case ETH_SS_STATS:
10438 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10439 break;
Michael Chan4cafd3f2005-05-29 14:56:34 -070010440 case ETH_SS_TEST:
10441 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10442 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010443 default:
10444 WARN_ON(1); /* we need a WARN() */
10445 break;
10446 }
10447}
10448
stephen hemminger81b87092011-04-04 08:43:50 +000010449static int tg3_set_phys_id(struct net_device *dev,
10450 enum ethtool_phys_id_state state)
Michael Chan4009a932005-09-05 17:52:54 -070010451{
10452 struct tg3 *tp = netdev_priv(dev);
Michael Chan4009a932005-09-05 17:52:54 -070010453
10454 if (!netif_running(tp->dev))
10455 return -EAGAIN;
10456
stephen hemminger81b87092011-04-04 08:43:50 +000010457 switch (state) {
10458 case ETHTOOL_ID_ACTIVE:
Allan, Bruce Wfce55922011-04-13 13:09:10 +000010459 return 1; /* cycle on/off once per second */
Michael Chan4009a932005-09-05 17:52:54 -070010460
stephen hemminger81b87092011-04-04 08:43:50 +000010461 case ETHTOOL_ID_ON:
10462 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10463 LED_CTRL_1000MBPS_ON |
10464 LED_CTRL_100MBPS_ON |
10465 LED_CTRL_10MBPS_ON |
10466 LED_CTRL_TRAFFIC_OVERRIDE |
10467 LED_CTRL_TRAFFIC_BLINK |
10468 LED_CTRL_TRAFFIC_LED);
10469 break;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010470
stephen hemminger81b87092011-04-04 08:43:50 +000010471 case ETHTOOL_ID_OFF:
10472 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10473 LED_CTRL_TRAFFIC_OVERRIDE);
10474 break;
Michael Chan4009a932005-09-05 17:52:54 -070010475
stephen hemminger81b87092011-04-04 08:43:50 +000010476 case ETHTOOL_ID_INACTIVE:
10477 tw32(MAC_LED_CTRL, tp->led_ctrl);
10478 break;
Michael Chan4009a932005-09-05 17:52:54 -070010479 }
stephen hemminger81b87092011-04-04 08:43:50 +000010480
Michael Chan4009a932005-09-05 17:52:54 -070010481 return 0;
10482}
10483
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010484static void tg3_get_ethtool_stats(struct net_device *dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -070010485 struct ethtool_stats *estats, u64 *tmp_stats)
10486{
10487 struct tg3 *tp = netdev_priv(dev);
10488 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10489}
10490
Matt Carlsonc3e94502011-04-13 11:05:08 +000010491static __be32 * tg3_vpd_readblock(struct tg3 *tp)
10492{
10493 int i;
10494 __be32 *buf;
10495 u32 offset = 0, len = 0;
10496 u32 magic, val;
10497
10498 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10499 tg3_nvram_read(tp, 0, &magic))
10500 return NULL;
10501
10502 if (magic == TG3_EEPROM_MAGIC) {
10503 for (offset = TG3_NVM_DIR_START;
10504 offset < TG3_NVM_DIR_END;
10505 offset += TG3_NVM_DIRENT_SIZE) {
10506 if (tg3_nvram_read(tp, offset, &val))
10507 return NULL;
10508
10509 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10510 TG3_NVM_DIRTYPE_EXTVPD)
10511 break;
10512 }
10513
10514 if (offset != TG3_NVM_DIR_END) {
10515 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10516 if (tg3_nvram_read(tp, offset + 4, &offset))
10517 return NULL;
10518
10519 offset = tg3_nvram_logical_addr(tp, offset);
10520 }
10521 }
10522
10523 if (!offset || !len) {
10524 offset = TG3_NVM_VPD_OFF;
10525 len = TG3_NVM_VPD_LEN;
10526 }
10527
10528 buf = kmalloc(len, GFP_KERNEL);
10529 if (buf == NULL)
10530 return NULL;
10531
10532 if (magic == TG3_EEPROM_MAGIC) {
10533 for (i = 0; i < len; i += 4) {
10534 /* The data is in little-endian format in NVRAM.
10535 * Use the big-endian read routines to preserve
10536 * the byte order as it exists in NVRAM.
10537 */
10538 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10539 goto error;
10540 }
10541 } else {
10542 u8 *ptr;
10543 ssize_t cnt;
10544 unsigned int pos = 0;
10545
10546 ptr = (u8 *)&buf[0];
10547 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10548 cnt = pci_read_vpd(tp->pdev, pos,
10549 len - pos, ptr);
10550 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10551 cnt = 0;
10552 else if (cnt < 0)
10553 goto error;
10554 }
10555 if (pos != len)
10556 goto error;
10557 }
10558
10559 return buf;
10560
10561error:
10562 kfree(buf);
10563 return NULL;
10564}
10565
Michael Chan566f86a2005-05-29 14:56:58 -070010566#define NVRAM_TEST_SIZE 0x100
Matt Carlsona5767de2007-11-12 21:10:58 -080010567#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10568#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10569#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
Michael Chanb16250e2006-09-27 16:10:14 -070010570#define NVRAM_SELFBOOT_HW_SIZE 0x20
10571#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
Michael Chan566f86a2005-05-29 14:56:58 -070010572
10573static int tg3_test_nvram(struct tg3 *tp)
10574{
Al Virob9fc7dc2007-12-17 22:59:57 -080010575 u32 csum, magic;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010576 __be32 *buf;
Andy Gospodarekab0049b2007-09-06 20:42:14 +010010577 int i, j, k, err = 0, size;
Michael Chan566f86a2005-05-29 14:56:58 -070010578
Matt Carlsondf259d82009-04-20 06:57:14 +000010579 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10580 return 0;
10581
Matt Carlsone4f34112009-02-25 14:25:00 +000010582 if (tg3_nvram_read(tp, 0, &magic) != 0)
Michael Chan1b277772006-03-20 22:27:48 -080010583 return -EIO;
10584
Michael Chan1b277772006-03-20 22:27:48 -080010585 if (magic == TG3_EEPROM_MAGIC)
10586 size = NVRAM_TEST_SIZE;
Michael Chanb16250e2006-09-27 16:10:14 -070010587 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
Matt Carlsona5767de2007-11-12 21:10:58 -080010588 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10589 TG3_EEPROM_SB_FORMAT_1) {
10590 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10591 case TG3_EEPROM_SB_REVISION_0:
10592 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10593 break;
10594 case TG3_EEPROM_SB_REVISION_2:
10595 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10596 break;
10597 case TG3_EEPROM_SB_REVISION_3:
10598 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10599 break;
10600 default:
10601 return 0;
10602 }
10603 } else
Michael Chan1b277772006-03-20 22:27:48 -080010604 return 0;
Michael Chanb16250e2006-09-27 16:10:14 -070010605 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10606 size = NVRAM_SELFBOOT_HW_SIZE;
10607 else
Michael Chan1b277772006-03-20 22:27:48 -080010608 return -EIO;
10609
10610 buf = kmalloc(size, GFP_KERNEL);
Michael Chan566f86a2005-05-29 14:56:58 -070010611 if (buf == NULL)
10612 return -ENOMEM;
10613
Michael Chan1b277772006-03-20 22:27:48 -080010614 err = -EIO;
10615 for (i = 0, j = 0; i < size; i += 4, j++) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000010616 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10617 if (err)
Michael Chan566f86a2005-05-29 14:56:58 -070010618 break;
Michael Chan566f86a2005-05-29 14:56:58 -070010619 }
Michael Chan1b277772006-03-20 22:27:48 -080010620 if (i < size)
Michael Chan566f86a2005-05-29 14:56:58 -070010621 goto out;
10622
Michael Chan1b277772006-03-20 22:27:48 -080010623 /* Selfboot format */
Matt Carlsona9dc5292009-02-25 14:25:30 +000010624 magic = be32_to_cpu(buf[0]);
Al Virob9fc7dc2007-12-17 22:59:57 -080010625 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
Michael Chanb16250e2006-09-27 16:10:14 -070010626 TG3_EEPROM_MAGIC_FW) {
Michael Chan1b277772006-03-20 22:27:48 -080010627 u8 *buf8 = (u8 *) buf, csum8 = 0;
10628
Al Virob9fc7dc2007-12-17 22:59:57 -080010629 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
Matt Carlsona5767de2007-11-12 21:10:58 -080010630 TG3_EEPROM_SB_REVISION_2) {
10631 /* For rev 2, the csum doesn't include the MBA. */
10632 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10633 csum8 += buf8[i];
10634 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10635 csum8 += buf8[i];
10636 } else {
10637 for (i = 0; i < size; i++)
10638 csum8 += buf8[i];
10639 }
Michael Chan1b277772006-03-20 22:27:48 -080010640
Adrian Bunkad96b482006-04-05 22:21:04 -070010641 if (csum8 == 0) {
10642 err = 0;
10643 goto out;
10644 }
10645
10646 err = -EIO;
10647 goto out;
Michael Chan1b277772006-03-20 22:27:48 -080010648 }
Michael Chan566f86a2005-05-29 14:56:58 -070010649
Al Virob9fc7dc2007-12-17 22:59:57 -080010650 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
Michael Chanb16250e2006-09-27 16:10:14 -070010651 TG3_EEPROM_MAGIC_HW) {
10652 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
Matt Carlsona9dc5292009-02-25 14:25:30 +000010653 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
Michael Chanb16250e2006-09-27 16:10:14 -070010654 u8 *buf8 = (u8 *) buf;
Michael Chanb16250e2006-09-27 16:10:14 -070010655
10656 /* Separate the parity bits and the data bytes. */
10657 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10658 if ((i == 0) || (i == 8)) {
10659 int l;
10660 u8 msk;
10661
10662 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10663 parity[k++] = buf8[i] & msk;
10664 i++;
Matt Carlson859a588792010-04-05 10:19:28 +000010665 } else if (i == 16) {
Michael Chanb16250e2006-09-27 16:10:14 -070010666 int l;
10667 u8 msk;
10668
10669 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10670 parity[k++] = buf8[i] & msk;
10671 i++;
10672
10673 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10674 parity[k++] = buf8[i] & msk;
10675 i++;
10676 }
10677 data[j++] = buf8[i];
10678 }
10679
10680 err = -EIO;
10681 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10682 u8 hw8 = hweight8(data[i]);
10683
10684 if ((hw8 & 0x1) && parity[i])
10685 goto out;
10686 else if (!(hw8 & 0x1) && !parity[i])
10687 goto out;
10688 }
10689 err = 0;
10690 goto out;
10691 }
10692
Matt Carlson01c3a392011-03-09 16:58:20 +000010693 err = -EIO;
10694
Michael Chan566f86a2005-05-29 14:56:58 -070010695 /* Bootstrap checksum at offset 0x10 */
10696 csum = calc_crc((unsigned char *) buf, 0x10);
Matt Carlson01c3a392011-03-09 16:58:20 +000010697 if (csum != le32_to_cpu(buf[0x10/4]))
Michael Chan566f86a2005-05-29 14:56:58 -070010698 goto out;
10699
10700 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10701 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
Matt Carlson01c3a392011-03-09 16:58:20 +000010702 if (csum != le32_to_cpu(buf[0xfc/4]))
Matt Carlsona9dc5292009-02-25 14:25:30 +000010703 goto out;
Michael Chan566f86a2005-05-29 14:56:58 -070010704
Matt Carlsonc3e94502011-04-13 11:05:08 +000010705 kfree(buf);
10706
10707 buf = tg3_vpd_readblock(tp);
10708 if (!buf)
10709 return -ENOMEM;
Matt Carlsond4894f32011-03-09 16:58:21 +000010710
10711 i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10712 PCI_VPD_LRDT_RO_DATA);
10713 if (i > 0) {
10714 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10715 if (j < 0)
10716 goto out;
10717
10718 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10719 goto out;
10720
10721 i += PCI_VPD_LRDT_TAG_SIZE;
10722 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10723 PCI_VPD_RO_KEYWORD_CHKSUM);
10724 if (j > 0) {
10725 u8 csum8 = 0;
10726
10727 j += PCI_VPD_INFO_FLD_HDR_SIZE;
10728
10729 for (i = 0; i <= j; i++)
10730 csum8 += ((u8 *)buf)[i];
10731
10732 if (csum8)
10733 goto out;
10734 }
10735 }
10736
Michael Chan566f86a2005-05-29 14:56:58 -070010737 err = 0;
10738
10739out:
10740 kfree(buf);
10741 return err;
10742}
10743
Michael Chanca430072005-05-29 14:57:23 -070010744#define TG3_SERDES_TIMEOUT_SEC 2
10745#define TG3_COPPER_TIMEOUT_SEC 6
10746
10747static int tg3_test_link(struct tg3 *tp)
10748{
10749 int i, max;
10750
10751 if (!netif_running(tp->dev))
10752 return -ENODEV;
10753
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010754 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Michael Chanca430072005-05-29 14:57:23 -070010755 max = TG3_SERDES_TIMEOUT_SEC;
10756 else
10757 max = TG3_COPPER_TIMEOUT_SEC;
10758
10759 for (i = 0; i < max; i++) {
10760 if (netif_carrier_ok(tp->dev))
10761 return 0;
10762
10763 if (msleep_interruptible(1000))
10764 break;
10765 }
10766
10767 return -EIO;
10768}
10769
Michael Chana71116d2005-05-29 14:58:11 -070010770/* Only test the commonly used registers */
David S. Miller30ca3e32006-03-20 23:02:36 -080010771static int tg3_test_registers(struct tg3 *tp)
Michael Chana71116d2005-05-29 14:58:11 -070010772{
Michael Chanb16250e2006-09-27 16:10:14 -070010773 int i, is_5705, is_5750;
Michael Chana71116d2005-05-29 14:58:11 -070010774 u32 offset, read_mask, write_mask, val, save_val, read_val;
10775 static struct {
10776 u16 offset;
10777 u16 flags;
10778#define TG3_FL_5705 0x1
10779#define TG3_FL_NOT_5705 0x2
10780#define TG3_FL_NOT_5788 0x4
Michael Chanb16250e2006-09-27 16:10:14 -070010781#define TG3_FL_NOT_5750 0x8
Michael Chana71116d2005-05-29 14:58:11 -070010782 u32 read_mask;
10783 u32 write_mask;
10784 } reg_tbl[] = {
10785 /* MAC Control Registers */
10786 { MAC_MODE, TG3_FL_NOT_5705,
10787 0x00000000, 0x00ef6f8c },
10788 { MAC_MODE, TG3_FL_5705,
10789 0x00000000, 0x01ef6b8c },
10790 { MAC_STATUS, TG3_FL_NOT_5705,
10791 0x03800107, 0x00000000 },
10792 { MAC_STATUS, TG3_FL_5705,
10793 0x03800100, 0x00000000 },
10794 { MAC_ADDR_0_HIGH, 0x0000,
10795 0x00000000, 0x0000ffff },
10796 { MAC_ADDR_0_LOW, 0x0000,
Matt Carlsonc6cdf432010-04-05 10:19:26 +000010797 0x00000000, 0xffffffff },
Michael Chana71116d2005-05-29 14:58:11 -070010798 { MAC_RX_MTU_SIZE, 0x0000,
10799 0x00000000, 0x0000ffff },
10800 { MAC_TX_MODE, 0x0000,
10801 0x00000000, 0x00000070 },
10802 { MAC_TX_LENGTHS, 0x0000,
10803 0x00000000, 0x00003fff },
10804 { MAC_RX_MODE, TG3_FL_NOT_5705,
10805 0x00000000, 0x000007fc },
10806 { MAC_RX_MODE, TG3_FL_5705,
10807 0x00000000, 0x000007dc },
10808 { MAC_HASH_REG_0, 0x0000,
10809 0x00000000, 0xffffffff },
10810 { MAC_HASH_REG_1, 0x0000,
10811 0x00000000, 0xffffffff },
10812 { MAC_HASH_REG_2, 0x0000,
10813 0x00000000, 0xffffffff },
10814 { MAC_HASH_REG_3, 0x0000,
10815 0x00000000, 0xffffffff },
10816
10817 /* Receive Data and Receive BD Initiator Control Registers. */
10818 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10819 0x00000000, 0xffffffff },
10820 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10821 0x00000000, 0xffffffff },
10822 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10823 0x00000000, 0x00000003 },
10824 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10825 0x00000000, 0xffffffff },
10826 { RCVDBDI_STD_BD+0, 0x0000,
10827 0x00000000, 0xffffffff },
10828 { RCVDBDI_STD_BD+4, 0x0000,
10829 0x00000000, 0xffffffff },
10830 { RCVDBDI_STD_BD+8, 0x0000,
10831 0x00000000, 0xffff0002 },
10832 { RCVDBDI_STD_BD+0xc, 0x0000,
10833 0x00000000, 0xffffffff },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010834
Michael Chana71116d2005-05-29 14:58:11 -070010835 /* Receive BD Initiator Control Registers. */
10836 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10837 0x00000000, 0xffffffff },
10838 { RCVBDI_STD_THRESH, TG3_FL_5705,
10839 0x00000000, 0x000003ff },
10840 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10841 0x00000000, 0xffffffff },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010842
Michael Chana71116d2005-05-29 14:58:11 -070010843 /* Host Coalescing Control Registers. */
10844 { HOSTCC_MODE, TG3_FL_NOT_5705,
10845 0x00000000, 0x00000004 },
10846 { HOSTCC_MODE, TG3_FL_5705,
10847 0x00000000, 0x000000f6 },
10848 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10849 0x00000000, 0xffffffff },
10850 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10851 0x00000000, 0x000003ff },
10852 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10853 0x00000000, 0xffffffff },
10854 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10855 0x00000000, 0x000003ff },
10856 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10857 0x00000000, 0xffffffff },
10858 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10859 0x00000000, 0x000000ff },
10860 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10861 0x00000000, 0xffffffff },
10862 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10863 0x00000000, 0x000000ff },
10864 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10865 0x00000000, 0xffffffff },
10866 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10867 0x00000000, 0xffffffff },
10868 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10869 0x00000000, 0xffffffff },
10870 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10871 0x00000000, 0x000000ff },
10872 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10873 0x00000000, 0xffffffff },
10874 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10875 0x00000000, 0x000000ff },
10876 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10877 0x00000000, 0xffffffff },
10878 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10879 0x00000000, 0xffffffff },
10880 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10881 0x00000000, 0xffffffff },
10882 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10883 0x00000000, 0xffffffff },
10884 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10885 0x00000000, 0xffffffff },
10886 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10887 0xffffffff, 0x00000000 },
10888 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10889 0xffffffff, 0x00000000 },
10890
10891 /* Buffer Manager Control Registers. */
Michael Chanb16250e2006-09-27 16:10:14 -070010892 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
Michael Chana71116d2005-05-29 14:58:11 -070010893 0x00000000, 0x007fff80 },
Michael Chanb16250e2006-09-27 16:10:14 -070010894 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
Michael Chana71116d2005-05-29 14:58:11 -070010895 0x00000000, 0x007fffff },
10896 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10897 0x00000000, 0x0000003f },
10898 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10899 0x00000000, 0x000001ff },
10900 { BUFMGR_MB_HIGH_WATER, 0x0000,
10901 0x00000000, 0x000001ff },
10902 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10903 0xffffffff, 0x00000000 },
10904 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10905 0xffffffff, 0x00000000 },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010906
Michael Chana71116d2005-05-29 14:58:11 -070010907 /* Mailbox Registers */
10908 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10909 0x00000000, 0x000001ff },
10910 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10911 0x00000000, 0x000001ff },
10912 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10913 0x00000000, 0x000007ff },
10914 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10915 0x00000000, 0x000001ff },
10916
10917 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10918 };
10919
Michael Chanb16250e2006-09-27 16:10:14 -070010920 is_5705 = is_5750 = 0;
10921 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
Michael Chana71116d2005-05-29 14:58:11 -070010922 is_5705 = 1;
Michael Chanb16250e2006-09-27 16:10:14 -070010923 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10924 is_5750 = 1;
10925 }
Michael Chana71116d2005-05-29 14:58:11 -070010926
10927 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10928 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10929 continue;
10930
10931 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10932 continue;
10933
10934 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10935 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10936 continue;
10937
Michael Chanb16250e2006-09-27 16:10:14 -070010938 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10939 continue;
10940
Michael Chana71116d2005-05-29 14:58:11 -070010941 offset = (u32) reg_tbl[i].offset;
10942 read_mask = reg_tbl[i].read_mask;
10943 write_mask = reg_tbl[i].write_mask;
10944
10945 /* Save the original register content */
10946 save_val = tr32(offset);
10947
10948 /* Determine the read-only value. */
10949 read_val = save_val & read_mask;
10950
10951 /* Write zero to the register, then make sure the read-only bits
10952 * are not changed and the read/write bits are all zeros.
10953 */
10954 tw32(offset, 0);
10955
10956 val = tr32(offset);
10957
10958 /* Test the read-only and read/write bits. */
10959 if (((val & read_mask) != read_val) || (val & write_mask))
10960 goto out;
10961
10962 /* Write ones to all the bits defined by RdMask and WrMask, then
10963 * make sure the read-only bits are not changed and the
10964 * read/write bits are all ones.
10965 */
10966 tw32(offset, read_mask | write_mask);
10967
10968 val = tr32(offset);
10969
10970 /* Test the read-only bits. */
10971 if ((val & read_mask) != read_val)
10972 goto out;
10973
10974 /* Test the read/write bits. */
10975 if ((val & write_mask) != write_mask)
10976 goto out;
10977
10978 tw32(offset, save_val);
10979 }
10980
10981 return 0;
10982
10983out:
Michael Chan9f88f292006-12-07 00:22:54 -080010984 if (netif_msg_hw(tp))
Matt Carlson2445e462010-04-05 10:19:21 +000010985 netdev_err(tp->dev,
10986 "Register test failed at offset %x\n", offset);
Michael Chana71116d2005-05-29 14:58:11 -070010987 tw32(offset, save_val);
10988 return -EIO;
10989}
10990
Michael Chan7942e1d2005-05-29 14:58:36 -070010991static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10992{
Arjan van de Venf71e1302006-03-03 21:33:57 -050010993 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
Michael Chan7942e1d2005-05-29 14:58:36 -070010994 int i;
10995 u32 j;
10996
Alejandro Martinez Ruize9edda62007-10-15 03:37:43 +020010997 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
Michael Chan7942e1d2005-05-29 14:58:36 -070010998 for (j = 0; j < len; j += 4) {
10999 u32 val;
11000
11001 tg3_write_mem(tp, offset + j, test_pattern[i]);
11002 tg3_read_mem(tp, offset + j, &val);
11003 if (val != test_pattern[i])
11004 return -EIO;
11005 }
11006 }
11007 return 0;
11008}
11009
11010static int tg3_test_memory(struct tg3 *tp)
11011{
11012 static struct mem_entry {
11013 u32 offset;
11014 u32 len;
11015 } mem_tbl_570x[] = {
Michael Chan38690192005-12-19 16:27:28 -080011016 { 0x00000000, 0x00b50},
Michael Chan7942e1d2005-05-29 14:58:36 -070011017 { 0x00002000, 0x1c000},
11018 { 0xffffffff, 0x00000}
11019 }, mem_tbl_5705[] = {
11020 { 0x00000100, 0x0000c},
11021 { 0x00000200, 0x00008},
Michael Chan7942e1d2005-05-29 14:58:36 -070011022 { 0x00004000, 0x00800},
11023 { 0x00006000, 0x01000},
11024 { 0x00008000, 0x02000},
11025 { 0x00010000, 0x0e000},
11026 { 0xffffffff, 0x00000}
Michael Chan79f4d132006-03-20 22:28:57 -080011027 }, mem_tbl_5755[] = {
11028 { 0x00000200, 0x00008},
11029 { 0x00004000, 0x00800},
11030 { 0x00006000, 0x00800},
11031 { 0x00008000, 0x02000},
11032 { 0x00010000, 0x0c000},
11033 { 0xffffffff, 0x00000}
Michael Chanb16250e2006-09-27 16:10:14 -070011034 }, mem_tbl_5906[] = {
11035 { 0x00000200, 0x00008},
11036 { 0x00004000, 0x00400},
11037 { 0x00006000, 0x00400},
11038 { 0x00008000, 0x01000},
11039 { 0x00010000, 0x01000},
11040 { 0xffffffff, 0x00000}
Matt Carlson8b5a6c42010-01-20 16:58:06 +000011041 }, mem_tbl_5717[] = {
11042 { 0x00000200, 0x00008},
11043 { 0x00010000, 0x0a000},
11044 { 0x00020000, 0x13c00},
11045 { 0xffffffff, 0x00000}
11046 }, mem_tbl_57765[] = {
11047 { 0x00000200, 0x00008},
11048 { 0x00004000, 0x00800},
11049 { 0x00006000, 0x09800},
11050 { 0x00010000, 0x0a000},
11051 { 0xffffffff, 0x00000}
Michael Chan7942e1d2005-05-29 14:58:36 -070011052 };
11053 struct mem_entry *mem_tbl;
11054 int err = 0;
11055 int i;
11056
Matt Carlson0a58d662011-04-05 14:22:45 +000011057 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
Matt Carlson8b5a6c42010-01-20 16:58:06 +000011058 mem_tbl = mem_tbl_5717;
11059 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11060 mem_tbl = mem_tbl_57765;
11061 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Matt Carlson321d32a2008-11-21 17:22:19 -080011062 mem_tbl = mem_tbl_5755;
11063 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11064 mem_tbl = mem_tbl_5906;
11065 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
11066 mem_tbl = mem_tbl_5705;
11067 else
Michael Chan7942e1d2005-05-29 14:58:36 -070011068 mem_tbl = mem_tbl_570x;
11069
11070 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
Matt Carlsonbe98da62010-07-11 09:31:46 +000011071 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11072 if (err)
Michael Chan7942e1d2005-05-29 14:58:36 -070011073 break;
11074 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011075
Michael Chan7942e1d2005-05-29 14:58:36 -070011076 return err;
11077}
11078
Michael Chan9f40dea2005-09-05 17:53:06 -070011079#define TG3_MAC_LOOPBACK 0
11080#define TG3_PHY_LOOPBACK 1
11081
Matt Carlson4852a862011-04-13 11:05:07 +000011082static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
Michael Chanc76949a2005-05-29 14:58:59 -070011083{
Michael Chan9f40dea2005-09-05 17:53:06 -070011084 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
Matt Carlsonfd2ce372009-09-01 12:51:13 +000011085 u32 desc_idx, coal_now;
Michael Chanc76949a2005-05-29 14:58:59 -070011086 struct sk_buff *skb, *rx_skb;
11087 u8 *tx_data;
11088 dma_addr_t map;
11089 int num_pkts, tx_len, rx_len, i, err;
11090 struct tg3_rx_buffer_desc *desc;
Matt Carlson898a56f2009-08-28 14:02:40 +000011091 struct tg3_napi *tnapi, *rnapi;
Matt Carlson8fea32b2010-09-15 08:59:58 +000011092 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
Michael Chanc76949a2005-05-29 14:58:59 -070011093
Matt Carlsonc8873402010-02-12 14:47:11 +000011094 tnapi = &tp->napi[0];
11095 rnapi = &tp->napi[0];
Matt Carlson0c1d0e22009-09-01 13:16:33 +000011096 if (tp->irq_cnt > 1) {
Matt Carlson1da85aa2010-09-30 10:34:34 +000011097 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
11098 rnapi = &tp->napi[1];
Matt Carlsonc8873402010-02-12 14:47:11 +000011099 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
11100 tnapi = &tp->napi[1];
Matt Carlson0c1d0e22009-09-01 13:16:33 +000011101 }
Matt Carlsonfd2ce372009-09-01 12:51:13 +000011102 coal_now = tnapi->coal_now | rnapi->coal_now;
Matt Carlson898a56f2009-08-28 14:02:40 +000011103
Michael Chan9f40dea2005-09-05 17:53:06 -070011104 if (loopback_mode == TG3_MAC_LOOPBACK) {
Michael Chanc94e3942005-09-27 12:12:42 -070011105 /* HW errata - mac loopback fails in some cases on 5780.
11106 * Normal traffic and PHY loopback are not affected by
Matt Carlsonaba49f22011-01-25 15:58:53 +000011107 * errata. Also, the MAC loopback test is deprecated for
11108 * all newer ASIC revisions.
Michael Chanc94e3942005-09-27 12:12:42 -070011109 */
Matt Carlsonaba49f22011-01-25 15:58:53 +000011110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11111 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
Michael Chanc94e3942005-09-27 12:12:42 -070011112 return 0;
11113
Matt Carlson49692ca2011-01-25 15:58:52 +000011114 mac_mode = tp->mac_mode &
11115 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11116 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070011117 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11118 mac_mode |= MAC_MODE_LINK_POLARITY;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011119 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
Michael Chan3f7045c2006-09-27 16:02:29 -070011120 mac_mode |= MAC_MODE_PORT_MODE_MII;
11121 else
11122 mac_mode |= MAC_MODE_PORT_MODE_GMII;
Michael Chan9f40dea2005-09-05 17:53:06 -070011123 tw32(MAC_MODE, mac_mode);
11124 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
Michael Chan3f7045c2006-09-27 16:02:29 -070011125 u32 val;
11126
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011127 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson7f97a4b2009-08-25 10:10:03 +000011128 tg3_phy_fet_toggle_apd(tp, false);
Michael Chan5d64ad32006-12-07 00:19:40 -080011129 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
11130 } else
11131 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
Michael Chan3f7045c2006-09-27 16:02:29 -070011132
Matt Carlson9ef8ca92007-07-11 19:48:29 -070011133 tg3_phy_toggle_automdix(tp, 0);
11134
Michael Chan3f7045c2006-09-27 16:02:29 -070011135 tg3_writephy(tp, MII_BMCR, val);
Michael Chanc94e3942005-09-27 12:12:42 -070011136 udelay(40);
Michael Chan5d64ad32006-12-07 00:19:40 -080011137
Matt Carlson49692ca2011-01-25 15:58:52 +000011138 mac_mode = tp->mac_mode &
11139 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011140 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson1061b7c2010-02-12 14:47:12 +000011141 tg3_writephy(tp, MII_TG3_FET_PTEST,
11142 MII_TG3_FET_PTEST_FRC_TX_LINK |
11143 MII_TG3_FET_PTEST_FRC_TX_LOCK);
11144 /* The write needs to be flushed for the AC131 */
11145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11146 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
Michael Chan5d64ad32006-12-07 00:19:40 -080011147 mac_mode |= MAC_MODE_PORT_MODE_MII;
11148 } else
11149 mac_mode |= MAC_MODE_PORT_MODE_GMII;
Michael Chanb16250e2006-09-27 16:10:14 -070011150
Michael Chanc94e3942005-09-27 12:12:42 -070011151 /* reset to prevent losing 1st rx packet intermittently */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011152 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
Michael Chanc94e3942005-09-27 12:12:42 -070011153 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
11154 udelay(10);
11155 tw32_f(MAC_RX_MODE, tp->rx_mode);
11156 }
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070011157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
Matt Carlson79eb6902010-02-17 15:17:03 +000011158 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
11159 if (masked_phy_id == TG3_PHY_ID_BCM5401)
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070011160 mac_mode &= ~MAC_MODE_LINK_POLARITY;
Matt Carlson79eb6902010-02-17 15:17:03 +000011161 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070011162 mac_mode |= MAC_MODE_LINK_POLARITY;
Michael Chanff18ff02006-03-27 23:17:27 -080011163 tg3_writephy(tp, MII_TG3_EXT_CTRL,
11164 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
11165 }
Michael Chan9f40dea2005-09-05 17:53:06 -070011166 tw32(MAC_MODE, mac_mode);
Matt Carlson49692ca2011-01-25 15:58:52 +000011167
11168 /* Wait for link */
11169 for (i = 0; i < 100; i++) {
11170 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11171 break;
11172 mdelay(1);
11173 }
Matt Carlson859a588792010-04-05 10:19:28 +000011174 } else {
Michael Chan9f40dea2005-09-05 17:53:06 -070011175 return -EINVAL;
Matt Carlson859a588792010-04-05 10:19:28 +000011176 }
Michael Chanc76949a2005-05-29 14:58:59 -070011177
11178 err = -EIO;
11179
Matt Carlson4852a862011-04-13 11:05:07 +000011180 tx_len = pktsz;
David S. Millera20e9c62006-07-31 22:38:16 -070011181 skb = netdev_alloc_skb(tp->dev, tx_len);
Jesper Juhla50bb7b2006-05-09 23:14:35 -070011182 if (!skb)
11183 return -ENOMEM;
11184
Michael Chanc76949a2005-05-29 14:58:59 -070011185 tx_data = skb_put(skb, tx_len);
11186 memcpy(tx_data, tp->dev->dev_addr, 6);
11187 memset(tx_data + 6, 0x0, 8);
11188
Matt Carlson4852a862011-04-13 11:05:07 +000011189 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
Michael Chanc76949a2005-05-29 14:58:59 -070011190
11191 for (i = 14; i < tx_len; i++)
11192 tx_data[i] = (u8) (i & 0xff);
11193
Alexander Duyckf4188d82009-12-02 16:48:38 +000011194 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11195 if (pci_dma_mapping_error(tp->pdev, map)) {
Matt Carlsona21771d2009-11-02 14:25:31 +000011196 dev_kfree_skb(skb);
11197 return -EIO;
11198 }
Michael Chanc76949a2005-05-29 14:58:59 -070011199
11200 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000011201 rnapi->coal_now);
Michael Chanc76949a2005-05-29 14:58:59 -070011202
11203 udelay(10);
11204
Matt Carlson898a56f2009-08-28 14:02:40 +000011205 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
Michael Chanc76949a2005-05-29 14:58:59 -070011206
Michael Chanc76949a2005-05-29 14:58:59 -070011207 num_pkts = 0;
11208
Alexander Duyckf4188d82009-12-02 16:48:38 +000011209 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
Michael Chanc76949a2005-05-29 14:58:59 -070011210
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011211 tnapi->tx_prod++;
Michael Chanc76949a2005-05-29 14:58:59 -070011212 num_pkts++;
11213
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011214 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11215 tr32_mailbox(tnapi->prodmbox);
Michael Chanc76949a2005-05-29 14:58:59 -070011216
11217 udelay(10);
11218
Matt Carlson303fc922009-11-02 14:27:34 +000011219 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11220 for (i = 0; i < 35; i++) {
Michael Chanc76949a2005-05-29 14:58:59 -070011221 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000011222 coal_now);
Michael Chanc76949a2005-05-29 14:58:59 -070011223
11224 udelay(10);
11225
Matt Carlson898a56f2009-08-28 14:02:40 +000011226 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11227 rx_idx = rnapi->hw_status->idx[0].rx_producer;
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011228 if ((tx_idx == tnapi->tx_prod) &&
Michael Chanc76949a2005-05-29 14:58:59 -070011229 (rx_idx == (rx_start_idx + num_pkts)))
11230 break;
11231 }
11232
Alexander Duyckf4188d82009-12-02 16:48:38 +000011233 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
Michael Chanc76949a2005-05-29 14:58:59 -070011234 dev_kfree_skb(skb);
11235
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011236 if (tx_idx != tnapi->tx_prod)
Michael Chanc76949a2005-05-29 14:58:59 -070011237 goto out;
11238
11239 if (rx_idx != rx_start_idx + num_pkts)
11240 goto out;
11241
Matt Carlson72334482009-08-28 14:03:01 +000011242 desc = &rnapi->rx_rcb[rx_start_idx];
Michael Chanc76949a2005-05-29 14:58:59 -070011243 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11244 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
Michael Chanc76949a2005-05-29 14:58:59 -070011245
11246 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11247 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11248 goto out;
11249
11250 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11251 if (rx_len != tx_len)
11252 goto out;
11253
Matt Carlson4852a862011-04-13 11:05:07 +000011254 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11255 if (opaque_key != RXD_OPAQUE_RING_STD)
11256 goto out;
Michael Chanc76949a2005-05-29 14:58:59 -070011257
Matt Carlson4852a862011-04-13 11:05:07 +000011258 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11259 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11260 } else {
11261 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11262 goto out;
11263
11264 rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11265 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], mapping);
11266 }
11267
Michael Chanc76949a2005-05-29 14:58:59 -070011268 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11269
11270 for (i = 14; i < tx_len; i++) {
11271 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11272 goto out;
11273 }
11274 err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011275
Michael Chanc76949a2005-05-29 14:58:59 -070011276 /* tg3_free_rings will unmap and free the rx_skb */
11277out:
11278 return err;
11279}
11280
Michael Chan9f40dea2005-09-05 17:53:06 -070011281#define TG3_MAC_LOOPBACK_FAILED 1
11282#define TG3_PHY_LOOPBACK_FAILED 2
11283#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11284 TG3_PHY_LOOPBACK_FAILED)
11285
11286static int tg3_test_loopback(struct tg3 *tp)
11287{
11288 int err = 0;
Matt Carlsonab789042011-01-25 15:58:54 +000011289 u32 eee_cap, cpmuctrl = 0;
Michael Chan9f40dea2005-09-05 17:53:06 -070011290
11291 if (!netif_running(tp->dev))
11292 return TG3_LOOPBACK_FAILED;
11293
Matt Carlsonab789042011-01-25 15:58:54 +000011294 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11295 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11296
Michael Chanb9ec6c12006-07-25 16:37:27 -070011297 err = tg3_reset_hw(tp, 1);
Matt Carlsonab789042011-01-25 15:58:54 +000011298 if (err) {
11299 err = TG3_LOOPBACK_FAILED;
11300 goto done;
11301 }
Michael Chan9f40dea2005-09-05 17:53:06 -070011302
Matt Carlson4a85f092011-04-20 07:57:37 +000011303 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
11304 int i;
11305
11306 /* Reroute all rx packets to the 1st queue */
11307 for (i = MAC_RSS_INDIR_TBL_0;
11308 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11309 tw32(i, 0x0);
11310 }
11311
Matt Carlson6833c042008-11-21 17:18:59 -080011312 /* Turn off gphy autopowerdown. */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011313 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
Matt Carlson6833c042008-11-21 17:18:59 -080011314 tg3_phy_toggle_apd(tp, false);
11315
Matt Carlson321d32a2008-11-21 17:22:19 -080011316 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
Matt Carlson9936bcf2007-10-10 18:03:07 -070011317 int i;
11318 u32 status;
11319
11320 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11321
11322 /* Wait for up to 40 microseconds to acquire lock. */
11323 for (i = 0; i < 4; i++) {
11324 status = tr32(TG3_CPMU_MUTEX_GNT);
11325 if (status == CPMU_MUTEX_GNT_DRIVER)
11326 break;
11327 udelay(10);
11328 }
11329
Matt Carlsonab789042011-01-25 15:58:54 +000011330 if (status != CPMU_MUTEX_GNT_DRIVER) {
11331 err = TG3_LOOPBACK_FAILED;
11332 goto done;
11333 }
Matt Carlson9936bcf2007-10-10 18:03:07 -070011334
Matt Carlsonb2a5c192008-04-03 21:44:44 -070011335 /* Turn off link-based power management. */
Matt Carlsone8750932007-11-12 21:11:51 -080011336 cpmuctrl = tr32(TG3_CPMU_CTRL);
Matt Carlson109115e2008-05-02 16:48:59 -070011337 tw32(TG3_CPMU_CTRL,
11338 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11339 CPMU_CTRL_LINK_AWARE_MODE));
Matt Carlson9936bcf2007-10-10 18:03:07 -070011340 }
11341
Matt Carlson4852a862011-04-13 11:05:07 +000011342 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK))
Michael Chan9f40dea2005-09-05 17:53:06 -070011343 err |= TG3_MAC_LOOPBACK_FAILED;
Matt Carlson9936bcf2007-10-10 18:03:07 -070011344
Matt Carlson4852a862011-04-13 11:05:07 +000011345 if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) &&
11346 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK))
11347 err |= (TG3_MAC_LOOPBACK_FAILED << 2);
11348
Matt Carlson321d32a2008-11-21 17:22:19 -080011349 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
Matt Carlson9936bcf2007-10-10 18:03:07 -070011350 tw32(TG3_CPMU_CTRL, cpmuctrl);
11351
11352 /* Release the mutex */
11353 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11354 }
11355
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011356 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Matt Carlsondd477002008-05-25 23:45:58 -070011357 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
Matt Carlson4852a862011-04-13 11:05:07 +000011358 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK))
Michael Chan9f40dea2005-09-05 17:53:06 -070011359 err |= TG3_PHY_LOOPBACK_FAILED;
Matt Carlson4852a862011-04-13 11:05:07 +000011360 if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) &&
11361 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK))
11362 err |= (TG3_PHY_LOOPBACK_FAILED << 2);
Michael Chan9f40dea2005-09-05 17:53:06 -070011363 }
11364
Matt Carlson6833c042008-11-21 17:18:59 -080011365 /* Re-enable gphy autopowerdown. */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011366 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
Matt Carlson6833c042008-11-21 17:18:59 -080011367 tg3_phy_toggle_apd(tp, true);
11368
Matt Carlsonab789042011-01-25 15:58:54 +000011369done:
11370 tp->phy_flags |= eee_cap;
11371
Michael Chan9f40dea2005-09-05 17:53:06 -070011372 return err;
11373}
11374
Michael Chan4cafd3f2005-05-29 14:56:34 -070011375static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11376 u64 *data)
11377{
Michael Chan566f86a2005-05-29 14:56:58 -070011378 struct tg3 *tp = netdev_priv(dev);
11379
Matt Carlson80096062010-08-02 11:26:06 +000011380 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000011381 tg3_power_up(tp);
Michael Chanbc1c7562006-03-20 17:48:03 -080011382
Michael Chan566f86a2005-05-29 14:56:58 -070011383 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11384
11385 if (tg3_test_nvram(tp) != 0) {
11386 etest->flags |= ETH_TEST_FL_FAILED;
11387 data[0] = 1;
11388 }
Michael Chanca430072005-05-29 14:57:23 -070011389 if (tg3_test_link(tp) != 0) {
11390 etest->flags |= ETH_TEST_FL_FAILED;
11391 data[1] = 1;
11392 }
Michael Chana71116d2005-05-29 14:58:11 -070011393 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011394 int err, err2 = 0, irq_sync = 0;
Michael Chana71116d2005-05-29 14:58:11 -070011395
Michael Chanbbe832c2005-06-24 20:20:04 -070011396 if (netif_running(dev)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011397 tg3_phy_stop(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070011398 tg3_netif_stop(tp);
11399 irq_sync = 1;
11400 }
11401
11402 tg3_full_lock(tp, irq_sync);
Michael Chana71116d2005-05-29 14:58:11 -070011403
11404 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
Michael Chanec41c7d2006-01-17 02:40:55 -080011405 err = tg3_nvram_lock(tp);
Michael Chana71116d2005-05-29 14:58:11 -070011406 tg3_halt_cpu(tp, RX_CPU_BASE);
11407 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11408 tg3_halt_cpu(tp, TX_CPU_BASE);
Michael Chanec41c7d2006-01-17 02:40:55 -080011409 if (!err)
11410 tg3_nvram_unlock(tp);
Michael Chana71116d2005-05-29 14:58:11 -070011411
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011412 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chand9ab5ad12006-03-20 22:27:35 -080011413 tg3_phy_reset(tp);
11414
Michael Chana71116d2005-05-29 14:58:11 -070011415 if (tg3_test_registers(tp) != 0) {
11416 etest->flags |= ETH_TEST_FL_FAILED;
11417 data[2] = 1;
11418 }
Michael Chan7942e1d2005-05-29 14:58:36 -070011419 if (tg3_test_memory(tp) != 0) {
11420 etest->flags |= ETH_TEST_FL_FAILED;
11421 data[3] = 1;
11422 }
Michael Chan9f40dea2005-09-05 17:53:06 -070011423 if ((data[4] = tg3_test_loopback(tp)) != 0)
Michael Chanc76949a2005-05-29 14:58:59 -070011424 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chana71116d2005-05-29 14:58:11 -070011425
David S. Millerf47c11e2005-06-24 20:18:35 -070011426 tg3_full_unlock(tp);
11427
Michael Chand4bc3922005-05-29 14:59:20 -070011428 if (tg3_test_interrupt(tp) != 0) {
11429 etest->flags |= ETH_TEST_FL_FAILED;
11430 data[5] = 1;
11431 }
David S. Millerf47c11e2005-06-24 20:18:35 -070011432
11433 tg3_full_lock(tp, 0);
Michael Chand4bc3922005-05-29 14:59:20 -070011434
Michael Chana71116d2005-05-29 14:58:11 -070011435 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11436 if (netif_running(dev)) {
11437 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011438 err2 = tg3_restart_hw(tp, 1);
11439 if (!err2)
Michael Chanb9ec6c12006-07-25 16:37:27 -070011440 tg3_netif_start(tp);
Michael Chana71116d2005-05-29 14:58:11 -070011441 }
David S. Millerf47c11e2005-06-24 20:18:35 -070011442
11443 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011444
11445 if (irq_sync && !err2)
11446 tg3_phy_start(tp);
Michael Chana71116d2005-05-29 14:58:11 -070011447 }
Matt Carlson80096062010-08-02 11:26:06 +000011448 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000011449 tg3_power_down(tp);
Michael Chanbc1c7562006-03-20 17:48:03 -080011450
Michael Chan4cafd3f2005-05-29 14:56:34 -070011451}
11452
Linus Torvalds1da177e2005-04-16 15:20:36 -070011453static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11454{
11455 struct mii_ioctl_data *data = if_mii(ifr);
11456 struct tg3 *tp = netdev_priv(dev);
11457 int err;
11458
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011459 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000011460 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011461 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011462 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000011463 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Richard Cochran28b04112010-07-17 08:48:55 +000011464 return phy_mii_ioctl(phydev, ifr, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011465 }
11466
Matt Carlson33f401a2010-04-05 10:19:27 +000011467 switch (cmd) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011468 case SIOCGMIIPHY:
Matt Carlson882e9792009-09-01 13:21:36 +000011469 data->phy_id = tp->phy_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011470
11471 /* fallthru */
11472 case SIOCGMIIREG: {
11473 u32 mii_regval;
11474
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011475 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011476 break; /* We have no PHY */
11477
Matt Carlson34eea5a2011-04-20 07:57:38 +000011478 if (!netif_running(dev))
Michael Chanbc1c7562006-03-20 17:48:03 -080011479 return -EAGAIN;
11480
David S. Millerf47c11e2005-06-24 20:18:35 -070011481 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011482 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
David S. Millerf47c11e2005-06-24 20:18:35 -070011483 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011484
11485 data->val_out = mii_regval;
11486
11487 return err;
11488 }
11489
11490 case SIOCSMIIREG:
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011491 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011492 break; /* We have no PHY */
11493
Matt Carlson34eea5a2011-04-20 07:57:38 +000011494 if (!netif_running(dev))
Michael Chanbc1c7562006-03-20 17:48:03 -080011495 return -EAGAIN;
11496
David S. Millerf47c11e2005-06-24 20:18:35 -070011497 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011498 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
David S. Millerf47c11e2005-06-24 20:18:35 -070011499 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011500
11501 return err;
11502
11503 default:
11504 /* do nothing */
11505 break;
11506 }
11507 return -EOPNOTSUPP;
11508}
11509
David S. Miller15f98502005-05-18 22:49:26 -070011510static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11511{
11512 struct tg3 *tp = netdev_priv(dev);
11513
11514 memcpy(ec, &tp->coal, sizeof(*ec));
11515 return 0;
11516}
11517
Michael Chand244c892005-07-05 14:42:33 -070011518static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11519{
11520 struct tg3 *tp = netdev_priv(dev);
11521 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11522 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11523
11524 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11525 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11526 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11527 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11528 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11529 }
11530
11531 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11532 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11533 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11534 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11535 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11536 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11537 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11538 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11539 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11540 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11541 return -EINVAL;
11542
11543 /* No rx interrupts will be generated if both are zero */
11544 if ((ec->rx_coalesce_usecs == 0) &&
11545 (ec->rx_max_coalesced_frames == 0))
11546 return -EINVAL;
11547
11548 /* No tx interrupts will be generated if both are zero */
11549 if ((ec->tx_coalesce_usecs == 0) &&
11550 (ec->tx_max_coalesced_frames == 0))
11551 return -EINVAL;
11552
11553 /* Only copy relevant parameters, ignore all others. */
11554 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11555 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11556 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11557 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11558 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11559 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11560 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11561 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11562 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11563
11564 if (netif_running(dev)) {
11565 tg3_full_lock(tp, 0);
11566 __tg3_set_coalesce(tp, &tp->coal);
11567 tg3_full_unlock(tp);
11568 }
11569 return 0;
11570}
11571
Jeff Garzik7282d492006-09-13 14:30:00 -040011572static const struct ethtool_ops tg3_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011573 .get_settings = tg3_get_settings,
11574 .set_settings = tg3_set_settings,
11575 .get_drvinfo = tg3_get_drvinfo,
11576 .get_regs_len = tg3_get_regs_len,
11577 .get_regs = tg3_get_regs,
11578 .get_wol = tg3_get_wol,
11579 .set_wol = tg3_set_wol,
11580 .get_msglevel = tg3_get_msglevel,
11581 .set_msglevel = tg3_set_msglevel,
11582 .nway_reset = tg3_nway_reset,
11583 .get_link = ethtool_op_get_link,
11584 .get_eeprom_len = tg3_get_eeprom_len,
11585 .get_eeprom = tg3_get_eeprom,
11586 .set_eeprom = tg3_set_eeprom,
11587 .get_ringparam = tg3_get_ringparam,
11588 .set_ringparam = tg3_set_ringparam,
11589 .get_pauseparam = tg3_get_pauseparam,
11590 .set_pauseparam = tg3_set_pauseparam,
Michael Chan4cafd3f2005-05-29 14:56:34 -070011591 .self_test = tg3_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011592 .get_strings = tg3_get_strings,
stephen hemminger81b87092011-04-04 08:43:50 +000011593 .set_phys_id = tg3_set_phys_id,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011594 .get_ethtool_stats = tg3_get_ethtool_stats,
David S. Miller15f98502005-05-18 22:49:26 -070011595 .get_coalesce = tg3_get_coalesce,
Michael Chand244c892005-07-05 14:42:33 -070011596 .set_coalesce = tg3_set_coalesce,
Jeff Garzikb9f2c042007-10-03 18:07:32 -070011597 .get_sset_count = tg3_get_sset_count,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011598};
11599
11600static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11601{
Michael Chan1b277772006-03-20 22:27:48 -080011602 u32 cursize, val, magic;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011603
11604 tp->nvram_size = EEPROM_CHIP_SIZE;
11605
Matt Carlsone4f34112009-02-25 14:25:00 +000011606 if (tg3_nvram_read(tp, 0, &magic) != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011607 return;
11608
Michael Chanb16250e2006-09-27 16:10:14 -070011609 if ((magic != TG3_EEPROM_MAGIC) &&
11610 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11611 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011612 return;
11613
11614 /*
11615 * Size the chip by reading offsets at increasing powers of two.
11616 * When we encounter our validation signature, we know the addressing
11617 * has wrapped around, and thus have our chip size.
11618 */
Michael Chan1b277772006-03-20 22:27:48 -080011619 cursize = 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011620
11621 while (cursize < tp->nvram_size) {
Matt Carlsone4f34112009-02-25 14:25:00 +000011622 if (tg3_nvram_read(tp, cursize, &val) != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011623 return;
11624
Michael Chan18201802006-03-20 22:29:15 -080011625 if (val == magic)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011626 break;
11627
11628 cursize <<= 1;
11629 }
11630
11631 tp->nvram_size = cursize;
11632}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011633
Linus Torvalds1da177e2005-04-16 15:20:36 -070011634static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11635{
11636 u32 val;
11637
Matt Carlsondf259d82009-04-20 06:57:14 +000011638 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11639 tg3_nvram_read(tp, 0, &val) != 0)
Michael Chan1b277772006-03-20 22:27:48 -080011640 return;
11641
11642 /* Selfboot format */
Michael Chan18201802006-03-20 22:29:15 -080011643 if (val != TG3_EEPROM_MAGIC) {
Michael Chan1b277772006-03-20 22:27:48 -080011644 tg3_get_eeprom_size(tp);
11645 return;
11646 }
11647
Matt Carlson6d348f22009-02-25 14:25:52 +000011648 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011649 if (val != 0) {
Matt Carlson6d348f22009-02-25 14:25:52 +000011650 /* This is confusing. We want to operate on the
11651 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11652 * call will read from NVRAM and byteswap the data
11653 * according to the byteswapping settings for all
11654 * other register accesses. This ensures the data we
11655 * want will always reside in the lower 16-bits.
11656 * However, the data in NVRAM is in LE format, which
11657 * means the data from the NVRAM read will always be
11658 * opposite the endianness of the CPU. The 16-bit
11659 * byteswap then brings the data to CPU endianness.
11660 */
11661 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011662 return;
11663 }
11664 }
Matt Carlsonfd1122a2008-05-02 16:48:36 -070011665 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011666}
11667
11668static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11669{
11670 u32 nvcfg1;
11671
11672 nvcfg1 = tr32(NVRAM_CFG1);
11673 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11674 tp->tg3_flags2 |= TG3_FLG2_FLASH;
Matt Carlson8590a602009-08-28 12:29:16 +000011675 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011676 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11677 tw32(NVRAM_CFG1, nvcfg1);
11678 }
11679
Michael Chan4c987482005-09-05 17:52:38 -070011680 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
Michael Chana4e2b342005-10-26 15:46:52 -070011681 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011682 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000011683 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11684 tp->nvram_jedecnum = JEDEC_ATMEL;
11685 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11686 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11687 break;
11688 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11689 tp->nvram_jedecnum = JEDEC_ATMEL;
11690 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11691 break;
11692 case FLASH_VENDOR_ATMEL_EEPROM:
11693 tp->nvram_jedecnum = JEDEC_ATMEL;
11694 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11695 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11696 break;
11697 case FLASH_VENDOR_ST:
11698 tp->nvram_jedecnum = JEDEC_ST;
11699 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11700 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11701 break;
11702 case FLASH_VENDOR_SAIFUN:
11703 tp->nvram_jedecnum = JEDEC_SAIFUN;
11704 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11705 break;
11706 case FLASH_VENDOR_SST_SMALL:
11707 case FLASH_VENDOR_SST_LARGE:
11708 tp->nvram_jedecnum = JEDEC_SST;
11709 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11710 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011711 }
Matt Carlson8590a602009-08-28 12:29:16 +000011712 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011713 tp->nvram_jedecnum = JEDEC_ATMEL;
11714 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11715 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11716 }
11717}
11718
Matt Carlsona1b950d2009-09-01 13:20:17 +000011719static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11720{
11721 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11722 case FLASH_5752PAGE_SIZE_256:
11723 tp->nvram_pagesize = 256;
11724 break;
11725 case FLASH_5752PAGE_SIZE_512:
11726 tp->nvram_pagesize = 512;
11727 break;
11728 case FLASH_5752PAGE_SIZE_1K:
11729 tp->nvram_pagesize = 1024;
11730 break;
11731 case FLASH_5752PAGE_SIZE_2K:
11732 tp->nvram_pagesize = 2048;
11733 break;
11734 case FLASH_5752PAGE_SIZE_4K:
11735 tp->nvram_pagesize = 4096;
11736 break;
11737 case FLASH_5752PAGE_SIZE_264:
11738 tp->nvram_pagesize = 264;
11739 break;
11740 case FLASH_5752PAGE_SIZE_528:
11741 tp->nvram_pagesize = 528;
11742 break;
11743 }
11744}
11745
Michael Chan361b4ac2005-04-21 17:11:21 -070011746static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11747{
11748 u32 nvcfg1;
11749
11750 nvcfg1 = tr32(NVRAM_CFG1);
11751
Michael Chane6af3012005-04-21 17:12:05 -070011752 /* NVRAM protection for TPM */
11753 if (nvcfg1 & (1 << 27))
Matt Carlsonf66a29b2009-11-13 13:03:36 +000011754 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
Michael Chane6af3012005-04-21 17:12:05 -070011755
Michael Chan361b4ac2005-04-21 17:11:21 -070011756 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000011757 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11758 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11759 tp->nvram_jedecnum = JEDEC_ATMEL;
11760 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11761 break;
11762 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11763 tp->nvram_jedecnum = JEDEC_ATMEL;
11764 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11765 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11766 break;
11767 case FLASH_5752VENDOR_ST_M45PE10:
11768 case FLASH_5752VENDOR_ST_M45PE20:
11769 case FLASH_5752VENDOR_ST_M45PE40:
11770 tp->nvram_jedecnum = JEDEC_ST;
11771 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11772 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11773 break;
Michael Chan361b4ac2005-04-21 17:11:21 -070011774 }
11775
11776 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
Matt Carlsona1b950d2009-09-01 13:20:17 +000011777 tg3_nvram_get_pagesize(tp, nvcfg1);
Matt Carlson8590a602009-08-28 12:29:16 +000011778 } else {
Michael Chan361b4ac2005-04-21 17:11:21 -070011779 /* For eeprom, set pagesize to maximum eeprom size */
11780 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11781
11782 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11783 tw32(NVRAM_CFG1, nvcfg1);
11784 }
11785}
11786
Michael Chand3c7b882006-03-23 01:28:25 -080011787static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11788{
Matt Carlson989a9d22007-05-05 11:51:05 -070011789 u32 nvcfg1, protect = 0;
Michael Chand3c7b882006-03-23 01:28:25 -080011790
11791 nvcfg1 = tr32(NVRAM_CFG1);
11792
11793 /* NVRAM protection for TPM */
Matt Carlson989a9d22007-05-05 11:51:05 -070011794 if (nvcfg1 & (1 << 27)) {
Matt Carlsonf66a29b2009-11-13 13:03:36 +000011795 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
Matt Carlson989a9d22007-05-05 11:51:05 -070011796 protect = 1;
11797 }
Michael Chand3c7b882006-03-23 01:28:25 -080011798
Matt Carlson989a9d22007-05-05 11:51:05 -070011799 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11800 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000011801 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11802 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11803 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11804 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11805 tp->nvram_jedecnum = JEDEC_ATMEL;
11806 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11807 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11808 tp->nvram_pagesize = 264;
11809 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11810 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11811 tp->nvram_size = (protect ? 0x3e200 :
11812 TG3_NVRAM_SIZE_512KB);
11813 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11814 tp->nvram_size = (protect ? 0x1f200 :
11815 TG3_NVRAM_SIZE_256KB);
11816 else
11817 tp->nvram_size = (protect ? 0x1f200 :
11818 TG3_NVRAM_SIZE_128KB);
11819 break;
11820 case FLASH_5752VENDOR_ST_M45PE10:
11821 case FLASH_5752VENDOR_ST_M45PE20:
11822 case FLASH_5752VENDOR_ST_M45PE40:
11823 tp->nvram_jedecnum = JEDEC_ST;
11824 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11825 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11826 tp->nvram_pagesize = 256;
11827 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11828 tp->nvram_size = (protect ?
11829 TG3_NVRAM_SIZE_64KB :
11830 TG3_NVRAM_SIZE_128KB);
11831 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11832 tp->nvram_size = (protect ?
11833 TG3_NVRAM_SIZE_64KB :
11834 TG3_NVRAM_SIZE_256KB);
11835 else
11836 tp->nvram_size = (protect ?
11837 TG3_NVRAM_SIZE_128KB :
11838 TG3_NVRAM_SIZE_512KB);
11839 break;
Michael Chand3c7b882006-03-23 01:28:25 -080011840 }
11841}
11842
Michael Chan1b277772006-03-20 22:27:48 -080011843static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11844{
11845 u32 nvcfg1;
11846
11847 nvcfg1 = tr32(NVRAM_CFG1);
11848
11849 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000011850 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11851 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11852 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11853 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11854 tp->nvram_jedecnum = JEDEC_ATMEL;
11855 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11856 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
Michael Chan1b277772006-03-20 22:27:48 -080011857
Matt Carlson8590a602009-08-28 12:29:16 +000011858 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11859 tw32(NVRAM_CFG1, nvcfg1);
11860 break;
11861 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11862 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11863 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11864 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11865 tp->nvram_jedecnum = JEDEC_ATMEL;
11866 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11867 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11868 tp->nvram_pagesize = 264;
11869 break;
11870 case FLASH_5752VENDOR_ST_M45PE10:
11871 case FLASH_5752VENDOR_ST_M45PE20:
11872 case FLASH_5752VENDOR_ST_M45PE40:
11873 tp->nvram_jedecnum = JEDEC_ST;
11874 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11875 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11876 tp->nvram_pagesize = 256;
11877 break;
Michael Chan1b277772006-03-20 22:27:48 -080011878 }
11879}
11880
Matt Carlson6b91fa02007-10-10 18:01:09 -070011881static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11882{
11883 u32 nvcfg1, protect = 0;
11884
11885 nvcfg1 = tr32(NVRAM_CFG1);
11886
11887 /* NVRAM protection for TPM */
11888 if (nvcfg1 & (1 << 27)) {
Matt Carlsonf66a29b2009-11-13 13:03:36 +000011889 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
Matt Carlson6b91fa02007-10-10 18:01:09 -070011890 protect = 1;
11891 }
11892
11893 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11894 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000011895 case FLASH_5761VENDOR_ATMEL_ADB021D:
11896 case FLASH_5761VENDOR_ATMEL_ADB041D:
11897 case FLASH_5761VENDOR_ATMEL_ADB081D:
11898 case FLASH_5761VENDOR_ATMEL_ADB161D:
11899 case FLASH_5761VENDOR_ATMEL_MDB021D:
11900 case FLASH_5761VENDOR_ATMEL_MDB041D:
11901 case FLASH_5761VENDOR_ATMEL_MDB081D:
11902 case FLASH_5761VENDOR_ATMEL_MDB161D:
11903 tp->nvram_jedecnum = JEDEC_ATMEL;
11904 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11905 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11906 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11907 tp->nvram_pagesize = 256;
11908 break;
11909 case FLASH_5761VENDOR_ST_A_M45PE20:
11910 case FLASH_5761VENDOR_ST_A_M45PE40:
11911 case FLASH_5761VENDOR_ST_A_M45PE80:
11912 case FLASH_5761VENDOR_ST_A_M45PE16:
11913 case FLASH_5761VENDOR_ST_M_M45PE20:
11914 case FLASH_5761VENDOR_ST_M_M45PE40:
11915 case FLASH_5761VENDOR_ST_M_M45PE80:
11916 case FLASH_5761VENDOR_ST_M_M45PE16:
11917 tp->nvram_jedecnum = JEDEC_ST;
11918 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11919 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11920 tp->nvram_pagesize = 256;
11921 break;
Matt Carlson6b91fa02007-10-10 18:01:09 -070011922 }
11923
11924 if (protect) {
11925 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11926 } else {
11927 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000011928 case FLASH_5761VENDOR_ATMEL_ADB161D:
11929 case FLASH_5761VENDOR_ATMEL_MDB161D:
11930 case FLASH_5761VENDOR_ST_A_M45PE16:
11931 case FLASH_5761VENDOR_ST_M_M45PE16:
11932 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11933 break;
11934 case FLASH_5761VENDOR_ATMEL_ADB081D:
11935 case FLASH_5761VENDOR_ATMEL_MDB081D:
11936 case FLASH_5761VENDOR_ST_A_M45PE80:
11937 case FLASH_5761VENDOR_ST_M_M45PE80:
11938 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11939 break;
11940 case FLASH_5761VENDOR_ATMEL_ADB041D:
11941 case FLASH_5761VENDOR_ATMEL_MDB041D:
11942 case FLASH_5761VENDOR_ST_A_M45PE40:
11943 case FLASH_5761VENDOR_ST_M_M45PE40:
11944 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11945 break;
11946 case FLASH_5761VENDOR_ATMEL_ADB021D:
11947 case FLASH_5761VENDOR_ATMEL_MDB021D:
11948 case FLASH_5761VENDOR_ST_A_M45PE20:
11949 case FLASH_5761VENDOR_ST_M_M45PE20:
11950 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11951 break;
Matt Carlson6b91fa02007-10-10 18:01:09 -070011952 }
11953 }
11954}
11955
Michael Chanb5d37722006-09-27 16:06:21 -070011956static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11957{
11958 tp->nvram_jedecnum = JEDEC_ATMEL;
11959 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11960 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11961}
11962
Matt Carlson321d32a2008-11-21 17:22:19 -080011963static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11964{
11965 u32 nvcfg1;
11966
11967 nvcfg1 = tr32(NVRAM_CFG1);
11968
11969 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11970 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11971 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11972 tp->nvram_jedecnum = JEDEC_ATMEL;
11973 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11974 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11975
11976 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11977 tw32(NVRAM_CFG1, nvcfg1);
11978 return;
11979 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11980 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11981 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11982 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11983 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11984 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11985 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11986 tp->nvram_jedecnum = JEDEC_ATMEL;
11987 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11988 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11989
11990 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11991 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11992 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11993 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11994 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11995 break;
11996 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11997 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11998 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11999 break;
12000 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12001 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12002 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12003 break;
12004 }
12005 break;
12006 case FLASH_5752VENDOR_ST_M45PE10:
12007 case FLASH_5752VENDOR_ST_M45PE20:
12008 case FLASH_5752VENDOR_ST_M45PE40:
12009 tp->nvram_jedecnum = JEDEC_ST;
12010 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12011 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12012
12013 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12014 case FLASH_5752VENDOR_ST_M45PE10:
12015 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12016 break;
12017 case FLASH_5752VENDOR_ST_M45PE20:
12018 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12019 break;
12020 case FLASH_5752VENDOR_ST_M45PE40:
12021 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12022 break;
12023 }
12024 break;
12025 default:
Matt Carlsondf259d82009-04-20 06:57:14 +000012026 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
Matt Carlson321d32a2008-11-21 17:22:19 -080012027 return;
12028 }
12029
Matt Carlsona1b950d2009-09-01 13:20:17 +000012030 tg3_nvram_get_pagesize(tp, nvcfg1);
12031 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
Matt Carlson321d32a2008-11-21 17:22:19 -080012032 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
Matt Carlsona1b950d2009-09-01 13:20:17 +000012033}
12034
12035
12036static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12037{
12038 u32 nvcfg1;
12039
12040 nvcfg1 = tr32(NVRAM_CFG1);
12041
12042 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12043 case FLASH_5717VENDOR_ATMEL_EEPROM:
12044 case FLASH_5717VENDOR_MICRO_EEPROM:
12045 tp->nvram_jedecnum = JEDEC_ATMEL;
12046 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12047 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12048
12049 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12050 tw32(NVRAM_CFG1, nvcfg1);
12051 return;
12052 case FLASH_5717VENDOR_ATMEL_MDB011D:
12053 case FLASH_5717VENDOR_ATMEL_ADB011B:
12054 case FLASH_5717VENDOR_ATMEL_ADB011D:
12055 case FLASH_5717VENDOR_ATMEL_MDB021D:
12056 case FLASH_5717VENDOR_ATMEL_ADB021B:
12057 case FLASH_5717VENDOR_ATMEL_ADB021D:
12058 case FLASH_5717VENDOR_ATMEL_45USPT:
12059 tp->nvram_jedecnum = JEDEC_ATMEL;
12060 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12061 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12062
12063 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12064 case FLASH_5717VENDOR_ATMEL_MDB021D:
Matt Carlson66ee33b2011-04-05 14:22:51 +000012065 /* Detect size with tg3_nvram_get_size() */
12066 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000012067 case FLASH_5717VENDOR_ATMEL_ADB021B:
12068 case FLASH_5717VENDOR_ATMEL_ADB021D:
12069 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12070 break;
12071 default:
12072 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12073 break;
12074 }
Matt Carlson321d32a2008-11-21 17:22:19 -080012075 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000012076 case FLASH_5717VENDOR_ST_M_M25PE10:
12077 case FLASH_5717VENDOR_ST_A_M25PE10:
12078 case FLASH_5717VENDOR_ST_M_M45PE10:
12079 case FLASH_5717VENDOR_ST_A_M45PE10:
12080 case FLASH_5717VENDOR_ST_M_M25PE20:
12081 case FLASH_5717VENDOR_ST_A_M25PE20:
12082 case FLASH_5717VENDOR_ST_M_M45PE20:
12083 case FLASH_5717VENDOR_ST_A_M45PE20:
12084 case FLASH_5717VENDOR_ST_25USPT:
12085 case FLASH_5717VENDOR_ST_45USPT:
12086 tp->nvram_jedecnum = JEDEC_ST;
12087 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12088 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12089
12090 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12091 case FLASH_5717VENDOR_ST_M_M25PE20:
Matt Carlsona1b950d2009-09-01 13:20:17 +000012092 case FLASH_5717VENDOR_ST_M_M45PE20:
Matt Carlson66ee33b2011-04-05 14:22:51 +000012093 /* Detect size with tg3_nvram_get_size() */
12094 break;
12095 case FLASH_5717VENDOR_ST_A_M25PE20:
Matt Carlsona1b950d2009-09-01 13:20:17 +000012096 case FLASH_5717VENDOR_ST_A_M45PE20:
12097 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12098 break;
12099 default:
12100 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12101 break;
12102 }
Matt Carlson321d32a2008-11-21 17:22:19 -080012103 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000012104 default:
12105 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
12106 return;
Matt Carlson321d32a2008-11-21 17:22:19 -080012107 }
Matt Carlsona1b950d2009-09-01 13:20:17 +000012108
12109 tg3_nvram_get_pagesize(tp, nvcfg1);
12110 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12111 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
Matt Carlson321d32a2008-11-21 17:22:19 -080012112}
12113
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012114static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12115{
12116 u32 nvcfg1, nvmpinstrp;
12117
12118 nvcfg1 = tr32(NVRAM_CFG1);
12119 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12120
12121 switch (nvmpinstrp) {
12122 case FLASH_5720_EEPROM_HD:
12123 case FLASH_5720_EEPROM_LD:
12124 tp->nvram_jedecnum = JEDEC_ATMEL;
12125 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12126
12127 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12128 tw32(NVRAM_CFG1, nvcfg1);
12129 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12130 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12131 else
12132 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12133 return;
12134 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12135 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12136 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12137 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12138 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12139 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12140 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12141 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12142 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12143 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12144 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12145 case FLASH_5720VENDOR_ATMEL_45USPT:
12146 tp->nvram_jedecnum = JEDEC_ATMEL;
12147 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12148 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12149
12150 switch (nvmpinstrp) {
12151 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12152 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12153 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12154 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12155 break;
12156 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12157 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12158 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12159 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12160 break;
12161 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12162 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12163 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12164 break;
12165 default:
12166 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12167 break;
12168 }
12169 break;
12170 case FLASH_5720VENDOR_M_ST_M25PE10:
12171 case FLASH_5720VENDOR_M_ST_M45PE10:
12172 case FLASH_5720VENDOR_A_ST_M25PE10:
12173 case FLASH_5720VENDOR_A_ST_M45PE10:
12174 case FLASH_5720VENDOR_M_ST_M25PE20:
12175 case FLASH_5720VENDOR_M_ST_M45PE20:
12176 case FLASH_5720VENDOR_A_ST_M25PE20:
12177 case FLASH_5720VENDOR_A_ST_M45PE20:
12178 case FLASH_5720VENDOR_M_ST_M25PE40:
12179 case FLASH_5720VENDOR_M_ST_M45PE40:
12180 case FLASH_5720VENDOR_A_ST_M25PE40:
12181 case FLASH_5720VENDOR_A_ST_M45PE40:
12182 case FLASH_5720VENDOR_M_ST_M25PE80:
12183 case FLASH_5720VENDOR_M_ST_M45PE80:
12184 case FLASH_5720VENDOR_A_ST_M25PE80:
12185 case FLASH_5720VENDOR_A_ST_M45PE80:
12186 case FLASH_5720VENDOR_ST_25USPT:
12187 case FLASH_5720VENDOR_ST_45USPT:
12188 tp->nvram_jedecnum = JEDEC_ST;
12189 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12190 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12191
12192 switch (nvmpinstrp) {
12193 case FLASH_5720VENDOR_M_ST_M25PE20:
12194 case FLASH_5720VENDOR_M_ST_M45PE20:
12195 case FLASH_5720VENDOR_A_ST_M25PE20:
12196 case FLASH_5720VENDOR_A_ST_M45PE20:
12197 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12198 break;
12199 case FLASH_5720VENDOR_M_ST_M25PE40:
12200 case FLASH_5720VENDOR_M_ST_M45PE40:
12201 case FLASH_5720VENDOR_A_ST_M25PE40:
12202 case FLASH_5720VENDOR_A_ST_M45PE40:
12203 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12204 break;
12205 case FLASH_5720VENDOR_M_ST_M25PE80:
12206 case FLASH_5720VENDOR_M_ST_M45PE80:
12207 case FLASH_5720VENDOR_A_ST_M25PE80:
12208 case FLASH_5720VENDOR_A_ST_M45PE80:
12209 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12210 break;
12211 default:
12212 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12213 break;
12214 }
12215 break;
12216 default:
12217 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
12218 return;
12219 }
12220
12221 tg3_nvram_get_pagesize(tp, nvcfg1);
12222 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12223 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
12224}
12225
Linus Torvalds1da177e2005-04-16 15:20:36 -070012226/* Chips other than 5700/5701 use the NVRAM for fetching info. */
12227static void __devinit tg3_nvram_init(struct tg3 *tp)
12228{
Linus Torvalds1da177e2005-04-16 15:20:36 -070012229 tw32_f(GRC_EEPROM_ADDR,
12230 (EEPROM_ADDR_FSM_RESET |
12231 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12232 EEPROM_ADDR_CLKPERD_SHIFT)));
12233
Michael Chan9d57f012006-12-07 00:23:25 -080012234 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012235
12236 /* Enable seeprom accesses. */
12237 tw32_f(GRC_LOCAL_CTRL,
12238 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12239 udelay(100);
12240
12241 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12242 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12243 tp->tg3_flags |= TG3_FLAG_NVRAM;
12244
Michael Chanec41c7d2006-01-17 02:40:55 -080012245 if (tg3_nvram_lock(tp)) {
Matt Carlson5129c3a2010-04-05 10:19:23 +000012246 netdev_warn(tp->dev,
12247 "Cannot get nvram lock, %s failed\n",
Joe Perches05dbe002010-02-17 19:44:19 +000012248 __func__);
Michael Chanec41c7d2006-01-17 02:40:55 -080012249 return;
12250 }
Michael Chane6af3012005-04-21 17:12:05 -070012251 tg3_enable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012252
Matt Carlson989a9d22007-05-05 11:51:05 -070012253 tp->nvram_size = 0;
12254
Michael Chan361b4ac2005-04-21 17:11:21 -070012255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12256 tg3_get_5752_nvram_info(tp);
Michael Chand3c7b882006-03-23 01:28:25 -080012257 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12258 tg3_get_5755_nvram_info(tp);
Matt Carlsond30cdd22007-10-07 23:28:35 -070012259 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlson57e69832008-05-25 23:48:31 -070012260 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12261 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
Michael Chan1b277772006-03-20 22:27:48 -080012262 tg3_get_5787_nvram_info(tp);
Matt Carlson6b91fa02007-10-10 18:01:09 -070012263 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12264 tg3_get_5761_nvram_info(tp);
Michael Chanb5d37722006-09-27 16:06:21 -070012265 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12266 tg3_get_5906_nvram_info(tp);
Matt Carlsonb703df62009-12-03 08:36:21 +000012267 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12268 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson321d32a2008-11-21 17:22:19 -080012269 tg3_get_57780_nvram_info(tp);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012270 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12271 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlsona1b950d2009-09-01 13:20:17 +000012272 tg3_get_5717_nvram_info(tp);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012273 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12274 tg3_get_5720_nvram_info(tp);
Michael Chan361b4ac2005-04-21 17:11:21 -070012275 else
12276 tg3_get_nvram_info(tp);
12277
Matt Carlson989a9d22007-05-05 11:51:05 -070012278 if (tp->nvram_size == 0)
12279 tg3_get_nvram_size(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012280
Michael Chane6af3012005-04-21 17:12:05 -070012281 tg3_disable_nvram_access(tp);
Michael Chan381291b2005-12-13 21:08:21 -080012282 tg3_nvram_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012283
12284 } else {
12285 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
12286
12287 tg3_get_eeprom_size(tp);
12288 }
12289}
12290
Linus Torvalds1da177e2005-04-16 15:20:36 -070012291static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12292 u32 offset, u32 len, u8 *buf)
12293{
12294 int i, j, rc = 0;
12295 u32 val;
12296
12297 for (i = 0; i < len; i += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080012298 u32 addr;
Matt Carlsona9dc5292009-02-25 14:25:30 +000012299 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012300
12301 addr = offset + i;
12302
12303 memcpy(&data, buf + i, 4);
12304
Matt Carlson62cedd12009-04-20 14:52:29 -070012305 /*
12306 * The SEEPROM interface expects the data to always be opposite
12307 * the native endian format. We accomplish this by reversing
12308 * all the operations that would have been performed on the
12309 * data from a call to tg3_nvram_read_be32().
12310 */
12311 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
Linus Torvalds1da177e2005-04-16 15:20:36 -070012312
12313 val = tr32(GRC_EEPROM_ADDR);
12314 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12315
12316 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12317 EEPROM_ADDR_READ);
12318 tw32(GRC_EEPROM_ADDR, val |
12319 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12320 (addr & EEPROM_ADDR_ADDR_MASK) |
12321 EEPROM_ADDR_START |
12322 EEPROM_ADDR_WRITE);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040012323
Michael Chan9d57f012006-12-07 00:23:25 -080012324 for (j = 0; j < 1000; j++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012325 val = tr32(GRC_EEPROM_ADDR);
12326
12327 if (val & EEPROM_ADDR_COMPLETE)
12328 break;
Michael Chan9d57f012006-12-07 00:23:25 -080012329 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012330 }
12331 if (!(val & EEPROM_ADDR_COMPLETE)) {
12332 rc = -EBUSY;
12333 break;
12334 }
12335 }
12336
12337 return rc;
12338}
12339
12340/* offset and length are dword aligned */
12341static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12342 u8 *buf)
12343{
12344 int ret = 0;
12345 u32 pagesize = tp->nvram_pagesize;
12346 u32 pagemask = pagesize - 1;
12347 u32 nvram_cmd;
12348 u8 *tmp;
12349
12350 tmp = kmalloc(pagesize, GFP_KERNEL);
12351 if (tmp == NULL)
12352 return -ENOMEM;
12353
12354 while (len) {
12355 int j;
Michael Chane6af3012005-04-21 17:12:05 -070012356 u32 phy_addr, page_off, size;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012357
12358 phy_addr = offset & ~pagemask;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040012359
Linus Torvalds1da177e2005-04-16 15:20:36 -070012360 for (j = 0; j < pagesize; j += 4) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000012361 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12362 (__be32 *) (tmp + j));
12363 if (ret)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012364 break;
12365 }
12366 if (ret)
12367 break;
12368
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012369 page_off = offset & pagemask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012370 size = pagesize;
12371 if (len < size)
12372 size = len;
12373
12374 len -= size;
12375
12376 memcpy(tmp + page_off, buf, size);
12377
12378 offset = offset + (pagesize - page_off);
12379
Michael Chane6af3012005-04-21 17:12:05 -070012380 tg3_enable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012381
12382 /*
12383 * Before we can erase the flash page, we need
12384 * to issue a special "write enable" command.
12385 */
12386 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12387
12388 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12389 break;
12390
12391 /* Erase the target page */
12392 tw32(NVRAM_ADDR, phy_addr);
12393
12394 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12395 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12396
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012397 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012398 break;
12399
12400 /* Issue another write enable to start the write. */
12401 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12402
12403 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12404 break;
12405
12406 for (j = 0; j < pagesize; j += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080012407 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012408
Al Virob9fc7dc2007-12-17 22:59:57 -080012409 data = *((__be32 *) (tmp + j));
Matt Carlsona9dc5292009-02-25 14:25:30 +000012410
Al Virob9fc7dc2007-12-17 22:59:57 -080012411 tw32(NVRAM_WRDATA, be32_to_cpu(data));
Linus Torvalds1da177e2005-04-16 15:20:36 -070012412
12413 tw32(NVRAM_ADDR, phy_addr + j);
12414
12415 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12416 NVRAM_CMD_WR;
12417
12418 if (j == 0)
12419 nvram_cmd |= NVRAM_CMD_FIRST;
12420 else if (j == (pagesize - 4))
12421 nvram_cmd |= NVRAM_CMD_LAST;
12422
12423 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12424 break;
12425 }
12426 if (ret)
12427 break;
12428 }
12429
12430 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12431 tg3_nvram_exec_cmd(tp, nvram_cmd);
12432
12433 kfree(tmp);
12434
12435 return ret;
12436}
12437
12438/* offset and length are dword aligned */
12439static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12440 u8 *buf)
12441{
12442 int i, ret = 0;
12443
12444 for (i = 0; i < len; i += 4, offset += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080012445 u32 page_off, phy_addr, nvram_cmd;
12446 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012447
12448 memcpy(&data, buf + i, 4);
Al Virob9fc7dc2007-12-17 22:59:57 -080012449 tw32(NVRAM_WRDATA, be32_to_cpu(data));
Linus Torvalds1da177e2005-04-16 15:20:36 -070012450
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012451 page_off = offset % tp->nvram_pagesize;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012452
Michael Chan18201802006-03-20 22:29:15 -080012453 phy_addr = tg3_nvram_phys_addr(tp, offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012454
12455 tw32(NVRAM_ADDR, phy_addr);
12456
12457 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12458
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012459 if (page_off == 0 || i == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012460 nvram_cmd |= NVRAM_CMD_FIRST;
Michael Chanf6d9a252006-04-29 19:00:24 -070012461 if (page_off == (tp->nvram_pagesize - 4))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012462 nvram_cmd |= NVRAM_CMD_LAST;
12463
12464 if (i == (len - 4))
12465 nvram_cmd |= NVRAM_CMD_LAST;
12466
Matt Carlson321d32a2008-11-21 17:22:19 -080012467 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12468 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
Michael Chan4c987482005-09-05 17:52:38 -070012469 (tp->nvram_jedecnum == JEDEC_ST) &&
12470 (nvram_cmd & NVRAM_CMD_FIRST)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012471
12472 if ((ret = tg3_nvram_exec_cmd(tp,
12473 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12474 NVRAM_CMD_DONE)))
12475
12476 break;
12477 }
12478 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12479 /* We always do complete word writes to eeprom. */
12480 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12481 }
12482
12483 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12484 break;
12485 }
12486 return ret;
12487}
12488
12489/* offset and length are dword aligned */
12490static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12491{
12492 int ret;
12493
Linus Torvalds1da177e2005-04-16 15:20:36 -070012494 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
Michael Chan314fba32005-04-21 17:07:04 -070012495 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12496 ~GRC_LCLCTRL_GPIO_OUTPUT1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012497 udelay(40);
12498 }
12499
12500 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12501 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
Matt Carlson859a588792010-04-05 10:19:28 +000012502 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012503 u32 grc_mode;
12504
Michael Chanec41c7d2006-01-17 02:40:55 -080012505 ret = tg3_nvram_lock(tp);
12506 if (ret)
12507 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012508
Michael Chane6af3012005-04-21 17:12:05 -070012509 tg3_enable_nvram_access(tp);
12510 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
Matt Carlsonf66a29b2009-11-13 13:03:36 +000012511 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012512 tw32(NVRAM_WRITE1, 0x406);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012513
12514 grc_mode = tr32(GRC_MODE);
12515 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12516
12517 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12518 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12519
12520 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12521 buf);
Matt Carlson859a588792010-04-05 10:19:28 +000012522 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012523 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12524 buf);
12525 }
12526
12527 grc_mode = tr32(GRC_MODE);
12528 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12529
Michael Chane6af3012005-04-21 17:12:05 -070012530 tg3_disable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012531 tg3_nvram_unlock(tp);
12532 }
12533
12534 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
Michael Chan314fba32005-04-21 17:07:04 -070012535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012536 udelay(40);
12537 }
12538
12539 return ret;
12540}
12541
12542struct subsys_tbl_ent {
12543 u16 subsys_vendor, subsys_devid;
12544 u32 phy_id;
12545};
12546
Matt Carlson24daf2b2010-02-17 15:17:02 +000012547static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012548 /* Broadcom boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012549 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012550 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012551 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012552 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012553 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012554 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012555 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12556 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12557 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012558 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012559 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012560 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012561 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12562 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12563 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012564 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012565 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012566 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012567 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012568 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012569 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012570 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012571
12572 /* 3com boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012573 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012574 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012575 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012576 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012577 { TG3PCI_SUBVENDOR_ID_3COM,
12578 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12579 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012580 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012581 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012582 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012583
12584 /* DELL boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012585 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000012586 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012587 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000012588 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012589 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000012590 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012591 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000012592 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012593
12594 /* Compaq boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012595 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000012596 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012597 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000012598 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012599 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12600 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12601 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000012602 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012603 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000012604 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012605
12606 /* IBM boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012607 { TG3PCI_SUBVENDOR_ID_IBM,
12608 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070012609};
12610
Matt Carlson24daf2b2010-02-17 15:17:02 +000012611static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012612{
12613 int i;
12614
12615 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12616 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12617 tp->pdev->subsystem_vendor) &&
12618 (subsys_id_to_phy_id[i].subsys_devid ==
12619 tp->pdev->subsystem_device))
12620 return &subsys_id_to_phy_id[i];
12621 }
12622 return NULL;
12623}
12624
Michael Chan7d0c41e2005-04-21 17:06:20 -070012625static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012626{
Linus Torvalds1da177e2005-04-16 15:20:36 -070012627 u32 val;
Michael Chancaf636c72006-03-22 01:05:31 -080012628 u16 pmcsr;
12629
12630 /* On some early chips the SRAM cannot be accessed in D3hot state,
12631 * so need make sure we're in D0.
12632 */
12633 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12634 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12635 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12636 msleep(1);
Michael Chan7d0c41e2005-04-21 17:06:20 -070012637
12638 /* Make sure register accesses (indirect or otherwise)
12639 * will function correctly.
12640 */
12641 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12642 tp->misc_host_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012643
David S. Millerf49639e2006-06-09 11:58:36 -070012644 /* The memory arbiter has to be enabled in order for SRAM accesses
12645 * to succeed. Normally on powerup the tg3 chip firmware will make
12646 * sure it is enabled, but other entities such as system netboot
12647 * code might disable it.
12648 */
12649 val = tr32(MEMARB_MODE);
12650 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12651
Matt Carlson79eb6902010-02-17 15:17:03 +000012652 tp->phy_id = TG3_PHY_ID_INVALID;
Michael Chan7d0c41e2005-04-21 17:06:20 -070012653 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12654
Gary Zambranoa85feb82007-05-05 11:52:19 -070012655 /* Assume an onboard device and WOL capable by default. */
12656 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
David S. Miller72b845e2006-03-14 14:11:48 -080012657
Michael Chanb5d37722006-09-27 16:06:21 -070012658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan9d26e212006-12-07 00:21:14 -080012659 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
Michael Chanb5d37722006-09-27 16:06:21 -070012660 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
Michael Chan9d26e212006-12-07 00:21:14 -080012661 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12662 }
Matt Carlson0527ba32007-10-10 18:03:30 -070012663 val = tr32(VCPU_CFGSHDW);
12664 if (val & VCPU_CFGSHDW_ASPM_DBNC)
Matt Carlson8ed5d972007-05-07 00:25:49 -070012665 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
Matt Carlson0527ba32007-10-10 18:03:30 -070012666 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
Matt Carlson20232762008-12-21 20:18:56 -080012667 (val & VCPU_CFGSHDW_WOL_MAGPKT))
Matt Carlson0527ba32007-10-10 18:03:30 -070012668 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
Matt Carlson05ac4cb2008-11-03 16:53:46 -080012669 goto done;
Michael Chanb5d37722006-09-27 16:06:21 -070012670 }
12671
Linus Torvalds1da177e2005-04-16 15:20:36 -070012672 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12673 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12674 u32 nic_cfg, led_cfg;
Matt Carlsona9daf362008-05-25 23:49:44 -070012675 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
Michael Chan7d0c41e2005-04-21 17:06:20 -070012676 int eeprom_phy_serdes = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012677
12678 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12679 tp->nic_sram_data_cfg = nic_cfg;
12680
12681 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12682 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12683 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12684 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12685 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12686 (ver > 0) && (ver < 0x100))
12687 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12688
Matt Carlsona9daf362008-05-25 23:49:44 -070012689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12690 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12691
Linus Torvalds1da177e2005-04-16 15:20:36 -070012692 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12693 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12694 eeprom_phy_serdes = 1;
12695
12696 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12697 if (nic_phy_id != 0) {
12698 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12699 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12700
12701 eeprom_phy_id = (id1 >> 16) << 10;
12702 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12703 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12704 } else
12705 eeprom_phy_id = 0;
12706
Michael Chan7d0c41e2005-04-21 17:06:20 -070012707 tp->phy_id = eeprom_phy_id;
Michael Chan747e8f82005-07-25 12:33:22 -070012708 if (eeprom_phy_serdes) {
Matt Carlsona50d0792010-06-05 17:24:37 +000012709 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012710 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Matt Carlsona50d0792010-06-05 17:24:37 +000012711 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012712 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
Michael Chan747e8f82005-07-25 12:33:22 -070012713 }
Michael Chan7d0c41e2005-04-21 17:06:20 -070012714
John W. Linvillecbf46852005-04-21 17:01:29 -070012715 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012716 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12717 SHASTA_EXT_LED_MODE_MASK);
John W. Linvillecbf46852005-04-21 17:01:29 -070012718 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070012719 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12720
12721 switch (led_cfg) {
12722 default:
12723 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12724 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12725 break;
12726
12727 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12728 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12729 break;
12730
12731 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12732 tp->led_ctrl = LED_CTRL_MODE_MAC;
Michael Chan9ba27792005-06-06 15:16:20 -070012733
12734 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12735 * read on some older 5700/5701 bootcode.
12736 */
12737 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12738 ASIC_REV_5700 ||
12739 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12740 ASIC_REV_5701)
12741 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12742
Linus Torvalds1da177e2005-04-16 15:20:36 -070012743 break;
12744
12745 case SHASTA_EXT_LED_SHARED:
12746 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12747 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12748 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12749 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12750 LED_CTRL_MODE_PHY_2);
12751 break;
12752
12753 case SHASTA_EXT_LED_MAC:
12754 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12755 break;
12756
12757 case SHASTA_EXT_LED_COMBO:
12758 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12759 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12760 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12761 LED_CTRL_MODE_PHY_2);
12762 break;
12763
Stephen Hemminger855e1112008-04-16 16:37:28 -070012764 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070012765
12766 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12767 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12768 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12769 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12770
Matt Carlsonb2a5c192008-04-03 21:44:44 -070012771 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12772 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
Matt Carlson5f608912007-11-12 21:17:07 -080012773
Michael Chan9d26e212006-12-07 00:21:14 -080012774 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012775 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
Michael Chan9d26e212006-12-07 00:21:14 -080012776 if ((tp->pdev->subsystem_vendor ==
12777 PCI_VENDOR_ID_ARIMA) &&
12778 (tp->pdev->subsystem_device == 0x205a ||
12779 tp->pdev->subsystem_device == 0x2063))
12780 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12781 } else {
David S. Millerf49639e2006-06-09 11:58:36 -070012782 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
Michael Chan9d26e212006-12-07 00:21:14 -080012783 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12784 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070012785
12786 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12787 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
John W. Linvillecbf46852005-04-21 17:01:29 -070012788 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012789 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12790 }
Matt Carlsonb2b98d42008-11-03 16:52:32 -080012791
12792 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12793 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
Matt Carlson0d3031d2007-10-10 18:02:43 -070012794 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
Matt Carlsonb2b98d42008-11-03 16:52:32 -080012795
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012796 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
Gary Zambranoa85feb82007-05-05 11:52:19 -070012797 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12798 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012799
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070012800 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
Matt Carlson05ac4cb2008-11-03 16:53:46 -080012801 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
Matt Carlson0527ba32007-10-10 18:03:30 -070012802 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12803
Linus Torvalds1da177e2005-04-16 15:20:36 -070012804 if (cfg2 & (1 << 17))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012805 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012806
12807 /* serdes signal pre-emphasis in register 0x590 set by */
12808 /* bootcode if bit 18 is set */
12809 if (cfg2 & (1 << 18))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012810 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
Matt Carlson8ed5d972007-05-07 00:25:49 -070012811
Matt Carlson1407deb2011-04-05 14:22:44 +000012812 if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) ||
Matt Carlson2e1e3292010-11-24 08:31:53 +000012813 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12814 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
Matt Carlson6833c042008-11-21 17:18:59 -080012815 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012816 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
Matt Carlson6833c042008-11-21 17:18:59 -080012817
Matt Carlson8c69b1e2010-08-02 11:26:00 +000012818 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12819 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Matt Carlson1407deb2011-04-05 14:22:44 +000012820 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
Matt Carlson8ed5d972007-05-07 00:25:49 -070012821 u32 cfg3;
12822
12823 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12824 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12825 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12826 }
Matt Carlsona9daf362008-05-25 23:49:44 -070012827
Matt Carlson14417062010-02-17 15:16:59 +000012828 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12829 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
Matt Carlsona9daf362008-05-25 23:49:44 -070012830 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12831 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12832 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12833 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012834 }
Matt Carlson05ac4cb2008-11-03 16:53:46 -080012835done:
Rafael J. Wysocki43067ed2011-02-10 06:53:09 +000012836 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
12837 device_set_wakeup_enable(&tp->pdev->dev,
Matt Carlson05ac4cb2008-11-03 16:53:46 -080012838 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
Rafael J. Wysocki43067ed2011-02-10 06:53:09 +000012839 else
12840 device_set_wakeup_capable(&tp->pdev->dev, false);
Michael Chan7d0c41e2005-04-21 17:06:20 -070012841}
12842
Matt Carlsonb2a5c192008-04-03 21:44:44 -070012843static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12844{
12845 int i;
12846 u32 val;
12847
12848 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12849 tw32(OTP_CTRL, cmd);
12850
12851 /* Wait for up to 1 ms for command to execute. */
12852 for (i = 0; i < 100; i++) {
12853 val = tr32(OTP_STATUS);
12854 if (val & OTP_STATUS_CMD_DONE)
12855 break;
12856 udelay(10);
12857 }
12858
12859 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12860}
12861
12862/* Read the gphy configuration from the OTP region of the chip. The gphy
12863 * configuration is a 32-bit value that straddles the alignment boundary.
12864 * We do two 32-bit reads and then shift and merge the results.
12865 */
12866static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12867{
12868 u32 bhalf_otp, thalf_otp;
12869
12870 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12871
12872 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12873 return 0;
12874
12875 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12876
12877 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12878 return 0;
12879
12880 thalf_otp = tr32(OTP_READ_DATA);
12881
12882 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12883
12884 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12885 return 0;
12886
12887 bhalf_otp = tr32(OTP_READ_DATA);
12888
12889 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12890}
12891
Matt Carlsone256f8a2011-03-09 16:58:24 +000012892static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12893{
12894 u32 adv = ADVERTISED_Autoneg |
12895 ADVERTISED_Pause;
12896
12897 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12898 adv |= ADVERTISED_1000baseT_Half |
12899 ADVERTISED_1000baseT_Full;
12900
12901 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12902 adv |= ADVERTISED_100baseT_Half |
12903 ADVERTISED_100baseT_Full |
12904 ADVERTISED_10baseT_Half |
12905 ADVERTISED_10baseT_Full |
12906 ADVERTISED_TP;
12907 else
12908 adv |= ADVERTISED_FIBRE;
12909
12910 tp->link_config.advertising = adv;
12911 tp->link_config.speed = SPEED_INVALID;
12912 tp->link_config.duplex = DUPLEX_INVALID;
12913 tp->link_config.autoneg = AUTONEG_ENABLE;
12914 tp->link_config.active_speed = SPEED_INVALID;
12915 tp->link_config.active_duplex = DUPLEX_INVALID;
12916 tp->link_config.orig_speed = SPEED_INVALID;
12917 tp->link_config.orig_duplex = DUPLEX_INVALID;
12918 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12919}
12920
Michael Chan7d0c41e2005-04-21 17:06:20 -070012921static int __devinit tg3_phy_probe(struct tg3 *tp)
12922{
12923 u32 hw_phy_id_1, hw_phy_id_2;
12924 u32 hw_phy_id, hw_phy_id_masked;
12925 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012926
Matt Carlsone256f8a2011-03-09 16:58:24 +000012927 /* flow control autonegotiation is default behavior */
12928 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12929 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12930
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070012931 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12932 return tg3_phy_init(tp);
12933
Linus Torvalds1da177e2005-04-16 15:20:36 -070012934 /* Reading the PHY ID register can conflict with ASF
Nick Andrew877d0312009-01-26 11:06:57 +010012935 * firmware access to the PHY hardware.
Linus Torvalds1da177e2005-04-16 15:20:36 -070012936 */
12937 err = 0;
Matt Carlson0d3031d2007-10-10 18:02:43 -070012938 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12939 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
Matt Carlson79eb6902010-02-17 15:17:03 +000012940 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012941 } else {
12942 /* Now read the physical PHY_ID from the chip and verify
12943 * that it is sane. If it doesn't look good, we fall back
12944 * to either the hard-coded table based PHY_ID and failing
12945 * that the value found in the eeprom area.
12946 */
12947 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12948 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12949
12950 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12951 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12952 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12953
Matt Carlson79eb6902010-02-17 15:17:03 +000012954 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012955 }
12956
Matt Carlson79eb6902010-02-17 15:17:03 +000012957 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012958 tp->phy_id = hw_phy_id;
Matt Carlson79eb6902010-02-17 15:17:03 +000012959 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012960 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Michael Chanda6b2d02005-08-19 12:54:29 -070012961 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012962 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012963 } else {
Matt Carlson79eb6902010-02-17 15:17:03 +000012964 if (tp->phy_id != TG3_PHY_ID_INVALID) {
Michael Chan7d0c41e2005-04-21 17:06:20 -070012965 /* Do nothing, phy ID already set up in
12966 * tg3_get_eeprom_hw_cfg().
12967 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070012968 } else {
12969 struct subsys_tbl_ent *p;
12970
12971 /* No eeprom signature? Try the hardcoded
12972 * subsys device table.
12973 */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012974 p = tg3_lookup_by_subsys(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012975 if (!p)
12976 return -ENODEV;
12977
12978 tp->phy_id = p->phy_id;
12979 if (!tp->phy_id ||
Matt Carlson79eb6902010-02-17 15:17:03 +000012980 tp->phy_id == TG3_PHY_ID_BCM8002)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012981 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012982 }
12983 }
12984
Matt Carlsona6b68da2010-12-06 08:28:52 +000012985 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12986 ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12987 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12988 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12989 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
Matt Carlson52b02d02010-10-14 10:37:41 +000012990 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12991
Matt Carlsone256f8a2011-03-09 16:58:24 +000012992 tg3_phy_init_link_config(tp);
12993
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012994 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
Matt Carlson0d3031d2007-10-10 18:02:43 -070012995 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070012996 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
Michael Chan3600d912006-12-07 00:21:48 -080012997 u32 bmsr, adv_reg, tg3_ctrl, mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012998
12999 tg3_readphy(tp, MII_BMSR, &bmsr);
13000 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13001 (bmsr & BMSR_LSTATUS))
13002 goto skip_phy_reset;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040013003
Linus Torvalds1da177e2005-04-16 15:20:36 -070013004 err = tg3_phy_reset(tp);
13005 if (err)
13006 return err;
13007
13008 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
13009 ADVERTISE_100HALF | ADVERTISE_100FULL |
13010 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
13011 tg3_ctrl = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013012 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013013 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
13014 MII_TG3_CTRL_ADV_1000_FULL);
13015 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13016 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
13017 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
13018 MII_TG3_CTRL_ENABLE_AS_MASTER);
13019 }
13020
Michael Chan3600d912006-12-07 00:21:48 -080013021 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13022 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13023 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
13024 if (!tg3_copper_is_advertising_all(tp, mask)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013025 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
13026
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013027 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Linus Torvalds1da177e2005-04-16 15:20:36 -070013028 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
13029
13030 tg3_writephy(tp, MII_BMCR,
13031 BMCR_ANENABLE | BMCR_ANRESTART);
13032 }
13033 tg3_phy_set_wirespeed(tp);
13034
13035 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013036 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Linus Torvalds1da177e2005-04-16 15:20:36 -070013037 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
13038 }
13039
13040skip_phy_reset:
Matt Carlson79eb6902010-02-17 15:17:03 +000013041 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013042 err = tg3_init_5401phy_dsp(tp);
13043 if (err)
13044 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013045
Linus Torvalds1da177e2005-04-16 15:20:36 -070013046 err = tg3_init_5401phy_dsp(tp);
13047 }
13048
Linus Torvalds1da177e2005-04-16 15:20:36 -070013049 return err;
13050}
13051
Matt Carlson184b8902010-04-05 10:19:25 +000013052static void __devinit tg3_read_vpd(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013053{
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013054 u8 *vpd_data;
Matt Carlson4181b2c2010-02-26 14:04:45 +000013055 unsigned int block_end, rosize, len;
Matt Carlson184b8902010-04-05 10:19:25 +000013056 int j, i = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013057
Matt Carlsonc3e94502011-04-13 11:05:08 +000013058 vpd_data = (u8 *)tg3_vpd_readblock(tp);
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013059 if (!vpd_data)
13060 goto out_no_vpd;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013061
Matt Carlson4181b2c2010-02-26 14:04:45 +000013062 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
13063 PCI_VPD_LRDT_RO_DATA);
13064 if (i < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013065 goto out_not_found;
Matt Carlson4181b2c2010-02-26 14:04:45 +000013066
13067 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13068 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13069 i += PCI_VPD_LRDT_TAG_SIZE;
13070
13071 if (block_end > TG3_NVM_VPD_LEN)
13072 goto out_not_found;
13073
Matt Carlson184b8902010-04-05 10:19:25 +000013074 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13075 PCI_VPD_RO_KEYWORD_MFR_ID);
13076 if (j > 0) {
13077 len = pci_vpd_info_field_size(&vpd_data[j]);
13078
13079 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13080 if (j + len > block_end || len != 4 ||
13081 memcmp(&vpd_data[j], "1028", 4))
13082 goto partno;
13083
13084 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13085 PCI_VPD_RO_KEYWORD_VENDOR0);
13086 if (j < 0)
13087 goto partno;
13088
13089 len = pci_vpd_info_field_size(&vpd_data[j]);
13090
13091 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13092 if (j + len > block_end)
13093 goto partno;
13094
13095 memcpy(tp->fw_ver, &vpd_data[j], len);
13096 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
13097 }
13098
13099partno:
Matt Carlson4181b2c2010-02-26 14:04:45 +000013100 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13101 PCI_VPD_RO_KEYWORD_PARTNO);
13102 if (i < 0)
13103 goto out_not_found;
13104
13105 len = pci_vpd_info_field_size(&vpd_data[i]);
13106
13107 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13108 if (len > TG3_BPN_SIZE ||
13109 (len + i) > TG3_NVM_VPD_LEN)
13110 goto out_not_found;
13111
13112 memcpy(tp->board_part_number, &vpd_data[i], len);
13113
Linus Torvalds1da177e2005-04-16 15:20:36 -070013114out_not_found:
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013115 kfree(vpd_data);
Matt Carlson37a949c2010-09-30 10:34:33 +000013116 if (tp->board_part_number[0])
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013117 return;
13118
13119out_no_vpd:
Matt Carlson37a949c2010-09-30 10:34:33 +000013120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13121 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13122 strcpy(tp->board_part_number, "BCM5717");
13123 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13124 strcpy(tp->board_part_number, "BCM5718");
13125 else
13126 goto nomatch;
13127 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13128 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13129 strcpy(tp->board_part_number, "BCM57780");
13130 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13131 strcpy(tp->board_part_number, "BCM57760");
13132 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13133 strcpy(tp->board_part_number, "BCM57790");
13134 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13135 strcpy(tp->board_part_number, "BCM57788");
13136 else
13137 goto nomatch;
13138 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13139 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13140 strcpy(tp->board_part_number, "BCM57761");
13141 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13142 strcpy(tp->board_part_number, "BCM57765");
13143 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13144 strcpy(tp->board_part_number, "BCM57781");
13145 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13146 strcpy(tp->board_part_number, "BCM57785");
13147 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13148 strcpy(tp->board_part_number, "BCM57791");
13149 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13150 strcpy(tp->board_part_number, "BCM57795");
13151 else
13152 goto nomatch;
13153 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chanb5d37722006-09-27 16:06:21 -070013154 strcpy(tp->board_part_number, "BCM95906");
Matt Carlson37a949c2010-09-30 10:34:33 +000013155 } else {
13156nomatch:
Michael Chanb5d37722006-09-27 16:06:21 -070013157 strcpy(tp->board_part_number, "none");
Matt Carlson37a949c2010-09-30 10:34:33 +000013158 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013159}
13160
Matt Carlson9c8a6202007-10-21 16:16:08 -070013161static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13162{
13163 u32 val;
13164
Matt Carlsone4f34112009-02-25 14:25:00 +000013165 if (tg3_nvram_read(tp, offset, &val) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070013166 (val & 0xfc000000) != 0x0c000000 ||
Matt Carlsone4f34112009-02-25 14:25:00 +000013167 tg3_nvram_read(tp, offset + 4, &val) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070013168 val != 0)
13169 return 0;
13170
13171 return 1;
13172}
13173
Matt Carlsonacd9c112009-02-25 14:26:33 +000013174static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13175{
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013176 u32 val, offset, start, ver_offset;
Matt Carlson75f99362010-04-05 10:19:24 +000013177 int i, dst_off;
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013178 bool newver = false;
Matt Carlsonacd9c112009-02-25 14:26:33 +000013179
13180 if (tg3_nvram_read(tp, 0xc, &offset) ||
13181 tg3_nvram_read(tp, 0x4, &start))
13182 return;
13183
13184 offset = tg3_nvram_logical_addr(tp, offset);
13185
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013186 if (tg3_nvram_read(tp, offset, &val))
Matt Carlsonacd9c112009-02-25 14:26:33 +000013187 return;
13188
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013189 if ((val & 0xfc000000) == 0x0c000000) {
13190 if (tg3_nvram_read(tp, offset + 4, &val))
Matt Carlsonacd9c112009-02-25 14:26:33 +000013191 return;
13192
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013193 if (val == 0)
13194 newver = true;
13195 }
13196
Matt Carlson75f99362010-04-05 10:19:24 +000013197 dst_off = strlen(tp->fw_ver);
13198
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013199 if (newver) {
Matt Carlson75f99362010-04-05 10:19:24 +000013200 if (TG3_VER_SIZE - dst_off < 16 ||
13201 tg3_nvram_read(tp, offset + 8, &ver_offset))
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013202 return;
13203
13204 offset = offset + ver_offset - start;
13205 for (i = 0; i < 16; i += 4) {
13206 __be32 v;
13207 if (tg3_nvram_read_be32(tp, offset + i, &v))
13208 return;
13209
Matt Carlson75f99362010-04-05 10:19:24 +000013210 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013211 }
13212 } else {
13213 u32 major, minor;
13214
13215 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13216 return;
13217
13218 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13219 TG3_NVM_BCVER_MAJSFT;
13220 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
Matt Carlson75f99362010-04-05 10:19:24 +000013221 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13222 "v%d.%02d", major, minor);
Matt Carlsonacd9c112009-02-25 14:26:33 +000013223 }
13224}
13225
Matt Carlsona6f6cb12009-02-25 14:27:43 +000013226static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13227{
13228 u32 val, major, minor;
13229
13230 /* Use native endian representation */
13231 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13232 return;
13233
13234 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13235 TG3_NVM_HWSB_CFG1_MAJSFT;
13236 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13237 TG3_NVM_HWSB_CFG1_MINSFT;
13238
13239 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13240}
13241
Matt Carlsondfe00d72008-11-21 17:19:41 -080013242static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13243{
13244 u32 offset, major, minor, build;
13245
Matt Carlson75f99362010-04-05 10:19:24 +000013246 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
Matt Carlsondfe00d72008-11-21 17:19:41 -080013247
13248 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13249 return;
13250
13251 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13252 case TG3_EEPROM_SB_REVISION_0:
13253 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13254 break;
13255 case TG3_EEPROM_SB_REVISION_2:
13256 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13257 break;
13258 case TG3_EEPROM_SB_REVISION_3:
13259 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13260 break;
Matt Carlsona4153d42010-02-17 15:16:56 +000013261 case TG3_EEPROM_SB_REVISION_4:
13262 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13263 break;
13264 case TG3_EEPROM_SB_REVISION_5:
13265 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13266 break;
Matt Carlsonbba226a2010-10-14 10:37:38 +000013267 case TG3_EEPROM_SB_REVISION_6:
13268 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13269 break;
Matt Carlsondfe00d72008-11-21 17:19:41 -080013270 default:
13271 return;
13272 }
13273
Matt Carlsone4f34112009-02-25 14:25:00 +000013274 if (tg3_nvram_read(tp, offset, &val))
Matt Carlsondfe00d72008-11-21 17:19:41 -080013275 return;
13276
13277 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13278 TG3_EEPROM_SB_EDH_BLD_SHFT;
13279 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13280 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13281 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13282
13283 if (minor > 99 || build > 26)
13284 return;
13285
Matt Carlson75f99362010-04-05 10:19:24 +000013286 offset = strlen(tp->fw_ver);
13287 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13288 " v%d.%02d", major, minor);
Matt Carlsondfe00d72008-11-21 17:19:41 -080013289
13290 if (build > 0) {
Matt Carlson75f99362010-04-05 10:19:24 +000013291 offset = strlen(tp->fw_ver);
13292 if (offset < TG3_VER_SIZE - 1)
13293 tp->fw_ver[offset] = 'a' + build - 1;
Matt Carlsondfe00d72008-11-21 17:19:41 -080013294 }
13295}
13296
Matt Carlsonacd9c112009-02-25 14:26:33 +000013297static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
Michael Chanc4e65752006-03-20 22:29:32 -080013298{
13299 u32 val, offset, start;
Matt Carlsonacd9c112009-02-25 14:26:33 +000013300 int i, vlen;
Matt Carlson9c8a6202007-10-21 16:16:08 -070013301
13302 for (offset = TG3_NVM_DIR_START;
13303 offset < TG3_NVM_DIR_END;
13304 offset += TG3_NVM_DIRENT_SIZE) {
Matt Carlsone4f34112009-02-25 14:25:00 +000013305 if (tg3_nvram_read(tp, offset, &val))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013306 return;
13307
13308 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13309 break;
13310 }
13311
13312 if (offset == TG3_NVM_DIR_END)
13313 return;
13314
13315 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
13316 start = 0x08000000;
Matt Carlsone4f34112009-02-25 14:25:00 +000013317 else if (tg3_nvram_read(tp, offset - 4, &start))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013318 return;
13319
Matt Carlsone4f34112009-02-25 14:25:00 +000013320 if (tg3_nvram_read(tp, offset + 4, &offset) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070013321 !tg3_fw_img_is_valid(tp, offset) ||
Matt Carlsone4f34112009-02-25 14:25:00 +000013322 tg3_nvram_read(tp, offset + 8, &val))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013323 return;
13324
13325 offset += val - start;
13326
Matt Carlsonacd9c112009-02-25 14:26:33 +000013327 vlen = strlen(tp->fw_ver);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013328
Matt Carlsonacd9c112009-02-25 14:26:33 +000013329 tp->fw_ver[vlen++] = ',';
13330 tp->fw_ver[vlen++] = ' ';
Matt Carlson9c8a6202007-10-21 16:16:08 -070013331
13332 for (i = 0; i < 4; i++) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000013333 __be32 v;
13334 if (tg3_nvram_read_be32(tp, offset, &v))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013335 return;
13336
Al Virob9fc7dc2007-12-17 22:59:57 -080013337 offset += sizeof(v);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013338
Matt Carlsonacd9c112009-02-25 14:26:33 +000013339 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13340 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013341 break;
13342 }
13343
Matt Carlsonacd9c112009-02-25 14:26:33 +000013344 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13345 vlen += sizeof(v);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013346 }
Matt Carlsonacd9c112009-02-25 14:26:33 +000013347}
13348
Matt Carlson7fd76442009-02-25 14:27:20 +000013349static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13350{
13351 int vlen;
13352 u32 apedata;
Matt Carlsonecc79642010-08-02 11:26:01 +000013353 char *fwtype;
Matt Carlson7fd76442009-02-25 14:27:20 +000013354
13355 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13356 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
13357 return;
13358
13359 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13360 if (apedata != APE_SEG_SIG_MAGIC)
13361 return;
13362
13363 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13364 if (!(apedata & APE_FW_STATUS_READY))
13365 return;
13366
13367 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13368
Matt Carlsondc6d0742010-09-15 08:59:55 +000013369 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13370 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
Matt Carlsonecc79642010-08-02 11:26:01 +000013371 fwtype = "NCSI";
Matt Carlsondc6d0742010-09-15 08:59:55 +000013372 } else {
Matt Carlsonecc79642010-08-02 11:26:01 +000013373 fwtype = "DASH";
Matt Carlsondc6d0742010-09-15 08:59:55 +000013374 }
Matt Carlsonecc79642010-08-02 11:26:01 +000013375
Matt Carlson7fd76442009-02-25 14:27:20 +000013376 vlen = strlen(tp->fw_ver);
13377
Matt Carlsonecc79642010-08-02 11:26:01 +000013378 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13379 fwtype,
Matt Carlson7fd76442009-02-25 14:27:20 +000013380 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13381 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13382 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13383 (apedata & APE_FW_VERSION_BLDMSK));
13384}
13385
Matt Carlsonacd9c112009-02-25 14:26:33 +000013386static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13387{
13388 u32 val;
Matt Carlson75f99362010-04-05 10:19:24 +000013389 bool vpd_vers = false;
13390
13391 if (tp->fw_ver[0] != 0)
13392 vpd_vers = true;
Matt Carlsonacd9c112009-02-25 14:26:33 +000013393
Matt Carlsondf259d82009-04-20 06:57:14 +000013394 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
Matt Carlson75f99362010-04-05 10:19:24 +000013395 strcat(tp->fw_ver, "sb");
Matt Carlsondf259d82009-04-20 06:57:14 +000013396 return;
13397 }
13398
Matt Carlsonacd9c112009-02-25 14:26:33 +000013399 if (tg3_nvram_read(tp, 0, &val))
13400 return;
13401
13402 if (val == TG3_EEPROM_MAGIC)
13403 tg3_read_bc_ver(tp);
13404 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13405 tg3_read_sb_ver(tp, val);
Matt Carlsona6f6cb12009-02-25 14:27:43 +000013406 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13407 tg3_read_hwsb_ver(tp);
Matt Carlsonacd9c112009-02-25 14:26:33 +000013408 else
13409 return;
13410
13411 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
Matt Carlson75f99362010-04-05 10:19:24 +000013412 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13413 goto done;
Matt Carlsonacd9c112009-02-25 14:26:33 +000013414
13415 tg3_read_mgmtfw_ver(tp);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013416
Matt Carlson75f99362010-04-05 10:19:24 +000013417done:
Matt Carlson9c8a6202007-10-21 16:16:08 -070013418 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
Michael Chanc4e65752006-03-20 22:29:32 -080013419}
13420
Michael Chan7544b092007-05-05 13:08:32 -070013421static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13422
Matt Carlson7cb32cf2010-09-30 10:34:36 +000013423static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13424{
Matt Carlsonde9f5232011-04-05 14:22:43 +000013425 if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
13426 return TG3_RX_RET_MAX_SIZE_5717;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000013427 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13428 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
Matt Carlsonde9f5232011-04-05 14:22:43 +000013429 return TG3_RX_RET_MAX_SIZE_5700;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000013430 else
Matt Carlsonde9f5232011-04-05 14:22:43 +000013431 return TG3_RX_RET_MAX_SIZE_5705;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000013432}
13433
Matt Carlson41434702011-03-09 16:58:22 +000013434static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
Joe Perches895950c2010-12-21 02:16:08 -080013435 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13436 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13437 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13438 { },
13439};
13440
Linus Torvalds1da177e2005-04-16 15:20:36 -070013441static int __devinit tg3_get_invariants(struct tg3 *tp)
13442{
Linus Torvalds1da177e2005-04-16 15:20:36 -070013443 u32 misc_ctrl_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013444 u32 pci_state_reg, grc_misc_cfg;
13445 u32 val;
13446 u16 pci_cmd;
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013447 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013448
Linus Torvalds1da177e2005-04-16 15:20:36 -070013449 /* Force memory write invalidate off. If we leave it on,
13450 * then on 5700_BX chips we have to enable a workaround.
13451 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13452 * to match the cacheline size. The Broadcom driver have this
13453 * workaround but turns MWI off all the times so never uses
13454 * it. This seems to suggest that the workaround is insufficient.
13455 */
13456 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13457 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13458 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13459
13460 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13461 * has the register indirect write enable bit set before
13462 * we try to access any of the MMIO registers. It is also
13463 * critical that the PCI-X hw workaround situation is decided
13464 * before that as well.
13465 */
13466 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13467 &misc_ctrl_reg);
13468
13469 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13470 MISC_HOST_CTRL_CHIPREV_SHIFT);
Matt Carlson795d01c2007-10-07 23:28:17 -070013471 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13472 u32 prod_id_asic_rev;
13473
Matt Carlson5001e2f2009-11-13 13:03:51 +000013474 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13475 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
Matt Carlsond78b59f2011-04-05 14:22:46 +000013476 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13477 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013478 pci_read_config_dword(tp->pdev,
13479 TG3PCI_GEN2_PRODID_ASICREV,
13480 &prod_id_asic_rev);
Matt Carlsonb703df62009-12-03 08:36:21 +000013481 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13482 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13483 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13484 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13485 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13486 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13487 pci_read_config_dword(tp->pdev,
13488 TG3PCI_GEN15_PRODID_ASICREV,
13489 &prod_id_asic_rev);
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013490 else
13491 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13492 &prod_id_asic_rev);
13493
Matt Carlson321d32a2008-11-21 17:22:19 -080013494 tp->pci_chip_rev_id = prod_id_asic_rev;
Matt Carlson795d01c2007-10-07 23:28:17 -070013495 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013496
Michael Chanff645be2005-04-21 17:09:53 -070013497 /* Wrong chip ID in 5752 A0. This code can be removed later
13498 * as A0 is not in production.
13499 */
13500 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13501 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13502
Michael Chan68929142005-08-09 20:17:14 -070013503 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13504 * we need to disable memory and use config. cycles
13505 * only to access all registers. The 5702/03 chips
13506 * can mistakenly decode the special cycles from the
13507 * ICH chipsets as memory write cycles, causing corruption
13508 * of register and memory space. Only certain ICH bridges
13509 * will drive special cycles with non-zero data during the
13510 * address phase which can fall within the 5703's address
13511 * range. This is not an ICH bug as the PCI spec allows
13512 * non-zero address during special cycles. However, only
13513 * these ICH bridges are known to drive non-zero addresses
13514 * during special cycles.
13515 *
13516 * Since special cycles do not cross PCI bridges, we only
13517 * enable this workaround if the 5703 is on the secondary
13518 * bus of these ICH bridges.
13519 */
13520 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13521 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13522 static struct tg3_dev_id {
13523 u32 vendor;
13524 u32 device;
13525 u32 rev;
13526 } ich_chipsets[] = {
13527 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13528 PCI_ANY_ID },
13529 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13530 PCI_ANY_ID },
13531 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13532 0xa },
13533 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13534 PCI_ANY_ID },
13535 { },
13536 };
13537 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13538 struct pci_dev *bridge = NULL;
13539
13540 while (pci_id->vendor != 0) {
13541 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13542 bridge);
13543 if (!bridge) {
13544 pci_id++;
13545 continue;
13546 }
13547 if (pci_id->rev != PCI_ANY_ID) {
Auke Kok44c10132007-06-08 15:46:36 -070013548 if (bridge->revision > pci_id->rev)
Michael Chan68929142005-08-09 20:17:14 -070013549 continue;
13550 }
13551 if (bridge->subordinate &&
13552 (bridge->subordinate->number ==
13553 tp->pdev->bus->number)) {
13554
13555 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13556 pci_dev_put(bridge);
13557 break;
13558 }
13559 }
13560 }
13561
Matt Carlson41588ba2008-04-19 18:12:33 -070013562 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13563 static struct tg3_dev_id {
13564 u32 vendor;
13565 u32 device;
13566 } bridge_chipsets[] = {
13567 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13568 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13569 { },
13570 };
13571 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13572 struct pci_dev *bridge = NULL;
13573
13574 while (pci_id->vendor != 0) {
13575 bridge = pci_get_device(pci_id->vendor,
13576 pci_id->device,
13577 bridge);
13578 if (!bridge) {
13579 pci_id++;
13580 continue;
13581 }
13582 if (bridge->subordinate &&
13583 (bridge->subordinate->number <=
13584 tp->pdev->bus->number) &&
13585 (bridge->subordinate->subordinate >=
13586 tp->pdev->bus->number)) {
13587 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13588 pci_dev_put(bridge);
13589 break;
13590 }
13591 }
13592 }
13593
Michael Chan4a29cc22006-03-19 13:21:12 -080013594 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13595 * DMA addresses > 40-bit. This bridge may have other additional
13596 * 57xx devices behind it in some 4-port NIC designs for example.
13597 * Any tg3 device found behind the bridge will also need the 40-bit
13598 * DMA workaround.
13599 */
Michael Chana4e2b342005-10-26 15:46:52 -070013600 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13601 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13602 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
Michael Chan4a29cc22006-03-19 13:21:12 -080013603 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
Michael Chan4cf78e42005-07-25 12:29:19 -070013604 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
Matt Carlson859a588792010-04-05 10:19:28 +000013605 } else {
Michael Chan4a29cc22006-03-19 13:21:12 -080013606 struct pci_dev *bridge = NULL;
13607
13608 do {
13609 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13610 PCI_DEVICE_ID_SERVERWORKS_EPB,
13611 bridge);
13612 if (bridge && bridge->subordinate &&
13613 (bridge->subordinate->number <=
13614 tp->pdev->bus->number) &&
13615 (bridge->subordinate->subordinate >=
13616 tp->pdev->bus->number)) {
13617 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13618 pci_dev_put(bridge);
13619 break;
13620 }
13621 } while (bridge);
13622 }
Michael Chan4cf78e42005-07-25 12:29:19 -070013623
Linus Torvalds1da177e2005-04-16 15:20:36 -070013624 /* Initialize misc host control in PCI block. */
13625 tp->misc_host_ctrl |= (misc_ctrl_reg &
13626 MISC_HOST_CTRL_CHIPREV);
13627 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13628 tp->misc_host_ctrl);
13629
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
Matt Carlsond78b59f2011-04-05 14:22:46 +000013632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13633 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
Michael Chan7544b092007-05-05 13:08:32 -070013634 tp->pdev_peer = tg3_find_peer(tp);
13635
Matt Carlsonc885e822010-08-02 11:25:57 +000013636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
Matt Carlsond78b59f2011-04-05 14:22:46 +000013637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
Matt Carlson0a58d662011-04-05 14:22:45 +000013639 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13640
13641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13642 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
Matt Carlson1407deb2011-04-05 14:22:44 +000013643 tp->tg3_flags3 |= TG3_FLG3_57765_PLUS;
Matt Carlsonc885e822010-08-02 11:25:57 +000013644
Matt Carlson321d32a2008-11-21 17:22:19 -080013645 /* Intentionally exclude ASIC_REV_5906 */
13646 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Michael Chand9ab5ad12006-03-20 22:27:35 -080013647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlsond30cdd22007-10-07 23:28:35 -070013648 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson9936bcf2007-10-10 18:03:07 -070013649 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson57e69832008-05-25 23:48:31 -070013650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Matt Carlson1407deb2011-04-05 14:22:44 +000013652 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
Matt Carlson321d32a2008-11-21 17:22:19 -080013653 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13654
13655 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13656 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
Michael Chanb5d37722006-09-27 16:06:21 -070013657 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080013658 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
Michael Chana4e2b342005-10-26 15:46:52 -070013659 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
John W. Linville6708e5c2005-04-21 17:00:52 -070013660 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13661
Matt Carlsoneb07a942011-04-20 07:57:36 +000013662
John W. Linville1b440c562005-04-21 17:03:18 -070013663 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13664 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13665 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13666
Matt Carlson027455a2008-12-21 20:19:30 -080013667 /* 5700 B0 chips do not support checksumming correctly due
13668 * to hardware bugs.
13669 */
Michał Mirosławdc668912011-04-07 03:35:07 +000013670 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
13671 u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
Eric Dumazet7fe876a2010-07-08 06:14:55 +000013672
Matt Carlson027455a2008-12-21 20:19:30 -080013673 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Eric Dumazet7fe876a2010-07-08 06:14:55 +000013674 features |= NETIF_F_IPV6_CSUM;
13675 tp->dev->features |= features;
Michał Mirosławdc668912011-04-07 03:35:07 +000013676 tp->dev->hw_features |= features;
13677 tp->dev->vlan_features |= features;
Matt Carlson027455a2008-12-21 20:19:30 -080013678 }
13679
Matt Carlson507399f2009-11-13 13:03:37 +000013680 /* Determine TSO capabilities */
Matt Carlson2866d952011-02-10 20:06:46 -080013681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlson4d163b72011-01-25 15:58:48 +000013682 ; /* Do nothing. HW bug. */
Matt Carlson1407deb2011-04-05 14:22:44 +000013683 else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
Matt Carlsone849cdc2009-11-13 13:03:38 +000013684 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13685 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13686 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Matt Carlson507399f2009-11-13 13:03:37 +000013687 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13688 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13689 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13691 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13692 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13693 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13694 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13695 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13696 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13697 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13698 tp->fw_needed = FIRMWARE_TG3TSO5;
13699 else
13700 tp->fw_needed = FIRMWARE_TG3TSO;
13701 }
13702
13703 tp->irq_max = 1;
13704
Michael Chan5a6f3072006-03-20 22:28:05 -080013705 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
Michael Chan7544b092007-05-05 13:08:32 -070013706 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13707 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13708 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13709 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13710 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13711 tp->pdev_peer == tp->pdev))
13712 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13713
Matt Carlson321d32a2008-11-21 17:22:19 -080013714 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
Michael Chanb5d37722006-09-27 16:06:21 -070013715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chanfcfa0a32006-03-20 22:28:41 -080013716 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
Michael Chan52c0fd82006-06-29 20:15:54 -070013717 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013718
Matt Carlson1407deb2011-04-05 14:22:44 +000013719 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
Matt Carlson507399f2009-11-13 13:03:37 +000013720 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13721 tp->irq_max = TG3_IRQ_MAX_VECS;
13722 }
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013723 }
Matt Carlson0e1406d2009-11-02 12:33:33 +000013724
Matt Carlson615774f2009-11-13 13:03:39 +000013725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
Matt Carlsona50d0792010-06-05 17:24:37 +000013726 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
Matt Carlson615774f2009-11-13 13:03:39 +000013727 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13728 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13729 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13730 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13731 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
Matt Carlson0e1406d2009-11-02 12:33:33 +000013732 }
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013733
Matt Carlson0a58d662011-04-05 14:22:45 +000013734 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
Matt Carlsonde9f5232011-04-05 14:22:43 +000013735 tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
13736
Matt Carlson1407deb2011-04-05 14:22:44 +000013737 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
Matt Carlson2866d952011-02-10 20:06:46 -080013738 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
Matt Carlsonb703df62009-12-03 08:36:21 +000013739 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13740
Matt Carlsonf51f3562008-05-25 23:45:08 -070013741 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
Matt Carlsonc6cdf432010-04-05 10:19:26 +000013742 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13743 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
Matt Carlson8f666b02009-08-28 13:58:24 +000013744 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
Michael Chan0f893dc2005-07-25 12:30:38 -070013745
Matt Carlson52f44902008-11-21 17:17:04 -080013746 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13747 &pci_state_reg);
13748
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013749 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13750 if (tp->pcie_cap != 0) {
13751 u16 lnkctl;
13752
Linus Torvalds1da177e2005-04-16 15:20:36 -070013753 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
Matt Carlson5f5c51e2007-11-12 21:19:37 -080013754
Matt Carlsoncf790032010-11-24 08:31:48 +000013755 tp->pcie_readrq = 4096;
Matt Carlsond78b59f2011-04-05 14:22:46 +000013756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13757 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
Matt Carlsonb4495ed2011-01-25 15:58:47 +000013758 tp->pcie_readrq = 2048;
Matt Carlsoncf790032010-11-24 08:31:48 +000013759
13760 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
Matt Carlson5f5c51e2007-11-12 21:19:37 -080013761
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013762 pci_read_config_word(tp->pdev,
13763 tp->pcie_cap + PCI_EXP_LNKCTL,
13764 &lnkctl);
13765 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13766 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Michael Chanc7835a72006-11-15 21:14:42 -080013767 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080013769 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson9cf74eb2009-04-20 06:58:27 +000013770 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13771 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013772 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
Matt Carlson614b0592010-01-20 16:58:02 +000013773 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13774 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
Michael Chanc7835a72006-11-15 21:14:42 -080013775 }
Matt Carlson52f44902008-11-21 17:17:04 -080013776 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
Matt Carlsonfcb389d2008-11-03 16:55:44 -080013777 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
Matt Carlson52f44902008-11-21 17:17:04 -080013778 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13779 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13780 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13781 if (!tp->pcix_cap) {
Matt Carlson2445e462010-04-05 10:19:21 +000013782 dev_err(&tp->pdev->dev,
13783 "Cannot find PCI-X capability, aborting\n");
Matt Carlson52f44902008-11-21 17:17:04 -080013784 return -EIO;
13785 }
13786
13787 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13788 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13789 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013790
Michael Chan399de502005-10-03 14:02:39 -070013791 /* If we have an AMD 762 or VIA K8T800 chipset, write
13792 * reordering to the mailbox registers done by the host
13793 * controller can cause major troubles. We read back from
13794 * every mailbox register write to force the writes to be
13795 * posted to the chip in order.
13796 */
Matt Carlson41434702011-03-09 16:58:22 +000013797 if (pci_dev_present(tg3_write_reorder_chipsets) &&
Michael Chan399de502005-10-03 14:02:39 -070013798 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13799 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13800
Matt Carlson69fc4052008-12-21 20:19:57 -080013801 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13802 &tp->pci_cacheline_sz);
13803 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13804 &tp->pci_lat_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13806 tp->pci_lat_timer < 64) {
13807 tp->pci_lat_timer = 64;
Matt Carlson69fc4052008-12-21 20:19:57 -080013808 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13809 tp->pci_lat_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013810 }
13811
Matt Carlson52f44902008-11-21 17:17:04 -080013812 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13813 /* 5700 BX chips need to have their TX producer index
13814 * mailboxes written twice to workaround a bug.
13815 */
13816 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
Matt Carlson9974a352007-10-07 23:27:28 -070013817
Matt Carlson52f44902008-11-21 17:17:04 -080013818 /* If we are in PCI-X mode, enable register write workaround.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013819 *
13820 * The workaround is to use indirect register accesses
13821 * for all chip writes not to mailbox registers.
13822 */
Matt Carlson52f44902008-11-21 17:17:04 -080013823 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013824 u32 pm_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013825
13826 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13827
13828 /* The chip can have it's power management PCI config
13829 * space registers clobbered due to this bug.
13830 * So explicitly force the chip into D0 here.
13831 */
Matt Carlson9974a352007-10-07 23:27:28 -070013832 pci_read_config_dword(tp->pdev,
13833 tp->pm_cap + PCI_PM_CTRL,
Linus Torvalds1da177e2005-04-16 15:20:36 -070013834 &pm_reg);
13835 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13836 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
Matt Carlson9974a352007-10-07 23:27:28 -070013837 pci_write_config_dword(tp->pdev,
13838 tp->pm_cap + PCI_PM_CTRL,
Linus Torvalds1da177e2005-04-16 15:20:36 -070013839 pm_reg);
13840
13841 /* Also, force SERR#/PERR# in PCI command. */
13842 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13843 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13844 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13845 }
13846 }
13847
Linus Torvalds1da177e2005-04-16 15:20:36 -070013848 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13849 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13850 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13851 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13852
13853 /* Chip-specific fixup from Broadcom driver */
13854 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13855 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13856 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13857 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13858 }
13859
Michael Chan1ee582d2005-08-09 20:16:46 -070013860 /* Default fast path register access methods */
Michael Chan20094932005-08-09 20:16:32 -070013861 tp->read32 = tg3_read32;
Michael Chan1ee582d2005-08-09 20:16:46 -070013862 tp->write32 = tg3_write32;
Michael Chan09ee9292005-08-09 20:17:00 -070013863 tp->read32_mbox = tg3_read32;
Michael Chan20094932005-08-09 20:16:32 -070013864 tp->write32_mbox = tg3_write32;
Michael Chan1ee582d2005-08-09 20:16:46 -070013865 tp->write32_tx_mbox = tg3_write32;
13866 tp->write32_rx_mbox = tg3_write32;
13867
13868 /* Various workaround register access methods */
13869 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13870 tp->write32 = tg3_write_indirect_reg32;
Matt Carlson98efd8a2007-05-05 12:47:25 -070013871 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13872 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13873 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13874 /*
13875 * Back to back register writes can cause problems on these
13876 * chips, the workaround is to read back all reg writes
13877 * except those to mailbox regs.
13878 *
13879 * See tg3_write_indirect_reg32().
13880 */
Michael Chan1ee582d2005-08-09 20:16:46 -070013881 tp->write32 = tg3_write_flush_reg32;
Matt Carlson98efd8a2007-05-05 12:47:25 -070013882 }
13883
Michael Chan1ee582d2005-08-09 20:16:46 -070013884 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13885 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13886 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13887 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13888 tp->write32_rx_mbox = tg3_write_flush_reg32;
13889 }
Michael Chan20094932005-08-09 20:16:32 -070013890
Michael Chan68929142005-08-09 20:17:14 -070013891 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13892 tp->read32 = tg3_read_indirect_reg32;
13893 tp->write32 = tg3_write_indirect_reg32;
13894 tp->read32_mbox = tg3_read_indirect_mbox;
13895 tp->write32_mbox = tg3_write_indirect_mbox;
13896 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13897 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13898
13899 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070013900 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070013901
13902 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13903 pci_cmd &= ~PCI_COMMAND_MEMORY;
13904 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13905 }
Michael Chanb5d37722006-09-27 16:06:21 -070013906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13907 tp->read32_mbox = tg3_read32_mbox_5906;
13908 tp->write32_mbox = tg3_write32_mbox_5906;
13909 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13910 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13911 }
Michael Chan68929142005-08-09 20:17:14 -070013912
Michael Chanbbadf502006-04-06 21:46:34 -070013913 if (tp->write32 == tg3_write_indirect_reg32 ||
13914 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13915 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
David S. Millerf49639e2006-06-09 11:58:36 -070013916 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
Michael Chanbbadf502006-04-06 21:46:34 -070013917 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13918
Michael Chan7d0c41e2005-04-21 17:06:20 -070013919 /* Get eeprom hw config before calling tg3_set_power_state().
Michael Chan9d26e212006-12-07 00:21:14 -080013920 * In particular, the TG3_FLG2_IS_NIC flag must be
Michael Chan7d0c41e2005-04-21 17:06:20 -070013921 * determined before calling tg3_set_power_state() so that
13922 * we know whether or not to switch out of Vaux power.
13923 * When the flag is set, it means that GPIO1 is used for eeprom
13924 * write protect and also implies that it is a LOM where GPIOs
13925 * are not used to switch power.
Jeff Garzik6aa20a22006-09-13 13:24:59 -040013926 */
Michael Chan7d0c41e2005-04-21 17:06:20 -070013927 tg3_get_eeprom_hw_cfg(tp);
13928
Matt Carlson0d3031d2007-10-10 18:02:43 -070013929 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13930 /* Allow reads and writes to the
13931 * APE register and memory space.
13932 */
13933 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +000013934 PCISTATE_ALLOW_APE_SHMEM_WR |
13935 PCISTATE_ALLOW_APE_PSPACE_WR;
Matt Carlson0d3031d2007-10-10 18:02:43 -070013936 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13937 pci_state_reg);
13938 }
13939
Matt Carlson9936bcf2007-10-10 18:03:07 -070013940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson57e69832008-05-25 23:48:31 -070013941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080013942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Matt Carlson1407deb2011-04-05 14:22:44 +000013944 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
Matt Carlsond30cdd22007-10-07 23:28:35 -070013945 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13946
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000013947 /* Set up tp->grc_local_ctrl before calling tg_power_up().
Michael Chan314fba32005-04-21 17:07:04 -070013948 * GPIO1 driven high will bring 5700's external PHY out of reset.
13949 * It is also used as eeprom write protect on LOMs.
13950 */
13951 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13952 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13953 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13954 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13955 GRC_LCLCTRL_GPIO_OUTPUT1);
Michael Chan3e7d83b2005-04-21 17:10:36 -070013956 /* Unused GPIO3 must be driven as output on 5752 because there
13957 * are no pull-up resistors on unused GPIO pins.
13958 */
13959 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13960 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
Michael Chan314fba32005-04-21 17:07:04 -070013961
Matt Carlson321d32a2008-11-21 17:22:19 -080013962 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlsoncb4ed1f2010-01-20 16:58:09 +000013963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Michael Chanaf36e6b2006-03-23 01:28:06 -080013965 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13966
Matt Carlson8d519ab2009-04-20 06:58:01 +000013967 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13968 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
Matt Carlson5f0c4a32008-06-09 15:41:12 -070013969 /* Turn off the debug UART. */
13970 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13971 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13972 /* Keep VMain power. */
13973 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13974 GRC_LCLCTRL_GPIO_OUTPUT0;
13975 }
13976
Linus Torvalds1da177e2005-04-16 15:20:36 -070013977 /* Force the chip into D0. */
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000013978 err = tg3_power_up(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013979 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000013980 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070013981 return err;
13982 }
13983
Linus Torvalds1da177e2005-04-16 15:20:36 -070013984 /* Derive initial jumbo mode from MTU assigned in
13985 * ether_setup() via the alloc_etherdev() call
13986 */
Michael Chan0f893dc2005-07-25 12:30:38 -070013987 if (tp->dev->mtu > ETH_DATA_LEN &&
Michael Chana4e2b342005-10-26 15:46:52 -070013988 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
Michael Chan0f893dc2005-07-25 12:30:38 -070013989 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013990
13991 /* Determine WakeOnLan speed to use. */
13992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13993 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13994 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13995 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13996 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13997 } else {
13998 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13999 }
14000
Matt Carlson7f97a4b2009-08-25 10:10:03 +000014001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014002 tp->phy_flags |= TG3_PHYFLG_IS_FET;
Matt Carlson7f97a4b2009-08-25 10:10:03 +000014003
Linus Torvalds1da177e2005-04-16 15:20:36 -070014004 /* A few boards don't want Ethernet@WireSpeed phy feature */
14005 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
14006 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
14007 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
Michael Chan747e8f82005-07-25 12:33:22 -070014008 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014009 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14010 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14011 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014012
14013 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14014 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014015 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014016 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014017 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014018
Matt Carlson321d32a2008-11-21 17:22:19 -080014019 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014020 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
Matt Carlson321d32a2008-11-21 17:22:19 -080014021 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000014022 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
Matt Carlson1407deb2011-04-05 14:22:44 +000014023 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
Michael Chanc424cb22006-04-29 18:56:34 -070014024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlsond30cdd22007-10-07 23:28:35 -070014025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlson9936bcf2007-10-10 18:03:07 -070014026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
Michael Chand4011ad2007-02-13 12:17:25 -080014028 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14029 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014030 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
Michael Chanc1d2a192007-01-08 19:57:20 -080014031 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014032 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
Matt Carlson321d32a2008-11-21 17:22:19 -080014033 } else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014034 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
Michael Chanc424cb22006-04-29 18:56:34 -070014035 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014036
Matt Carlsonb2a5c192008-04-03 21:44:44 -070014037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14038 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14039 tp->phy_otp = tg3_read_otp_phycfg(tp);
14040 if (tp->phy_otp == 0)
14041 tp->phy_otp = TG3_OTP_DEFAULT;
14042 }
14043
Matt Carlsonf51f3562008-05-25 23:45:08 -070014044 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
Matt Carlson8ef21422008-05-02 16:47:53 -070014045 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14046 else
14047 tp->mi_mode = MAC_MI_MODE_BASE;
14048
Linus Torvalds1da177e2005-04-16 15:20:36 -070014049 tp->coalesce_mode = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014050 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14051 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14052 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14053
Matt Carlson4d958472011-04-20 07:57:35 +000014054 /* Set these bits to enable statistics workaround. */
14055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14056 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14057 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14058 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14059 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14060 }
14061
Matt Carlson321d32a2008-11-21 17:22:19 -080014062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlson57e69832008-05-25 23:48:31 -070014064 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
14065
Matt Carlson158d7ab2008-05-29 01:37:54 -070014066 err = tg3_mdio_init(tp);
14067 if (err)
14068 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014069
14070 /* Initialize data/descriptor byte/word swapping. */
14071 val = tr32(GRC_MODE);
Matt Carlsonf2096f92011-04-05 14:22:48 +000014072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14073 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14074 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14075 GRC_MODE_B2HRX_ENABLE |
14076 GRC_MODE_HTX2B_ENABLE |
14077 GRC_MODE_HOST_STACKUP);
14078 else
14079 val &= GRC_MODE_HOST_STACKUP;
14080
Linus Torvalds1da177e2005-04-16 15:20:36 -070014081 tw32(GRC_MODE, val | tp->grc_mode);
14082
14083 tg3_switch_clocks(tp);
14084
14085 /* Clear this out for sanity. */
14086 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14087
14088 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14089 &pci_state_reg);
14090 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14091 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
14092 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14093
14094 if (chiprevid == CHIPREV_ID_5701_A0 ||
14095 chiprevid == CHIPREV_ID_5701_B0 ||
14096 chiprevid == CHIPREV_ID_5701_B2 ||
14097 chiprevid == CHIPREV_ID_5701_B5) {
14098 void __iomem *sram_base;
14099
14100 /* Write some dummy words into the SRAM status block
14101 * area, see if it reads back correctly. If the return
14102 * value is bad, force enable the PCIX workaround.
14103 */
14104 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14105
14106 writel(0x00000000, sram_base);
14107 writel(0x00000000, sram_base + 4);
14108 writel(0xffffffff, sram_base + 4);
14109 if (readl(sram_base) != 0x00000000)
14110 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
14111 }
14112 }
14113
14114 udelay(50);
14115 tg3_nvram_init(tp);
14116
14117 grc_misc_cfg = tr32(GRC_MISC_CFG);
14118 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14119
Linus Torvalds1da177e2005-04-16 15:20:36 -070014120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14121 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14122 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14123 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
14124
David S. Millerfac9b832005-05-18 22:46:34 -070014125 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
14126 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
14127 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
14128 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
14129 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14130 HOSTCC_MODE_CLRTICK_TXBD);
14131
14132 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14133 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14134 tp->misc_host_ctrl);
14135 }
14136
Matt Carlson3bda1252008-08-15 14:08:22 -070014137 /* Preserve the APE MAC_MODE bits */
14138 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
Matt Carlsond2394e6b2010-11-24 08:31:47 +000014139 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
Matt Carlson3bda1252008-08-15 14:08:22 -070014140 else
14141 tp->mac_mode = TG3_DEF_MAC_MODE;
14142
Linus Torvalds1da177e2005-04-16 15:20:36 -070014143 /* these are limited to 10/100 only */
14144 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14145 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14146 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14147 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14148 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14149 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14150 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14151 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14152 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
Michael Chan676917d2006-12-07 00:20:22 -080014153 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14154 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
Matt Carlson321d32a2008-11-21 17:22:19 -080014155 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
Matt Carlsond1101142010-02-17 15:16:55 +000014156 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14157 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014158 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14159 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014160
14161 err = tg3_phy_probe(tp);
14162 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000014163 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014164 /* ... but do not return immediately ... */
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014165 tg3_mdio_fini(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014166 }
14167
Matt Carlson184b8902010-04-05 10:19:25 +000014168 tg3_read_vpd(tp);
Michael Chanc4e65752006-03-20 22:29:32 -080014169 tg3_read_fw_ver(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014170
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014171 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14172 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014173 } else {
14174 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014175 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014176 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014177 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014178 }
14179
14180 /* 5700 {AX,BX} chips have a broken status block link
14181 * change bit implementation, so we must use the
14182 * status register in those cases.
14183 */
14184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14185 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14186 else
14187 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
14188
14189 /* The led_ctrl is set during tg3_phy_probe, here we might
14190 * have to force the link status polling mechanism based
14191 * upon subsystem IDs.
14192 */
14193 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
Michael Chan007a880d2007-05-31 14:49:51 -070014194 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014195 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14196 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14197 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014198 }
14199
14200 /* For all SERDES we poll the MAC status register. */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014201 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014202 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
14203 else
14204 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
14205
Matt Carlsonbf933c82011-01-25 15:58:49 +000014206 tp->rx_offset = NET_IP_ALIGN;
Matt Carlsond2757fc2010-04-12 06:58:27 +000014207 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
Matt Carlsond2757fc2010-04-12 06:58:27 +000014209 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
Matt Carlsonbf933c82011-01-25 15:58:49 +000014210 tp->rx_offset = 0;
Matt Carlsond2757fc2010-04-12 06:58:27 +000014211#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Matt Carlson9dc7a112010-04-12 06:58:28 +000014212 tp->rx_copy_thresh = ~(u16)0;
Matt Carlsond2757fc2010-04-12 06:58:27 +000014213#endif
14214 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014215
Matt Carlson2c49a442010-09-30 10:34:35 +000014216 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14217 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000014218 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14219
Matt Carlson2c49a442010-09-30 10:34:35 +000014220 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
Michael Chanf92905d2006-06-29 20:14:29 -070014221
14222 /* Increment the rx prod index on the rx std ring by at most
14223 * 8 for these chips to workaround hw errata.
14224 */
14225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14228 tp->rx_std_max_post = 8;
14229
Matt Carlson8ed5d972007-05-07 00:25:49 -070014230 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
14231 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14232 PCIE_PWR_MGMT_L1_THRESH_MSK;
14233
Linus Torvalds1da177e2005-04-16 15:20:36 -070014234 return err;
14235}
14236
David S. Miller49b6e95f2007-03-29 01:38:42 -070014237#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070014238static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14239{
14240 struct net_device *dev = tp->dev;
14241 struct pci_dev *pdev = tp->pdev;
David S. Miller49b6e95f2007-03-29 01:38:42 -070014242 struct device_node *dp = pci_device_to_OF_node(pdev);
David S. Miller374d4ca2007-03-29 01:57:57 -070014243 const unsigned char *addr;
David S. Miller49b6e95f2007-03-29 01:38:42 -070014244 int len;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014245
David S. Miller49b6e95f2007-03-29 01:38:42 -070014246 addr = of_get_property(dp, "local-mac-address", &len);
14247 if (addr && len == 6) {
14248 memcpy(dev->dev_addr, addr, 6);
14249 memcpy(dev->perm_addr, dev->dev_addr, 6);
14250 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014251 }
14252 return -ENODEV;
14253}
14254
14255static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14256{
14257 struct net_device *dev = tp->dev;
14258
14259 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
John W. Linville2ff43692005-09-12 14:44:20 -070014260 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014261 return 0;
14262}
14263#endif
14264
14265static int __devinit tg3_get_device_address(struct tg3 *tp)
14266{
14267 struct net_device *dev = tp->dev;
14268 u32 hi, lo, mac_offset;
Michael Chan008652b2006-03-27 23:14:53 -080014269 int addr_ok = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014270
David S. Miller49b6e95f2007-03-29 01:38:42 -070014271#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070014272 if (!tg3_get_macaddr_sparc(tp))
14273 return 0;
14274#endif
14275
14276 mac_offset = 0x7c;
David S. Millerf49639e2006-06-09 11:58:36 -070014277 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
Michael Chana4e2b342005-10-26 15:46:52 -070014278 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070014279 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14280 mac_offset = 0xcc;
14281 if (tg3_nvram_lock(tp))
14282 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14283 else
14284 tg3_nvram_unlock(tp);
Matt Carlson0a58d662011-04-05 14:22:45 +000014285 } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
Matt Carlsona50d0792010-06-05 17:24:37 +000014286 if (PCI_FUNC(tp->pdev->devfn) & 1)
Matt Carlsona1b950d2009-09-01 13:20:17 +000014287 mac_offset = 0xcc;
Matt Carlsona50d0792010-06-05 17:24:37 +000014288 if (PCI_FUNC(tp->pdev->devfn) > 1)
14289 mac_offset += 0x18c;
Matt Carlsona1b950d2009-09-01 13:20:17 +000014290 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Michael Chanb5d37722006-09-27 16:06:21 -070014291 mac_offset = 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014292
14293 /* First try to get it from MAC address mailbox. */
14294 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14295 if ((hi >> 16) == 0x484b) {
14296 dev->dev_addr[0] = (hi >> 8) & 0xff;
14297 dev->dev_addr[1] = (hi >> 0) & 0xff;
14298
14299 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14300 dev->dev_addr[2] = (lo >> 24) & 0xff;
14301 dev->dev_addr[3] = (lo >> 16) & 0xff;
14302 dev->dev_addr[4] = (lo >> 8) & 0xff;
14303 dev->dev_addr[5] = (lo >> 0) & 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014304
Michael Chan008652b2006-03-27 23:14:53 -080014305 /* Some old bootcode may report a 0 MAC address in SRAM */
14306 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14307 }
14308 if (!addr_ok) {
14309 /* Next, try NVRAM. */
Matt Carlsondf259d82009-04-20 06:57:14 +000014310 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
14311 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
Matt Carlson6d348f22009-02-25 14:25:52 +000014312 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
Matt Carlson62cedd12009-04-20 14:52:29 -070014313 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14314 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
Michael Chan008652b2006-03-27 23:14:53 -080014315 }
14316 /* Finally just fetch it out of the MAC control regs. */
14317 else {
14318 hi = tr32(MAC_ADDR_0_HIGH);
14319 lo = tr32(MAC_ADDR_0_LOW);
14320
14321 dev->dev_addr[5] = lo & 0xff;
14322 dev->dev_addr[4] = (lo >> 8) & 0xff;
14323 dev->dev_addr[3] = (lo >> 16) & 0xff;
14324 dev->dev_addr[2] = (lo >> 24) & 0xff;
14325 dev->dev_addr[1] = hi & 0xff;
14326 dev->dev_addr[0] = (hi >> 8) & 0xff;
14327 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014328 }
14329
14330 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
David S. Miller7582a332008-03-20 15:53:15 -070014331#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070014332 if (!tg3_get_default_macaddr_sparc(tp))
14333 return 0;
14334#endif
14335 return -EINVAL;
14336 }
John W. Linville2ff43692005-09-12 14:44:20 -070014337 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014338 return 0;
14339}
14340
David S. Miller59e6b432005-05-18 22:50:10 -070014341#define BOUNDARY_SINGLE_CACHELINE 1
14342#define BOUNDARY_MULTI_CACHELINE 2
14343
14344static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14345{
14346 int cacheline_size;
14347 u8 byte;
14348 int goal;
14349
14350 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14351 if (byte == 0)
14352 cacheline_size = 1024;
14353 else
14354 cacheline_size = (int) byte * 4;
14355
14356 /* On 5703 and later chips, the boundary bits have no
14357 * effect.
14358 */
14359 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14360 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14361 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14362 goto out;
14363
14364#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14365 goal = BOUNDARY_MULTI_CACHELINE;
14366#else
14367#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14368 goal = BOUNDARY_SINGLE_CACHELINE;
14369#else
14370 goal = 0;
14371#endif
14372#endif
14373
Matt Carlson1407deb2011-04-05 14:22:44 +000014374 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000014375 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14376 goto out;
14377 }
14378
David S. Miller59e6b432005-05-18 22:50:10 -070014379 if (!goal)
14380 goto out;
14381
14382 /* PCI controllers on most RISC systems tend to disconnect
14383 * when a device tries to burst across a cache-line boundary.
14384 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14385 *
14386 * Unfortunately, for PCI-E there are only limited
14387 * write-side controls for this, and thus for reads
14388 * we will still get the disconnects. We'll also waste
14389 * these PCI cycles for both read and write for chips
14390 * other than 5700 and 5701 which do not implement the
14391 * boundary bits.
14392 */
14393 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14394 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14395 switch (cacheline_size) {
14396 case 16:
14397 case 32:
14398 case 64:
14399 case 128:
14400 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14401 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14402 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14403 } else {
14404 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14405 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14406 }
14407 break;
14408
14409 case 256:
14410 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14411 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14412 break;
14413
14414 default:
14415 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14416 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14417 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070014418 }
David S. Miller59e6b432005-05-18 22:50:10 -070014419 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14420 switch (cacheline_size) {
14421 case 16:
14422 case 32:
14423 case 64:
14424 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14425 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14426 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14427 break;
14428 }
14429 /* fallthrough */
14430 case 128:
14431 default:
14432 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14433 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14434 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070014435 }
David S. Miller59e6b432005-05-18 22:50:10 -070014436 } else {
14437 switch (cacheline_size) {
14438 case 16:
14439 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14440 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14441 DMA_RWCTRL_WRITE_BNDRY_16);
14442 break;
14443 }
14444 /* fallthrough */
14445 case 32:
14446 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14447 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14448 DMA_RWCTRL_WRITE_BNDRY_32);
14449 break;
14450 }
14451 /* fallthrough */
14452 case 64:
14453 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14454 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14455 DMA_RWCTRL_WRITE_BNDRY_64);
14456 break;
14457 }
14458 /* fallthrough */
14459 case 128:
14460 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14461 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14462 DMA_RWCTRL_WRITE_BNDRY_128);
14463 break;
14464 }
14465 /* fallthrough */
14466 case 256:
14467 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14468 DMA_RWCTRL_WRITE_BNDRY_256);
14469 break;
14470 case 512:
14471 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14472 DMA_RWCTRL_WRITE_BNDRY_512);
14473 break;
14474 case 1024:
14475 default:
14476 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14477 DMA_RWCTRL_WRITE_BNDRY_1024);
14478 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070014479 }
David S. Miller59e6b432005-05-18 22:50:10 -070014480 }
14481
14482out:
14483 return val;
14484}
14485
Linus Torvalds1da177e2005-04-16 15:20:36 -070014486static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14487{
14488 struct tg3_internal_buffer_desc test_desc;
14489 u32 sram_dma_descs;
14490 int i, ret;
14491
14492 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14493
14494 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14495 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14496 tw32(RDMAC_STATUS, 0);
14497 tw32(WDMAC_STATUS, 0);
14498
14499 tw32(BUFMGR_MODE, 0);
14500 tw32(FTQ_RESET, 0);
14501
14502 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14503 test_desc.addr_lo = buf_dma & 0xffffffff;
14504 test_desc.nic_mbuf = 0x00002100;
14505 test_desc.len = size;
14506
14507 /*
14508 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14509 * the *second* time the tg3 driver was getting loaded after an
14510 * initial scan.
14511 *
14512 * Broadcom tells me:
14513 * ...the DMA engine is connected to the GRC block and a DMA
14514 * reset may affect the GRC block in some unpredictable way...
14515 * The behavior of resets to individual blocks has not been tested.
14516 *
14517 * Broadcom noted the GRC reset will also reset all sub-components.
14518 */
14519 if (to_device) {
14520 test_desc.cqid_sqid = (13 << 8) | 2;
14521
14522 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14523 udelay(40);
14524 } else {
14525 test_desc.cqid_sqid = (16 << 8) | 7;
14526
14527 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14528 udelay(40);
14529 }
14530 test_desc.flags = 0x00000005;
14531
14532 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14533 u32 val;
14534
14535 val = *(((u32 *)&test_desc) + i);
14536 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14537 sram_dma_descs + (i * sizeof(u32)));
14538 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14539 }
14540 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14541
Matt Carlson859a588792010-04-05 10:19:28 +000014542 if (to_device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014543 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
Matt Carlson859a588792010-04-05 10:19:28 +000014544 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070014545 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014546
14547 ret = -ENODEV;
14548 for (i = 0; i < 40; i++) {
14549 u32 val;
14550
14551 if (to_device)
14552 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14553 else
14554 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14555 if ((val & 0xffff) == sram_dma_descs) {
14556 ret = 0;
14557 break;
14558 }
14559
14560 udelay(100);
14561 }
14562
14563 return ret;
14564}
14565
David S. Millerded73402005-05-23 13:59:47 -070014566#define TEST_BUFFER_SIZE 0x2000
Linus Torvalds1da177e2005-04-16 15:20:36 -070014567
Matt Carlson41434702011-03-09 16:58:22 +000014568static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
Joe Perches895950c2010-12-21 02:16:08 -080014569 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14570 { },
14571};
14572
Linus Torvalds1da177e2005-04-16 15:20:36 -070014573static int __devinit tg3_test_dma(struct tg3 *tp)
14574{
14575 dma_addr_t buf_dma;
David S. Miller59e6b432005-05-18 22:50:10 -070014576 u32 *buf, saved_dma_rwctrl;
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000014577 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014578
Matt Carlson4bae65c2010-11-24 08:31:52 +000014579 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14580 &buf_dma, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014581 if (!buf) {
14582 ret = -ENOMEM;
14583 goto out_nofree;
14584 }
14585
14586 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14587 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14588
David S. Miller59e6b432005-05-18 22:50:10 -070014589 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014590
Matt Carlson1407deb2011-04-05 14:22:44 +000014591 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000014592 goto out;
14593
Linus Torvalds1da177e2005-04-16 15:20:36 -070014594 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14595 /* DMA read watermark not used on PCIE */
14596 tp->dma_rwctrl |= 0x00180000;
14597 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
Michael Chan85e94ce2005-04-21 17:05:28 -070014598 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14599 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014600 tp->dma_rwctrl |= 0x003f0000;
14601 else
14602 tp->dma_rwctrl |= 0x003f000f;
14603 } else {
14604 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14605 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14606 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
Michael Chan49afdeb2007-02-13 12:17:03 -080014607 u32 read_water = 0x7;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014608
Michael Chan4a29cc22006-03-19 13:21:12 -080014609 /* If the 5704 is behind the EPB bridge, we can
14610 * do the less restrictive ONE_DMA workaround for
14611 * better performance.
14612 */
14613 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14614 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14615 tp->dma_rwctrl |= 0x8000;
14616 else if (ccval == 0x6 || ccval == 0x7)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014617 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14618
Michael Chan49afdeb2007-02-13 12:17:03 -080014619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14620 read_water = 4;
David S. Miller59e6b432005-05-18 22:50:10 -070014621 /* Set bit 23 to enable PCIX hw bug fix */
Michael Chan49afdeb2007-02-13 12:17:03 -080014622 tp->dma_rwctrl |=
14623 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14624 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14625 (1 << 23);
Michael Chan4cf78e42005-07-25 12:29:19 -070014626 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14627 /* 5780 always in PCIX mode */
14628 tp->dma_rwctrl |= 0x00144000;
Michael Chana4e2b342005-10-26 15:46:52 -070014629 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14630 /* 5714 always in PCIX mode */
14631 tp->dma_rwctrl |= 0x00148000;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014632 } else {
14633 tp->dma_rwctrl |= 0x001b000f;
14634 }
14635 }
14636
14637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14639 tp->dma_rwctrl &= 0xfffffff0;
14640
14641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14643 /* Remove this if it causes problems for some boards. */
14644 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14645
14646 /* On 5700/5701 chips, we need to set this bit.
14647 * Otherwise the chip will issue cacheline transactions
14648 * to streamable DMA memory with not all the byte
14649 * enables turned on. This is an error on several
14650 * RISC PCI controllers, in particular sparc64.
14651 *
14652 * On 5703/5704 chips, this bit has been reassigned
14653 * a different meaning. In particular, it is used
14654 * on those chips to enable a PCI-X workaround.
14655 */
14656 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14657 }
14658
14659 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14660
14661#if 0
14662 /* Unneeded, already done by tg3_get_invariants. */
14663 tg3_switch_clocks(tp);
14664#endif
14665
Linus Torvalds1da177e2005-04-16 15:20:36 -070014666 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14667 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14668 goto out;
14669
David S. Miller59e6b432005-05-18 22:50:10 -070014670 /* It is best to perform DMA test with maximum write burst size
14671 * to expose the 5700/5701 write DMA bug.
14672 */
14673 saved_dma_rwctrl = tp->dma_rwctrl;
14674 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14675 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14676
Linus Torvalds1da177e2005-04-16 15:20:36 -070014677 while (1) {
14678 u32 *p = buf, i;
14679
14680 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14681 p[i] = i;
14682
14683 /* Send the buffer to the chip. */
14684 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14685 if (ret) {
Matt Carlson2445e462010-04-05 10:19:21 +000014686 dev_err(&tp->pdev->dev,
14687 "%s: Buffer write failed. err = %d\n",
14688 __func__, ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014689 break;
14690 }
14691
14692#if 0
14693 /* validate data reached card RAM correctly. */
14694 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14695 u32 val;
14696 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14697 if (le32_to_cpu(val) != p[i]) {
Matt Carlson2445e462010-04-05 10:19:21 +000014698 dev_err(&tp->pdev->dev,
14699 "%s: Buffer corrupted on device! "
14700 "(%d != %d)\n", __func__, val, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014701 /* ret = -ENODEV here? */
14702 }
14703 p[i] = 0;
14704 }
14705#endif
14706 /* Now read it back. */
14707 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14708 if (ret) {
Matt Carlson5129c3a2010-04-05 10:19:23 +000014709 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14710 "err = %d\n", __func__, ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014711 break;
14712 }
14713
14714 /* Verify it. */
14715 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14716 if (p[i] == i)
14717 continue;
14718
David S. Miller59e6b432005-05-18 22:50:10 -070014719 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14720 DMA_RWCTRL_WRITE_BNDRY_16) {
14721 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014722 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14723 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14724 break;
14725 } else {
Matt Carlson2445e462010-04-05 10:19:21 +000014726 dev_err(&tp->pdev->dev,
14727 "%s: Buffer corrupted on read back! "
14728 "(%d != %d)\n", __func__, p[i], i);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014729 ret = -ENODEV;
14730 goto out;
14731 }
14732 }
14733
14734 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14735 /* Success. */
14736 ret = 0;
14737 break;
14738 }
14739 }
David S. Miller59e6b432005-05-18 22:50:10 -070014740 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14741 DMA_RWCTRL_WRITE_BNDRY_16) {
Michael Chan6d1cfba2005-06-08 14:13:14 -070014742
David S. Miller59e6b432005-05-18 22:50:10 -070014743 /* DMA test passed without adjusting DMA boundary,
Michael Chan6d1cfba2005-06-08 14:13:14 -070014744 * now look for chipsets that are known to expose the
14745 * DMA bug without failing the test.
David S. Miller59e6b432005-05-18 22:50:10 -070014746 */
Matt Carlson41434702011-03-09 16:58:22 +000014747 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
Michael Chan6d1cfba2005-06-08 14:13:14 -070014748 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14749 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
Matt Carlson859a588792010-04-05 10:19:28 +000014750 } else {
Michael Chan6d1cfba2005-06-08 14:13:14 -070014751 /* Safe to use the calculated DMA boundary. */
14752 tp->dma_rwctrl = saved_dma_rwctrl;
Matt Carlson859a588792010-04-05 10:19:28 +000014753 }
Michael Chan6d1cfba2005-06-08 14:13:14 -070014754
David S. Miller59e6b432005-05-18 22:50:10 -070014755 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14756 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014757
14758out:
Matt Carlson4bae65c2010-11-24 08:31:52 +000014759 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014760out_nofree:
14761 return ret;
14762}
14763
Linus Torvalds1da177e2005-04-16 15:20:36 -070014764static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14765{
Matt Carlson1407deb2011-04-05 14:22:44 +000014766 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
Matt Carlson666bc832010-01-20 16:58:03 +000014767 tp->bufmgr_config.mbuf_read_dma_low_water =
14768 DEFAULT_MB_RDMA_LOW_WATER_5705;
14769 tp->bufmgr_config.mbuf_mac_rx_low_water =
14770 DEFAULT_MB_MACRX_LOW_WATER_57765;
14771 tp->bufmgr_config.mbuf_high_water =
14772 DEFAULT_MB_HIGH_WATER_57765;
14773
14774 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14775 DEFAULT_MB_RDMA_LOW_WATER_5705;
14776 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14777 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14778 tp->bufmgr_config.mbuf_high_water_jumbo =
14779 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14780 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
Michael Chanfdfec1722005-07-25 12:31:48 -070014781 tp->bufmgr_config.mbuf_read_dma_low_water =
14782 DEFAULT_MB_RDMA_LOW_WATER_5705;
14783 tp->bufmgr_config.mbuf_mac_rx_low_water =
14784 DEFAULT_MB_MACRX_LOW_WATER_5705;
14785 tp->bufmgr_config.mbuf_high_water =
14786 DEFAULT_MB_HIGH_WATER_5705;
Michael Chanb5d37722006-09-27 16:06:21 -070014787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14788 tp->bufmgr_config.mbuf_mac_rx_low_water =
14789 DEFAULT_MB_MACRX_LOW_WATER_5906;
14790 tp->bufmgr_config.mbuf_high_water =
14791 DEFAULT_MB_HIGH_WATER_5906;
14792 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014793
Michael Chanfdfec1722005-07-25 12:31:48 -070014794 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14795 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14796 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14797 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14798 tp->bufmgr_config.mbuf_high_water_jumbo =
14799 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14800 } else {
14801 tp->bufmgr_config.mbuf_read_dma_low_water =
14802 DEFAULT_MB_RDMA_LOW_WATER;
14803 tp->bufmgr_config.mbuf_mac_rx_low_water =
14804 DEFAULT_MB_MACRX_LOW_WATER;
14805 tp->bufmgr_config.mbuf_high_water =
14806 DEFAULT_MB_HIGH_WATER;
14807
14808 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14809 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14810 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14811 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14812 tp->bufmgr_config.mbuf_high_water_jumbo =
14813 DEFAULT_MB_HIGH_WATER_JUMBO;
14814 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014815
14816 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14817 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14818}
14819
14820static char * __devinit tg3_phy_string(struct tg3 *tp)
14821{
Matt Carlson79eb6902010-02-17 15:17:03 +000014822 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14823 case TG3_PHY_ID_BCM5400: return "5400";
14824 case TG3_PHY_ID_BCM5401: return "5401";
14825 case TG3_PHY_ID_BCM5411: return "5411";
14826 case TG3_PHY_ID_BCM5701: return "5701";
14827 case TG3_PHY_ID_BCM5703: return "5703";
14828 case TG3_PHY_ID_BCM5704: return "5704";
14829 case TG3_PHY_ID_BCM5705: return "5705";
14830 case TG3_PHY_ID_BCM5750: return "5750";
14831 case TG3_PHY_ID_BCM5752: return "5752";
14832 case TG3_PHY_ID_BCM5714: return "5714";
14833 case TG3_PHY_ID_BCM5780: return "5780";
14834 case TG3_PHY_ID_BCM5755: return "5755";
14835 case TG3_PHY_ID_BCM5787: return "5787";
14836 case TG3_PHY_ID_BCM5784: return "5784";
14837 case TG3_PHY_ID_BCM5756: return "5722/5756";
14838 case TG3_PHY_ID_BCM5906: return "5906";
14839 case TG3_PHY_ID_BCM5761: return "5761";
14840 case TG3_PHY_ID_BCM5718C: return "5718C";
14841 case TG3_PHY_ID_BCM5718S: return "5718S";
14842 case TG3_PHY_ID_BCM57765: return "57765";
Matt Carlson302b5002010-06-05 17:24:38 +000014843 case TG3_PHY_ID_BCM5719C: return "5719C";
Matt Carlson6418f2c2011-04-05 14:22:49 +000014844 case TG3_PHY_ID_BCM5720C: return "5720C";
Matt Carlson79eb6902010-02-17 15:17:03 +000014845 case TG3_PHY_ID_BCM8002: return "8002/serdes";
Linus Torvalds1da177e2005-04-16 15:20:36 -070014846 case 0: return "serdes";
14847 default: return "unknown";
Stephen Hemminger855e1112008-04-16 16:37:28 -070014848 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014849}
14850
Michael Chanf9804dd2005-09-27 12:13:10 -070014851static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14852{
14853 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14854 strcpy(str, "PCI Express");
14855 return str;
14856 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14857 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14858
14859 strcpy(str, "PCIX:");
14860
14861 if ((clock_ctrl == 7) ||
14862 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14863 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14864 strcat(str, "133MHz");
14865 else if (clock_ctrl == 0)
14866 strcat(str, "33MHz");
14867 else if (clock_ctrl == 2)
14868 strcat(str, "50MHz");
14869 else if (clock_ctrl == 4)
14870 strcat(str, "66MHz");
14871 else if (clock_ctrl == 6)
14872 strcat(str, "100MHz");
Michael Chanf9804dd2005-09-27 12:13:10 -070014873 } else {
14874 strcpy(str, "PCI:");
14875 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14876 strcat(str, "66MHz");
14877 else
14878 strcat(str, "33MHz");
14879 }
14880 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14881 strcat(str, ":32-bit");
14882 else
14883 strcat(str, ":64-bit");
14884 return str;
14885}
14886
Michael Chan8c2dc7e2005-12-19 16:26:02 -080014887static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014888{
14889 struct pci_dev *peer;
14890 unsigned int func, devnr = tp->pdev->devfn & ~7;
14891
14892 for (func = 0; func < 8; func++) {
14893 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14894 if (peer && peer != tp->pdev)
14895 break;
14896 pci_dev_put(peer);
14897 }
Michael Chan16fe9d72005-12-13 21:09:54 -080014898 /* 5704 can be configured in single-port mode, set peer to
14899 * tp->pdev in that case.
14900 */
14901 if (!peer) {
14902 peer = tp->pdev;
14903 return peer;
14904 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014905
14906 /*
14907 * We don't need to keep the refcount elevated; there's no way
14908 * to remove one half of this device without removing the other
14909 */
14910 pci_dev_put(peer);
14911
14912 return peer;
14913}
14914
David S. Miller15f98502005-05-18 22:49:26 -070014915static void __devinit tg3_init_coal(struct tg3 *tp)
14916{
14917 struct ethtool_coalesce *ec = &tp->coal;
14918
14919 memset(ec, 0, sizeof(*ec));
14920 ec->cmd = ETHTOOL_GCOALESCE;
14921 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14922 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14923 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14924 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14925 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14926 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14927 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14928 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14929 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14930
14931 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14932 HOSTCC_MODE_CLRTICK_TXBD)) {
14933 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14934 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14935 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14936 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14937 }
Michael Chand244c892005-07-05 14:42:33 -070014938
14939 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14940 ec->rx_coalesce_usecs_irq = 0;
14941 ec->tx_coalesce_usecs_irq = 0;
14942 ec->stats_block_coalesce_usecs = 0;
14943 }
David S. Miller15f98502005-05-18 22:49:26 -070014944}
14945
Stephen Hemminger7c7d64b2008-11-19 22:25:36 -080014946static const struct net_device_ops tg3_netdev_ops = {
14947 .ndo_open = tg3_open,
14948 .ndo_stop = tg3_close,
Stephen Hemminger00829822008-11-20 20:14:53 -080014949 .ndo_start_xmit = tg3_start_xmit,
Eric Dumazet511d2222010-07-07 20:44:24 +000014950 .ndo_get_stats64 = tg3_get_stats64,
Stephen Hemminger00829822008-11-20 20:14:53 -080014951 .ndo_validate_addr = eth_validate_addr,
14952 .ndo_set_multicast_list = tg3_set_rx_mode,
14953 .ndo_set_mac_address = tg3_set_mac_addr,
14954 .ndo_do_ioctl = tg3_ioctl,
14955 .ndo_tx_timeout = tg3_tx_timeout,
14956 .ndo_change_mtu = tg3_change_mtu,
Michał Mirosławdc668912011-04-07 03:35:07 +000014957 .ndo_fix_features = tg3_fix_features,
Stephen Hemminger00829822008-11-20 20:14:53 -080014958#ifdef CONFIG_NET_POLL_CONTROLLER
14959 .ndo_poll_controller = tg3_poll_controller,
14960#endif
14961};
14962
14963static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14964 .ndo_open = tg3_open,
14965 .ndo_stop = tg3_close,
14966 .ndo_start_xmit = tg3_start_xmit_dma_bug,
Eric Dumazet511d2222010-07-07 20:44:24 +000014967 .ndo_get_stats64 = tg3_get_stats64,
Stephen Hemminger7c7d64b2008-11-19 22:25:36 -080014968 .ndo_validate_addr = eth_validate_addr,
14969 .ndo_set_multicast_list = tg3_set_rx_mode,
14970 .ndo_set_mac_address = tg3_set_mac_addr,
14971 .ndo_do_ioctl = tg3_ioctl,
14972 .ndo_tx_timeout = tg3_tx_timeout,
14973 .ndo_change_mtu = tg3_change_mtu,
Stephen Hemminger7c7d64b2008-11-19 22:25:36 -080014974#ifdef CONFIG_NET_POLL_CONTROLLER
14975 .ndo_poll_controller = tg3_poll_controller,
14976#endif
14977};
14978
Linus Torvalds1da177e2005-04-16 15:20:36 -070014979static int __devinit tg3_init_one(struct pci_dev *pdev,
14980 const struct pci_device_id *ent)
14981{
Linus Torvalds1da177e2005-04-16 15:20:36 -070014982 struct net_device *dev;
14983 struct tg3 *tp;
Matt Carlson646c9ed2009-09-01 12:58:41 +000014984 int i, err, pm_cap;
14985 u32 sndmbx, rcvmbx, intmbx;
Michael Chanf9804dd2005-09-27 12:13:10 -070014986 char str[40];
Michael Chan72f2afb2006-03-06 19:28:35 -080014987 u64 dma_mask, persist_dma_mask;
Michał Mirosławdc668912011-04-07 03:35:07 +000014988 u32 hw_features = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014989
Joe Perches05dbe002010-02-17 19:44:19 +000014990 printk_once(KERN_INFO "%s\n", version);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014991
14992 err = pci_enable_device(pdev);
14993 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000014994 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070014995 return err;
14996 }
14997
Linus Torvalds1da177e2005-04-16 15:20:36 -070014998 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14999 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000015000 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015001 goto err_out_disable_pdev;
15002 }
15003
15004 pci_set_master(pdev);
15005
15006 /* Find power-management capability. */
15007 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15008 if (pm_cap == 0) {
Matt Carlson2445e462010-04-05 10:19:21 +000015009 dev_err(&pdev->dev,
15010 "Cannot find Power Management capability, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015011 err = -EIO;
15012 goto err_out_free_res;
15013 }
15014
Matt Carlsonfe5f5782009-09-01 13:09:39 +000015015 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015016 if (!dev) {
Matt Carlson2445e462010-04-05 10:19:21 +000015017 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015018 err = -ENOMEM;
15019 goto err_out_free_res;
15020 }
15021
Linus Torvalds1da177e2005-04-16 15:20:36 -070015022 SET_NETDEV_DEV(dev, &pdev->dev);
15023
Linus Torvalds1da177e2005-04-16 15:20:36 -070015024 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015025
15026 tp = netdev_priv(dev);
15027 tp->pdev = pdev;
15028 tp->dev = dev;
15029 tp->pm_cap = pm_cap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015030 tp->rx_mode = TG3_DEF_RX_MODE;
15031 tp->tx_mode = TG3_DEF_TX_MODE;
Matt Carlson8ef21422008-05-02 16:47:53 -070015032
Linus Torvalds1da177e2005-04-16 15:20:36 -070015033 if (tg3_debug > 0)
15034 tp->msg_enable = tg3_debug;
15035 else
15036 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15037
15038 /* The word/byte swap controls here control register access byte
15039 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15040 * setting below.
15041 */
15042 tp->misc_host_ctrl =
15043 MISC_HOST_CTRL_MASK_PCI_INT |
15044 MISC_HOST_CTRL_WORD_SWAP |
15045 MISC_HOST_CTRL_INDIR_ACCESS |
15046 MISC_HOST_CTRL_PCISTATE_RW;
15047
15048 /* The NONFRM (non-frame) byte/word swap controls take effect
15049 * on descriptor entries, anything which isn't packet data.
15050 *
15051 * The StrongARM chips on the board (one for tx, one for rx)
15052 * are running in big-endian mode.
15053 */
15054 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15055 GRC_MODE_WSWAP_NONFRM_DATA);
15056#ifdef __BIG_ENDIAN
15057 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15058#endif
15059 spin_lock_init(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015060 spin_lock_init(&tp->indirect_lock);
David Howellsc4028952006-11-22 14:57:56 +000015061 INIT_WORK(&tp->reset_task, tg3_reset_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015062
Matt Carlsond5fe4882008-11-21 17:20:32 -080015063 tp->regs = pci_ioremap_bar(pdev, BAR_0);
Andy Gospodarekab0049b2007-09-06 20:42:14 +010015064 if (!tp->regs) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015065 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015066 err = -ENOMEM;
15067 goto err_out_free_dev;
15068 }
15069
Linus Torvalds1da177e2005-04-16 15:20:36 -070015070 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15071 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015072
Linus Torvalds1da177e2005-04-16 15:20:36 -070015073 dev->ethtool_ops = &tg3_ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015074 dev->watchdog_timeo = TG3_TX_TIMEOUT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015075 dev->irq = pdev->irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015076
15077 err = tg3_get_invariants(tp);
15078 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015079 dev_err(&pdev->dev,
15080 "Problem fetching invariants of chip, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015081 goto err_out_iounmap;
15082 }
15083
Matt Carlson615774f2009-11-13 13:03:39 +000015084 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
Matt Carlson0a58d662011-04-05 14:22:45 +000015085 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
Stephen Hemminger00829822008-11-20 20:14:53 -080015086 dev->netdev_ops = &tg3_netdev_ops;
15087 else
15088 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
15089
15090
Michael Chan4a29cc22006-03-19 13:21:12 -080015091 /* The EPB bridge inside 5714, 5715, and 5780 and any
15092 * device behind the EPB cannot support DMA addresses > 40-bit.
Michael Chan72f2afb2006-03-06 19:28:35 -080015093 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15094 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15095 * do DMA address check in tg3_start_xmit().
15096 */
Michael Chan4a29cc22006-03-19 13:21:12 -080015097 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
Yang Hongyang284901a2009-04-06 19:01:15 -070015098 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
Michael Chan4a29cc22006-03-19 13:21:12 -080015099 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
Yang Hongyang50cf1562009-04-06 19:01:14 -070015100 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
Michael Chan72f2afb2006-03-06 19:28:35 -080015101#ifdef CONFIG_HIGHMEM
Yang Hongyang6a355282009-04-06 19:01:13 -070015102 dma_mask = DMA_BIT_MASK(64);
Michael Chan72f2afb2006-03-06 19:28:35 -080015103#endif
Michael Chan4a29cc22006-03-19 13:21:12 -080015104 } else
Yang Hongyang6a355282009-04-06 19:01:13 -070015105 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
Michael Chan72f2afb2006-03-06 19:28:35 -080015106
15107 /* Configure DMA attributes. */
Yang Hongyang284901a2009-04-06 19:01:15 -070015108 if (dma_mask > DMA_BIT_MASK(32)) {
Michael Chan72f2afb2006-03-06 19:28:35 -080015109 err = pci_set_dma_mask(pdev, dma_mask);
15110 if (!err) {
15111 dev->features |= NETIF_F_HIGHDMA;
15112 err = pci_set_consistent_dma_mask(pdev,
15113 persist_dma_mask);
15114 if (err < 0) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015115 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15116 "DMA for consistent allocations\n");
Michael Chan72f2afb2006-03-06 19:28:35 -080015117 goto err_out_iounmap;
15118 }
15119 }
15120 }
Yang Hongyang284901a2009-04-06 19:01:15 -070015121 if (err || dma_mask == DMA_BIT_MASK(32)) {
15122 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Michael Chan72f2afb2006-03-06 19:28:35 -080015123 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015124 dev_err(&pdev->dev,
15125 "No usable DMA configuration, aborting\n");
Michael Chan72f2afb2006-03-06 19:28:35 -080015126 goto err_out_iounmap;
15127 }
15128 }
15129
Michael Chanfdfec1722005-07-25 12:31:48 -070015130 tg3_init_bufmgr_config(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015131
Matt Carlson507399f2009-11-13 13:03:37 +000015132 /* Selectively allow TSO based on operating conditions */
15133 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
15134 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
15135 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
15136 else {
15137 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
15138 tp->fw_needed = NULL;
15139 }
15140
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080015141 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
Matt Carlson9e9fd122009-01-19 16:57:45 -080015142 tp->fw_needed = FIRMWARE_TG3;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080015143
Michael Chan4e3a7aa2006-03-20 17:47:44 -080015144 /* TSO is on by default on chips that support hardware TSO.
15145 * Firmware TSO on older chips gives lower performance, so it
15146 * is off by default, but can be enabled using ethtool.
15147 */
Matt Carlsone849cdc2009-11-13 13:03:38 +000015148 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
Michał Mirosławdc668912011-04-07 03:35:07 +000015149 (dev->features & NETIF_F_IP_CSUM))
15150 hw_features |= NETIF_F_TSO;
Matt Carlsone849cdc2009-11-13 13:03:38 +000015151 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
15152 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
Michał Mirosławdc668912011-04-07 03:35:07 +000015153 if (dev->features & NETIF_F_IPV6_CSUM)
15154 hw_features |= NETIF_F_TSO6;
Matt Carlsone849cdc2009-11-13 13:03:38 +000015155 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
15156 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson57e69832008-05-25 23:48:31 -070015157 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15158 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
Matt Carlson321d32a2008-11-21 17:22:19 -080015159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Michał Mirosławdc668912011-04-07 03:35:07 +000015160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15161 hw_features |= NETIF_F_TSO_ECN;
Michael Chanb0026622006-07-03 19:42:14 -070015162 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015163
Michał Mirosławdc668912011-04-07 03:35:07 +000015164 dev->hw_features |= hw_features;
15165 dev->features |= hw_features;
15166 dev->vlan_features |= hw_features;
15167
Linus Torvalds1da177e2005-04-16 15:20:36 -070015168 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15169 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
15170 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15171 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
15172 tp->rx_pending = 63;
15173 }
15174
Linus Torvalds1da177e2005-04-16 15:20:36 -070015175 err = tg3_get_device_address(tp);
15176 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015177 dev_err(&pdev->dev,
15178 "Could not obtain valid ethernet address, aborting\n");
Matt Carlson026a6c22009-12-03 08:36:24 +000015179 goto err_out_iounmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015180 }
15181
Matt Carlson0d3031d2007-10-10 18:02:43 -070015182 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
Matt Carlson63532392008-11-03 16:49:57 -080015183 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
Al Viro79ea13c2008-01-24 02:06:46 -080015184 if (!tp->aperegs) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015185 dev_err(&pdev->dev,
15186 "Cannot map APE registers, aborting\n");
Matt Carlson0d3031d2007-10-10 18:02:43 -070015187 err = -ENOMEM;
Matt Carlson026a6c22009-12-03 08:36:24 +000015188 goto err_out_iounmap;
Matt Carlson0d3031d2007-10-10 18:02:43 -070015189 }
15190
15191 tg3_ape_lock_init(tp);
Matt Carlson7fd76442009-02-25 14:27:20 +000015192
15193 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
15194 tg3_read_dash_ver(tp);
Matt Carlson0d3031d2007-10-10 18:02:43 -070015195 }
15196
Matt Carlsonc88864d2007-11-12 21:07:01 -080015197 /*
15198 * Reset chip in case UNDI or EFI driver did not shutdown
15199 * DMA self test will enable WDMAC and we'll see (spurious)
15200 * pending DMA on the PCI bus at that point.
15201 */
15202 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15203 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15204 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15205 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15206 }
15207
15208 err = tg3_test_dma(tp);
15209 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015210 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
Matt Carlsonc88864d2007-11-12 21:07:01 -080015211 goto err_out_apeunmap;
15212 }
15213
Matt Carlson78f90dc2009-11-13 13:03:42 +000015214 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15215 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15216 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
Matt Carlson6fd45cb2010-09-15 08:59:57 +000015217 for (i = 0; i < tp->irq_max; i++) {
Matt Carlson78f90dc2009-11-13 13:03:42 +000015218 struct tg3_napi *tnapi = &tp->napi[i];
15219
15220 tnapi->tp = tp;
15221 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15222
15223 tnapi->int_mbox = intmbx;
15224 if (i < 4)
15225 intmbx += 0x8;
15226 else
15227 intmbx += 0x4;
15228
15229 tnapi->consmbox = rcvmbx;
15230 tnapi->prodmbox = sndmbx;
15231
Matt Carlson66cfd1b2010-09-30 10:34:30 +000015232 if (i)
Matt Carlson78f90dc2009-11-13 13:03:42 +000015233 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
Matt Carlson66cfd1b2010-09-30 10:34:30 +000015234 else
Matt Carlson78f90dc2009-11-13 13:03:42 +000015235 tnapi->coal_now = HOSTCC_MODE_NOW;
Matt Carlson78f90dc2009-11-13 13:03:42 +000015236
15237 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
15238 break;
15239
15240 /*
15241 * If we support MSIX, we'll be using RSS. If we're using
15242 * RSS, the first vector only handles link interrupts and the
15243 * remaining vectors handle rx and tx interrupts. Reuse the
15244 * mailbox values for the next iteration. The values we setup
15245 * above are still useful for the single vectored mode.
15246 */
15247 if (!i)
15248 continue;
15249
15250 rcvmbx += 0x8;
15251
15252 if (sndmbx & 0x4)
15253 sndmbx -= 0x4;
15254 else
15255 sndmbx += 0xc;
15256 }
15257
Matt Carlsonc88864d2007-11-12 21:07:01 -080015258 tg3_init_coal(tp);
15259
Michael Chanc49a1562006-12-17 17:07:29 -080015260 pci_set_drvdata(pdev, dev);
15261
Linus Torvalds1da177e2005-04-16 15:20:36 -070015262 err = register_netdev(dev);
15263 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015264 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
Matt Carlson0d3031d2007-10-10 18:02:43 -070015265 goto err_out_apeunmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015266 }
15267
Joe Perches05dbe002010-02-17 19:44:19 +000015268 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15269 tp->board_part_number,
15270 tp->pci_chip_rev_id,
15271 tg3_bus_string(tp, str),
15272 dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015273
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015274 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000015275 struct phy_device *phydev;
15276 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlson5129c3a2010-04-05 10:19:23 +000015277 netdev_info(dev,
15278 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
Joe Perches05dbe002010-02-17 19:44:19 +000015279 phydev->drv->name, dev_name(&phydev->dev));
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015280 } else {
15281 char *ethtype;
15282
15283 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15284 ethtype = "10/100Base-TX";
15285 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15286 ethtype = "1000Base-SX";
15287 else
15288 ethtype = "10/100/1000Base-T";
15289
Matt Carlson5129c3a2010-04-05 10:19:23 +000015290 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015291 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
15292 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
15293 }
Matt Carlsondf59c942008-11-03 16:52:56 -080015294
Joe Perches05dbe002010-02-17 19:44:19 +000015295 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
Michał Mirosławdc668912011-04-07 03:35:07 +000015296 (dev->features & NETIF_F_RXCSUM) != 0,
Joe Perches05dbe002010-02-17 19:44:19 +000015297 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015298 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
Joe Perches05dbe002010-02-17 19:44:19 +000015299 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
15300 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
15301 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15302 tp->dma_rwctrl,
15303 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15304 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015305
15306 return 0;
15307
Matt Carlson0d3031d2007-10-10 18:02:43 -070015308err_out_apeunmap:
15309 if (tp->aperegs) {
15310 iounmap(tp->aperegs);
15311 tp->aperegs = NULL;
15312 }
15313
Linus Torvalds1da177e2005-04-16 15:20:36 -070015314err_out_iounmap:
Michael Chan68929142005-08-09 20:17:14 -070015315 if (tp->regs) {
15316 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070015317 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070015318 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015319
15320err_out_free_dev:
15321 free_netdev(dev);
15322
15323err_out_free_res:
15324 pci_release_regions(pdev);
15325
15326err_out_disable_pdev:
15327 pci_disable_device(pdev);
15328 pci_set_drvdata(pdev, NULL);
15329 return err;
15330}
15331
15332static void __devexit tg3_remove_one(struct pci_dev *pdev)
15333{
15334 struct net_device *dev = pci_get_drvdata(pdev);
15335
15336 if (dev) {
15337 struct tg3 *tp = netdev_priv(dev);
15338
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080015339 if (tp->fw)
15340 release_firmware(tp->fw);
15341
Tejun Heo23f333a2010-12-12 16:45:14 +010015342 cancel_work_sync(&tp->reset_task);
Matt Carlson158d7ab2008-05-29 01:37:54 -070015343
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015344 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15345 tg3_phy_fini(tp);
Matt Carlson158d7ab2008-05-29 01:37:54 -070015346 tg3_mdio_fini(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015347 }
Matt Carlson158d7ab2008-05-29 01:37:54 -070015348
Linus Torvalds1da177e2005-04-16 15:20:36 -070015349 unregister_netdev(dev);
Matt Carlson0d3031d2007-10-10 18:02:43 -070015350 if (tp->aperegs) {
15351 iounmap(tp->aperegs);
15352 tp->aperegs = NULL;
15353 }
Michael Chan68929142005-08-09 20:17:14 -070015354 if (tp->regs) {
15355 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070015356 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070015357 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015358 free_netdev(dev);
15359 pci_release_regions(pdev);
15360 pci_disable_device(pdev);
15361 pci_set_drvdata(pdev, NULL);
15362 }
15363}
15364
Eric Dumazetaa6027c2011-01-01 05:22:46 +000015365#ifdef CONFIG_PM_SLEEP
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015366static int tg3_suspend(struct device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015367{
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015368 struct pci_dev *pdev = to_pci_dev(device);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015369 struct net_device *dev = pci_get_drvdata(pdev);
15370 struct tg3 *tp = netdev_priv(dev);
15371 int err;
15372
15373 if (!netif_running(dev))
15374 return 0;
15375
Tejun Heo23f333a2010-12-12 16:45:14 +010015376 flush_work_sync(&tp->reset_task);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015377 tg3_phy_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015378 tg3_netif_stop(tp);
15379
15380 del_timer_sync(&tp->timer);
15381
David S. Millerf47c11e2005-06-24 20:18:35 -070015382 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015383 tg3_disable_ints(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -070015384 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015385
15386 netif_device_detach(dev);
15387
David S. Millerf47c11e2005-06-24 20:18:35 -070015388 tg3_full_lock(tp, 0);
Michael Chan944d9802005-05-29 14:57:48 -070015389 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chan6a9eba12005-12-13 21:08:58 -080015390 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
David S. Millerf47c11e2005-06-24 20:18:35 -070015391 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015392
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015393 err = tg3_power_down_prepare(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015394 if (err) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015395 int err2;
15396
David S. Millerf47c11e2005-06-24 20:18:35 -070015397 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015398
Michael Chan6a9eba12005-12-13 21:08:58 -080015399 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015400 err2 = tg3_restart_hw(tp, 1);
15401 if (err2)
Michael Chanb9ec6c12006-07-25 16:37:27 -070015402 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015403
15404 tp->timer.expires = jiffies + tp->timer_offset;
15405 add_timer(&tp->timer);
15406
15407 netif_device_attach(dev);
15408 tg3_netif_start(tp);
15409
Michael Chanb9ec6c12006-07-25 16:37:27 -070015410out:
David S. Millerf47c11e2005-06-24 20:18:35 -070015411 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015412
15413 if (!err2)
15414 tg3_phy_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015415 }
15416
15417 return err;
15418}
15419
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015420static int tg3_resume(struct device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015421{
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015422 struct pci_dev *pdev = to_pci_dev(device);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015423 struct net_device *dev = pci_get_drvdata(pdev);
15424 struct tg3 *tp = netdev_priv(dev);
15425 int err;
15426
15427 if (!netif_running(dev))
15428 return 0;
15429
Linus Torvalds1da177e2005-04-16 15:20:36 -070015430 netif_device_attach(dev);
15431
David S. Millerf47c11e2005-06-24 20:18:35 -070015432 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015433
Michael Chan6a9eba12005-12-13 21:08:58 -080015434 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
Michael Chanb9ec6c12006-07-25 16:37:27 -070015435 err = tg3_restart_hw(tp, 1);
15436 if (err)
15437 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015438
15439 tp->timer.expires = jiffies + tp->timer_offset;
15440 add_timer(&tp->timer);
15441
Linus Torvalds1da177e2005-04-16 15:20:36 -070015442 tg3_netif_start(tp);
15443
Michael Chanb9ec6c12006-07-25 16:37:27 -070015444out:
David S. Millerf47c11e2005-06-24 20:18:35 -070015445 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015446
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015447 if (!err)
15448 tg3_phy_start(tp);
15449
Michael Chanb9ec6c12006-07-25 16:37:27 -070015450 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015451}
15452
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015453static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
Eric Dumazetaa6027c2011-01-01 05:22:46 +000015454#define TG3_PM_OPS (&tg3_pm_ops)
15455
15456#else
15457
15458#define TG3_PM_OPS NULL
15459
15460#endif /* CONFIG_PM_SLEEP */
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015461
Linus Torvalds1da177e2005-04-16 15:20:36 -070015462static struct pci_driver tg3_driver = {
15463 .name = DRV_MODULE_NAME,
15464 .id_table = tg3_pci_tbl,
15465 .probe = tg3_init_one,
15466 .remove = __devexit_p(tg3_remove_one),
Eric Dumazetaa6027c2011-01-01 05:22:46 +000015467 .driver.pm = TG3_PM_OPS,
Linus Torvalds1da177e2005-04-16 15:20:36 -070015468};
15469
15470static int __init tg3_init(void)
15471{
Jeff Garzik29917622006-08-19 17:48:59 -040015472 return pci_register_driver(&tg3_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015473}
15474
15475static void __exit tg3_cleanup(void)
15476{
15477 pci_unregister_driver(&tg3_driver);
15478}
15479
15480module_init(tg3_init);
15481module_exit(tg3_cleanup);