| Huang Rui | 0e5ca0d | 2017-03-03 18:37:23 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Author: Huang Rui |
| 23 | * |
| 24 | */ |
| 25 | #ifndef __AMDGPU_PSP_H__ |
| 26 | #define __AMDGPU_PSP_H__ |
| 27 | |
| 28 | #include "amdgpu.h" |
| 29 | #include "psp_gfx_if.h" |
| 30 | |
| 31 | #define PSP_FENCE_BUFFER_SIZE 0x1000 |
| 32 | #define PSP_CMD_BUFFER_SIZE 0x1000 |
| 33 | #define PSP_ASD_BIN_SIZE 0x40000 |
| 34 | #define PSP_ASD_SHARED_MEM_SIZE 0x4000 |
| 35 | |
| 36 | enum psp_ring_type |
| 37 | { |
| 38 | PSP_RING_TYPE__INVALID = 0, |
| 39 | /* |
| 40 | * These values map to the way the PSP kernel identifies the |
| 41 | * rings. |
| 42 | */ |
| 43 | PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ |
| 44 | PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ |
| 45 | }; |
| 46 | |
| 47 | struct psp_ring |
| 48 | { |
| 49 | enum psp_ring_type ring_type; |
| 50 | struct psp_gfx_rb_frame *ring_mem; |
| 51 | uint64_t ring_mem_mc_addr; |
| 52 | void *ring_mem_handle; |
| 53 | uint32_t ring_size; |
| 54 | }; |
| 55 | |
| 56 | struct psp_context |
| 57 | { |
| 58 | struct amdgpu_device *adev; |
| 59 | struct psp_ring km_ring; |
| 60 | |
| 61 | int (*init_microcode)(struct psp_context *psp); |
| 62 | int (*bootloader_load_sysdrv)(struct psp_context *psp); |
| 63 | int (*bootloader_load_sos)(struct psp_context *psp); |
| 64 | int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode, |
| 65 | struct psp_gfx_cmd_resp *cmd); |
| 66 | int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); |
| 67 | int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode, |
| 68 | uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index); |
| 69 | bool (*compare_sram_data)(struct psp_context *psp, |
| 70 | struct amdgpu_firmware_info *ucode, |
| 71 | enum AMDGPU_UCODE_ID ucode_type); |
| 72 | bool (*smu_reload_quirk)(struct psp_context *psp); |
| 73 | |
| 74 | /* sos firmware */ |
| 75 | const struct firmware *sos_fw; |
| 76 | uint32_t sos_fw_version; |
| 77 | uint32_t sos_feature_version; |
| 78 | uint32_t sys_bin_size; |
| 79 | uint32_t sos_bin_size; |
| 80 | uint8_t *sys_start_addr; |
| 81 | uint8_t *sos_start_addr; |
| 82 | |
| 83 | /* tmr buffer */ |
| 84 | struct amdgpu_bo *tmr_bo; |
| 85 | uint64_t tmr_mc_addr; |
| 86 | void *tmr_buf; |
| 87 | |
| 88 | /* asd firmware */ |
| 89 | const struct firmware *asd_fw; |
| 90 | uint32_t asd_fw_version; |
| 91 | uint32_t asd_feature_version; |
| 92 | uint32_t asd_ucode_size; |
| 93 | uint8_t *asd_start_addr; |
| 94 | |
| 95 | /* fence buffer */ |
| 96 | struct amdgpu_bo *fence_buf_bo; |
| 97 | uint64_t fence_buf_mc_addr; |
| 98 | void *fence_buf; |
| 99 | }; |
| 100 | |
| 101 | struct amdgpu_psp_funcs { |
| 102 | bool (*check_fw_loading_status)(struct amdgpu_device *adev, |
| 103 | enum AMDGPU_UCODE_ID); |
| 104 | }; |
| 105 | |
| 106 | #define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type)) |
| 107 | #define psp_ring_init(psp, type) (psp)->ring_init((psp), (type)) |
| 108 | #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ |
| 109 | (psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) |
| 110 | #define psp_compare_sram_data(psp, ucode, type) \ |
| 111 | (psp)->compare_sram_data((psp), (ucode), (type)) |
| 112 | #define psp_init_microcode(psp) \ |
| 113 | ((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0) |
| 114 | #define psp_bootloader_load_sysdrv(psp) \ |
| 115 | ((psp)->bootloader_load_sysdrv ? (psp)->bootloader_load_sysdrv((psp)) : 0) |
| 116 | #define psp_bootloader_load_sos(psp) \ |
| 117 | ((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0) |
| 118 | #define psp_smu_reload_quirk(psp) \ |
| 119 | ((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false) |
| 120 | |
| 121 | extern const struct amd_ip_funcs psp_ip_funcs; |
| 122 | |
| 123 | extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; |
| 124 | extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, |
| 125 | uint32_t field_val, uint32_t mask, bool check_changed); |
| 126 | |
| 127 | #endif |