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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010044#include <linux/list.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020045#include <net/switchdev.h>
Jiri Pirkoc4745502016-02-26 17:32:26 +010046#include <net/devlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020047
Elad Raz3a49b4f2016-01-10 21:06:28 +010048#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020049#include "core.h"
50
51#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */
53#define MLXSW_SP_VFID_BR_MAX 8192 /* Bridged VLAN interfaces */
54#define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX)
55
Jiri Pirko0d65fc12015-12-03 12:12:28 +010056#define MLXSW_SP_LAG_MAX 64
57#define MLXSW_SP_PORT_PER_LAG_MAX 16
Jiri Pirko56ade8f2015-10-16 14:01:37 +020058
Elad Raz53ae6282016-01-10 21:06:26 +010059#define MLXSW_SP_MID_MAX 7000
60
Ido Schimmel18f1e702016-02-26 17:32:31 +010061#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
62
63#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
64
Jiri Pirko56ade8f2015-10-16 14:01:37 +020065struct mlxsw_sp_port;
66
Jiri Pirko0d65fc12015-12-03 12:12:28 +010067struct mlxsw_sp_upper {
68 struct net_device *dev;
69 unsigned int ref_count;
70};
71
Ido Schimmel7f71eb42015-12-15 16:03:37 +010072struct mlxsw_sp_vfid {
73 struct list_head list;
74 u16 nr_vports;
75 u16 vfid; /* Starting at 0 */
Ido Schimmel26f0e7f2015-12-15 16:03:44 +010076 struct net_device *br_dev;
Ido Schimmel7f71eb42015-12-15 16:03:37 +010077 u16 vid;
78};
79
Elad Raz3a49b4f2016-01-10 21:06:28 +010080struct mlxsw_sp_mid {
81 struct list_head list;
82 unsigned char addr[ETH_ALEN];
83 u16 vid;
84 u16 mid;
85 unsigned int ref_count;
86};
87
Ido Schimmel7f71eb42015-12-15 16:03:37 +010088static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
89{
90 return MLXSW_SP_VFID_BASE + vfid;
91}
92
Ido Schimmelaac78a42015-12-15 16:03:42 +010093static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
94{
95 return fid - MLXSW_SP_VFID_BASE;
96}
97
98static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
99{
100 return fid >= MLXSW_SP_VFID_BASE;
101}
102
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200103struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100104 struct {
105 struct list_head list;
106 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_VFID_PORT_MAX)];
107 } port_vfids;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100108 struct {
109 struct list_head list;
110 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_VFID_BR_MAX)];
111 } br_vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100112 struct {
113 struct list_head list;
114 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_MID_MAX)];
115 } br_mids;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200116 unsigned long active_fids[BITS_TO_LONGS(VLAN_N_VID)];
117 struct mlxsw_sp_port **ports;
118 struct mlxsw_core *core;
119 const struct mlxsw_bus_info *bus_info;
120 unsigned char base_mac[ETH_ALEN];
121 struct {
122 struct delayed_work dw;
123#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
124 unsigned int interval; /* ms */
125 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800126#define MLXSW_SP_MIN_AGEING_TIME 10
127#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200128#define MLXSW_SP_DEFAULT_AGEING_TIME 300
129 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100130 struct mlxsw_sp_upper master_bridge;
131 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
Ido Schimmel558c2d52016-02-26 17:32:29 +0100132 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200133};
134
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100135static inline struct mlxsw_sp_upper *
136mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
137{
138 return &mlxsw_sp->lags[lag_id];
139}
140
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200141struct mlxsw_sp_port_pcpu_stats {
142 u64 rx_packets;
143 u64 rx_bytes;
144 u64 tx_packets;
145 u64 tx_bytes;
146 struct u64_stats_sync syncp;
147 u32 tx_dropped;
148};
149
150struct mlxsw_sp_port {
151 struct net_device *dev;
152 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
153 struct mlxsw_sp *mlxsw_sp;
154 u8 local_port;
155 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100156 u8 learning:1,
157 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100158 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100159 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100160 lagged:1,
161 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200162 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100163 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100164 struct {
165 struct list_head list;
166 struct mlxsw_sp_vfid *vfid;
167 u16 vid;
168 } vport;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200169 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100170 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100171 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200172 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100173 struct list_head vports_list;
Jiri Pirkoc4745502016-02-26 17:32:26 +0100174 struct devlink_port devlink_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200175};
176
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100177static inline struct mlxsw_sp_port *
178mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
179{
180 struct mlxsw_sp_port *mlxsw_sp_port;
181 u8 local_port;
182
183 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
184 lag_id, port_index);
185 mlxsw_sp_port = mlxsw_sp->ports[local_port];
186 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
187}
188
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100189static inline bool
190mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
191{
192 return mlxsw_sp_port->vport.vfid;
193}
194
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100195static inline struct net_device *
196mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
197{
198 return mlxsw_sp_vport->vport.vfid->br_dev;
199}
200
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100201static inline u16
202mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
203{
204 return mlxsw_sp_vport->vport.vid;
205}
206
207static inline u16
208mlxsw_sp_vport_vfid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
209{
210 return mlxsw_sp_vport->vport.vfid->vfid;
211}
212
213static inline struct mlxsw_sp_port *
214mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
215{
216 struct mlxsw_sp_port *mlxsw_sp_vport;
217
218 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
219 vport.list) {
220 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
221 return mlxsw_sp_vport;
222 }
223
224 return NULL;
225}
226
Ido Schimmelaac78a42015-12-15 16:03:42 +0100227static inline struct mlxsw_sp_port *
228mlxsw_sp_port_vport_find_by_vfid(const struct mlxsw_sp_port *mlxsw_sp_port,
229 u16 vfid)
230{
231 struct mlxsw_sp_port *mlxsw_sp_vport;
232
233 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
234 vport.list) {
235 if (mlxsw_sp_vport_vfid_get(mlxsw_sp_vport) == vfid)
236 return mlxsw_sp_vport;
237 }
238
239 return NULL;
240}
241
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200242enum mlxsw_sp_flood_table {
243 MLXSW_SP_FLOOD_TABLE_UC,
244 MLXSW_SP_FLOOD_TABLE_BM,
245};
246
247int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
248int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
249
250int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
251void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
252int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
253void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
254void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
255int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
256 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
257 u16 vid);
258int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
259 u16 vid_end, bool is_member, bool untagged);
260int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
261 u16 vid);
262int mlxsw_sp_port_kill_vid(struct net_device *dev,
263 __be16 __always_unused proto, u16 vid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100264int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 vfid,
Ido Schimmel19ae6122015-12-15 16:03:39 +0100265 bool set, bool only_uc);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100266void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100267int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200268
269#endif