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gerrit-public.fairphone.software / kernel / msm-5.4 / b5d903c2d656e9bc54bc76554a477d796a63120d / . / arch / nds32 / Kconfig.cpu
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Greentime Hue71ea3b2017-10-25 15:03:49 +0800[diff] [blame]1comment "Processor Features"
2
3config CPU_BIG_ENDIAN
Greentime Hub3b112b2018-04-19 16:26:43 +0800[diff] [blame]4 def_bool !CPU_LITTLE_ENDIAN
Greentime Hue71ea3b2017-10-25 15:03:49 +0800[diff] [blame]5
6config CPU_LITTLE_ENDIAN
Greentime Hub3b112b2018-04-19 16:26:43 +0800[diff] [blame]7 bool "Little endian"
8 default y
Greentime Hue71ea3b2017-10-25 15:03:49 +0800[diff] [blame]9
10config HWZOL
11 bool "hardware zero overhead loop support"
12 depends on CPU_D10 || CPU_D15
13 default n
14 help
15 A set of Zero-Overhead Loop mechanism is provided to reduce the
16 instruction fetch and execution overhead of loop-control instructions.
17 It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
18 You don't need to save these registers if you can make sure your user
19 program doesn't use these registers.
20
21 If unsure, say N.
22
23config CPU_CACHE_ALIASING
24 bool "Aliasing cache"
25 depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
26 default y
27 help
28 If this CPU is using VIPT data cache and its cache way size is larger
29 than page size, say Y. If it is using PIPT data cache, say N.
30
31 If unsure, say Y.
32
33choice
34 prompt "minimum CPU type"
35 default CPU_V3
36 help
37 The data cache of N15/D15 is implemented as PIPT and it will not cause
38 the cache aliasing issue. The rest cpus(N13, N10 and D10) are
39 implemented as VIPT data cache. It may cause the cache aliasing issue
40 if its cache way size is larger than page size. You can specify the
41 CPU type direcly or choose CPU_V3 if unsure.
42
43 A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
44 A kernel built for N15 is able to run on N15 or D15.
45 A kernel built for D10 is able to run on D10 or D15.
46 A kernel built for D15 is able to run on D15.
47 A kernel built for N13 is able to run on N15, N13 or D15.
48
49config CPU_N15
50 bool "AndesCore N15"
51config CPU_N13
52 bool "AndesCore N13"
53 select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
54config CPU_N10
55 bool "AndesCore N10"
56 select CPU_CACHE_ALIASING
57config CPU_D15
58 bool "AndesCore D15"
59config CPU_D10
60 bool "AndesCore D10"
61 select CPU_CACHE_ALIASING
62config CPU_V3
63 bool "AndesCore v3 compatible"
64 select CPU_CACHE_ALIASING
65endchoice
66choice
67 prompt "Paging -- page size "
68 default ANDES_PAGE_SIZE_4KB
69config ANDES_PAGE_SIZE_4KB
70 bool "use 4KB page size"
71config ANDES_PAGE_SIZE_8KB
72 bool "use 8KB page size"
73endchoice
74
75config CPU_ICACHE_DISABLE
76 bool "Disable I-Cache"
77 help
78 Say Y here to disable the processor instruction cache. Unless
79 you have a reason not to or are unsure, say N.
80
81config CPU_DCACHE_DISABLE
82 bool "Disable D-Cache"
83 help
84 Say Y here to disable the processor data cache. Unless
85 you have a reason not to or are unsure, say N.
86
87config CPU_DCACHE_WRITETHROUGH
88 bool "Force write through D-cache"
89 depends on !CPU_DCACHE_DISABLE
90 help
91 Say Y here to use the data cache in writethrough mode. Unless you
92 specifically require this or are unsure, say N.
93
94config WBNA
95 bool "WBNA"
96 default n
97 help
98 Say Y here to enable write-back memory with no-write-allocation policy.
99
100config ALIGNMENT_TRAP
101 bool "Kernel support unaligned access handling by sw"
102 depends on PROC_FS
103 default n
104 help
105 Andes processors cannot load/store information which is not
106 naturally aligned on the bus, i.e., a 4 byte load must start at an
107 address divisible by 4. On 32-bit Andes processors, these non-aligned
108 load/store instructions will be emulated in software if you say Y
109 here, which has a severe performance impact. With an IP-only
110 configuration it is safe to say N, otherwise say Y.
111
112config HW_SUPPORT_UNALIGNMENT_ACCESS
113 bool "Kernel support unaligned access handling by hw"
114 depends on !ALIGNMENT_TRAP
115 default n
116 help
117 Andes processors load/store world/half-word instructions can access
118 unaligned memory locations without generating the Data Alignment
119 Check exceptions. With an IP-only configuration it is safe to say N,
120 otherwise say Y.
121
122config HIGHMEM
123 bool "High Memory Support"
124 depends on MMU && !CPU_CACHE_ALIASING
125 help
126 The address space of Andes processors is only 4 Gigabytes large
127 and it has to accommodate user address space, kernel address
128 space as well as some memory mapped IO. That means that, if you
129 have a large amount of physical memory and/or IO, not all of the
130 memory can be "permanently mapped" by the kernel. The physical
131 memory that is not permanently mapped is called "high memory".
132
133 Depending on the selected kernel/user memory split, minimum
134 vmalloc space and actual amount of RAM, you may not need this
135 option which should result in a slightly faster kernel.
136
137 If unsure, say N.
138
139config CACHE_L2
140 bool "Support L2 cache"
141 default y
142 help
143 Say Y here to enable L2 cache if your SoC are integrated with L2CC.
144 If unsure, say N.
145
146menu "Memory configuration"
147
148choice
149 prompt "Memory split"
150 depends on MMU
151 default VMSPLIT_3G_OPT
152 help
153 Select the desired split between kernel and user memory.
154
155 If you are not absolutely sure what you are doing, leave this
156 option alone!
157
158 config VMSPLIT_3G
159 bool "3G/1G user/kernel split"
160 config VMSPLIT_3G_OPT
161 bool "3G/1G user/kernel split (for full 1G low memory)"
162 config VMSPLIT_2G
163 bool "2G/2G user/kernel split"
164 config VMSPLIT_1G
165 bool "1G/3G user/kernel split"
166endchoice
167
168config PAGE_OFFSET
169 hex
170 default 0x40000000 if VMSPLIT_1G
171 default 0x80000000 if VMSPLIT_2G
172 default 0xB0000000 if VMSPLIT_3G_OPT
173 default 0xC0000000
174
175endmenu