blob: ef174748825f3288f58b8d89d0a041b28a109a14 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/***************************************************************************/
2
3/*
Greg Ungererb671b652006-06-26 10:33:10 +10004 * pit.c -- Freescale ColdFire PIT timer. Currently this type of
5 * hardware timer only exists in the Freescale ColdFire
Greg Ungererf15bf192005-11-07 14:09:50 +10006 * 5270/5271, 5282 and other CPUs.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Greg Ungererb671b652006-06-26 10:33:10 +10008 * Copyright (C) 1999-2006, Greg Ungerer (gerg@snapgear.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
10 *
11 */
12
13/***************************************************************************/
14
15#include <linux/config.h>
16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/param.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
Greg Ungererb671b652006-06-26 10:33:10 +100021#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/irq.h>
23#include <asm/coldfire.h>
24#include <asm/mcfpit.h>
25#include <asm/mcfsim.h>
26
27/***************************************************************************/
28
Greg Ungererb671b652006-06-26 10:33:10 +100029/*
30 * By default use timer1 as the system clock timer.
31 */
32#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
33
34/***************************************************************************/
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036void coldfire_pit_tick(void)
37{
Greg Ungererb671b652006-06-26 10:33:10 +100038 unsigned short pcsr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
40 /* Reset the ColdFire timer */
Greg Ungererb671b652006-06-26 10:33:10 +100041 pcsr = __raw_readw(TA(MCFPIT_PCSR));
42 __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
Linus Torvalds1da177e2005-04-16 15:20:36 -070043}
44
45/***************************************************************************/
46
47void coldfire_pit_init(irqreturn_t (*handler)(int, void *, struct pt_regs *))
48{
49 volatile unsigned char *icrp;
50 volatile unsigned long *imrp;
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52 request_irq(MCFINT_VECBASE + MCFINT_PIT1, handler, SA_INTERRUPT,
53 "ColdFire Timer", NULL);
54
55 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
56 MCFINTC_ICR0 + MCFINT_PIT1);
Greg Ungererf15bf192005-11-07 14:09:50 +100057 *icrp = ICR_INTRCONF;
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
Greg Ungererf15bf192005-11-07 14:09:50 +100059 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
60 *imrp &= ~MCFPIT_IMR_IBIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
62 /* Set up PIT timer 1 as poll clock */
Greg Ungererb671b652006-06-26 10:33:10 +100063 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
64 __raw_writew(((MCF_CLK / 2) / 64) / HZ, TA(MCFPIT_PMR));
65 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW |
66 MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
Linus Torvalds1da177e2005-04-16 15:20:36 -070067}
68
69/***************************************************************************/
70
71unsigned long coldfire_pit_offset(void)
72{
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 volatile unsigned long *ipr;
74 unsigned long pmr, pcntr, offset;
75
Greg Ungererf15bf192005-11-07 14:09:50 +100076 ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
Greg Ungererb671b652006-06-26 10:33:10 +100078 pmr = __raw_readw(TA(MCFPIT_PMR));
79 pcntr = __raw_readw(TA(MCFPIT_PCNTR));
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
81 /*
82 * If we are still in the first half of the upcount and a
83 * timer interupt is pending, then add on a ticks worth of time.
84 */
85 offset = ((pmr - pcntr) * (1000000 / HZ)) / pmr;
Greg Ungererf15bf192005-11-07 14:09:50 +100086 if ((offset < (1000000 / HZ / 2)) && (*ipr & MCFPIT_IMR_IBIT))
Linus Torvalds1da177e2005-04-16 15:20:36 -070087 offset += 1000000 / HZ;
88 return offset;
89}
90
91/***************************************************************************/