Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2017 Sean Wang <sean.wang@mediatek.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include <dt-bindings/input/input.h> |
| 9 | #include "mt7623.dtsi" |
| 10 | #include "mt6323.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "Bananapi BPI-R2"; |
| 14 | compatible = "bananapi,bpi-r2", "mediatek,mt7623"; |
| 15 | |
| 16 | aliases { |
| 17 | serial2 = &uart2; |
| 18 | }; |
| 19 | |
| 20 | chosen { |
| 21 | stdout-path = "serial2:115200n8"; |
| 22 | }; |
| 23 | |
| 24 | cpus { |
| 25 | cpu@0 { |
| 26 | proc-supply = <&mt6323_vproc_reg>; |
| 27 | }; |
| 28 | |
| 29 | cpu@1 { |
| 30 | proc-supply = <&mt6323_vproc_reg>; |
| 31 | }; |
| 32 | |
| 33 | cpu@2 { |
| 34 | proc-supply = <&mt6323_vproc_reg>; |
| 35 | }; |
| 36 | |
| 37 | cpu@3 { |
| 38 | proc-supply = <&mt6323_vproc_reg>; |
| 39 | }; |
| 40 | }; |
| 41 | |
| 42 | gpio_keys { |
| 43 | compatible = "gpio-keys"; |
| 44 | pinctrl-names = "default"; |
| 45 | pinctrl-0 = <&key_pins_a>; |
| 46 | |
| 47 | factory { |
| 48 | label = "factory"; |
| 49 | linux,code = <BTN_0>; |
| 50 | gpios = <&pio 256 GPIO_ACTIVE_LOW>; |
| 51 | }; |
| 52 | |
| 53 | wps { |
| 54 | label = "wps"; |
| 55 | linux,code = <KEY_WPS_BUTTON>; |
| 56 | gpios = <&pio 257 GPIO_ACTIVE_HIGH>; |
| 57 | }; |
| 58 | }; |
| 59 | |
| 60 | leds { |
| 61 | compatible = "gpio-leds"; |
| 62 | pinctrl-names = "default"; |
| 63 | pinctrl-0 = <&led_pins_a>; |
| 64 | |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 65 | blue { |
| 66 | label = "bpi-r2:pio:blue"; |
| 67 | gpios = <&pio 241 GPIO_ACTIVE_HIGH>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 68 | default-state = "off"; |
| 69 | }; |
| 70 | |
| 71 | green { |
| 72 | label = "bpi-r2:pio:green"; |
| 73 | gpios = <&pio 240 GPIO_ACTIVE_HIGH>; |
| 74 | default-state = "off"; |
| 75 | }; |
| 76 | |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 77 | red { |
| 78 | label = "bpi-r2:pio:red"; |
| 79 | gpios = <&pio 239 GPIO_ACTIVE_HIGH>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 80 | default-state = "off"; |
| 81 | }; |
| 82 | }; |
| 83 | |
| 84 | memory@80000000 { |
| 85 | reg = <0 0x80000000 0 0x40000000>; |
| 86 | }; |
| 87 | }; |
| 88 | |
| 89 | &cir { |
| 90 | pinctrl-names = "default"; |
| 91 | pinctrl-0 = <&cir_pins_a>; |
| 92 | status = "okay"; |
| 93 | }; |
| 94 | |
| 95 | &crypto { |
| 96 | status = "okay"; |
| 97 | }; |
| 98 | |
| 99 | ð { |
| 100 | status = "okay"; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 101 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 102 | gmac0: mac@0 { |
| 103 | compatible = "mediatek,eth-mac"; |
| 104 | reg = <0>; |
| 105 | phy-mode = "trgmii"; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 106 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 107 | fixed-link { |
| 108 | speed = <1000>; |
| 109 | full-duplex; |
| 110 | pause; |
| 111 | }; |
| 112 | }; |
| 113 | |
| 114 | mdio: mdio-bus { |
| 115 | #address-cells = <1>; |
| 116 | #size-cells = <0>; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 117 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 118 | switch@0 { |
| 119 | compatible = "mediatek,mt7530"; |
| 120 | #address-cells = <1>; |
| 121 | #size-cells = <0>; |
| 122 | reg = <0>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 123 | pinctrl-names = "default"; |
| 124 | reset-gpios = <&pio 33 0>; |
| 125 | core-supply = <&mt6323_vpa_reg>; |
| 126 | io-supply = <&mt6323_vemc3v3_reg>; |
| 127 | |
| 128 | ports { |
| 129 | #address-cells = <1>; |
| 130 | #size-cells = <0>; |
| 131 | reg = <0>; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 132 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 133 | port@0 { |
| 134 | reg = <0>; |
| 135 | label = "wan"; |
| 136 | }; |
| 137 | |
| 138 | port@1 { |
| 139 | reg = <1>; |
| 140 | label = "lan0"; |
| 141 | }; |
| 142 | |
| 143 | port@2 { |
| 144 | reg = <2>; |
| 145 | label = "lan1"; |
| 146 | }; |
| 147 | |
| 148 | port@3 { |
| 149 | reg = <3>; |
| 150 | label = "lan2"; |
| 151 | }; |
| 152 | |
| 153 | port@4 { |
| 154 | reg = <4>; |
| 155 | label = "lan3"; |
| 156 | }; |
| 157 | |
| 158 | port@6 { |
| 159 | reg = <6>; |
| 160 | label = "cpu"; |
| 161 | ethernet = <&gmac0>; |
| 162 | phy-mode = "trgmii"; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 163 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 164 | fixed-link { |
| 165 | speed = <1000>; |
| 166 | full-duplex; |
| 167 | }; |
| 168 | }; |
| 169 | }; |
| 170 | }; |
| 171 | }; |
| 172 | }; |
| 173 | |
| 174 | &i2c0 { |
| 175 | pinctrl-names = "default"; |
| 176 | pinctrl-0 = <&i2c0_pins_a>; |
| 177 | status = "okay"; |
| 178 | }; |
| 179 | |
| 180 | &i2c1 { |
| 181 | pinctrl-names = "default"; |
| 182 | pinctrl-0 = <&i2c1_pins_a>; |
| 183 | status = "okay"; |
| 184 | }; |
| 185 | |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 186 | &mmc0 { |
| 187 | pinctrl-names = "default", "state_uhs"; |
| 188 | pinctrl-0 = <&mmc0_pins_default>; |
| 189 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 190 | status = "okay"; |
| 191 | bus-width = <8>; |
| 192 | max-frequency = <50000000>; |
| 193 | cap-mmc-highspeed; |
| 194 | vmmc-supply = <&mt6323_vemc3v3_reg>; |
| 195 | vqmmc-supply = <&mt6323_vio18_reg>; |
| 196 | non-removable; |
| 197 | }; |
| 198 | |
| 199 | &mmc1 { |
| 200 | pinctrl-names = "default", "state_uhs"; |
| 201 | pinctrl-0 = <&mmc1_pins_default>; |
| 202 | pinctrl-1 = <&mmc1_pins_uhs>; |
| 203 | status = "okay"; |
| 204 | bus-width = <4>; |
| 205 | max-frequency = <50000000>; |
| 206 | cap-sd-highspeed; |
Sean Wang | b96a696 | 2017-12-07 14:43:24 +0800 | [diff] [blame^] | 207 | cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 208 | vmmc-supply = <&mt6323_vmch_reg>; |
| 209 | vqmmc-supply = <&mt6323_vio18_reg>; |
| 210 | }; |
| 211 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 212 | &pio { |
| 213 | cir_pins_a:cir@0 { |
| 214 | pins_cir { |
| 215 | pinmux = <MT7623_PIN_46_IR_FUNC_IR>; |
| 216 | bias-disable; |
| 217 | }; |
| 218 | }; |
| 219 | |
| 220 | i2c0_pins_a: i2c@0 { |
| 221 | pins_i2c0 { |
| 222 | pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, |
| 223 | <MT7623_PIN_76_SCL0_FUNC_SCL0>; |
| 224 | bias-disable; |
| 225 | }; |
| 226 | }; |
| 227 | |
| 228 | i2c1_pins_a: i2c@1 { |
| 229 | pin_i2c1 { |
| 230 | pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>, |
| 231 | <MT7623_PIN_58_SCL1_FUNC_SCL1>; |
| 232 | bias-disable; |
| 233 | }; |
| 234 | }; |
| 235 | |
| 236 | i2s0_pins_a: i2s@0 { |
| 237 | pin_i2s0 { |
| 238 | pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>, |
| 239 | <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>, |
| 240 | <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>, |
| 241 | <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>, |
| 242 | <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>; |
| 243 | drive-strength = <MTK_DRIVE_12mA>; |
| 244 | bias-pull-down; |
| 245 | }; |
| 246 | }; |
| 247 | |
| 248 | i2s1_pins_a: i2s@1 { |
| 249 | pin_i2s1 { |
| 250 | pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>, |
| 251 | <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>, |
| 252 | <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>, |
| 253 | <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>, |
| 254 | <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>; |
| 255 | drive-strength = <MTK_DRIVE_12mA>; |
| 256 | bias-pull-down; |
| 257 | }; |
| 258 | }; |
| 259 | |
| 260 | key_pins_a: keys@0 { |
| 261 | pins_keys { |
| 262 | pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, |
| 263 | <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ; |
| 264 | input-enable; |
| 265 | }; |
| 266 | }; |
| 267 | |
| 268 | led_pins_a: leds@0 { |
| 269 | pins_leds { |
| 270 | pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>, |
| 271 | <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>, |
| 272 | <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>; |
| 273 | }; |
| 274 | }; |
| 275 | |
| 276 | mmc0_pins_default: mmc0default { |
| 277 | pins_cmd_dat { |
| 278 | pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
| 279 | <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
| 280 | <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
| 281 | <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
| 282 | <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
| 283 | <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
| 284 | <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
| 285 | <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
| 286 | <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
| 287 | input-enable; |
| 288 | bias-pull-up; |
| 289 | }; |
| 290 | |
| 291 | pins_clk { |
| 292 | pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
| 293 | bias-pull-down; |
| 294 | }; |
| 295 | |
| 296 | pins_rst { |
| 297 | pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
| 298 | bias-pull-up; |
| 299 | }; |
| 300 | }; |
| 301 | |
| 302 | mmc0_pins_uhs: mmc0 { |
| 303 | pins_cmd_dat { |
| 304 | pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
| 305 | <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
| 306 | <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
| 307 | <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
| 308 | <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
| 309 | <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
| 310 | <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
| 311 | <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
| 312 | <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
| 313 | input-enable; |
| 314 | drive-strength = <MTK_DRIVE_2mA>; |
| 315 | bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
| 316 | }; |
| 317 | |
| 318 | pins_clk { |
| 319 | pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
| 320 | drive-strength = <MTK_DRIVE_2mA>; |
| 321 | bias-pull-down = <MTK_PUPD_SET_R1R0_01>; |
| 322 | }; |
| 323 | |
| 324 | pins_rst { |
| 325 | pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
| 326 | bias-pull-up; |
| 327 | }; |
| 328 | }; |
| 329 | |
| 330 | mmc1_pins_default: mmc1default { |
| 331 | pins_cmd_dat { |
| 332 | pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, |
| 333 | <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, |
| 334 | <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, |
| 335 | <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, |
| 336 | <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; |
| 337 | input-enable; |
| 338 | drive-strength = <MTK_DRIVE_4mA>; |
| 339 | bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
| 340 | }; |
| 341 | |
| 342 | pins_clk { |
| 343 | pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; |
| 344 | bias-pull-down; |
| 345 | drive-strength = <MTK_DRIVE_4mA>; |
| 346 | }; |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 347 | |
| 348 | pins_wp { |
| 349 | pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>; |
| 350 | input-enable; |
| 351 | bias-pull-up; |
| 352 | }; |
| 353 | |
| 354 | pins_insert { |
| 355 | pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>; |
| 356 | bias-pull-up; |
| 357 | }; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 358 | }; |
| 359 | |
| 360 | mmc1_pins_uhs: mmc1 { |
| 361 | pins_cmd_dat { |
| 362 | pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, |
| 363 | <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, |
| 364 | <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, |
| 365 | <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, |
| 366 | <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; |
| 367 | input-enable; |
| 368 | drive-strength = <MTK_DRIVE_4mA>; |
| 369 | bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
| 370 | }; |
| 371 | |
| 372 | pins_clk { |
| 373 | pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; |
| 374 | drive-strength = <MTK_DRIVE_4mA>; |
| 375 | bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
| 376 | }; |
| 377 | }; |
| 378 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 379 | pwm_pins_a: pwm@0 { |
| 380 | pins_pwm { |
| 381 | pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, |
| 382 | <MT7623_PIN_204_PWM1_FUNC_PWM1>, |
| 383 | <MT7623_PIN_205_PWM2_FUNC_PWM2>, |
| 384 | <MT7623_PIN_206_PWM3_FUNC_PWM3>, |
| 385 | <MT7623_PIN_207_PWM4_FUNC_PWM4>; |
| 386 | }; |
| 387 | }; |
| 388 | |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 389 | spi0_pins_a: spi@0 { |
| 390 | pins_spi { |
| 391 | pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>, |
| 392 | <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>, |
| 393 | <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>, |
| 394 | <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>; |
| 395 | bias-disable; |
| 396 | }; |
| 397 | }; |
| 398 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 399 | uart0_pins_a: uart@0 { |
| 400 | pins_dat { |
| 401 | pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>, |
| 402 | <MT7623_PIN_80_UTXD0_FUNC_UTXD0>; |
| 403 | }; |
| 404 | }; |
| 405 | |
| 406 | uart1_pins_a: uart@1 { |
| 407 | pins_dat { |
| 408 | pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>, |
| 409 | <MT7623_PIN_82_UTXD1_FUNC_UTXD1>; |
| 410 | }; |
| 411 | }; |
| 412 | }; |
| 413 | |
| 414 | &pwm { |
| 415 | pinctrl-names = "default"; |
| 416 | pinctrl-0 = <&pwm_pins_a>; |
| 417 | status = "okay"; |
| 418 | }; |
| 419 | |
| 420 | &pwrap { |
| 421 | mt6323 { |
| 422 | mt6323led: led { |
| 423 | compatible = "mediatek,mt6323-led"; |
| 424 | #address-cells = <1>; |
| 425 | #size-cells = <0>; |
| 426 | |
| 427 | led@0 { |
| 428 | reg = <0>; |
| 429 | label = "bpi-r2:isink:green"; |
| 430 | default-state = "off"; |
| 431 | }; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 432 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 433 | led@1 { |
| 434 | reg = <1>; |
| 435 | label = "bpi-r2:isink:red"; |
| 436 | default-state = "off"; |
| 437 | }; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 438 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 439 | led@2 { |
| 440 | reg = <2>; |
| 441 | label = "bpi-r2:isink:blue"; |
| 442 | default-state = "off"; |
| 443 | }; |
| 444 | }; |
| 445 | }; |
| 446 | }; |
| 447 | |
| 448 | &spi0 { |
| 449 | pinctrl-names = "default"; |
| 450 | pinctrl-0 = <&spi0_pins_a>; |
| 451 | status = "okay"; |
| 452 | }; |
| 453 | |
| 454 | &uart0 { |
| 455 | pinctrl-names = "default"; |
| 456 | pinctrl-0 = <&uart0_pins_a>; |
| 457 | status = "disabled"; |
| 458 | }; |
| 459 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 460 | &uart1 { |
| 461 | pinctrl-names = "default"; |
| 462 | pinctrl-0 = <&uart1_pins_a>; |
| 463 | status = "disabled"; |
| 464 | }; |
| 465 | |
| 466 | &uart2 { |
| 467 | status = "okay"; |
| 468 | }; |
| 469 | |
| 470 | &usb1 { |
| 471 | vusb33-supply = <&mt6323_vusb_reg>; |
| 472 | status = "okay"; |
| 473 | }; |
| 474 | |
| 475 | &usb2 { |
| 476 | vusb33-supply = <&mt6323_vusb_reg>; |
| 477 | status = "okay"; |
| 478 | }; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 479 | |
| 480 | &u3phy1 { |
| 481 | status = "okay"; |
| 482 | }; |
| 483 | |
| 484 | &u3phy2 { |
| 485 | status = "okay"; |
| 486 | }; |
| 487 | |