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Zou Nan hai8187a2b2010-05-21 09:08:55 +08001#ifndef _INTEL_RINGBUFFER_H_
2#define _INTEL_RINGBUFFER_H_
3
Brad Volkin44e895a2014-05-10 14:10:43 -07004#include <linux/hashtable.h>
Chris Wilson06fbca72015-04-07 16:20:36 +01005#include "i915_gem_batch_pool.h"
Brad Volkin44e895a2014-05-10 14:10:43 -07006
7#define I915_CMD_HASH_ORDER 9
8
Oscar Mateo47122742014-07-24 17:04:28 +01009/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
10 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
11 * to give some inclination as to some of the magic values used in the various
12 * workarounds!
13 */
14#define CACHELINE_BYTES 64
Arun Siluvery17ee9502015-06-19 19:07:01 +010015#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
Oscar Mateo47122742014-07-24 17:04:28 +010016
Ville Syrjälä633cf8f2012-12-03 18:43:32 +020017/*
18 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
19 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
20 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
21 *
22 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
23 * cacheline, the Head Pointer must not be greater than the Tail
24 * Pointer."
25 */
26#define I915_RING_FREE_SPACE 64
27
Zou Nan hai8187a2b2010-05-21 09:08:55 +080028struct intel_hw_status_page {
Daniel Vetter4225d0f2012-04-26 23:28:16 +020029 u32 *page_addr;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080030 unsigned int gfx_addr;
Chris Wilson05394f32010-11-08 19:18:58 +000031 struct drm_i915_gem_object *obj;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080032};
33
Ben Widawskyb7287d82011-04-25 11:22:22 -070034#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
35#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080036
Ben Widawskyb7287d82011-04-25 11:22:22 -070037#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
38#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080039
Ben Widawskyb7287d82011-04-25 11:22:22 -070040#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
41#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080042
Ben Widawskyb7287d82011-04-25 11:22:22 -070043#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
44#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080045
Ben Widawskyb7287d82011-04-25 11:22:22 -070046#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
47#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
Daniel Vetter870e86d2010-08-02 16:29:44 +020048
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +053049#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
Chris Wilson9991ae72014-04-02 16:36:07 +010050#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +053051
Ben Widawsky3e789982014-06-30 09:53:37 -070052/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
53 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
54 */
Chris Wilson8c126722016-04-07 07:29:14 +010055#define gen8_semaphore_seqno_size sizeof(uint64_t)
56#define GEN8_SEMAPHORE_OFFSET(__from, __to) \
57 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
Ben Widawsky3e789982014-06-30 09:53:37 -070058#define GEN8_SIGNAL_OFFSET(__ring, to) \
59 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
Chris Wilson8c126722016-04-07 07:29:14 +010060 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
Ben Widawsky3e789982014-06-30 09:53:37 -070061#define GEN8_WAIT_OFFSET(__ring, from) \
62 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
Chris Wilson8c126722016-04-07 07:29:14 +010063 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
Ben Widawsky3e789982014-06-30 09:53:37 -070064
Jani Nikulaf2f4d822013-08-11 12:44:01 +030065enum intel_ring_hangcheck_action {
Mika Kuoppalada661462013-09-06 16:03:28 +030066 HANGCHECK_IDLE = 0,
Jani Nikulaf2f4d822013-08-11 12:44:01 +030067 HANGCHECK_WAIT,
68 HANGCHECK_ACTIVE,
69 HANGCHECK_KICK,
70 HANGCHECK_HUNG,
71};
Mika Kuoppalaad8beae2013-06-12 12:35:32 +030072
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +020073#define HANGCHECK_SCORE_RING_HUNG 31
74
Mika Kuoppala92cab732013-05-24 17:16:07 +030075struct intel_ring_hangcheck {
Chris Wilson50877442014-03-21 12:41:53 +000076 u64 acthd;
Mika Kuoppala92cab732013-05-24 17:16:07 +030077 u32 seqno;
Chris Wilson12471ba2016-04-09 10:57:55 +010078 unsigned user_interrupts;
Mika Kuoppala05407ff2013-05-30 09:04:29 +030079 int score;
Mika Kuoppalaad8beae2013-06-12 12:35:32 +030080 enum intel_ring_hangcheck_action action;
Chris Wilson4be17382014-06-06 10:22:29 +010081 int deadlock;
Mika Kuoppala61642ff2015-12-01 17:56:12 +020082 u32 instdone[I915_NUM_INSTDONE_REG];
Mika Kuoppala92cab732013-05-24 17:16:07 +030083};
84
Oscar Mateo8ee14972014-05-22 14:13:34 +010085struct intel_ringbuffer {
86 struct drm_i915_gem_object *obj;
87 void __iomem *virtual_start;
Tvrtko Ursulin0eb973d2016-01-15 15:10:28 +000088 struct i915_vma *vma;
Oscar Mateo8ee14972014-05-22 14:13:34 +010089
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +000090 struct intel_engine_cs *engine;
Chris Wilson608c1a52015-09-03 13:01:40 +010091 struct list_head link;
Daniel Vetter0c7dd532014-08-11 16:17:44 +020092
Oscar Mateo8ee14972014-05-22 14:13:34 +010093 u32 head;
94 u32 tail;
95 int space;
96 int size;
97 int effective_size;
98
99 /** We track the position of the requests in the ring buffer, and
100 * when each is retired we increment last_retired_head as the GPU
101 * must have finished processing the request and so we know we
102 * can advance the ringbuffer up to that position.
103 *
104 * last_retired_head is set to -1 after the value is consumed so
105 * we can detect new retirements.
106 */
107 u32 last_retired_head;
108};
109
Chris Wilsone2efd132016-05-24 14:53:34 +0100110struct i915_gem_context;
Jordan Justen361b0272016-03-06 23:30:27 -0800111struct drm_i915_reg_table;
Nick Hoath21076372015-01-15 13:10:38 +0000112
Arun Siluvery17ee9502015-06-19 19:07:01 +0100113/*
114 * we use a single page to load ctx workarounds so all of these
115 * values are referred in terms of dwords
116 *
117 * struct i915_wa_ctx_bb:
118 * offset: specifies batch starting position, also helpful in case
119 * if we want to have multiple batches at different offsets based on
120 * some criteria. It is not a requirement at the moment but provides
121 * an option for future use.
122 * size: size of the batch in DWORDS
123 */
124struct i915_ctx_workarounds {
125 struct i915_wa_ctx_bb {
126 u32 offset;
127 u32 size;
128 } indirect_ctx, per_ctx;
129 struct drm_i915_gem_object *obj;
130};
131
Chris Wilsonc0336662016-05-06 15:40:21 +0100132struct intel_engine_cs {
133 struct drm_i915_private *i915;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800134 const char *name;
Tvrtko Ursulin117897f2016-03-16 11:00:40 +0000135 enum intel_engine_id {
Tvrtko Ursulinde1add32016-01-15 15:12:50 +0000136 RCS = 0,
Daniel Vetter96154f22011-12-14 13:57:00 +0100137 BCS,
Tvrtko Ursulinde1add32016-01-15 15:12:50 +0000138 VCS,
139 VCS2, /* Keep instances of the same type engine together. */
140 VECS
Chris Wilson92204342010-09-18 11:02:01 +0100141 } id;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000142#define I915_NUM_ENGINES 5
Tvrtko Ursulinde1add32016-01-15 15:12:50 +0000143#define _VCS(n) (VCS + (n))
Chris Wilson426960b2016-01-15 16:51:46 +0000144 unsigned int exec_id;
Chris Wilson215a7e32016-04-29 13:18:23 +0100145 unsigned int hw_id;
146 unsigned int guc_id; /* XXX same as hw_id? */
Daniel Vetter333e9fe2010-08-02 16:24:01 +0200147 u32 mmio_base;
Oscar Mateo8ee14972014-05-22 14:13:34 +0100148 struct intel_ringbuffer *buffer;
Chris Wilson608c1a52015-09-03 13:01:40 +0100149 struct list_head buffers;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800150
Chris Wilson06fbca72015-04-07 16:20:36 +0100151 /*
152 * A pool of objects to use as shadow copies of client batch buffers
153 * when the command parser is enabled. Prevents the client from
154 * modifying the batch contents after software parsing.
155 */
156 struct i915_gem_batch_pool batch_pool;
157
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800158 struct intel_hw_status_page status_page;
Arun Siluvery17ee9502015-06-19 19:07:01 +0100159 struct i915_ctx_workarounds wa_ctx;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800160
Daniel Vetterc7113cc2013-07-04 23:35:29 +0200161 unsigned irq_refcount; /* protected by dev_priv->irq_lock */
Daniel Vetter6a848cc2012-04-11 22:12:46 +0200162 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
John Harrison581c26e82014-11-24 18:49:39 +0000163 struct drm_i915_gem_request *trace_irq_req;
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100164 bool __must_check (*irq_get)(struct intel_engine_cs *ring);
165 void (*irq_put)(struct intel_engine_cs *ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800166
Daniel Vetterecfe00d2014-11-20 00:33:04 +0100167 int (*init_hw)(struct intel_engine_cs *ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800168
John Harrison87531812015-05-29 17:43:44 +0100169 int (*init_context)(struct drm_i915_gem_request *req);
Arun Siluvery86d7f232014-08-26 14:44:50 +0100170
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100171 void (*write_tail)(struct intel_engine_cs *ring,
Chris Wilson297b0c52010-10-22 17:02:41 +0100172 u32 value);
John Harrisona84c3ae2015-05-29 17:43:57 +0100173 int __must_check (*flush)(struct drm_i915_gem_request *req,
Chris Wilsonb72f3ac2011-01-04 17:34:02 +0000174 u32 invalidate_domains,
175 u32 flush_domains);
John Harrisonee044a82015-05-29 17:44:00 +0100176 int (*add_request)(struct drm_i915_gem_request *req);
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100177 /* Some chipsets are not quite as coherent as advertised and need
178 * an expensive kick to force a true read of the up-to-date seqno.
179 * However, the up-to-date seqno is not always required and the last
180 * seen value is good enough. Note that the seqno will always be
181 * monotonic, even if not coherent.
182 */
Chris Wilsonc04e0f32016-04-09 10:57:54 +0100183 void (*irq_seqno_barrier)(struct intel_engine_cs *ring);
184 u32 (*get_seqno)(struct intel_engine_cs *ring);
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100185 void (*set_seqno)(struct intel_engine_cs *ring,
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200186 u32 seqno);
John Harrison53fddaf2015-05-29 17:44:02 +0100187 int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
Ben Widawsky9bcb1442014-04-28 19:29:25 -0700188 u64 offset, u32 length,
John Harrison8e004ef2015-02-13 11:48:10 +0000189 unsigned dispatch_flags);
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100190#define I915_DISPATCH_SECURE 0x1
Daniel Vetterb45305f2012-12-17 16:21:27 +0100191#define I915_DISPATCH_PINNED 0x2
Abdiel Janulgue919032e2015-06-16 13:39:40 +0300192#define I915_DISPATCH_RS 0x4
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100193 void (*cleanup)(struct intel_engine_cs *ring);
Ben Widawskyebc348b2014-04-29 14:52:28 -0700194
Ben Widawsky3e789982014-06-30 09:53:37 -0700195 /* GEN8 signal/wait table - never trust comments!
196 * signal to signal to signal to signal to signal to
197 * RCS VCS BCS VECS VCS2
198 * --------------------------------------------------------------------
199 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
200 * |-------------------------------------------------------------------
201 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
202 * |-------------------------------------------------------------------
203 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
204 * |-------------------------------------------------------------------
205 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
206 * |-------------------------------------------------------------------
207 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
208 * |-------------------------------------------------------------------
209 *
210 * Generalization:
211 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
212 * ie. transpose of g(x, y)
213 *
214 * sync from sync from sync from sync from sync from
215 * RCS VCS BCS VECS VCS2
216 * --------------------------------------------------------------------
217 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
218 * |-------------------------------------------------------------------
219 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
220 * |-------------------------------------------------------------------
221 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
222 * |-------------------------------------------------------------------
223 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
224 * |-------------------------------------------------------------------
225 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
226 * |-------------------------------------------------------------------
227 *
228 * Generalization:
229 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
230 * ie. transpose of f(x, y)
231 */
Ben Widawskyebc348b2014-04-29 14:52:28 -0700232 struct {
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000233 u32 sync_seqno[I915_NUM_ENGINES-1];
Ben Widawsky78325f22014-04-29 14:52:29 -0700234
Ben Widawsky3e789982014-06-30 09:53:37 -0700235 union {
236 struct {
237 /* our mbox written by others */
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000238 u32 wait[I915_NUM_ENGINES];
Ben Widawsky3e789982014-06-30 09:53:37 -0700239 /* mboxes this ring signals to */
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000240 i915_reg_t signal[I915_NUM_ENGINES];
Ben Widawsky3e789982014-06-30 09:53:37 -0700241 } mbox;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000242 u64 signal_ggtt[I915_NUM_ENGINES];
Ben Widawsky3e789982014-06-30 09:53:37 -0700243 };
Ben Widawsky78325f22014-04-29 14:52:29 -0700244
245 /* AKA wait() */
John Harrison599d9242015-05-29 17:44:04 +0100246 int (*sync_to)(struct drm_i915_gem_request *to_req,
247 struct intel_engine_cs *from,
Ben Widawsky78325f22014-04-29 14:52:29 -0700248 u32 seqno);
John Harrisonf7169682015-05-29 17:44:05 +0100249 int (*signal)(struct drm_i915_gem_request *signaller_req,
Ben Widawsky024a43e2014-04-29 14:52:30 -0700250 /* num_dwords needed by caller */
251 unsigned int num_dwords);
Ben Widawskyebc348b2014-04-29 14:52:28 -0700252 } semaphore;
Ben Widawskyad776f82013-05-28 19:22:18 -0700253
Oscar Mateo4da46e12014-07-24 17:04:27 +0100254 /* Execlists */
Tvrtko Ursulin27af5ee2016-04-04 12:11:56 +0100255 struct tasklet_struct irq_tasklet;
256 spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
Michel Thierryacdd8842014-07-24 17:04:38 +0100257 struct list_head execlist_queue;
Tvrtko Ursulin37566852016-04-12 14:37:31 +0100258 unsigned int fw_domains;
Tvrtko Ursulinc6a2ac72016-02-26 16:58:32 +0000259 unsigned int next_context_status_buffer;
260 unsigned int idle_lite_restore_wa;
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000261 bool disable_lite_restore_wa;
262 u32 ctx_desc_template;
Oscar Mateo73d477f2014-07-24 17:04:31 +0100263 u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
John Harrisonc4e76632015-05-29 17:44:01 +0100264 int (*emit_request)(struct drm_i915_gem_request *request);
John Harrison7deb4d32015-05-29 17:43:59 +0100265 int (*emit_flush)(struct drm_i915_gem_request *request,
Oscar Mateo47122742014-07-24 17:04:28 +0100266 u32 invalidate_domains,
267 u32 flush_domains);
John Harrisonbe795fc2015-05-29 17:44:03 +0100268 int (*emit_bb_start)(struct drm_i915_gem_request *req,
John Harrison8e004ef2015-02-13 11:48:10 +0000269 u64 offset, unsigned dispatch_flags);
Oscar Mateo4da46e12014-07-24 17:04:27 +0100270
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800271 /**
272 * List of objects currently involved in rendering from the
273 * ringbuffer.
274 *
275 * Includes buffers having the contents of their GPU caches
John Harrison97b2a6a2014-11-24 18:49:26 +0000276 * flushed, not necessarily primitives. last_read_req
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800277 * represents when the rendering involved will be completed.
278 *
279 * A reference is held on the buffer while on this list.
280 */
281 struct list_head active_list;
282
283 /**
284 * List of breadcrumbs associated with GPU requests currently
285 * outstanding.
286 */
287 struct list_head request_list;
288
Chris Wilsona56ba562010-09-28 10:07:56 +0100289 /**
Tomas Elf94f7bbe2015-07-09 15:30:57 +0100290 * Seqno of request most recently submitted to request_list.
291 * Used exclusively by hang checker to avoid grabbing lock while
292 * inspecting request list.
293 */
294 u32 last_submitted_seqno;
Chris Wilson12471ba2016-04-09 10:57:55 +0100295 unsigned user_interrupts;
Tomas Elf94f7bbe2015-07-09 15:30:57 +0100296
Daniel Vettercc889e02012-06-13 20:45:19 +0200297 bool gpu_caches_dirty;
Chris Wilsona56ba562010-09-28 10:07:56 +0100298
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800299 wait_queue_head_t irq_queue;
Zou Nan hai8d192152010-11-02 16:31:01 +0800300
Chris Wilsone2efd132016-05-24 14:53:34 +0100301 struct i915_gem_context *last_context;
Ben Widawsky40521052012-06-04 14:42:43 -0700302
Mika Kuoppala92cab732013-05-24 17:16:07 +0300303 struct intel_ring_hangcheck hangcheck;
304
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100305 struct {
306 struct drm_i915_gem_object *obj;
307 u32 gtt_offset;
308 volatile u32 *cpu_page;
309 } scratch;
Brad Volkin351e3db2014-02-18 10:15:46 -0800310
Brad Volkin44e895a2014-05-10 14:10:43 -0700311 bool needs_cmd_parser;
312
Brad Volkin351e3db2014-02-18 10:15:46 -0800313 /*
Brad Volkin44e895a2014-05-10 14:10:43 -0700314 * Table of commands the command parser needs to know about
Brad Volkin351e3db2014-02-18 10:15:46 -0800315 * for this ring.
316 */
Brad Volkin44e895a2014-05-10 14:10:43 -0700317 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
Brad Volkin351e3db2014-02-18 10:15:46 -0800318
319 /*
320 * Table of registers allowed in commands that read/write registers.
321 */
Jordan Justen361b0272016-03-06 23:30:27 -0800322 const struct drm_i915_reg_table *reg_tables;
323 int reg_table_count;
Brad Volkin351e3db2014-02-18 10:15:46 -0800324
325 /*
326 * Returns the bitmask for the length field of the specified command.
327 * Return 0 for an unrecognized/invalid command.
328 *
329 * If the command parser finds an entry for a command in the ring's
330 * cmd_tables, it gets the command's length based on the table entry.
331 * If not, it calls this function to determine the per-ring length field
332 * encoding for the command (i.e. certain opcode ranges use certain bits
333 * to encode the command length in the header).
334 */
335 u32 (*get_cmd_length_mask)(u32 cmd_header);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800336};
337
Dave Gordonb0366a52015-12-08 15:02:36 +0000338static inline bool
Tvrtko Ursulin117897f2016-03-16 11:00:40 +0000339intel_engine_initialized(struct intel_engine_cs *engine)
Dave Gordonb0366a52015-12-08 15:02:36 +0000340{
Chris Wilsonc0336662016-05-06 15:40:21 +0100341 return engine->i915 != NULL;
Dave Gordonb0366a52015-12-08 15:02:36 +0000342}
Chris Wilsonb4519512012-05-11 14:29:30 +0100343
Daniel Vetter96154f22011-12-14 13:57:00 +0100344static inline unsigned
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000345intel_engine_flag(struct intel_engine_cs *engine)
Daniel Vetter96154f22011-12-14 13:57:00 +0100346{
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000347 return 1 << engine->id;
Daniel Vetter96154f22011-12-14 13:57:00 +0100348}
349
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800350static inline u32
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000351intel_ring_sync_index(struct intel_engine_cs *engine,
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100352 struct intel_engine_cs *other)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000353{
354 int idx;
355
356 /*
Rodrigo Vividdd4dbc2014-06-30 09:51:11 -0700357 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
358 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
359 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
360 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
361 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000362 */
363
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000364 idx = (other - engine) - 1;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000365 if (idx < 0)
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000366 idx += I915_NUM_ENGINES;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000367
368 return idx;
369}
370
Imre Deak319404d2015-08-14 18:35:27 +0300371static inline void
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000372intel_flush_status_page(struct intel_engine_cs *engine, int reg)
Imre Deak319404d2015-08-14 18:35:27 +0300373{
Chris Wilson0d317ce2016-04-09 10:57:56 +0100374 mb();
375 clflush(&engine->status_page.page_addr[reg]);
376 mb();
Imre Deak319404d2015-08-14 18:35:27 +0300377}
378
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000379static inline u32
Chris Wilson5dd8e502016-04-09 10:57:57 +0100380intel_read_status_page(struct intel_engine_cs *engine, int reg)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800381{
Daniel Vetter4225d0f2012-04-26 23:28:16 +0200382 /* Ensure that the compiler doesn't optimize away the load. */
Chris Wilson5dd8e502016-04-09 10:57:57 +0100383 return READ_ONCE(engine->status_page.page_addr[reg]);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800384}
385
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200386static inline void
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000387intel_write_status_page(struct intel_engine_cs *engine,
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200388 int reg, u32 value)
389{
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000390 engine->status_page.page_addr[reg] = value;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200391}
392
Jani Nikulae2828912016-01-18 09:19:47 +0200393/*
Chris Wilson311bd682011-01-13 19:06:50 +0000394 * Reads a dword out of the status page, which is written to from the command
395 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
396 * MI_STORE_DATA_IMM.
397 *
398 * The following dwords have a reserved meaning:
399 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
400 * 0x04: ring 0 head pointer
401 * 0x05: ring 1 head pointer (915-class)
402 * 0x06: ring 2 head pointer (915-class)
403 * 0x10-0x1b: Context status DWords (GM45)
404 * 0x1f: Last written status offset. (GM45)
Thomas Danielb07da532015-02-18 11:48:21 +0000405 * 0x20-0x2f: Reserved (Gen6+)
Chris Wilson311bd682011-01-13 19:06:50 +0000406 *
Thomas Danielb07da532015-02-18 11:48:21 +0000407 * The area from dword 0x30 to 0x3ff is available for driver usage.
Chris Wilson311bd682011-01-13 19:06:50 +0000408 */
Thomas Danielb07da532015-02-18 11:48:21 +0000409#define I915_GEM_HWS_INDEX 0x30
Chris Wilson7c17d372016-01-20 15:43:35 +0200410#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
Thomas Danielb07da532015-02-18 11:48:21 +0000411#define I915_GEM_HWS_SCRATCH_INDEX 0x40
Jesse Barnes9a289772012-10-26 09:42:42 -0700412#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
Chris Wilson311bd682011-01-13 19:06:50 +0000413
Chris Wilson01101fa2015-09-03 13:01:39 +0100414struct intel_ringbuffer *
415intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
Chris Wilsonc0336662016-05-06 15:40:21 +0100416int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000417 struct intel_ringbuffer *ringbuf);
Chris Wilson01101fa2015-09-03 13:01:39 +0100418void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
419void intel_ringbuffer_free(struct intel_ringbuffer *ring);
Oscar Mateo84c23772014-07-24 17:04:15 +0100420
Tvrtko Ursulin117897f2016-03-16 11:00:40 +0000421void intel_stop_engine(struct intel_engine_cs *engine);
422void intel_cleanup_engine(struct intel_engine_cs *engine);
Ben Widawsky96f298a2011-03-19 18:14:27 -0700423
John Harrison6689cb22015-03-19 12:30:08 +0000424int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
425
John Harrison5fb9de12015-05-29 17:44:07 +0100426int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
John Harrisonbba09b12015-05-29 17:44:06 +0100427int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000428static inline void intel_ring_emit(struct intel_engine_cs *engine,
Chris Wilson78501ea2010-10-27 12:18:21 +0100429 u32 data)
Chris Wilsone898cd22010-08-04 15:18:14 +0100430{
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000431 struct intel_ringbuffer *ringbuf = engine->buffer;
Oscar Mateo93b0a4e2014-05-22 14:13:36 +0100432 iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
433 ringbuf->tail += 4;
Chris Wilsone898cd22010-08-04 15:18:14 +0100434}
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000435static inline void intel_ring_emit_reg(struct intel_engine_cs *engine,
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200436 i915_reg_t reg)
Ville Syrjäläf92a9162015-11-04 23:20:07 +0200437{
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000438 intel_ring_emit(engine, i915_mmio_reg_offset(reg));
Ville Syrjäläf92a9162015-11-04 23:20:07 +0200439}
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000440static inline void intel_ring_advance(struct intel_engine_cs *engine)
Chris Wilson09246732013-08-10 22:16:32 +0100441{
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000442 struct intel_ringbuffer *ringbuf = engine->buffer;
Oscar Mateo93b0a4e2014-05-22 14:13:36 +0100443 ringbuf->tail &= ringbuf->size - 1;
Chris Wilson09246732013-08-10 22:16:32 +0100444}
Oscar Mateo82e104c2014-07-24 17:04:26 +0100445int __intel_ring_space(int head, int tail, int size);
Dave Gordonebd0fd42014-11-27 11:22:49 +0000446void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
Tvrtko Ursulin117897f2016-03-16 11:00:40 +0000447bool intel_engine_stopped(struct intel_engine_cs *engine);
Chris Wilson09246732013-08-10 22:16:32 +0100448
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000449int __must_check intel_engine_idle(struct intel_engine_cs *engine);
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000450void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno);
John Harrison4866d722015-05-29 17:43:55 +0100451int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
John Harrison2f200552015-05-29 17:43:53 +0100452int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800453
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000454void intel_fini_pipe_control(struct intel_engine_cs *engine);
455int intel_init_pipe_control(struct intel_engine_cs *engine);
Oscar Mateo9b1136d2014-07-24 17:04:24 +0100456
Xiang, Haihao5c1143b2010-09-16 10:43:11 +0800457int intel_init_render_ring_buffer(struct drm_device *dev);
458int intel_init_bsd_ring_buffer(struct drm_device *dev);
Zhao Yakui845f74a2014-04-17 10:37:37 +0800459int intel_init_bsd2_ring_buffer(struct drm_device *dev);
Chris Wilson549f7362010-10-19 11:19:32 +0100460int intel_init_blt_ring_buffer(struct drm_device *dev);
Ben Widawsky9a8a2212013-05-28 19:22:23 -0700461int intel_init_vebox_ring_buffer(struct drm_device *dev);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800462
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000463u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
Daniel Vetter79f321b2010-09-24 21:20:10 +0200464
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000465int init_workarounds_ring(struct intel_engine_cs *engine);
Michel Thierry771b9a52014-11-11 16:47:33 +0000466
Oscar Mateo1b5d0632014-07-03 16:28:04 +0100467static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
Chris Wilsona71d8d92012-02-15 11:25:36 +0000468{
Oscar Mateo1b5d0632014-07-03 16:28:04 +0100469 return ringbuf->tail;
Chris Wilsona71d8d92012-02-15 11:25:36 +0000470}
471
John Harrison29b1b412015-06-18 13:10:09 +0100472/*
473 * Arbitrary size for largest possible 'add request' sequence. The code paths
474 * are complex and variable. Empirical measurement shows that the worst case
Chris Wilson596e5ef2016-04-29 09:07:04 +0100475 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
476 * we need to allocate double the largest single packet within that emission
477 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
John Harrison29b1b412015-06-18 13:10:09 +0100478 */
Chris Wilson596e5ef2016-04-29 09:07:04 +0100479#define MIN_SPACE_FOR_ADD_REQUEST 336
John Harrison29b1b412015-06-18 13:10:09 +0100480
Chris Wilsona58c01a2016-04-29 13:18:21 +0100481static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
482{
483 return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
484}
485
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800486#endif /* _INTEL_RINGBUFFER_H_ */