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eric miaofe69af02008-02-14 15:48:23 +08001/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
Ezequiel Garciade484a32013-11-07 12:17:10 -030010 *
11 * See Documentation/mtd/nand/pxa3xx-nand.txt for more details.
eric miaofe69af02008-02-14 15:48:23 +080012 */
13
Haojian Zhuanga88bdbb2009-09-11 19:33:58 +080014#include <linux/kernel.h>
eric miaofe69af02008-02-14 15:48:23 +080015#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/partitions.h>
David Woodhousea1c06ee2008-04-22 20:39:43 +010024#include <linux/io.h>
Maxime Ripardafca11e2015-04-07 15:32:45 +020025#include <linux/iopoll.h>
David Woodhousea1c06ee2008-04-22 20:39:43 +010026#include <linux/irq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090027#include <linux/slab.h>
Daniel Mack1e7ba632012-07-22 19:51:02 +020028#include <linux/of.h>
29#include <linux/of_device.h>
Ezequiel Garcia776f2652013-11-14 18:25:28 -030030#include <linux/of_mtd.h>
eric miaofe69af02008-02-14 15:48:23 +080031
Rob Herringce914e62015-04-30 15:17:47 -050032#if defined(CONFIG_ARM) && (defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP))
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -030033#define ARCH_HAS_DMA
34#endif
35
36#ifdef ARCH_HAS_DMA
Eric Miaoafb5b5c2008-12-01 11:43:08 +080037#include <mach/dma.h>
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -030038#endif
39
Arnd Bergmann293b2da2012-08-24 15:16:48 +020040#include <linux/platform_data/mtd-nand-pxa3xx.h>
eric miaofe69af02008-02-14 15:48:23 +080041
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -050042#define CHIP_DELAY_TIMEOUT msecs_to_jiffies(200)
43#define NAND_STOP_DELAY msecs_to_jiffies(40)
Lei Wen4eb2da82011-02-28 10:32:13 +080044#define PAGE_CHUNK_SIZE (2048)
eric miaofe69af02008-02-14 15:48:23 +080045
Ezequiel Garcia62e8b852013-10-04 15:30:38 -030046/*
47 * Define a buffer size for the initial command that detects the flash device:
Ezequiel Garciac1634092015-08-03 11:31:26 -030048 * STATUS, READID and PARAM.
49 * ONFI param page is 256 bytes, and there are three redundant copies
50 * to be read. JEDEC param page is 512 bytes, and there are also three
51 * redundant copies to be read.
52 * Hence this buffer should be at least 512 x 3. Let's pick 2048.
Ezequiel Garcia62e8b852013-10-04 15:30:38 -030053 */
Ezequiel Garciac1634092015-08-03 11:31:26 -030054#define INIT_BUFFER_SIZE 2048
Ezequiel Garcia62e8b852013-10-04 15:30:38 -030055
eric miaofe69af02008-02-14 15:48:23 +080056/* registers and bit definitions */
57#define NDCR (0x00) /* Control register */
58#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
59#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
60#define NDSR (0x14) /* Status Register */
61#define NDPCR (0x18) /* Page Count Register */
62#define NDBDR0 (0x1C) /* Bad Block Register 0 */
63#define NDBDR1 (0x20) /* Bad Block Register 1 */
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -030064#define NDECCCTRL (0x28) /* ECC control */
eric miaofe69af02008-02-14 15:48:23 +080065#define NDDB (0x40) /* Data Buffer */
66#define NDCB0 (0x48) /* Command Buffer0 */
67#define NDCB1 (0x4C) /* Command Buffer1 */
68#define NDCB2 (0x50) /* Command Buffer2 */
69
70#define NDCR_SPARE_EN (0x1 << 31)
71#define NDCR_ECC_EN (0x1 << 30)
72#define NDCR_DMA_EN (0x1 << 29)
73#define NDCR_ND_RUN (0x1 << 28)
74#define NDCR_DWIDTH_C (0x1 << 27)
75#define NDCR_DWIDTH_M (0x1 << 26)
76#define NDCR_PAGE_SZ (0x1 << 24)
77#define NDCR_NCSX (0x1 << 23)
78#define NDCR_ND_MODE (0x3 << 21)
79#define NDCR_NAND_MODE (0x0)
80#define NDCR_CLR_PG_CNT (0x1 << 20)
Lei Wenf8155a42011-02-28 10:32:11 +080081#define NDCR_STOP_ON_UNCOR (0x1 << 19)
eric miaofe69af02008-02-14 15:48:23 +080082#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
83#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
84
85#define NDCR_RA_START (0x1 << 15)
86#define NDCR_PG_PER_BLK (0x1 << 14)
87#define NDCR_ND_ARB_EN (0x1 << 12)
Lei Wenf8155a42011-02-28 10:32:11 +080088#define NDCR_INT_MASK (0xFFF)
eric miaofe69af02008-02-14 15:48:23 +080089
90#define NDSR_MASK (0xfff)
Ezequiel Garcia87f53362013-11-14 18:25:39 -030091#define NDSR_ERR_CNT_OFF (16)
92#define NDSR_ERR_CNT_MASK (0x1f)
93#define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
Lei Wenf8155a42011-02-28 10:32:11 +080094#define NDSR_RDY (0x1 << 12)
95#define NDSR_FLASH_RDY (0x1 << 11)
eric miaofe69af02008-02-14 15:48:23 +080096#define NDSR_CS0_PAGED (0x1 << 10)
97#define NDSR_CS1_PAGED (0x1 << 9)
98#define NDSR_CS0_CMDD (0x1 << 8)
99#define NDSR_CS1_CMDD (0x1 << 7)
100#define NDSR_CS0_BBD (0x1 << 6)
101#define NDSR_CS1_BBD (0x1 << 5)
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300102#define NDSR_UNCORERR (0x1 << 4)
103#define NDSR_CORERR (0x1 << 3)
eric miaofe69af02008-02-14 15:48:23 +0800104#define NDSR_WRDREQ (0x1 << 2)
105#define NDSR_RDDREQ (0x1 << 1)
106#define NDSR_WRCMDREQ (0x1)
107
Ezequiel Garcia41a63432013-08-12 14:14:51 -0300108#define NDCB0_LEN_OVRD (0x1 << 28)
Lei Wen4eb2da82011-02-28 10:32:13 +0800109#define NDCB0_ST_ROW_EN (0x1 << 26)
eric miaofe69af02008-02-14 15:48:23 +0800110#define NDCB0_AUTO_RS (0x1 << 25)
111#define NDCB0_CSEL (0x1 << 24)
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300112#define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
113#define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
eric miaofe69af02008-02-14 15:48:23 +0800114#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
115#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
116#define NDCB0_NC (0x1 << 20)
117#define NDCB0_DBC (0x1 << 19)
118#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
119#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
120#define NDCB0_CMD2_MASK (0xff << 8)
121#define NDCB0_CMD1_MASK (0xff)
122#define NDCB0_ADDR_CYC_SHIFT (16)
123
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300124#define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
125#define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
126#define EXT_CMD_TYPE_READ 4 /* Read */
127#define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
128#define EXT_CMD_TYPE_FINAL 3 /* Final command */
129#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
130#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
131
eric miaofe69af02008-02-14 15:48:23 +0800132/* macros for registers read/write */
133#define nand_writel(info, off, val) \
Thomas Petazzonib7e460622014-05-22 14:56:52 +0200134 writel_relaxed((val), (info)->mmio_base + (off))
eric miaofe69af02008-02-14 15:48:23 +0800135
136#define nand_readl(info, off) \
Thomas Petazzonib7e460622014-05-22 14:56:52 +0200137 readl_relaxed((info)->mmio_base + (off))
eric miaofe69af02008-02-14 15:48:23 +0800138
139/* error code and state */
140enum {
141 ERR_NONE = 0,
142 ERR_DMABUSERR = -1,
143 ERR_SENDCMD = -2,
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300144 ERR_UNCORERR = -3,
eric miaofe69af02008-02-14 15:48:23 +0800145 ERR_BBERR = -4,
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300146 ERR_CORERR = -5,
eric miaofe69af02008-02-14 15:48:23 +0800147};
148
149enum {
Lei Wenf8155a42011-02-28 10:32:11 +0800150 STATE_IDLE = 0,
Lei Wend4568822011-07-14 20:44:32 -0700151 STATE_PREPARED,
eric miaofe69af02008-02-14 15:48:23 +0800152 STATE_CMD_HANDLE,
153 STATE_DMA_READING,
154 STATE_DMA_WRITING,
155 STATE_DMA_DONE,
156 STATE_PIO_READING,
157 STATE_PIO_WRITING,
Lei Wenf8155a42011-02-28 10:32:11 +0800158 STATE_CMD_DONE,
159 STATE_READY,
eric miaofe69af02008-02-14 15:48:23 +0800160};
161
Ezequiel Garciac0f3b862013-08-10 16:34:52 -0300162enum pxa3xx_nand_variant {
163 PXA3XX_NAND_VARIANT_PXA,
164 PXA3XX_NAND_VARIANT_ARMADA370,
165};
166
Lei Wend4568822011-07-14 20:44:32 -0700167struct pxa3xx_nand_host {
168 struct nand_chip chip;
Lei Wend4568822011-07-14 20:44:32 -0700169 struct mtd_info *mtd;
170 void *info_data;
eric miaofe69af02008-02-14 15:48:23 +0800171
Lei Wend4568822011-07-14 20:44:32 -0700172 /* page size of attached chip */
Lei Wend4568822011-07-14 20:44:32 -0700173 int use_ecc;
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700174 int cs;
Lei Wend4568822011-07-14 20:44:32 -0700175
176 /* calculated from pxa3xx_nand_flash data */
177 unsigned int col_addr_cycles;
178 unsigned int row_addr_cycles;
179 size_t read_id_bytes;
180
Lei Wend4568822011-07-14 20:44:32 -0700181};
182
183struct pxa3xx_nand_info {
Lei Wen401e67e2011-02-28 10:32:14 +0800184 struct nand_hw_control controller;
eric miaofe69af02008-02-14 15:48:23 +0800185 struct platform_device *pdev;
eric miaofe69af02008-02-14 15:48:23 +0800186
187 struct clk *clk;
188 void __iomem *mmio_base;
Haojian Zhuang8638fac2009-09-10 14:11:44 +0800189 unsigned long mmio_phys;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300190 struct completion cmd_complete, dev_ready;
eric miaofe69af02008-02-14 15:48:23 +0800191
192 unsigned int buf_start;
193 unsigned int buf_count;
Ezequiel Garcia62e8b852013-10-04 15:30:38 -0300194 unsigned int buf_size;
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300195 unsigned int data_buff_pos;
196 unsigned int oob_buff_pos;
eric miaofe69af02008-02-14 15:48:23 +0800197
198 /* DMA information */
199 int drcmr_dat;
200 int drcmr_cmd;
201
202 unsigned char *data_buff;
Lei Wen18c81b12010-08-17 17:25:57 +0800203 unsigned char *oob_buff;
eric miaofe69af02008-02-14 15:48:23 +0800204 dma_addr_t data_buff_phys;
eric miaofe69af02008-02-14 15:48:23 +0800205 int data_dma_ch;
206 struct pxa_dma_desc *data_desc;
207 dma_addr_t data_desc_addr;
208
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700209 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
eric miaofe69af02008-02-14 15:48:23 +0800210 unsigned int state;
211
Ezequiel Garciac0f3b862013-08-10 16:34:52 -0300212 /*
213 * This driver supports NFCv1 (as found in PXA SoC)
214 * and NFCv2 (as found in Armada 370/XP SoC).
215 */
216 enum pxa3xx_nand_variant variant;
217
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700218 int cs;
eric miaofe69af02008-02-14 15:48:23 +0800219 int use_ecc; /* use HW ECC ? */
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300220 int ecc_bch; /* using BCH ECC? */
eric miaofe69af02008-02-14 15:48:23 +0800221 int use_dma; /* use DMA ? */
Ezequiel Garcia5bb653e2013-08-12 14:14:49 -0300222 int use_spare; /* use spare ? */
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300223 int need_wait;
eric miaofe69af02008-02-14 15:48:23 +0800224
Ezequiel Garcia2128b082013-11-07 12:17:16 -0300225 unsigned int data_size; /* data to be read from FIFO */
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300226 unsigned int chunk_size; /* split commands chunk size */
Lei Wend4568822011-07-14 20:44:32 -0700227 unsigned int oob_size;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300228 unsigned int spare_size;
229 unsigned int ecc_size;
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300230 unsigned int ecc_err_cnt;
231 unsigned int max_bitflips;
eric miaofe69af02008-02-14 15:48:23 +0800232 int retcode;
eric miaofe69af02008-02-14 15:48:23 +0800233
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300234 /* cached register value */
235 uint32_t reg_ndcr;
236 uint32_t ndtr0cs0;
237 uint32_t ndtr1cs0;
238
eric miaofe69af02008-02-14 15:48:23 +0800239 /* generated NDCBx register values */
240 uint32_t ndcb0;
241 uint32_t ndcb1;
242 uint32_t ndcb2;
Ezequiel Garcia3a1a3442013-08-12 14:14:50 -0300243 uint32_t ndcb3;
eric miaofe69af02008-02-14 15:48:23 +0800244};
245
Rusty Russell90ab5ee2012-01-13 09:32:20 +1030246static bool use_dma = 1;
eric miaofe69af02008-02-14 15:48:23 +0800247module_param(use_dma, bool, 0444);
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300248MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
eric miaofe69af02008-02-14 15:48:23 +0800249
Lei Wenc1f82472010-08-17 13:50:23 +0800250static struct pxa3xx_nand_timing timing[] = {
Lei Wen227a8862010-08-18 18:00:03 +0800251 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
252 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
253 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
254 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
eric miaofe69af02008-02-14 15:48:23 +0800255};
256
Lei Wenc1f82472010-08-17 13:50:23 +0800257static struct pxa3xx_nand_flash builtin_flash_types[] = {
Lei Wen4332c112011-03-03 11:27:01 +0800258{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
259{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
260{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
261{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
262{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
263{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
264{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
265{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
266{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
eric miaofe69af02008-02-14 15:48:23 +0800267};
268
Ezequiel Garcia776f2652013-11-14 18:25:28 -0300269static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
270static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
271
272static struct nand_bbt_descr bbt_main_descr = {
273 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
274 | NAND_BBT_2BIT | NAND_BBT_VERSION,
275 .offs = 8,
276 .len = 6,
277 .veroffs = 14,
278 .maxblocks = 8, /* Last 8 blocks in each chip */
279 .pattern = bbt_pattern
280};
281
282static struct nand_bbt_descr bbt_mirror_descr = {
283 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
284 | NAND_BBT_2BIT | NAND_BBT_VERSION,
285 .offs = 8,
286 .len = 6,
287 .veroffs = 14,
288 .maxblocks = 8, /* Last 8 blocks in each chip */
289 .pattern = bbt_mirror_pattern
290};
291
Rodolfo Giometti3db227b2014-01-13 15:35:38 +0100292static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
293 .eccbytes = 32,
294 .eccpos = {
295 32, 33, 34, 35, 36, 37, 38, 39,
296 40, 41, 42, 43, 44, 45, 46, 47,
297 48, 49, 50, 51, 52, 53, 54, 55,
298 56, 57, 58, 59, 60, 61, 62, 63},
299 .oobfree = { {2, 30} }
300};
301
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300302static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
303 .eccbytes = 64,
304 .eccpos = {
305 32, 33, 34, 35, 36, 37, 38, 39,
306 40, 41, 42, 43, 44, 45, 46, 47,
307 48, 49, 50, 51, 52, 53, 54, 55,
308 56, 57, 58, 59, 60, 61, 62, 63,
309 96, 97, 98, 99, 100, 101, 102, 103,
310 104, 105, 106, 107, 108, 109, 110, 111,
311 112, 113, 114, 115, 116, 117, 118, 119,
312 120, 121, 122, 123, 124, 125, 126, 127},
313 /* Bootrom looks in bytes 0 & 5 for bad blocks */
314 .oobfree = { {6, 26}, { 64, 32} }
315};
316
317static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
318 .eccbytes = 128,
319 .eccpos = {
320 32, 33, 34, 35, 36, 37, 38, 39,
321 40, 41, 42, 43, 44, 45, 46, 47,
322 48, 49, 50, 51, 52, 53, 54, 55,
323 56, 57, 58, 59, 60, 61, 62, 63},
324 .oobfree = { }
325};
326
Lei Wen227a8862010-08-18 18:00:03 +0800327/* Define a default flash type setting serve as flash detecting only */
328#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
329
eric miaofe69af02008-02-14 15:48:23 +0800330#define NDTR0_tCH(c) (min((c), 7) << 19)
331#define NDTR0_tCS(c) (min((c), 7) << 16)
332#define NDTR0_tWH(c) (min((c), 7) << 11)
333#define NDTR0_tWP(c) (min((c), 7) << 8)
334#define NDTR0_tRH(c) (min((c), 7) << 3)
335#define NDTR0_tRP(c) (min((c), 7) << 0)
336
337#define NDTR1_tR(c) (min((c), 65535) << 16)
338#define NDTR1_tWHR(c) (min((c), 15) << 4)
339#define NDTR1_tAR(c) (min((c), 15) << 0)
340
341/* convert nano-seconds to nand flash controller clock cycles */
Axel Lin93b352f2010-08-16 16:09:09 +0800342#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
eric miaofe69af02008-02-14 15:48:23 +0800343
Jingoo Han17754ad2014-05-07 17:49:13 +0900344static const struct of_device_id pxa3xx_nand_dt_ids[] = {
Ezequiel Garciac7e9c7e2013-11-07 12:17:14 -0300345 {
346 .compatible = "marvell,pxa3xx-nand",
347 .data = (void *)PXA3XX_NAND_VARIANT_PXA,
348 },
Ezequiel Garcia1963ff92013-12-24 12:40:07 -0300349 {
350 .compatible = "marvell,armada370-nand",
351 .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
352 },
Ezequiel Garciac7e9c7e2013-11-07 12:17:14 -0300353 {}
354};
355MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
356
357static enum pxa3xx_nand_variant
358pxa3xx_nand_get_variant(struct platform_device *pdev)
359{
360 const struct of_device_id *of_id =
361 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
362 if (!of_id)
363 return PXA3XX_NAND_VARIANT_PXA;
364 return (enum pxa3xx_nand_variant)of_id->data;
365}
366
Lei Wend4568822011-07-14 20:44:32 -0700367static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
Enrico Scholz7dad4822008-08-29 12:59:50 +0200368 const struct pxa3xx_nand_timing *t)
eric miaofe69af02008-02-14 15:48:23 +0800369{
Lei Wend4568822011-07-14 20:44:32 -0700370 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +0800371 unsigned long nand_clk = clk_get_rate(info->clk);
372 uint32_t ndtr0, ndtr1;
373
374 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
375 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
376 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
377 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
378 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
379 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
380
381 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
382 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
383 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
384
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300385 info->ndtr0cs0 = ndtr0;
386 info->ndtr1cs0 = ndtr1;
eric miaofe69af02008-02-14 15:48:23 +0800387 nand_writel(info, NDTR0CS0, ndtr0);
388 nand_writel(info, NDTR1CS0, ndtr1);
389}
390
Ezequiel Garcia6a3e4862013-11-07 12:17:18 -0300391/*
392 * Set the data and OOB size, depending on the selected
393 * spare and ECC configuration.
394 * Only applicable to READ0, READOOB and PAGEPROG commands.
395 */
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300396static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info,
397 struct mtd_info *mtd)
eric miaofe69af02008-02-14 15:48:23 +0800398{
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300399 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
Lei Wen9d8b1042010-08-17 14:09:30 +0800400
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300401 info->data_size = mtd->writesize;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300402 if (!oob_enable)
Lei Wen9d8b1042010-08-17 14:09:30 +0800403 return;
Lei Wen9d8b1042010-08-17 14:09:30 +0800404
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300405 info->oob_size = info->spare_size;
406 if (!info->use_ecc)
407 info->oob_size += info->ecc_size;
Lei Wen18c81b12010-08-17 17:25:57 +0800408}
409
Lei Wenf8155a42011-02-28 10:32:11 +0800410/**
411 * NOTE: it is a must to set ND_RUN firstly, then write
412 * command buffer, otherwise, it does not work.
413 * We enable all the interrupt at the same time, and
414 * let pxa3xx_nand_irq to handle all logic.
415 */
416static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
417{
418 uint32_t ndcr;
419
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300420 ndcr = info->reg_ndcr;
Ezequiel Garciacd9d1182013-08-12 14:14:48 -0300421
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300422 if (info->use_ecc) {
Ezequiel Garciacd9d1182013-08-12 14:14:48 -0300423 ndcr |= NDCR_ECC_EN;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300424 if (info->ecc_bch)
425 nand_writel(info, NDECCCTRL, 0x1);
426 } else {
Ezequiel Garciacd9d1182013-08-12 14:14:48 -0300427 ndcr &= ~NDCR_ECC_EN;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300428 if (info->ecc_bch)
429 nand_writel(info, NDECCCTRL, 0x0);
430 }
Ezequiel Garciacd9d1182013-08-12 14:14:48 -0300431
432 if (info->use_dma)
433 ndcr |= NDCR_DMA_EN;
434 else
435 ndcr &= ~NDCR_DMA_EN;
436
Ezequiel Garcia5bb653e2013-08-12 14:14:49 -0300437 if (info->use_spare)
438 ndcr |= NDCR_SPARE_EN;
439 else
440 ndcr &= ~NDCR_SPARE_EN;
441
Lei Wenf8155a42011-02-28 10:32:11 +0800442 ndcr |= NDCR_ND_RUN;
443
444 /* clear status bits and run */
445 nand_writel(info, NDCR, 0);
446 nand_writel(info, NDSR, NDSR_MASK);
447 nand_writel(info, NDCR, ndcr);
448}
449
450static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
451{
452 uint32_t ndcr;
453 int timeout = NAND_STOP_DELAY;
454
455 /* wait RUN bit in NDCR become 0 */
456 ndcr = nand_readl(info, NDCR);
457 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
458 ndcr = nand_readl(info, NDCR);
459 udelay(1);
460 }
461
462 if (timeout <= 0) {
463 ndcr &= ~NDCR_ND_RUN;
464 nand_writel(info, NDCR, ndcr);
465 }
466 /* clear status bits */
467 nand_writel(info, NDSR, NDSR_MASK);
468}
469
Ezequiel Garcia57ff88f2013-08-12 14:14:57 -0300470static void __maybe_unused
471enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
eric miaofe69af02008-02-14 15:48:23 +0800472{
473 uint32_t ndcr;
474
475 ndcr = nand_readl(info, NDCR);
476 nand_writel(info, NDCR, ndcr & ~int_mask);
477}
478
479static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
480{
481 uint32_t ndcr;
482
483 ndcr = nand_readl(info, NDCR);
484 nand_writel(info, NDCR, ndcr | int_mask);
485}
486
Maxime Ripard8dad0382015-02-18 11:32:07 +0100487static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
488{
489 if (info->ecc_bch) {
Maxime Ripardafca11e2015-04-07 15:32:45 +0200490 u32 val;
491 int ret;
Maxime Ripard8dad0382015-02-18 11:32:07 +0100492
493 /*
494 * According to the datasheet, when reading from NDDB
495 * with BCH enabled, after each 32 bytes reads, we
496 * have to make sure that the NDSR.RDDREQ bit is set.
497 *
498 * Drain the FIFO 8 32 bits reads at a time, and skip
499 * the polling on the last read.
500 */
501 while (len > 8) {
Rob Herringce914e62015-04-30 15:17:47 -0500502 readsl(info->mmio_base + NDDB, data, 8);
Maxime Ripard8dad0382015-02-18 11:32:07 +0100503
Maxime Ripardafca11e2015-04-07 15:32:45 +0200504 ret = readl_relaxed_poll_timeout(info->mmio_base + NDSR, val,
505 val & NDSR_RDDREQ, 1000, 5000);
506 if (ret) {
507 dev_err(&info->pdev->dev,
508 "Timeout on RDDREQ while draining the FIFO\n");
509 return;
Maxime Ripard8dad0382015-02-18 11:32:07 +0100510 }
511
512 data += 32;
513 len -= 8;
514 }
515 }
516
Rob Herringce914e62015-04-30 15:17:47 -0500517 readsl(info->mmio_base + NDDB, data, len);
Maxime Ripard8dad0382015-02-18 11:32:07 +0100518}
519
Lei Wenf8155a42011-02-28 10:32:11 +0800520static void handle_data_pio(struct pxa3xx_nand_info *info)
eric miaofe69af02008-02-14 15:48:23 +0800521{
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300522 unsigned int do_bytes = min(info->data_size, info->chunk_size);
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300523
eric miaofe69af02008-02-14 15:48:23 +0800524 switch (info->state) {
525 case STATE_PIO_WRITING:
Rob Herringce914e62015-04-30 15:17:47 -0500526 writesl(info->mmio_base + NDDB,
527 info->data_buff + info->data_buff_pos,
528 DIV_ROUND_UP(do_bytes, 4));
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300529
Lei Wen9d8b1042010-08-17 14:09:30 +0800530 if (info->oob_size > 0)
Rob Herringce914e62015-04-30 15:17:47 -0500531 writesl(info->mmio_base + NDDB,
532 info->oob_buff + info->oob_buff_pos,
533 DIV_ROUND_UP(info->oob_size, 4));
eric miaofe69af02008-02-14 15:48:23 +0800534 break;
535 case STATE_PIO_READING:
Maxime Ripard8dad0382015-02-18 11:32:07 +0100536 drain_fifo(info,
537 info->data_buff + info->data_buff_pos,
538 DIV_ROUND_UP(do_bytes, 4));
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300539
Lei Wen9d8b1042010-08-17 14:09:30 +0800540 if (info->oob_size > 0)
Maxime Ripard8dad0382015-02-18 11:32:07 +0100541 drain_fifo(info,
542 info->oob_buff + info->oob_buff_pos,
543 DIV_ROUND_UP(info->oob_size, 4));
eric miaofe69af02008-02-14 15:48:23 +0800544 break;
545 default:
Lei Wenda675b42011-07-14 20:44:31 -0700546 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
eric miaofe69af02008-02-14 15:48:23 +0800547 info->state);
Lei Wenf8155a42011-02-28 10:32:11 +0800548 BUG();
eric miaofe69af02008-02-14 15:48:23 +0800549 }
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300550
551 /* Update buffer pointers for multi-page read/write */
552 info->data_buff_pos += do_bytes;
553 info->oob_buff_pos += info->oob_size;
554 info->data_size -= do_bytes;
eric miaofe69af02008-02-14 15:48:23 +0800555}
556
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -0300557#ifdef ARCH_HAS_DMA
Lei Wenf8155a42011-02-28 10:32:11 +0800558static void start_data_dma(struct pxa3xx_nand_info *info)
eric miaofe69af02008-02-14 15:48:23 +0800559{
560 struct pxa_dma_desc *desc = info->data_desc;
Lei Wen9d8b1042010-08-17 14:09:30 +0800561 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
eric miaofe69af02008-02-14 15:48:23 +0800562
563 desc->ddadr = DDADR_STOP;
564 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
565
Lei Wenf8155a42011-02-28 10:32:11 +0800566 switch (info->state) {
567 case STATE_DMA_WRITING:
eric miaofe69af02008-02-14 15:48:23 +0800568 desc->dsadr = info->data_buff_phys;
Haojian Zhuang8638fac2009-09-10 14:11:44 +0800569 desc->dtadr = info->mmio_phys + NDDB;
eric miaofe69af02008-02-14 15:48:23 +0800570 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
Lei Wenf8155a42011-02-28 10:32:11 +0800571 break;
572 case STATE_DMA_READING:
eric miaofe69af02008-02-14 15:48:23 +0800573 desc->dtadr = info->data_buff_phys;
Haojian Zhuang8638fac2009-09-10 14:11:44 +0800574 desc->dsadr = info->mmio_phys + NDDB;
eric miaofe69af02008-02-14 15:48:23 +0800575 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
Lei Wenf8155a42011-02-28 10:32:11 +0800576 break;
577 default:
Lei Wenda675b42011-07-14 20:44:31 -0700578 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
Lei Wenf8155a42011-02-28 10:32:11 +0800579 info->state);
580 BUG();
eric miaofe69af02008-02-14 15:48:23 +0800581 }
582
583 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
584 DDADR(info->data_dma_ch) = info->data_desc_addr;
585 DCSR(info->data_dma_ch) |= DCSR_RUN;
586}
587
588static void pxa3xx_nand_data_dma_irq(int channel, void *data)
589{
590 struct pxa3xx_nand_info *info = data;
591 uint32_t dcsr;
592
593 dcsr = DCSR(channel);
594 DCSR(channel) = dcsr;
595
596 if (dcsr & DCSR_BUSERR) {
597 info->retcode = ERR_DMABUSERR;
eric miaofe69af02008-02-14 15:48:23 +0800598 }
599
Lei Wenf8155a42011-02-28 10:32:11 +0800600 info->state = STATE_DMA_DONE;
601 enable_int(info, NDCR_INT_MASK);
602 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
eric miaofe69af02008-02-14 15:48:23 +0800603}
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -0300604#else
605static void start_data_dma(struct pxa3xx_nand_info *info)
606{}
607#endif
eric miaofe69af02008-02-14 15:48:23 +0800608
Robert Jarzmik24542252015-02-20 19:36:43 +0100609static irqreturn_t pxa3xx_nand_irq_thread(int irq, void *data)
610{
611 struct pxa3xx_nand_info *info = data;
612
613 handle_data_pio(info);
614
615 info->state = STATE_CMD_DONE;
616 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
617
618 return IRQ_HANDLED;
619}
620
eric miaofe69af02008-02-14 15:48:23 +0800621static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
622{
623 struct pxa3xx_nand_info *info = devid;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300624 unsigned int status, is_completed = 0, is_ready = 0;
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700625 unsigned int ready, cmd_done;
Robert Jarzmik24542252015-02-20 19:36:43 +0100626 irqreturn_t ret = IRQ_HANDLED;
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700627
628 if (info->cs == 0) {
629 ready = NDSR_FLASH_RDY;
630 cmd_done = NDSR_CS0_CMDD;
631 } else {
632 ready = NDSR_RDY;
633 cmd_done = NDSR_CS1_CMDD;
634 }
eric miaofe69af02008-02-14 15:48:23 +0800635
636 status = nand_readl(info, NDSR);
637
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300638 if (status & NDSR_UNCORERR)
639 info->retcode = ERR_UNCORERR;
640 if (status & NDSR_CORERR) {
641 info->retcode = ERR_CORERR;
642 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
643 info->ecc_bch)
644 info->ecc_err_cnt = NDSR_ERR_CNT(status);
645 else
646 info->ecc_err_cnt = 1;
647
648 /*
649 * Each chunk composing a page is corrected independently,
650 * and we need to store maximum number of corrected bitflips
651 * to return it to the MTD layer in ecc.read_page().
652 */
653 info->max_bitflips = max_t(unsigned int,
654 info->max_bitflips,
655 info->ecc_err_cnt);
656 }
Lei Wenf8155a42011-02-28 10:32:11 +0800657 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
658 /* whether use dma to transfer data */
eric miaofe69af02008-02-14 15:48:23 +0800659 if (info->use_dma) {
Lei Wenf8155a42011-02-28 10:32:11 +0800660 disable_int(info, NDCR_INT_MASK);
661 info->state = (status & NDSR_RDDREQ) ?
662 STATE_DMA_READING : STATE_DMA_WRITING;
663 start_data_dma(info);
664 goto NORMAL_IRQ_EXIT;
eric miaofe69af02008-02-14 15:48:23 +0800665 } else {
Lei Wenf8155a42011-02-28 10:32:11 +0800666 info->state = (status & NDSR_RDDREQ) ?
667 STATE_PIO_READING : STATE_PIO_WRITING;
Robert Jarzmik24542252015-02-20 19:36:43 +0100668 ret = IRQ_WAKE_THREAD;
669 goto NORMAL_IRQ_EXIT;
eric miaofe69af02008-02-14 15:48:23 +0800670 }
Lei Wenf8155a42011-02-28 10:32:11 +0800671 }
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700672 if (status & cmd_done) {
Lei Wenf8155a42011-02-28 10:32:11 +0800673 info->state = STATE_CMD_DONE;
674 is_completed = 1;
675 }
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700676 if (status & ready) {
eric miaofe69af02008-02-14 15:48:23 +0800677 info->state = STATE_READY;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300678 is_ready = 1;
Lei Wen401e67e2011-02-28 10:32:14 +0800679 }
Lei Wenf8155a42011-02-28 10:32:11 +0800680
681 if (status & NDSR_WRCMDREQ) {
682 nand_writel(info, NDSR, NDSR_WRCMDREQ);
683 status &= ~NDSR_WRCMDREQ;
684 info->state = STATE_CMD_HANDLE;
Ezequiel Garcia3a1a3442013-08-12 14:14:50 -0300685
686 /*
687 * Command buffer registers NDCB{0-2} (and optionally NDCB3)
688 * must be loaded by writing directly either 12 or 16
689 * bytes directly to NDCB0, four bytes at a time.
690 *
691 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
692 * but each NDCBx register can be read.
693 */
Lei Wenf8155a42011-02-28 10:32:11 +0800694 nand_writel(info, NDCB0, info->ndcb0);
695 nand_writel(info, NDCB0, info->ndcb1);
696 nand_writel(info, NDCB0, info->ndcb2);
Ezequiel Garcia3a1a3442013-08-12 14:14:50 -0300697
698 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
699 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
700 nand_writel(info, NDCB0, info->ndcb3);
eric miaofe69af02008-02-14 15:48:23 +0800701 }
Lei Wenf8155a42011-02-28 10:32:11 +0800702
703 /* clear NDSR to let the controller exit the IRQ */
eric miaofe69af02008-02-14 15:48:23 +0800704 nand_writel(info, NDSR, status);
Lei Wenf8155a42011-02-28 10:32:11 +0800705 if (is_completed)
706 complete(&info->cmd_complete);
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300707 if (is_ready)
708 complete(&info->dev_ready);
Lei Wenf8155a42011-02-28 10:32:11 +0800709NORMAL_IRQ_EXIT:
Robert Jarzmik24542252015-02-20 19:36:43 +0100710 return ret;
eric miaofe69af02008-02-14 15:48:23 +0800711}
712
eric miaofe69af02008-02-14 15:48:23 +0800713static inline int is_buf_blank(uint8_t *buf, size_t len)
714{
715 for (; len > 0; len--)
716 if (*buf++ != 0xff)
717 return 0;
718 return 1;
719}
720
Ezequiel Garcia86beeba2013-11-14 18:25:31 -0300721static void set_command_address(struct pxa3xx_nand_info *info,
722 unsigned int page_size, uint16_t column, int page_addr)
723{
724 /* small page addr setting */
725 if (page_size < PAGE_CHUNK_SIZE) {
726 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
727 | (column & 0xFF);
728
729 info->ndcb2 = 0;
730 } else {
731 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
732 | (column & 0xFFFF);
733
734 if (page_addr & 0xFF0000)
735 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
736 else
737 info->ndcb2 = 0;
738 }
739}
740
Ezequiel Garciac39ff032013-11-14 18:25:33 -0300741static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
Lei Wen4eb2da82011-02-28 10:32:13 +0800742{
Ezequiel Garcia39f83d12013-11-14 18:25:34 -0300743 struct pxa3xx_nand_host *host = info->host[info->cs];
744 struct mtd_info *mtd = host->mtd;
745
Lei Wen4eb2da82011-02-28 10:32:13 +0800746 /* reset data and oob column point to handle data */
Lei Wen401e67e2011-02-28 10:32:14 +0800747 info->buf_start = 0;
748 info->buf_count = 0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800749 info->oob_size = 0;
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300750 info->data_buff_pos = 0;
751 info->oob_buff_pos = 0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800752 info->use_ecc = 0;
Ezequiel Garcia5bb653e2013-08-12 14:14:49 -0300753 info->use_spare = 1;
Lei Wen4eb2da82011-02-28 10:32:13 +0800754 info->retcode = ERR_NONE;
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300755 info->ecc_err_cnt = 0;
Ezequiel Garciaf0e6a32e2013-11-14 18:25:30 -0300756 info->ndcb3 = 0;
Ezequiel Garciad20d0a62013-12-18 18:44:08 -0300757 info->need_wait = 0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800758
759 switch (command) {
760 case NAND_CMD_READ0:
761 case NAND_CMD_PAGEPROG:
762 info->use_ecc = 1;
763 case NAND_CMD_READOOB:
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300764 pxa3xx_set_datasize(info, mtd);
Lei Wen4eb2da82011-02-28 10:32:13 +0800765 break;
Ezequiel Garcia41a63432013-08-12 14:14:51 -0300766 case NAND_CMD_PARAM:
767 info->use_spare = 0;
768 break;
Lei Wen4eb2da82011-02-28 10:32:13 +0800769 default:
770 info->ndcb1 = 0;
771 info->ndcb2 = 0;
772 break;
773 }
Ezequiel Garcia39f83d12013-11-14 18:25:34 -0300774
775 /*
776 * If we are about to issue a read command, or about to set
777 * the write address, then clean the data buffer.
778 */
779 if (command == NAND_CMD_READ0 ||
780 command == NAND_CMD_READOOB ||
781 command == NAND_CMD_SEQIN) {
782
783 info->buf_count = mtd->writesize + mtd->oobsize;
784 memset(info->data_buff, 0xFF, info->buf_count);
785 }
786
Ezequiel Garciac39ff032013-11-14 18:25:33 -0300787}
788
789static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300790 int ext_cmd_type, uint16_t column, int page_addr)
Ezequiel Garciac39ff032013-11-14 18:25:33 -0300791{
792 int addr_cycle, exec_cmd;
793 struct pxa3xx_nand_host *host;
794 struct mtd_info *mtd;
795
796 host = info->host[info->cs];
797 mtd = host->mtd;
798 addr_cycle = 0;
799 exec_cmd = 1;
800
801 if (info->cs != 0)
802 info->ndcb0 = NDCB0_CSEL;
803 else
804 info->ndcb0 = 0;
805
806 if (command == NAND_CMD_SEQIN)
807 exec_cmd = 0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800808
Lei Wend4568822011-07-14 20:44:32 -0700809 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
810 + host->col_addr_cycles);
Lei Wen4eb2da82011-02-28 10:32:13 +0800811
812 switch (command) {
813 case NAND_CMD_READOOB:
814 case NAND_CMD_READ0:
Ezequiel Garciaec821352013-08-12 14:14:54 -0300815 info->buf_start = column;
816 info->ndcb0 |= NDCB0_CMD_TYPE(0)
817 | addr_cycle
818 | NAND_CMD_READ0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800819
Ezequiel Garciaec821352013-08-12 14:14:54 -0300820 if (command == NAND_CMD_READOOB)
821 info->buf_start += mtd->writesize;
822
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300823 /*
824 * Multiple page read needs an 'extended command type' field,
825 * which is either naked-read or last-read according to the
826 * state.
827 */
828 if (mtd->writesize == PAGE_CHUNK_SIZE) {
Ezequiel Garciaec821352013-08-12 14:14:54 -0300829 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300830 } else if (mtd->writesize > PAGE_CHUNK_SIZE) {
831 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
832 | NDCB0_LEN_OVRD
833 | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
834 info->ndcb3 = info->chunk_size +
835 info->oob_size;
836 }
Lei Wen4eb2da82011-02-28 10:32:13 +0800837
Ezequiel Garcia01d99472013-11-14 18:25:32 -0300838 set_command_address(info, mtd->writesize, column, page_addr);
Ezequiel Garcia01d99472013-11-14 18:25:32 -0300839 break;
840
Lei Wen4eb2da82011-02-28 10:32:13 +0800841 case NAND_CMD_SEQIN:
Lei Wen4eb2da82011-02-28 10:32:13 +0800842
Ezequiel Garciae7f9a6a2013-11-14 18:25:35 -0300843 info->buf_start = column;
844 set_command_address(info, mtd->writesize, 0, page_addr);
Ezequiel Garcia535cb572013-11-14 18:25:38 -0300845
846 /*
847 * Multiple page programming needs to execute the initial
848 * SEQIN command that sets the page address.
849 */
850 if (mtd->writesize > PAGE_CHUNK_SIZE) {
851 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
852 | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
853 | addr_cycle
854 | command;
855 /* No data transfer in this case */
856 info->data_size = 0;
857 exec_cmd = 1;
858 }
Lei Wen4eb2da82011-02-28 10:32:13 +0800859 break;
860
861 case NAND_CMD_PAGEPROG:
862 if (is_buf_blank(info->data_buff,
863 (mtd->writesize + mtd->oobsize))) {
864 exec_cmd = 0;
865 break;
866 }
867
Ezequiel Garcia535cb572013-11-14 18:25:38 -0300868 /* Second command setting for large pages */
869 if (mtd->writesize > PAGE_CHUNK_SIZE) {
870 /*
871 * Multiple page write uses the 'extended command'
872 * field. This can be used to issue a command dispatch
873 * or a naked-write depending on the current stage.
874 */
875 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
876 | NDCB0_LEN_OVRD
877 | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
878 info->ndcb3 = info->chunk_size +
879 info->oob_size;
880
881 /*
882 * This is the command dispatch that completes a chunked
883 * page program operation.
884 */
885 if (info->data_size == 0) {
886 info->ndcb0 = NDCB0_CMD_TYPE(0x1)
887 | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
888 | command;
889 info->ndcb1 = 0;
890 info->ndcb2 = 0;
891 info->ndcb3 = 0;
892 }
893 } else {
894 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
895 | NDCB0_AUTO_RS
896 | NDCB0_ST_ROW_EN
897 | NDCB0_DBC
898 | (NAND_CMD_PAGEPROG << 8)
899 | NAND_CMD_SEQIN
900 | addr_cycle;
901 }
Lei Wen4eb2da82011-02-28 10:32:13 +0800902 break;
903
Ezequiel Garciace0268f2013-05-14 08:15:25 -0300904 case NAND_CMD_PARAM:
Ezequiel Garciac1634092015-08-03 11:31:26 -0300905 info->buf_count = INIT_BUFFER_SIZE;
Ezequiel Garciace0268f2013-05-14 08:15:25 -0300906 info->ndcb0 |= NDCB0_CMD_TYPE(0)
907 | NDCB0_ADDR_CYC(1)
Ezequiel Garcia41a63432013-08-12 14:14:51 -0300908 | NDCB0_LEN_OVRD
Ezequiel Garciaec821352013-08-12 14:14:54 -0300909 | command;
Ezequiel Garciace0268f2013-05-14 08:15:25 -0300910 info->ndcb1 = (column & 0xFF);
Ezequiel Garciac1634092015-08-03 11:31:26 -0300911 info->ndcb3 = INIT_BUFFER_SIZE;
912 info->data_size = INIT_BUFFER_SIZE;
Ezequiel Garciace0268f2013-05-14 08:15:25 -0300913 break;
914
Lei Wen4eb2da82011-02-28 10:32:13 +0800915 case NAND_CMD_READID:
Lei Wend4568822011-07-14 20:44:32 -0700916 info->buf_count = host->read_id_bytes;
Lei Wen4eb2da82011-02-28 10:32:13 +0800917 info->ndcb0 |= NDCB0_CMD_TYPE(3)
918 | NDCB0_ADDR_CYC(1)
Ezequiel Garciaec821352013-08-12 14:14:54 -0300919 | command;
Ezequiel Garciad14231f2013-05-14 08:15:24 -0300920 info->ndcb1 = (column & 0xFF);
Lei Wen4eb2da82011-02-28 10:32:13 +0800921
922 info->data_size = 8;
923 break;
924 case NAND_CMD_STATUS:
Lei Wen4eb2da82011-02-28 10:32:13 +0800925 info->buf_count = 1;
926 info->ndcb0 |= NDCB0_CMD_TYPE(4)
927 | NDCB0_ADDR_CYC(1)
Ezequiel Garciaec821352013-08-12 14:14:54 -0300928 | command;
Lei Wen4eb2da82011-02-28 10:32:13 +0800929
930 info->data_size = 8;
931 break;
932
933 case NAND_CMD_ERASE1:
Lei Wen4eb2da82011-02-28 10:32:13 +0800934 info->ndcb0 |= NDCB0_CMD_TYPE(2)
935 | NDCB0_AUTO_RS
936 | NDCB0_ADDR_CYC(3)
937 | NDCB0_DBC
Ezequiel Garciaec821352013-08-12 14:14:54 -0300938 | (NAND_CMD_ERASE2 << 8)
939 | NAND_CMD_ERASE1;
Lei Wen4eb2da82011-02-28 10:32:13 +0800940 info->ndcb1 = page_addr;
941 info->ndcb2 = 0;
942
943 break;
944 case NAND_CMD_RESET:
Lei Wen4eb2da82011-02-28 10:32:13 +0800945 info->ndcb0 |= NDCB0_CMD_TYPE(5)
Ezequiel Garciaec821352013-08-12 14:14:54 -0300946 | command;
Lei Wen4eb2da82011-02-28 10:32:13 +0800947
948 break;
949
950 case NAND_CMD_ERASE2:
951 exec_cmd = 0;
952 break;
953
954 default:
955 exec_cmd = 0;
Lei Wenda675b42011-07-14 20:44:31 -0700956 dev_err(&info->pdev->dev, "non-supported command %x\n",
957 command);
Lei Wen4eb2da82011-02-28 10:32:13 +0800958 break;
959 }
960
961 return exec_cmd;
962}
963
Ezequiel Garcia5cbbdc62013-12-18 18:44:09 -0300964static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
965 int column, int page_addr)
eric miaofe69af02008-02-14 15:48:23 +0800966{
Lei Wend4568822011-07-14 20:44:32 -0700967 struct pxa3xx_nand_host *host = mtd->priv;
968 struct pxa3xx_nand_info *info = host->info_data;
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -0500969 int exec_cmd;
eric miaofe69af02008-02-14 15:48:23 +0800970
Lei Wen4eb2da82011-02-28 10:32:13 +0800971 /*
972 * if this is a x16 device ,then convert the input
973 * "byte" address into a "word" address appropriate
974 * for indexing a word-oriented device
975 */
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300976 if (info->reg_ndcr & NDCR_DWIDTH_M)
Lei Wen4eb2da82011-02-28 10:32:13 +0800977 column /= 2;
eric miaofe69af02008-02-14 15:48:23 +0800978
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700979 /*
980 * There may be different NAND chip hooked to
981 * different chip select, so check whether
982 * chip select has been changed, if yes, reset the timing
983 */
984 if (info->cs != host->cs) {
985 info->cs = host->cs;
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300986 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
987 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700988 }
989
Ezequiel Garciac39ff032013-11-14 18:25:33 -0300990 prepare_start_command(info, command);
991
Lei Wend4568822011-07-14 20:44:32 -0700992 info->state = STATE_PREPARED;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300993 exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
994
Lei Wenf8155a42011-02-28 10:32:11 +0800995 if (exec_cmd) {
996 init_completion(&info->cmd_complete);
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300997 init_completion(&info->dev_ready);
998 info->need_wait = 1;
Lei Wenf8155a42011-02-28 10:32:11 +0800999 pxa3xx_nand_start(info);
1000
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -05001001 if (!wait_for_completion_timeout(&info->cmd_complete,
1002 CHIP_DELAY_TIMEOUT)) {
Lei Wenda675b42011-07-14 20:44:31 -07001003 dev_err(&info->pdev->dev, "Wait time out!!!\n");
Lei Wenf8155a42011-02-28 10:32:11 +08001004 /* Stop State Machine for next command cycle */
1005 pxa3xx_nand_stop(info);
1006 }
eric miaofe69af02008-02-14 15:48:23 +08001007 }
Lei Wend4568822011-07-14 20:44:32 -07001008 info->state = STATE_IDLE;
eric miaofe69af02008-02-14 15:48:23 +08001009}
1010
Ezequiel Garcia5cbbdc62013-12-18 18:44:09 -03001011static void nand_cmdfunc_extended(struct mtd_info *mtd,
1012 const unsigned command,
1013 int column, int page_addr)
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001014{
1015 struct pxa3xx_nand_host *host = mtd->priv;
1016 struct pxa3xx_nand_info *info = host->info_data;
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -05001017 int exec_cmd, ext_cmd_type;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001018
1019 /*
1020 * if this is a x16 device then convert the input
1021 * "byte" address into a "word" address appropriate
1022 * for indexing a word-oriented device
1023 */
1024 if (info->reg_ndcr & NDCR_DWIDTH_M)
1025 column /= 2;
1026
1027 /*
1028 * There may be different NAND chip hooked to
1029 * different chip select, so check whether
1030 * chip select has been changed, if yes, reset the timing
1031 */
1032 if (info->cs != host->cs) {
1033 info->cs = host->cs;
1034 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1035 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
1036 }
1037
1038 /* Select the extended command for the first command */
1039 switch (command) {
1040 case NAND_CMD_READ0:
1041 case NAND_CMD_READOOB:
1042 ext_cmd_type = EXT_CMD_TYPE_MONO;
1043 break;
Ezequiel Garcia535cb572013-11-14 18:25:38 -03001044 case NAND_CMD_SEQIN:
1045 ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
1046 break;
1047 case NAND_CMD_PAGEPROG:
1048 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
1049 break;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001050 default:
1051 ext_cmd_type = 0;
Ezequiel Garcia535cb572013-11-14 18:25:38 -03001052 break;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001053 }
1054
1055 prepare_start_command(info, command);
1056
1057 /*
1058 * Prepare the "is ready" completion before starting a command
1059 * transaction sequence. If the command is not executed the
1060 * completion will be completed, see below.
1061 *
1062 * We can do that inside the loop because the command variable
1063 * is invariant and thus so is the exec_cmd.
1064 */
1065 info->need_wait = 1;
1066 init_completion(&info->dev_ready);
1067 do {
1068 info->state = STATE_PREPARED;
1069 exec_cmd = prepare_set_command(info, command, ext_cmd_type,
1070 column, page_addr);
1071 if (!exec_cmd) {
1072 info->need_wait = 0;
1073 complete(&info->dev_ready);
1074 break;
1075 }
1076
1077 init_completion(&info->cmd_complete);
1078 pxa3xx_nand_start(info);
1079
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -05001080 if (!wait_for_completion_timeout(&info->cmd_complete,
1081 CHIP_DELAY_TIMEOUT)) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001082 dev_err(&info->pdev->dev, "Wait time out!!!\n");
1083 /* Stop State Machine for next command cycle */
1084 pxa3xx_nand_stop(info);
1085 break;
1086 }
1087
1088 /* Check if the sequence is complete */
Ezequiel Garcia535cb572013-11-14 18:25:38 -03001089 if (info->data_size == 0 && command != NAND_CMD_PAGEPROG)
1090 break;
1091
1092 /*
1093 * After a splitted program command sequence has issued
1094 * the command dispatch, the command sequence is complete.
1095 */
1096 if (info->data_size == 0 &&
1097 command == NAND_CMD_PAGEPROG &&
1098 ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001099 break;
1100
1101 if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
1102 /* Last read: issue a 'last naked read' */
1103 if (info->data_size == info->chunk_size)
1104 ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
1105 else
1106 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
Ezequiel Garcia535cb572013-11-14 18:25:38 -03001107
1108 /*
1109 * If a splitted program command has no more data to transfer,
1110 * the command dispatch must be issued to complete.
1111 */
1112 } else if (command == NAND_CMD_PAGEPROG &&
1113 info->data_size == 0) {
1114 ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001115 }
1116 } while (1);
1117
1118 info->state = STATE_IDLE;
1119}
1120
Josh Wufdbad98d2012-06-25 18:07:45 +08001121static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
Brian Norris1fbb9382012-05-02 10:14:55 -07001122 struct nand_chip *chip, const uint8_t *buf, int oob_required)
Lei Wenf8155a42011-02-28 10:32:11 +08001123{
1124 chip->write_buf(mtd, buf, mtd->writesize);
1125 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
Josh Wufdbad98d2012-06-25 18:07:45 +08001126
1127 return 0;
Lei Wenf8155a42011-02-28 10:32:11 +08001128}
1129
1130static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
Brian Norris1fbb9382012-05-02 10:14:55 -07001131 struct nand_chip *chip, uint8_t *buf, int oob_required,
1132 int page)
Lei Wenf8155a42011-02-28 10:32:11 +08001133{
Lei Wend4568822011-07-14 20:44:32 -07001134 struct pxa3xx_nand_host *host = mtd->priv;
1135 struct pxa3xx_nand_info *info = host->info_data;
Lei Wenf8155a42011-02-28 10:32:11 +08001136
1137 chip->read_buf(mtd, buf, mtd->writesize);
1138 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1139
Ezequiel Garcia87f53362013-11-14 18:25:39 -03001140 if (info->retcode == ERR_CORERR && info->use_ecc) {
1141 mtd->ecc_stats.corrected += info->ecc_err_cnt;
1142
1143 } else if (info->retcode == ERR_UNCORERR) {
Lei Wenf8155a42011-02-28 10:32:11 +08001144 /*
1145 * for blank page (all 0xff), HW will calculate its ECC as
1146 * 0, which is different from the ECC information within
Ezequiel Garcia87f53362013-11-14 18:25:39 -03001147 * OOB, ignore such uncorrectable errors
Lei Wenf8155a42011-02-28 10:32:11 +08001148 */
1149 if (is_buf_blank(buf, mtd->writesize))
Daniel Mack543e32d2011-06-07 03:01:07 -07001150 info->retcode = ERR_NONE;
1151 else
Lei Wenf8155a42011-02-28 10:32:11 +08001152 mtd->ecc_stats.failed++;
1153 }
1154
Ezequiel Garcia87f53362013-11-14 18:25:39 -03001155 return info->max_bitflips;
Lei Wenf8155a42011-02-28 10:32:11 +08001156}
1157
eric miaofe69af02008-02-14 15:48:23 +08001158static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
1159{
Lei Wend4568822011-07-14 20:44:32 -07001160 struct pxa3xx_nand_host *host = mtd->priv;
1161 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +08001162 char retval = 0xFF;
1163
1164 if (info->buf_start < info->buf_count)
1165 /* Has just send a new command? */
1166 retval = info->data_buff[info->buf_start++];
1167
1168 return retval;
1169}
1170
1171static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
1172{
Lei Wend4568822011-07-14 20:44:32 -07001173 struct pxa3xx_nand_host *host = mtd->priv;
1174 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +08001175 u16 retval = 0xFFFF;
1176
1177 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
1178 retval = *((u16 *)(info->data_buff+info->buf_start));
1179 info->buf_start += 2;
1180 }
1181 return retval;
1182}
1183
1184static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1185{
Lei Wend4568822011-07-14 20:44:32 -07001186 struct pxa3xx_nand_host *host = mtd->priv;
1187 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +08001188 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
1189
1190 memcpy(buf, info->data_buff + info->buf_start, real_len);
1191 info->buf_start += real_len;
1192}
1193
1194static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
1195 const uint8_t *buf, int len)
1196{
Lei Wend4568822011-07-14 20:44:32 -07001197 struct pxa3xx_nand_host *host = mtd->priv;
1198 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +08001199 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
1200
1201 memcpy(info->data_buff + info->buf_start, buf, real_len);
1202 info->buf_start += real_len;
1203}
1204
eric miaofe69af02008-02-14 15:48:23 +08001205static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
1206{
1207 return;
1208}
1209
1210static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1211{
Lei Wend4568822011-07-14 20:44:32 -07001212 struct pxa3xx_nand_host *host = mtd->priv;
1213 struct pxa3xx_nand_info *info = host->info_data;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001214
1215 if (info->need_wait) {
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001216 info->need_wait = 0;
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -05001217 if (!wait_for_completion_timeout(&info->dev_ready,
1218 CHIP_DELAY_TIMEOUT)) {
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001219 dev_err(&info->pdev->dev, "Ready time out!!!\n");
1220 return NAND_STATUS_FAIL;
1221 }
1222 }
eric miaofe69af02008-02-14 15:48:23 +08001223
1224 /* pxa3xx_nand_send_command has waited for command complete */
1225 if (this->state == FL_WRITING || this->state == FL_ERASING) {
1226 if (info->retcode == ERR_NONE)
1227 return 0;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001228 else
1229 return NAND_STATUS_FAIL;
eric miaofe69af02008-02-14 15:48:23 +08001230 }
1231
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001232 return NAND_STATUS_READY;
eric miaofe69af02008-02-14 15:48:23 +08001233}
1234
eric miaofe69af02008-02-14 15:48:23 +08001235static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
Enrico Scholzc8c17c82008-08-29 12:59:51 +02001236 const struct pxa3xx_nand_flash *f)
eric miaofe69af02008-02-14 15:48:23 +08001237{
1238 struct platform_device *pdev = info->pdev;
Jingoo Han453810b2013-07-30 17:18:33 +09001239 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001240 struct pxa3xx_nand_host *host = info->host[info->cs];
Lei Wenf8155a42011-02-28 10:32:11 +08001241 uint32_t ndcr = 0x0; /* enable all interrupts */
eric miaofe69af02008-02-14 15:48:23 +08001242
Lei Wenda675b42011-07-14 20:44:31 -07001243 if (f->page_size != 2048 && f->page_size != 512) {
1244 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
eric miaofe69af02008-02-14 15:48:23 +08001245 return -EINVAL;
Lei Wenda675b42011-07-14 20:44:31 -07001246 }
eric miaofe69af02008-02-14 15:48:23 +08001247
Lei Wenda675b42011-07-14 20:44:31 -07001248 if (f->flash_width != 16 && f->flash_width != 8) {
1249 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
eric miaofe69af02008-02-14 15:48:23 +08001250 return -EINVAL;
Lei Wenda675b42011-07-14 20:44:31 -07001251 }
eric miaofe69af02008-02-14 15:48:23 +08001252
1253 /* calculate flash information */
Lei Wend4568822011-07-14 20:44:32 -07001254 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
eric miaofe69af02008-02-14 15:48:23 +08001255
1256 /* calculate addressing information */
Lei Wend4568822011-07-14 20:44:32 -07001257 host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
eric miaofe69af02008-02-14 15:48:23 +08001258
1259 if (f->num_blocks * f->page_per_block > 65536)
Lei Wend4568822011-07-14 20:44:32 -07001260 host->row_addr_cycles = 3;
eric miaofe69af02008-02-14 15:48:23 +08001261 else
Lei Wend4568822011-07-14 20:44:32 -07001262 host->row_addr_cycles = 2;
eric miaofe69af02008-02-14 15:48:23 +08001263
1264 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
Lei Wend4568822011-07-14 20:44:32 -07001265 ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
eric miaofe69af02008-02-14 15:48:23 +08001266 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
1267 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
1268 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
1269 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
1270
Lei Wend4568822011-07-14 20:44:32 -07001271 ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
eric miaofe69af02008-02-14 15:48:23 +08001272 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
1273
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -03001274 info->reg_ndcr = ndcr;
eric miaofe69af02008-02-14 15:48:23 +08001275
Lei Wend4568822011-07-14 20:44:32 -07001276 pxa3xx_nand_set_timing(host, f->timing);
eric miaofe69af02008-02-14 15:48:23 +08001277 return 0;
1278}
1279
Mike Rapoportf2710492009-02-17 13:54:47 +02001280static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
1281{
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001282 /*
1283 * We set 0 by hard coding here, for we don't support keep_config
1284 * when there is more than one chip attached to the controller
1285 */
1286 struct pxa3xx_nand_host *host = info->host[0];
Mike Rapoportf2710492009-02-17 13:54:47 +02001287 uint32_t ndcr = nand_readl(info, NDCR);
Mike Rapoportf2710492009-02-17 13:54:47 +02001288
Lei Wend4568822011-07-14 20:44:32 -07001289 if (ndcr & NDCR_PAGE_SZ) {
Ezequiel Garcia2128b082013-11-07 12:17:16 -03001290 /* Controller's FIFO size */
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001291 info->chunk_size = 2048;
Lei Wend4568822011-07-14 20:44:32 -07001292 host->read_id_bytes = 4;
1293 } else {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001294 info->chunk_size = 512;
Lei Wend4568822011-07-14 20:44:32 -07001295 host->read_id_bytes = 2;
1296 }
1297
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001298 /* Set an initial chunk size */
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -03001299 info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
1300 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
1301 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
Mike Rapoportf2710492009-02-17 13:54:47 +02001302 return 0;
1303}
1304
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -03001305#ifdef ARCH_HAS_DMA
eric miaofe69af02008-02-14 15:48:23 +08001306static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1307{
1308 struct platform_device *pdev = info->pdev;
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001309 int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc);
eric miaofe69af02008-02-14 15:48:23 +08001310
1311 if (use_dma == 0) {
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001312 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
eric miaofe69af02008-02-14 15:48:23 +08001313 if (info->data_buff == NULL)
1314 return -ENOMEM;
1315 return 0;
1316 }
1317
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001318 info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size,
eric miaofe69af02008-02-14 15:48:23 +08001319 &info->data_buff_phys, GFP_KERNEL);
1320 if (info->data_buff == NULL) {
1321 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
1322 return -ENOMEM;
1323 }
1324
eric miaofe69af02008-02-14 15:48:23 +08001325 info->data_desc = (void *)info->data_buff + data_desc_offset;
1326 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
1327
1328 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
1329 pxa3xx_nand_data_dma_irq, info);
1330 if (info->data_dma_ch < 0) {
1331 dev_err(&pdev->dev, "failed to request data dma\n");
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001332 dma_free_coherent(&pdev->dev, info->buf_size,
eric miaofe69af02008-02-14 15:48:23 +08001333 info->data_buff, info->data_buff_phys);
1334 return info->data_dma_ch;
1335 }
1336
Ezequiel Garcia95b26562013-10-04 15:30:37 -03001337 /*
1338 * Now that DMA buffers are allocated we turn on
1339 * DMA proper for I/O operations.
1340 */
1341 info->use_dma = 1;
eric miaofe69af02008-02-14 15:48:23 +08001342 return 0;
1343}
1344
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001345static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
1346{
1347 struct platform_device *pdev = info->pdev;
Ezequiel Garcia15b540c2013-12-10 09:57:15 -03001348 if (info->use_dma) {
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001349 pxa_free_dma(info->data_dma_ch);
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001350 dma_free_coherent(&pdev->dev, info->buf_size,
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001351 info->data_buff, info->data_buff_phys);
1352 } else {
1353 kfree(info->data_buff);
1354 }
1355}
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -03001356#else
1357static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1358{
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001359 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -03001360 if (info->data_buff == NULL)
1361 return -ENOMEM;
1362 return 0;
1363}
1364
1365static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
1366{
1367 kfree(info->data_buff);
1368}
1369#endif
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001370
Lei Wen401e67e2011-02-28 10:32:14 +08001371static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
eric miaofe69af02008-02-14 15:48:23 +08001372{
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001373 struct mtd_info *mtd;
Ezequiel Garcia2d79ab12013-11-07 12:17:15 -03001374 struct nand_chip *chip;
Lei Wend4568822011-07-14 20:44:32 -07001375 int ret;
Ezequiel Garcia2d79ab12013-11-07 12:17:15 -03001376
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001377 mtd = info->host[info->cs]->mtd;
Ezequiel Garcia2d79ab12013-11-07 12:17:15 -03001378 chip = mtd->priv;
1379
Lei Wen401e67e2011-02-28 10:32:14 +08001380 /* use the common timing to make a try */
Lei Wend4568822011-07-14 20:44:32 -07001381 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
1382 if (ret)
1383 return ret;
1384
Ezequiel Garcia2d79ab12013-11-07 12:17:15 -03001385 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
Ezequiel Garcia56704d82013-11-14 18:25:27 -03001386 ret = chip->waitfunc(mtd, chip);
1387 if (ret & NAND_STATUS_FAIL)
1388 return -ENODEV;
Lei Wend4568822011-07-14 20:44:32 -07001389
Ezequiel Garcia56704d82013-11-14 18:25:27 -03001390 return 0;
Lei Wen401e67e2011-02-28 10:32:14 +08001391}
eric miaofe69af02008-02-14 15:48:23 +08001392
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001393static int pxa_ecc_init(struct pxa3xx_nand_info *info,
1394 struct nand_ecc_ctrl *ecc,
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001395 int strength, int ecc_stepsize, int page_size)
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001396{
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001397 if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001398 info->chunk_size = 2048;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001399 info->spare_size = 40;
1400 info->ecc_size = 24;
1401 ecc->mode = NAND_ECC_HW;
1402 ecc->size = 512;
1403 ecc->strength = 1;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001404
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001405 } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001406 info->chunk_size = 512;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001407 info->spare_size = 8;
1408 info->ecc_size = 8;
1409 ecc->mode = NAND_ECC_HW;
1410 ecc->size = 512;
1411 ecc->strength = 1;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001412
Brian Norris6033a942013-11-14 14:41:32 -08001413 /*
1414 * Required ECC: 4-bit correction per 512 bytes
1415 * Select: 16-bit correction per 2048 bytes
1416 */
Rodolfo Giometti3db227b2014-01-13 15:35:38 +01001417 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
1418 info->ecc_bch = 1;
1419 info->chunk_size = 2048;
1420 info->spare_size = 32;
1421 info->ecc_size = 32;
1422 ecc->mode = NAND_ECC_HW;
1423 ecc->size = info->chunk_size;
1424 ecc->layout = &ecc_layout_2KB_bch4bit;
1425 ecc->strength = 16;
Rodolfo Giometti3db227b2014-01-13 15:35:38 +01001426
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001427 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001428 info->ecc_bch = 1;
1429 info->chunk_size = 2048;
1430 info->spare_size = 32;
1431 info->ecc_size = 32;
1432 ecc->mode = NAND_ECC_HW;
1433 ecc->size = info->chunk_size;
1434 ecc->layout = &ecc_layout_4KB_bch4bit;
1435 ecc->strength = 16;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001436
Brian Norris6033a942013-11-14 14:41:32 -08001437 /*
1438 * Required ECC: 8-bit correction per 512 bytes
1439 * Select: 16-bit correction per 1024 bytes
1440 */
1441 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001442 info->ecc_bch = 1;
1443 info->chunk_size = 1024;
1444 info->spare_size = 0;
1445 info->ecc_size = 32;
1446 ecc->mode = NAND_ECC_HW;
1447 ecc->size = info->chunk_size;
1448 ecc->layout = &ecc_layout_4KB_bch8bit;
1449 ecc->strength = 16;
Ezequiel Garciaeee01662014-05-14 14:58:07 -03001450 } else {
1451 dev_err(&info->pdev->dev,
1452 "ECC strength %d at page size %d is not supported\n",
1453 strength, page_size);
1454 return -ENODEV;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001455 }
Ezequiel Garciaeee01662014-05-14 14:58:07 -03001456
1457 dev_info(&info->pdev->dev, "ECC strength %d, ECC step size %d\n",
1458 ecc->strength, ecc->size);
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001459 return 0;
1460}
1461
Lei Wen401e67e2011-02-28 10:32:14 +08001462static int pxa3xx_nand_scan(struct mtd_info *mtd)
1463{
Lei Wend4568822011-07-14 20:44:32 -07001464 struct pxa3xx_nand_host *host = mtd->priv;
1465 struct pxa3xx_nand_info *info = host->info_data;
Lei Wen401e67e2011-02-28 10:32:14 +08001466 struct platform_device *pdev = info->pdev;
Jingoo Han453810b2013-07-30 17:18:33 +09001467 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
Lei Wen0fab0282011-06-07 03:01:06 -07001468 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
Lei Wen401e67e2011-02-28 10:32:14 +08001469 const struct pxa3xx_nand_flash *f = NULL;
1470 struct nand_chip *chip = mtd->priv;
1471 uint32_t id = -1;
Lei Wen4332c112011-03-03 11:27:01 +08001472 uint64_t chipsize;
Lei Wen401e67e2011-02-28 10:32:14 +08001473 int i, ret, num;
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001474 uint16_t ecc_strength, ecc_step;
Lei Wen401e67e2011-02-28 10:32:14 +08001475
1476 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
Lei Wen4332c112011-03-03 11:27:01 +08001477 goto KEEP_CONFIG;
Lei Wen401e67e2011-02-28 10:32:14 +08001478
Antoine Ténartbc3e00f2015-08-18 10:59:10 +02001479 /* Set a default chunk size */
1480 info->chunk_size = 512;
1481
Lei Wen401e67e2011-02-28 10:32:14 +08001482 ret = pxa3xx_nand_sensing(info);
Lei Wend4568822011-07-14 20:44:32 -07001483 if (ret) {
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001484 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
1485 info->cs);
Lei Wen401e67e2011-02-28 10:32:14 +08001486
Lei Wend4568822011-07-14 20:44:32 -07001487 return ret;
Lei Wen401e67e2011-02-28 10:32:14 +08001488 }
1489
1490 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
1491 id = *((uint16_t *)(info->data_buff));
1492 if (id != 0)
Lei Wenda675b42011-07-14 20:44:31 -07001493 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
Lei Wen401e67e2011-02-28 10:32:14 +08001494 else {
Lei Wenda675b42011-07-14 20:44:31 -07001495 dev_warn(&info->pdev->dev,
1496 "Read out ID 0, potential timing set wrong!!\n");
Lei Wen401e67e2011-02-28 10:32:14 +08001497
1498 return -EINVAL;
1499 }
1500
1501 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
1502 for (i = 0; i < num; i++) {
1503 if (i < pdata->num_flash)
1504 f = pdata->flash + i;
1505 else
1506 f = &builtin_flash_types[i - pdata->num_flash + 1];
1507
1508 /* find the chip in default list */
Lei Wen4332c112011-03-03 11:27:01 +08001509 if (f->chip_id == id)
Lei Wen401e67e2011-02-28 10:32:14 +08001510 break;
Lei Wen401e67e2011-02-28 10:32:14 +08001511 }
1512
Lei Wen4332c112011-03-03 11:27:01 +08001513 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
Lei Wenda675b42011-07-14 20:44:31 -07001514 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
Lei Wen401e67e2011-02-28 10:32:14 +08001515
1516 return -EINVAL;
1517 }
1518
Lei Wend4568822011-07-14 20:44:32 -07001519 ret = pxa3xx_nand_config_flash(info, f);
1520 if (ret) {
1521 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1522 return ret;
1523 }
1524
Antoine Ténart7c2f7172015-02-12 15:53:27 +01001525 memset(pxa3xx_flash_ids, 0, sizeof(pxa3xx_flash_ids));
1526
Lei Wen4332c112011-03-03 11:27:01 +08001527 pxa3xx_flash_ids[0].name = f->name;
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +02001528 pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
Lei Wen4332c112011-03-03 11:27:01 +08001529 pxa3xx_flash_ids[0].pagesize = f->page_size;
1530 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1531 pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1532 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1533 if (f->flash_width == 16)
1534 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
Lei Wen0fab0282011-06-07 03:01:06 -07001535 pxa3xx_flash_ids[1].name = NULL;
1536 def = pxa3xx_flash_ids;
Lei Wen4332c112011-03-03 11:27:01 +08001537KEEP_CONFIG:
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -03001538 if (info->reg_ndcr & NDCR_DWIDTH_M)
Lei Wend4568822011-07-14 20:44:32 -07001539 chip->options |= NAND_BUSWIDTH_16;
1540
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001541 /* Device detection must be done with ECC disabled */
1542 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
1543 nand_writel(info, NDECCCTRL, 0x0);
1544
Lei Wen0fab0282011-06-07 03:01:06 -07001545 if (nand_scan_ident(mtd, 1, def))
Lei Wen4332c112011-03-03 11:27:01 +08001546 return -ENODEV;
Ezequiel Garcia776f2652013-11-14 18:25:28 -03001547
1548 if (pdata->flash_bbt) {
1549 /*
1550 * We'll use a bad block table stored in-flash and don't
1551 * allow writing the bad block marker to the flash.
1552 */
1553 chip->bbt_options |= NAND_BBT_USE_FLASH |
1554 NAND_BBT_NO_OOB_BBM;
1555 chip->bbt_td = &bbt_main_descr;
1556 chip->bbt_md = &bbt_mirror_descr;
1557 }
1558
Ezequiel Garcia5cbbdc62013-12-18 18:44:09 -03001559 /*
1560 * If the page size is bigger than the FIFO size, let's check
1561 * we are given the right variant and then switch to the extended
1562 * (aka splitted) command handling,
1563 */
1564 if (mtd->writesize > PAGE_CHUNK_SIZE) {
1565 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
1566 chip->cmdfunc = nand_cmdfunc_extended;
1567 } else {
1568 dev_err(&info->pdev->dev,
1569 "unsupported page size on this variant\n");
1570 return -ENODEV;
1571 }
1572 }
1573
Ezequiel Garcia5b3e5072014-05-14 14:58:08 -03001574 if (pdata->ecc_strength && pdata->ecc_step_size) {
1575 ecc_strength = pdata->ecc_strength;
1576 ecc_step = pdata->ecc_step_size;
1577 } else {
1578 ecc_strength = chip->ecc_strength_ds;
1579 ecc_step = chip->ecc_step_ds;
1580 }
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001581
1582 /* Set default ECC strength requirements on non-ONFI devices */
1583 if (ecc_strength < 1 && ecc_step < 1) {
1584 ecc_strength = 1;
1585 ecc_step = 512;
1586 }
1587
1588 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
1589 ecc_step, mtd->writesize);
Ezequiel Garciaeee01662014-05-14 14:58:07 -03001590 if (ret)
1591 return ret;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001592
Lei Wen4332c112011-03-03 11:27:01 +08001593 /* calculate addressing information */
Lei Wend4568822011-07-14 20:44:32 -07001594 if (mtd->writesize >= 2048)
1595 host->col_addr_cycles = 2;
1596 else
1597 host->col_addr_cycles = 1;
1598
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001599 /* release the initial buffer */
1600 kfree(info->data_buff);
1601
1602 /* allocate the real data + oob buffer */
1603 info->buf_size = mtd->writesize + mtd->oobsize;
1604 ret = pxa3xx_nand_init_buff(info);
1605 if (ret)
1606 return ret;
Lei Wen4332c112011-03-03 11:27:01 +08001607 info->oob_buff = info->data_buff + mtd->writesize;
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001608
Lei Wen4332c112011-03-03 11:27:01 +08001609 if ((mtd->size >> chip->page_shift) > 65536)
Lei Wend4568822011-07-14 20:44:32 -07001610 host->row_addr_cycles = 3;
Lei Wen4332c112011-03-03 11:27:01 +08001611 else
Lei Wend4568822011-07-14 20:44:32 -07001612 host->row_addr_cycles = 2;
Lei Wen401e67e2011-02-28 10:32:14 +08001613 return nand_scan_tail(mtd);
eric miaofe69af02008-02-14 15:48:23 +08001614}
1615
Lei Wend4568822011-07-14 20:44:32 -07001616static int alloc_nand_resource(struct platform_device *pdev)
eric miaofe69af02008-02-14 15:48:23 +08001617{
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001618 struct pxa3xx_nand_platform_data *pdata;
eric miaofe69af02008-02-14 15:48:23 +08001619 struct pxa3xx_nand_info *info;
Lei Wend4568822011-07-14 20:44:32 -07001620 struct pxa3xx_nand_host *host;
Haojian Zhuang6e308f82012-08-20 13:40:31 +08001621 struct nand_chip *chip = NULL;
eric miaofe69af02008-02-14 15:48:23 +08001622 struct mtd_info *mtd;
1623 struct resource *r;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001624 int ret, irq, cs;
eric miaofe69af02008-02-14 15:48:23 +08001625
Jingoo Han453810b2013-07-30 17:18:33 +09001626 pdata = dev_get_platdata(&pdev->dev);
Robert Jarzmike423c902015-02-08 21:02:09 +01001627 if (pdata->num_cs <= 0)
1628 return -ENODEV;
Ezequiel Garcia4c073cd2013-04-17 13:38:09 -03001629 info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1630 sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1631 if (!info)
Lei Wend4568822011-07-14 20:44:32 -07001632 return -ENOMEM;
eric miaofe69af02008-02-14 15:48:23 +08001633
eric miaofe69af02008-02-14 15:48:23 +08001634 info->pdev = pdev;
Ezequiel Garciac7e9c7e2013-11-07 12:17:14 -03001635 info->variant = pxa3xx_nand_get_variant(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001636 for (cs = 0; cs < pdata->num_cs; cs++) {
Rob Herringce914e62015-04-30 15:17:47 -05001637 mtd = (void *)&info[1] + (sizeof(*mtd) + sizeof(*host)) * cs;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001638 chip = (struct nand_chip *)(&mtd[1]);
1639 host = (struct pxa3xx_nand_host *)chip;
1640 info->host[cs] = host;
1641 host->mtd = mtd;
1642 host->cs = cs;
1643 host->info_data = info;
1644 mtd->priv = host;
1645 mtd->owner = THIS_MODULE;
eric miaofe69af02008-02-14 15:48:23 +08001646
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001647 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1648 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1649 chip->controller = &info->controller;
1650 chip->waitfunc = pxa3xx_nand_waitfunc;
1651 chip->select_chip = pxa3xx_nand_select_chip;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001652 chip->read_word = pxa3xx_nand_read_word;
1653 chip->read_byte = pxa3xx_nand_read_byte;
1654 chip->read_buf = pxa3xx_nand_read_buf;
1655 chip->write_buf = pxa3xx_nand_write_buf;
Ezequiel Garcia664c7f52013-11-07 12:17:12 -03001656 chip->options |= NAND_NO_SUBPAGE_WRITE;
Ezequiel Garcia5cbbdc62013-12-18 18:44:09 -03001657 chip->cmdfunc = nand_cmdfunc;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001658 }
Lei Wen401e67e2011-02-28 10:32:14 +08001659
1660 spin_lock_init(&chip->controller->lock);
1661 init_waitqueue_head(&chip->controller->wq);
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001662 info->clk = devm_clk_get(&pdev->dev, NULL);
eric miaofe69af02008-02-14 15:48:23 +08001663 if (IS_ERR(info->clk)) {
1664 dev_err(&pdev->dev, "failed to get nand clock\n");
Ezequiel Garcia4c073cd2013-04-17 13:38:09 -03001665 return PTR_ERR(info->clk);
eric miaofe69af02008-02-14 15:48:23 +08001666 }
Ezequiel Garcia1f8eaff2013-04-17 13:38:13 -03001667 ret = clk_prepare_enable(info->clk);
1668 if (ret < 0)
1669 return ret;
eric miaofe69af02008-02-14 15:48:23 +08001670
Ezequiel Garcia6b45c1e2013-08-12 14:14:58 -03001671 if (use_dma) {
1672 /*
1673 * This is a dirty hack to make this driver work from
1674 * devicetree bindings. It can be removed once we have
1675 * a prober DMA controller framework for DT.
1676 */
1677 if (pdev->dev.of_node &&
1678 of_machine_is_compatible("marvell,pxa3xx")) {
1679 info->drcmr_dat = 97;
1680 info->drcmr_cmd = 99;
1681 } else {
1682 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1683 if (r == NULL) {
1684 dev_err(&pdev->dev,
1685 "no resource defined for data DMA\n");
1686 ret = -ENXIO;
1687 goto fail_disable_clk;
1688 }
1689 info->drcmr_dat = r->start;
eric miaofe69af02008-02-14 15:48:23 +08001690
Ezequiel Garcia6b45c1e2013-08-12 14:14:58 -03001691 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1692 if (r == NULL) {
1693 dev_err(&pdev->dev,
1694 "no resource defined for cmd DMA\n");
1695 ret = -ENXIO;
1696 goto fail_disable_clk;
1697 }
1698 info->drcmr_cmd = r->start;
Daniel Mack1e7ba632012-07-22 19:51:02 +02001699 }
eric miaofe69af02008-02-14 15:48:23 +08001700 }
eric miaofe69af02008-02-14 15:48:23 +08001701
1702 irq = platform_get_irq(pdev, 0);
1703 if (irq < 0) {
1704 dev_err(&pdev->dev, "no IRQ resource defined\n");
1705 ret = -ENXIO;
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001706 goto fail_disable_clk;
eric miaofe69af02008-02-14 15:48:23 +08001707 }
1708
1709 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Ezequiel Garcia0ddd8462013-04-17 13:38:10 -03001710 info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1711 if (IS_ERR(info->mmio_base)) {
1712 ret = PTR_ERR(info->mmio_base);
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001713 goto fail_disable_clk;
eric miaofe69af02008-02-14 15:48:23 +08001714 }
Haojian Zhuang8638fac2009-09-10 14:11:44 +08001715 info->mmio_phys = r->start;
eric miaofe69af02008-02-14 15:48:23 +08001716
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001717 /* Allocate a buffer to allow flash detection */
1718 info->buf_size = INIT_BUFFER_SIZE;
1719 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
1720 if (info->data_buff == NULL) {
1721 ret = -ENOMEM;
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001722 goto fail_disable_clk;
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001723 }
eric miaofe69af02008-02-14 15:48:23 +08001724
Haojian Zhuang346e1252009-09-10 14:27:23 +08001725 /* initialize all interrupts to be disabled */
1726 disable_int(info, NDSR_MASK);
1727
Robert Jarzmik24542252015-02-20 19:36:43 +01001728 ret = request_threaded_irq(irq, pxa3xx_nand_irq,
1729 pxa3xx_nand_irq_thread, IRQF_ONESHOT,
1730 pdev->name, info);
eric miaofe69af02008-02-14 15:48:23 +08001731 if (ret < 0) {
1732 dev_err(&pdev->dev, "failed to request IRQ\n");
1733 goto fail_free_buf;
1734 }
1735
Lei Wene353a202011-03-03 11:08:30 +08001736 platform_set_drvdata(pdev, info);
eric miaofe69af02008-02-14 15:48:23 +08001737
Lei Wend4568822011-07-14 20:44:32 -07001738 return 0;
eric miaofe69af02008-02-14 15:48:23 +08001739
eric miaofe69af02008-02-14 15:48:23 +08001740fail_free_buf:
Lei Wen401e67e2011-02-28 10:32:14 +08001741 free_irq(irq, info);
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001742 kfree(info->data_buff);
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001743fail_disable_clk:
Ezequiel Garciafb320612013-04-17 13:38:12 -03001744 clk_disable_unprepare(info->clk);
Lei Wend4568822011-07-14 20:44:32 -07001745 return ret;
eric miaofe69af02008-02-14 15:48:23 +08001746}
1747
1748static int pxa3xx_nand_remove(struct platform_device *pdev)
1749{
Lei Wene353a202011-03-03 11:08:30 +08001750 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001751 struct pxa3xx_nand_platform_data *pdata;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001752 int irq, cs;
eric miaofe69af02008-02-14 15:48:23 +08001753
Lei Wend4568822011-07-14 20:44:32 -07001754 if (!info)
1755 return 0;
1756
Jingoo Han453810b2013-07-30 17:18:33 +09001757 pdata = dev_get_platdata(&pdev->dev);
eric miaofe69af02008-02-14 15:48:23 +08001758
Haojian Zhuangdbf59862009-09-10 14:22:55 +08001759 irq = platform_get_irq(pdev, 0);
1760 if (irq >= 0)
1761 free_irq(irq, info);
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001762 pxa3xx_nand_free_buff(info);
Mike Rapoport82a72d12009-02-17 13:54:46 +02001763
Ezequiel Garciafb320612013-04-17 13:38:12 -03001764 clk_disable_unprepare(info->clk);
Mike Rapoport82a72d12009-02-17 13:54:46 +02001765
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001766 for (cs = 0; cs < pdata->num_cs; cs++)
1767 nand_release(info->host[cs]->mtd);
eric miaofe69af02008-02-14 15:48:23 +08001768 return 0;
1769}
1770
Daniel Mack1e7ba632012-07-22 19:51:02 +02001771static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1772{
1773 struct pxa3xx_nand_platform_data *pdata;
1774 struct device_node *np = pdev->dev.of_node;
1775 const struct of_device_id *of_id =
1776 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1777
1778 if (!of_id)
1779 return 0;
1780
1781 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1782 if (!pdata)
1783 return -ENOMEM;
1784
1785 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1786 pdata->enable_arbiter = 1;
1787 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1788 pdata->keep_config = 1;
1789 of_property_read_u32(np, "num-cs", &pdata->num_cs);
Ezequiel Garcia776f2652013-11-14 18:25:28 -03001790 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
Daniel Mack1e7ba632012-07-22 19:51:02 +02001791
Ezequiel Garcia5b3e5072014-05-14 14:58:08 -03001792 pdata->ecc_strength = of_get_nand_ecc_strength(np);
1793 if (pdata->ecc_strength < 0)
1794 pdata->ecc_strength = 0;
1795
1796 pdata->ecc_step_size = of_get_nand_ecc_step_size(np);
1797 if (pdata->ecc_step_size < 0)
1798 pdata->ecc_step_size = 0;
1799
Daniel Mack1e7ba632012-07-22 19:51:02 +02001800 pdev->dev.platform_data = pdata;
1801
1802 return 0;
1803}
Daniel Mack1e7ba632012-07-22 19:51:02 +02001804
Lei Wene353a202011-03-03 11:08:30 +08001805static int pxa3xx_nand_probe(struct platform_device *pdev)
1806{
1807 struct pxa3xx_nand_platform_data *pdata;
Daniel Mack1e7ba632012-07-22 19:51:02 +02001808 struct mtd_part_parser_data ppdata = {};
Lei Wene353a202011-03-03 11:08:30 +08001809 struct pxa3xx_nand_info *info;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001810 int ret, cs, probe_success;
Lei Wene353a202011-03-03 11:08:30 +08001811
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -03001812#ifndef ARCH_HAS_DMA
1813 if (use_dma) {
1814 use_dma = 0;
1815 dev_warn(&pdev->dev,
1816 "This platform can't do DMA on this device\n");
1817 }
1818#endif
Daniel Mack1e7ba632012-07-22 19:51:02 +02001819 ret = pxa3xx_nand_probe_dt(pdev);
1820 if (ret)
1821 return ret;
1822
Jingoo Han453810b2013-07-30 17:18:33 +09001823 pdata = dev_get_platdata(&pdev->dev);
Lei Wene353a202011-03-03 11:08:30 +08001824 if (!pdata) {
1825 dev_err(&pdev->dev, "no platform data defined\n");
1826 return -ENODEV;
1827 }
1828
Lei Wend4568822011-07-14 20:44:32 -07001829 ret = alloc_nand_resource(pdev);
1830 if (ret) {
1831 dev_err(&pdev->dev, "alloc nand resource failed\n");
1832 return ret;
1833 }
Lei Wene353a202011-03-03 11:08:30 +08001834
Lei Wend4568822011-07-14 20:44:32 -07001835 info = platform_get_drvdata(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001836 probe_success = 0;
1837 for (cs = 0; cs < pdata->num_cs; cs++) {
Ezequiel Garciab7655bc2013-08-12 14:14:52 -03001838 struct mtd_info *mtd = info->host[cs]->mtd;
Ezequiel Garciaf4555782013-08-12 14:14:53 -03001839
Ezequiel Garcia18a84e92013-10-19 18:19:25 -03001840 /*
1841 * The mtd name matches the one used in 'mtdparts' kernel
1842 * parameter. This name cannot be changed or otherwise
1843 * user's mtd partitions configuration would get broken.
1844 */
1845 mtd->name = "pxa3xx_nand-0";
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001846 info->cs = cs;
Ezequiel Garciab7655bc2013-08-12 14:14:52 -03001847 ret = pxa3xx_nand_scan(mtd);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001848 if (ret) {
1849 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1850 cs);
1851 continue;
1852 }
1853
Daniel Mack1e7ba632012-07-22 19:51:02 +02001854 ppdata.of_node = pdev->dev.of_node;
Ezequiel Garciab7655bc2013-08-12 14:14:52 -03001855 ret = mtd_device_parse_register(mtd, NULL,
Daniel Mack1e7ba632012-07-22 19:51:02 +02001856 &ppdata, pdata->parts[cs],
Artem Bityutskiy42d7fbe2012-03-09 19:24:26 +02001857 pdata->nr_parts[cs]);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001858 if (!ret)
1859 probe_success = 1;
1860 }
1861
1862 if (!probe_success) {
Lei Wene353a202011-03-03 11:08:30 +08001863 pxa3xx_nand_remove(pdev);
1864 return -ENODEV;
1865 }
1866
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001867 return 0;
Lei Wene353a202011-03-03 11:08:30 +08001868}
1869
eric miaofe69af02008-02-14 15:48:23 +08001870#ifdef CONFIG_PM
1871static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1872{
Lei Wene353a202011-03-03 11:08:30 +08001873 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001874 struct pxa3xx_nand_platform_data *pdata;
1875 struct mtd_info *mtd;
1876 int cs;
eric miaofe69af02008-02-14 15:48:23 +08001877
Jingoo Han453810b2013-07-30 17:18:33 +09001878 pdata = dev_get_platdata(&pdev->dev);
Lei Wenf8155a42011-02-28 10:32:11 +08001879 if (info->state) {
eric miaofe69af02008-02-14 15:48:23 +08001880 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1881 return -EAGAIN;
1882 }
1883
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001884 for (cs = 0; cs < pdata->num_cs; cs++) {
1885 mtd = info->host[cs]->mtd;
Artem Bityutskiy3fe4bae2011-12-23 19:25:16 +02001886 mtd_suspend(mtd);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001887 }
1888
eric miaofe69af02008-02-14 15:48:23 +08001889 return 0;
1890}
1891
1892static int pxa3xx_nand_resume(struct platform_device *pdev)
1893{
Lei Wene353a202011-03-03 11:08:30 +08001894 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001895 struct pxa3xx_nand_platform_data *pdata;
1896 struct mtd_info *mtd;
1897 int cs;
Lei Wen051fc412011-07-14 20:44:30 -07001898
Jingoo Han453810b2013-07-30 17:18:33 +09001899 pdata = dev_get_platdata(&pdev->dev);
Lei Wen051fc412011-07-14 20:44:30 -07001900 /* We don't want to handle interrupt without calling mtd routine */
1901 disable_int(info, NDCR_INT_MASK);
eric miaofe69af02008-02-14 15:48:23 +08001902
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001903 /*
1904 * Directly set the chip select to a invalid value,
1905 * then the driver would reset the timing according
1906 * to current chip select at the beginning of cmdfunc
1907 */
1908 info->cs = 0xff;
eric miaofe69af02008-02-14 15:48:23 +08001909
Lei Wen051fc412011-07-14 20:44:30 -07001910 /*
1911 * As the spec says, the NDSR would be updated to 0x1800 when
1912 * doing the nand_clk disable/enable.
1913 * To prevent it damaging state machine of the driver, clear
1914 * all status before resume
1915 */
1916 nand_writel(info, NDSR, NDSR_MASK);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001917 for (cs = 0; cs < pdata->num_cs; cs++) {
1918 mtd = info->host[cs]->mtd;
Artem Bityutskiyead995f2011-12-23 19:31:25 +02001919 mtd_resume(mtd);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001920 }
1921
Lei Wen18c81b12010-08-17 17:25:57 +08001922 return 0;
eric miaofe69af02008-02-14 15:48:23 +08001923}
1924#else
1925#define pxa3xx_nand_suspend NULL
1926#define pxa3xx_nand_resume NULL
1927#endif
1928
1929static struct platform_driver pxa3xx_nand_driver = {
1930 .driver = {
1931 .name = "pxa3xx-nand",
Sachin Kamat5576bc72013-09-30 15:10:24 +05301932 .of_match_table = pxa3xx_nand_dt_ids,
eric miaofe69af02008-02-14 15:48:23 +08001933 },
1934 .probe = pxa3xx_nand_probe,
1935 .remove = pxa3xx_nand_remove,
1936 .suspend = pxa3xx_nand_suspend,
1937 .resume = pxa3xx_nand_resume,
1938};
1939
Axel Linf99640d2011-11-27 20:45:03 +08001940module_platform_driver(pxa3xx_nand_driver);
eric miaofe69af02008-02-14 15:48:23 +08001941
1942MODULE_LICENSE("GPL");
1943MODULE_DESCRIPTION("PXA3xx NAND controller driver");