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gerrit-public.fairphone.software / kernel / msm-5.4 / be5537542743f72c7cedddd145c17cf7706baa23 / . / arch / mips / include / asm / mach-cavium-octeon / dma-coherence.h
blob: 6eb1ee548b11edeee7df508f9297e5d682db2547 [file] [log] [blame]
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
7 *
8 *
9 * Similar to mach-generic/dma-coherence.h except
10 * plat_device_is_coherent hard coded to return 1.
11 *
12 */
13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
15
David Daney368b0622013-06-20 16:10:50 +0200[diff] [blame]16#include <linux/bug.h>
17
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]18struct device;
19
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]20extern void octeon_pci_dma_init(void);
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]21
22static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
23 size_t size)
24{
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]25 BUG();
David Daney368b0622013-06-20 16:10:50 +0200[diff] [blame]26 return 0;
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]27}
28
29static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
30 struct page *page)
31{
David Daney48e1fd52010-10-01 13:27:32 -0700[diff] [blame]32 BUG();
David Daney368b0622013-06-20 16:10:50 +0200[diff] [blame]33 return 0;
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]34}
35
Kevin Cernekee3807ef3f62009-04-23 17:25:12 -0700[diff] [blame]36static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
37 dma_addr_t dma_addr)
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]38{
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]39 BUG();
David Daney368b0622013-06-20 16:10:50 +0200[diff] [blame]40 return 0;
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]41}
42
Kevin Cernekeed3f634b2009-04-23 17:03:43 -0700[diff] [blame]43static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
44 size_t size, enum dma_data_direction direction)
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]45{
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]46 BUG();
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]47}
48
49static inline int plat_dma_supported(struct device *dev, u64 mask)
50{
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]51 BUG();
David Daney368b0622013-06-20 16:10:50 +0200[diff] [blame]52 return 0;
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]53}
54
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]55static inline int plat_device_is_coherent(struct device *dev)
56{
57 return 1;
58}
59
Ralf Baechle0acbfc62015-03-27 15:10:30 +0100[diff] [blame]60static inline void plat_post_dma_flush(struct device *dev)
61{
62}
63
Christoph Hellwigea8c64a2018-01-10 16:21:13 +0100[diff] [blame]64static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
65{
66 if (!dev->dma_mask)
67 return false;
68
69 return addr + size - 1 <= *dev->dma_mask;
70}
71
Christoph Hellwigb6e05472018-03-19 11:38:24 +0100[diff] [blame]72dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
73phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]74
75struct dma_map_ops;
Bart Van Assche52997092017-01-20 13:04:01 -0800[diff] [blame]76extern const struct dma_map_ops *octeon_pci_dma_map_ops;
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]77extern char *octeon_swiotlb;
78
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]79#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */