| Matthew McClintock | bec6ba4 | 2015-11-19 17:19:31 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | /dts-v1/; |
| 15 | |
| 16 | #include "skeleton.dtsi" |
| 17 | #include <dt-bindings/clock/qcom,gcc-ipq4019.h> |
| 18 | |
| 19 | / { |
| 20 | model = "Qualcomm Technologies, Inc. IPQ4019"; |
| 21 | compatible = "qcom,ipq4019"; |
| 22 | interrupt-parent = <&intc>; |
| 23 | |
| 24 | cpus { |
| 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; |
| 27 | cpu@0 { |
| 28 | device_type = "cpu"; |
| 29 | compatible = "arm,cortex-a7"; |
| 30 | reg = <0x0>; |
| 31 | clocks = <&gcc GCC_APPS_CLK_SRC>; |
| 32 | }; |
| 33 | |
| 34 | cpu@1 { |
| 35 | device_type = "cpu"; |
| 36 | compatible = "arm,cortex-a7"; |
| 37 | reg = <0x1>; |
| 38 | clocks = <&gcc GCC_APPS_CLK_SRC>; |
| 39 | }; |
| 40 | |
| 41 | cpu@2 { |
| 42 | device_type = "cpu"; |
| 43 | compatible = "arm,cortex-a7"; |
| 44 | reg = <0x2>; |
| 45 | clocks = <&gcc GCC_APPS_CLK_SRC>; |
| 46 | }; |
| 47 | |
| 48 | cpu@3 { |
| 49 | device_type = "cpu"; |
| 50 | compatible = "arm,cortex-a7"; |
| 51 | reg = <0x3>; |
| 52 | clocks = <&gcc GCC_APPS_CLK_SRC>; |
| 53 | }; |
| 54 | }; |
| 55 | |
| 56 | clocks { |
| 57 | sleep_clk: sleep_clk { |
| 58 | compatible = "fixed-clock"; |
| 59 | clock-frequency = <32768>; |
| 60 | #clock-cells = <0>; |
| 61 | }; |
| 62 | }; |
| 63 | |
| 64 | soc { |
| 65 | #address-cells = <1>; |
| 66 | #size-cells = <1>; |
| 67 | ranges; |
| 68 | compatible = "simple-bus"; |
| 69 | |
| 70 | intc: interrupt-controller@b000000 { |
| 71 | compatible = "qcom,msm-qgic2"; |
| 72 | interrupt-controller; |
| 73 | #interrupt-cells = <3>; |
| 74 | reg = <0x0b000000 0x1000>, |
| 75 | <0x0b002000 0x1000>; |
| 76 | }; |
| 77 | |
| 78 | gcc: clock-controller@1800000 { |
| 79 | compatible = "qcom,gcc-ipq4019"; |
| 80 | #clock-cells = <1>; |
| 81 | #reset-cells = <1>; |
| 82 | reg = <0x1800000 0x60000>; |
| 83 | }; |
| 84 | |
| 85 | tlmm: pinctrl@0x01000000 { |
| 86 | compatible = "qcom,ipq4019-pinctrl"; |
| 87 | reg = <0x01000000 0x300000>; |
| 88 | gpio-controller; |
| 89 | #gpio-cells = <2>; |
| 90 | interrupt-controller; |
| 91 | #interrupt-cells = <2>; |
| 92 | interrupts = <0 208 0>; |
| 93 | }; |
| 94 | |
| 95 | serial@78af000 { |
| 96 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 97 | reg = <0x78af000 0x200>; |
| 98 | interrupts = <0 107 0>; |
| 99 | status = "disabled"; |
| 100 | clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, |
| 101 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 102 | clock-names = "core", "iface"; |
| 103 | }; |
| 104 | |
| 105 | serial@78b0000 { |
| 106 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 107 | reg = <0x78b0000 0x200>; |
| 108 | interrupts = <0 108 0>; |
| 109 | status = "disabled"; |
| 110 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, |
| 111 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 112 | clock-names = "core", "iface"; |
| 113 | }; |
| 114 | }; |
| 115 | }; |