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Auke Kok9d5c8242008-01-24 02:22:38 -08001/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _IGB_H_
32#define _IGB_H_
33
34#include "e1000_mac.h"
35#include "e1000_82575.h"
36
37struct igb_adapter;
38
39/* Interrupt defines */
40#define IGB_MAX_TX_CLEAN 72
41
42#define IGB_MIN_DYN_ITR 3000
43#define IGB_MAX_DYN_ITR 96000
44#define IGB_START_ITR 6000
45
46#define IGB_DYN_ITR_PACKET_THRESHOLD 2
47#define IGB_DYN_ITR_LENGTH_LOW 200
48#define IGB_DYN_ITR_LENGTH_HIGH 1000
49
50/* TX/RX descriptor defines */
51#define IGB_DEFAULT_TXD 256
52#define IGB_MIN_TXD 80
53#define IGB_MAX_TXD 4096
54
55#define IGB_DEFAULT_RXD 256
56#define IGB_MIN_RXD 80
57#define IGB_MAX_RXD 4096
58
59#define IGB_DEFAULT_ITR 3 /* dynamic */
60#define IGB_MAX_ITR_USECS 10000
61#define IGB_MIN_ITR_USECS 10
62
63/* Transmit and receive queues */
64#define IGB_MAX_RX_QUEUES 4
Peter P Waskiewicz Jr661086d2008-07-08 15:06:51 -070065#define IGB_MAX_TX_QUEUES 4
Auke Kok9d5c8242008-01-24 02:22:38 -080066
67/* RX descriptor control thresholds.
68 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
69 * descriptors available in its onboard memory.
70 * Setting this to 0 disables RX descriptor prefetch.
71 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
72 * available in host memory.
73 * If PTHRESH is 0, this should also be 0.
74 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
75 * descriptors until either it has this many to write back, or the
76 * ITR timer expires.
77 */
78#define IGB_RX_PTHRESH 16
79#define IGB_RX_HTHRESH 8
80#define IGB_RX_WTHRESH 1
81
82/* this is the size past which hardware will drop packets when setting LPE=0 */
83#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
84
85/* Supported Rx Buffer Sizes */
86#define IGB_RXBUFFER_128 128 /* Used for packet split */
87#define IGB_RXBUFFER_256 256 /* Used for packet split */
88#define IGB_RXBUFFER_512 512
89#define IGB_RXBUFFER_1024 1024
90#define IGB_RXBUFFER_2048 2048
91#define IGB_RXBUFFER_4096 4096
92#define IGB_RXBUFFER_8192 8192
93#define IGB_RXBUFFER_16384 16384
94
95/* Packet Buffer allocations */
96
97
98/* How many Tx Descriptors do we need to call netif_wake_queue ? */
99#define IGB_TX_QUEUE_WAKE 16
100/* How many Rx Buffers do we bundle into one write to the hardware ? */
101#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
102
103#define AUTO_ALL_MODES 0
104#define IGB_EEPROM_APME 0x0400
105
106#ifndef IGB_MASTER_SLAVE
107/* Switch to override PHY master/slave setting */
108#define IGB_MASTER_SLAVE e1000_ms_hw_default
109#endif
110
111#define IGB_MNG_VLAN_NONE -1
112
113/* wrapper around a pointer to a socket buffer,
114 * so a DMA handle can be stored along with the buffer */
115struct igb_buffer {
116 struct sk_buff *skb;
117 dma_addr_t dma;
118 union {
119 /* TX */
120 struct {
121 unsigned long time_stamp;
122 u32 length;
123 };
124 /* RX */
125 struct {
126 struct page *page;
127 u64 page_dma;
Alexander Duyckbf36c1a2008-07-08 15:11:40 -0700128 unsigned int page_offset;
Auke Kok9d5c8242008-01-24 02:22:38 -0800129 };
130 };
131};
132
133struct igb_queue_stats {
134 u64 packets;
135 u64 bytes;
136};
137
138struct igb_ring {
139 struct igb_adapter *adapter; /* backlink */
140 void *desc; /* descriptor ring memory */
141 dma_addr_t dma; /* phys address of the ring */
142 unsigned int size; /* length of desc. ring in bytes */
143 unsigned int count; /* number of desc. in the ring */
144 u16 next_to_use;
145 u16 next_to_clean;
146 u16 head;
147 u16 tail;
148 struct igb_buffer *buffer_info; /* array of buffer info structs */
149
150 u32 eims_value;
151 u32 itr_val;
152 u16 itr_register;
153 u16 cpu;
154
PJ Waskiewicz844290e2008-06-27 11:00:39 -0700155 int queue_index;
Auke Kok9d5c8242008-01-24 02:22:38 -0800156 unsigned int total_bytes;
157 unsigned int total_packets;
158
159 union {
160 /* TX */
161 struct {
Alexander Duycke21ed352008-07-08 15:07:24 -0700162 struct igb_queue_stats tx_stats;
Auke Kok9d5c8242008-01-24 02:22:38 -0800163 bool detect_tx_hung;
164 };
165 /* RX */
166 struct {
Auke Kok9d5c8242008-01-24 02:22:38 -0800167 int no_itr_adjust;
168 struct igb_queue_stats rx_stats;
169 struct napi_struct napi;
170 };
171 };
172
173 char name[IFNAMSIZ + 5];
174};
175
176#define IGB_DESC_UNUSED(R) \
177 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
178 (R)->next_to_clean - (R)->next_to_use - 1)
179
180#define E1000_RX_DESC_ADV(R, i) \
181 (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
182#define E1000_TX_DESC_ADV(R, i) \
183 (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
184#define E1000_TX_CTXTDESC_ADV(R, i) \
185 (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
186#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
187#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
188#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
189
190/* board specific private data structure */
191
192struct igb_adapter {
193 struct timer_list watchdog_timer;
194 struct timer_list phy_info_timer;
195 struct vlan_group *vlgrp;
196 u16 mng_vlan_id;
197 u32 bd_number;
198 u32 rx_buffer_len;
199 u32 wol;
200 u32 en_mng_pt;
201 u16 link_speed;
202 u16 link_duplex;
203 unsigned int total_tx_bytes;
204 unsigned int total_tx_packets;
205 unsigned int total_rx_bytes;
206 unsigned int total_rx_packets;
207 /* Interrupt Throttle Rate */
208 u32 itr;
209 u32 itr_setting;
210 u16 tx_itr;
211 u16 rx_itr;
212 int set_itr;
213
214 struct work_struct reset_task;
215 struct work_struct watchdog_task;
216 bool fc_autoneg;
217 u8 tx_timeout_factor;
218 struct timer_list blink_timer;
219 unsigned long led_status;
220
221 /* TX */
222 struct igb_ring *tx_ring; /* One per active queue */
223 unsigned int restart_queue;
224 unsigned long tx_queue_len;
225 u32 txd_cmd;
226 u32 gotc;
227 u64 gotc_old;
228 u64 tpt_old;
229 u64 colc_old;
230 u32 tx_timeout_count;
231
232 /* RX */
233 struct igb_ring *rx_ring; /* One per active queue */
234 int num_tx_queues;
235 int num_rx_queues;
236
237 u64 hw_csum_err;
238 u64 hw_csum_good;
239 u64 rx_hdr_split;
240 u32 alloc_rx_buff_failed;
241 bool rx_csum;
242 u32 gorc;
243 u64 gorc_old;
244 u16 rx_ps_hdr_size;
245 u32 max_frame_size;
246 u32 min_frame_size;
247
248 /* OS defined structs */
249 struct net_device *netdev;
250 struct napi_struct napi;
251 struct pci_dev *pdev;
252 struct net_device_stats net_stats;
253
254 /* structs defined in e1000_hw.h */
255 struct e1000_hw hw;
256 struct e1000_hw_stats stats;
257 struct e1000_phy_info phy_info;
258 struct e1000_phy_stats phy_stats;
259
260 u32 test_icr;
261 struct igb_ring test_tx_ring;
262 struct igb_ring test_rx_ring;
263
264 int msg_enable;
265 struct msix_entry *msix_entries;
266 u32 eims_enable_mask;
PJ Waskiewicz844290e2008-06-27 11:00:39 -0700267 u32 eims_other;
Auke Kok9d5c8242008-01-24 02:22:38 -0800268
269 /* to not mess up cache alignment, always add to the bottom */
270 unsigned long state;
Alexander Duyck7dfc16f2008-07-08 15:10:46 -0700271 unsigned int flags;
Auke Kok9d5c8242008-01-24 02:22:38 -0800272 u32 eeprom_wol;
Taku Izumi42bfd33a2008-06-20 12:10:30 +0900273
274 /* for ioport free */
275 int bars;
276 int need_ioport;
Peter P Waskiewicz Jr661086d2008-07-08 15:06:51 -0700277
278#ifdef CONFIG_NETDEVICES_MULTIQUEUE
279 struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
280#endif /* CONFIG_NETDEVICES_MULTIQUEUE */
Auke Kok9d5c8242008-01-24 02:22:38 -0800281};
282
Alexander Duyck7dfc16f2008-07-08 15:10:46 -0700283#define IGB_FLAG_HAS_MSI (1 << 0)
284#define IGB_FLAG_MSI_ENABLE (1 << 1)
285#define IGB_FLAG_HAS_DCA (1 << 2)
286#define IGB_FLAG_DCA_ENABLED (1 << 3)
287#define IGB_FLAG_IN_NETPOLL (1 << 5)
288#define IGB_FLAG_QUAD_PORT_A (1 << 6)
289#define IGB_FLAG_NEED_CTX_IDX (1 << 7)
290
Auke Kok9d5c8242008-01-24 02:22:38 -0800291enum e1000_state_t {
292 __IGB_TESTING,
293 __IGB_RESETTING,
294 __IGB_DOWN
295};
296
297enum igb_boards {
298 board_82575,
299};
300
301extern char igb_driver_name[];
302extern char igb_driver_version[];
303
304extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
305extern int igb_up(struct igb_adapter *);
306extern void igb_down(struct igb_adapter *);
307extern void igb_reinit_locked(struct igb_adapter *);
308extern void igb_reset(struct igb_adapter *);
309extern int igb_set_spd_dplx(struct igb_adapter *, u16);
310extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
311extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
312extern void igb_update_stats(struct igb_adapter *);
313extern void igb_set_ethtool_ops(struct net_device *);
314
315#endif /* _IGB_H_ */