blob: cc34356ab0b5bece05057aab55fa567c116a2d0a [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001#include "drmP.h"
2#include "nouveau_drv.h"
3#include "nouveau_dma.h"
4#include "nouveau_fbcon.h"
5
6static void
7nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
8{
9 struct nouveau_fbcon_par *par = info->par;
10 struct drm_device *dev = par->dev;
11 struct drm_nouveau_private *dev_priv = dev->dev_private;
12 struct nouveau_channel *chan = dev_priv->channel;
13
14 if (info->state != FBINFO_STATE_RUNNING)
15 return;
16
17 if (!(info->flags & FBINFO_HWACCEL_DISABLED) &&
18 RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) {
19 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
20
21 info->flags |= FBINFO_HWACCEL_DISABLED;
22 }
23
24 if (info->flags & FBINFO_HWACCEL_DISABLED) {
25 cfb_fillrect(info, rect);
26 return;
27 }
28
29 if (rect->rop != ROP_COPY) {
30 BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
31 OUT_RING(chan, 1);
32 }
33 BEGIN_RING(chan, NvSub2D, 0x0588, 1);
Ben Skeggsbf5302b2010-01-04 09:10:55 +100034 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
35 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
36 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
37 else
38 OUT_RING(chan, rect->color);
Ben Skeggs6ee73862009-12-11 19:24:15 +100039 BEGIN_RING(chan, NvSub2D, 0x0600, 4);
40 OUT_RING(chan, rect->dx);
41 OUT_RING(chan, rect->dy);
42 OUT_RING(chan, rect->dx + rect->width);
43 OUT_RING(chan, rect->dy + rect->height);
44 if (rect->rop != ROP_COPY) {
45 BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
46 OUT_RING(chan, 3);
47 }
48 FIRE_RING(chan);
49}
50
51static void
52nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
53{
54 struct nouveau_fbcon_par *par = info->par;
55 struct drm_device *dev = par->dev;
56 struct drm_nouveau_private *dev_priv = dev->dev_private;
57 struct nouveau_channel *chan = dev_priv->channel;
58
59 if (info->state != FBINFO_STATE_RUNNING)
60 return;
61
62 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) {
63 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
64
65 info->flags |= FBINFO_HWACCEL_DISABLED;
66 }
67
68 if (info->flags & FBINFO_HWACCEL_DISABLED) {
69 cfb_copyarea(info, region);
70 return;
71 }
72
73 BEGIN_RING(chan, NvSub2D, 0x0110, 1);
74 OUT_RING(chan, 0);
75 BEGIN_RING(chan, NvSub2D, 0x08b0, 4);
76 OUT_RING(chan, region->dx);
77 OUT_RING(chan, region->dy);
78 OUT_RING(chan, region->width);
79 OUT_RING(chan, region->height);
80 BEGIN_RING(chan, NvSub2D, 0x08d0, 4);
81 OUT_RING(chan, 0);
82 OUT_RING(chan, region->sx);
83 OUT_RING(chan, 0);
84 OUT_RING(chan, region->sy);
85 FIRE_RING(chan);
86}
87
88static void
89nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
90{
91 struct nouveau_fbcon_par *par = info->par;
92 struct drm_device *dev = par->dev;
93 struct drm_nouveau_private *dev_priv = dev->dev_private;
94 struct nouveau_channel *chan = dev_priv->channel;
95 uint32_t width, dwords, *data = (uint32_t *)image->data;
96 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
97 uint32_t *palette = info->pseudo_palette;
98
99 if (info->state != FBINFO_STATE_RUNNING)
100 return;
101
102 if (image->depth != 1) {
103 cfb_imageblit(info, image);
104 return;
105 }
106
107 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) {
108 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
109 info->flags |= FBINFO_HWACCEL_DISABLED;
110 }
111
112 if (info->flags & FBINFO_HWACCEL_DISABLED) {
113 cfb_imageblit(info, image);
114 return;
115 }
116
117 width = (image->width + 31) & ~31;
118 dwords = (width * image->height) >> 5;
119
120 BEGIN_RING(chan, NvSub2D, 0x0814, 2);
121 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
122 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
123 OUT_RING(chan, palette[image->bg_color] | mask);
124 OUT_RING(chan, palette[image->fg_color] | mask);
125 } else {
126 OUT_RING(chan, image->bg_color);
127 OUT_RING(chan, image->fg_color);
128 }
129 BEGIN_RING(chan, NvSub2D, 0x0838, 2);
130 OUT_RING(chan, image->width);
131 OUT_RING(chan, image->height);
132 BEGIN_RING(chan, NvSub2D, 0x0850, 4);
133 OUT_RING(chan, 0);
134 OUT_RING(chan, image->dx);
135 OUT_RING(chan, 0);
136 OUT_RING(chan, image->dy);
137
138 while (dwords) {
139 int push = dwords > 2047 ? 2047 : dwords;
140
141 if (RING_SPACE(chan, push + 1)) {
142 NV_ERROR(dev,
143 "GPU lockup - switching to software fbcon\n");
144 info->flags |= FBINFO_HWACCEL_DISABLED;
145 cfb_imageblit(info, image);
146 return;
147 }
148
149 dwords -= push;
150
151 BEGIN_RING(chan, NvSub2D, 0x40000860, push);
152 OUT_RINGp(chan, data, push);
153 data += push;
154 }
155
156 FIRE_RING(chan);
157}
158
159int
160nv50_fbcon_accel_init(struct fb_info *info)
161{
162 struct nouveau_fbcon_par *par = info->par;
163 struct drm_device *dev = par->dev;
164 struct drm_nouveau_private *dev_priv = dev->dev_private;
165 struct nouveau_channel *chan = dev_priv->channel;
166 struct nouveau_gpuobj *eng2d = NULL;
167 int ret, format;
168
169 switch (info->var.bits_per_pixel) {
170 case 8:
171 format = 0xf3;
172 break;
173 case 15:
174 format = 0xf8;
175 break;
176 case 16:
177 format = 0xe8;
178 break;
179 case 32:
180 switch (info->var.transp.length) {
181 case 0: /* depth 24 */
182 case 8: /* depth 32, just use 24.. */
183 format = 0xe6;
184 break;
185 case 2: /* depth 30 */
186 format = 0xd1;
187 break;
188 default:
189 return -EINVAL;
190 }
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 ret = nouveau_gpuobj_gr_new(dev_priv->channel, 0x502d, &eng2d);
197 if (ret)
198 return ret;
199
200 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, Nv2D, eng2d, NULL);
201 if (ret)
202 return ret;
203
204 ret = RING_SPACE(chan, 59);
205 if (ret) {
206 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
207 return ret;
208 }
209
210 BEGIN_RING(chan, NvSub2D, 0x0000, 1);
211 OUT_RING(chan, Nv2D);
212 BEGIN_RING(chan, NvSub2D, 0x0180, 4);
213 OUT_RING(chan, NvNotify0);
214 OUT_RING(chan, chan->vram_handle);
215 OUT_RING(chan, chan->vram_handle);
216 OUT_RING(chan, chan->vram_handle);
217 BEGIN_RING(chan, NvSub2D, 0x0290, 1);
218 OUT_RING(chan, 0);
219 BEGIN_RING(chan, NvSub2D, 0x0888, 1);
220 OUT_RING(chan, 1);
221 BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
222 OUT_RING(chan, 3);
223 BEGIN_RING(chan, NvSub2D, 0x02a0, 1);
224 OUT_RING(chan, 0x55);
225 BEGIN_RING(chan, NvSub2D, 0x08c0, 4);
226 OUT_RING(chan, 0);
227 OUT_RING(chan, 1);
228 OUT_RING(chan, 0);
229 OUT_RING(chan, 1);
230 BEGIN_RING(chan, NvSub2D, 0x0580, 2);
231 OUT_RING(chan, 4);
232 OUT_RING(chan, format);
233 BEGIN_RING(chan, NvSub2D, 0x02e8, 2);
234 OUT_RING(chan, 2);
235 OUT_RING(chan, 1);
236 BEGIN_RING(chan, NvSub2D, 0x0804, 1);
237 OUT_RING(chan, format);
238 BEGIN_RING(chan, NvSub2D, 0x0800, 1);
239 OUT_RING(chan, 1);
240 BEGIN_RING(chan, NvSub2D, 0x0808, 3);
241 OUT_RING(chan, 0);
242 OUT_RING(chan, 0);
243 OUT_RING(chan, 0);
244 BEGIN_RING(chan, NvSub2D, 0x081c, 1);
245 OUT_RING(chan, 1);
246 BEGIN_RING(chan, NvSub2D, 0x0840, 4);
247 OUT_RING(chan, 0);
248 OUT_RING(chan, 1);
249 OUT_RING(chan, 0);
250 OUT_RING(chan, 1);
251 BEGIN_RING(chan, NvSub2D, 0x0200, 2);
252 OUT_RING(chan, format);
253 OUT_RING(chan, 1);
254 BEGIN_RING(chan, NvSub2D, 0x0214, 5);
255 OUT_RING(chan, info->fix.line_length);
256 OUT_RING(chan, info->var.xres_virtual);
257 OUT_RING(chan, info->var.yres_virtual);
258 OUT_RING(chan, 0);
259 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys +
260 dev_priv->vm_vram_base);
261 BEGIN_RING(chan, NvSub2D, 0x0230, 2);
262 OUT_RING(chan, format);
263 OUT_RING(chan, 1);
264 BEGIN_RING(chan, NvSub2D, 0x0244, 5);
265 OUT_RING(chan, info->fix.line_length);
266 OUT_RING(chan, info->var.xres_virtual);
267 OUT_RING(chan, info->var.yres_virtual);
268 OUT_RING(chan, 0);
269 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys +
270 dev_priv->vm_vram_base);
271
272 info->fbops->fb_fillrect = nv50_fbcon_fillrect;
273 info->fbops->fb_copyarea = nv50_fbcon_copyarea;
274 info->fbops->fb_imageblit = nv50_fbcon_imageblit;
275 return 0;
276}
277