blob: 6e8e42361fd5406e7d345bd9aefbc00e950f2cc5 [file] [log] [blame]
Andrew F. Davis34e45ad2015-10-20 16:28:57 -05001/*
2 * Driver for the Texas Instruments DP83848 PHY
3 *
Andrew F. Davis2f678642016-02-07 11:47:17 -06004 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
Andrew F. Davis34e45ad2015-10-20 16:28:57 -05005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/module.h>
17#include <linux/phy.h>
18
Andrew F. Davis68336292016-02-07 11:47:18 -060019#define TI_DP83848C_PHY_ID 0x20005ca0
Alvaro G. M93b43fd2017-01-17 09:08:16 +010020#define TI_DP83620_PHY_ID 0x20005ce0
Andrew F. Davis68336292016-02-07 11:47:18 -060021#define NS_DP83848C_PHY_ID 0x20005c90
Andrew F. Davisd1782f72016-02-07 11:47:20 -060022#define TLK10X_PHY_ID 0x2000a210
Andrew F. Davis34e45ad2015-10-20 16:28:57 -050023
24/* Registers */
Andrew F. Davis5fed0392016-02-07 11:47:21 -060025#define DP83848_MICR 0x11 /* MII Interrupt Control Register */
26#define DP83848_MISR 0x12 /* MII Interrupt Status Register */
Andrew F. Davis34e45ad2015-10-20 16:28:57 -050027
28/* MICR Register Fields */
29#define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
30#define DP83848_MICR_INTEN BIT(1) /* Interrupt Enable */
31
32/* MISR Register Fields */
33#define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
34#define DP83848_MISR_FHF_INT_EN BIT(1) /* False Carrier Counter */
35#define DP83848_MISR_ANC_INT_EN BIT(2) /* Auto-negotiation complete */
36#define DP83848_MISR_DUP_INT_EN BIT(3) /* Duplex Status */
37#define DP83848_MISR_SPD_INT_EN BIT(4) /* Speed status */
38#define DP83848_MISR_LINK_INT_EN BIT(5) /* Link status */
39#define DP83848_MISR_ED_INT_EN BIT(6) /* Energy detect */
40#define DP83848_MISR_LQM_INT_EN BIT(7) /* Link Quality Monitor */
41
Andrew F. Daviscf13be52016-02-07 11:47:19 -060042#define DP83848_INT_EN_MASK \
43 (DP83848_MISR_ANC_INT_EN | \
44 DP83848_MISR_DUP_INT_EN | \
45 DP83848_MISR_SPD_INT_EN | \
46 DP83848_MISR_LINK_INT_EN)
47
Andrew F. Davis34e45ad2015-10-20 16:28:57 -050048static int dp83848_ack_interrupt(struct phy_device *phydev)
49{
50 int err = phy_read(phydev, DP83848_MISR);
51
52 return err < 0 ? err : 0;
53}
54
55static int dp83848_config_intr(struct phy_device *phydev)
56{
Andrew F. Daviscf13be52016-02-07 11:47:19 -060057 int control, ret;
58
59 control = phy_read(phydev, DP83848_MICR);
60 if (control < 0)
61 return control;
Andrew F. Davis34e45ad2015-10-20 16:28:57 -050062
63 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
Andrew F. Daviscf13be52016-02-07 11:47:19 -060064 control |= DP83848_MICR_INT_OE;
65 control |= DP83848_MICR_INTEN;
Andrew F. Davis34e45ad2015-10-20 16:28:57 -050066
Andrew F. Daviscf13be52016-02-07 11:47:19 -060067 ret = phy_write(phydev, DP83848_MISR, DP83848_INT_EN_MASK);
68 if (ret < 0)
69 return ret;
70 } else {
71 control &= ~DP83848_MICR_INTEN;
Andrew F. Davis34e45ad2015-10-20 16:28:57 -050072 }
73
Andrew F. Daviscf13be52016-02-07 11:47:19 -060074 return phy_write(phydev, DP83848_MICR, control);
Andrew F. Davis34e45ad2015-10-20 16:28:57 -050075}
76
Alvaro Gamez Machadob718e8c2018-06-08 12:23:39 +020077static int dp83848_config_init(struct phy_device *phydev)
78{
79 int err;
80 int val;
81
82 err = genphy_config_init(phydev);
83 if (err < 0)
84 return err;
85
86 /* DP83620 always reports Auto Negotiation Ability on BMSR. Instead,
87 * we check initial value of BMCR Auto negotiation enable bit
88 */
89 val = phy_read(phydev, MII_BMCR);
90 if (!(val & BMCR_ANENABLE))
91 phydev->autoneg = AUTONEG_DISABLE;
92
93 return 0;
94}
95
Andrew F. Davis34e45ad2015-10-20 16:28:57 -050096static struct mdio_device_id __maybe_unused dp83848_tbl[] = {
Andrew F. Davis68336292016-02-07 11:47:18 -060097 { TI_DP83848C_PHY_ID, 0xfffffff0 },
98 { NS_DP83848C_PHY_ID, 0xfffffff0 },
Alvaro G. M93b43fd2017-01-17 09:08:16 +010099 { TI_DP83620_PHY_ID, 0xfffffff0 },
Andrew F. Davisd1782f72016-02-07 11:47:20 -0600100 { TLK10X_PHY_ID, 0xfffffff0 },
Andrew F. Davis34e45ad2015-10-20 16:28:57 -0500101 { }
102};
103MODULE_DEVICE_TABLE(mdio, dp83848_tbl);
104
Alvaro Gamez Machadob718e8c2018-06-08 12:23:39 +0200105#define DP83848_PHY_DRIVER(_id, _name, _config_init) \
Andrew F. Davis2f678642016-02-07 11:47:17 -0600106 { \
107 .phy_id = _id, \
108 .phy_id_mask = 0xfffffff0, \
109 .name = _name, \
110 .features = PHY_BASIC_FEATURES, \
111 .flags = PHY_HAS_INTERRUPT, \
112 \
113 .soft_reset = genphy_soft_reset, \
Alvaro Gamez Machadob718e8c2018-06-08 12:23:39 +0200114 .config_init = _config_init, \
Andrew F. Davis2f678642016-02-07 11:47:17 -0600115 .suspend = genphy_suspend, \
116 .resume = genphy_resume, \
Andrew F. Davis2f678642016-02-07 11:47:17 -0600117 \
118 /* IRQ related */ \
119 .ack_interrupt = dp83848_ack_interrupt, \
120 .config_intr = dp83848_config_intr, \
121 }
122
Andrew F. Davis34e45ad2015-10-20 16:28:57 -0500123static struct phy_driver dp83848_driver[] = {
Alvaro Gamez Machadob718e8c2018-06-08 12:23:39 +0200124 DP83848_PHY_DRIVER(TI_DP83848C_PHY_ID, "TI DP83848C 10/100 Mbps PHY",
125 genphy_config_init),
126 DP83848_PHY_DRIVER(NS_DP83848C_PHY_ID, "NS DP83848C 10/100 Mbps PHY",
127 genphy_config_init),
128 DP83848_PHY_DRIVER(TI_DP83620_PHY_ID, "TI DP83620 10/100 Mbps PHY",
129 dp83848_config_init),
130 DP83848_PHY_DRIVER(TLK10X_PHY_ID, "TI TLK10X 10/100 Mbps PHY",
131 genphy_config_init),
Andrew F. Davis34e45ad2015-10-20 16:28:57 -0500132};
133module_phy_driver(dp83848_driver);
134
135MODULE_DESCRIPTION("Texas Instruments DP83848 PHY driver");
Andrew F. Davis3d17cc32017-01-05 14:44:50 -0600136MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
Andrew F. Davis34e45ad2015-10-20 16:28:57 -0500137MODULE_LICENSE("GPL");