blob: 0888e50f6b1732a54911223281c64a69d80e6def [file] [log] [blame]
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +01001/*
2 * Driver for the MDIO interface of Marvell network interfaces.
3 *
4 * Since the MDIO interface of Marvell network interfaces is shared
5 * between all network interfaces, having a single driver allows to
6 * handle concurrent accesses properly (you may have four Ethernet
Leigh Brownd4a0acb2013-10-29 09:33:34 +00007 * ports, but they in fact share the same SMI interface to access
8 * the MDIO bus). This driver is currently used by the mvneta and
9 * mv643xx_eth drivers.
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010010 *
11 * Copyright (C) 2012 Marvell
12 *
13 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 *
15 * This file is licensed under the terms of the GNU General Public
16 * License version 2. This program is licensed "as is" without any
17 * warranty of any kind, whether express or implied.
18 */
19
Antoine Ténart14ef8b32017-06-15 16:43:16 +020020#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010024#include <linux/kernel.h>
25#include <linux/module.h>
Antoine Ténartc0ac08f2017-06-15 16:43:23 +020026#include <linux/of_device.h>
Florian Fainelli7111b712013-03-22 03:39:25 +000027#include <linux/of_mdio.h>
Antoine Ténart14ef8b32017-06-15 16:43:16 +020028#include <linux/phy.h>
29#include <linux/platform_device.h>
Florian Fainelli2ec98522013-03-22 03:39:27 +000030#include <linux/sched.h>
31#include <linux/wait.h>
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010032
Antoine Ténart2040ef22017-06-15 16:43:17 +020033#define MVMDIO_SMI_DATA_SHIFT 0
34#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
35#define MVMDIO_SMI_PHY_REG_SHIFT 21
36#define MVMDIO_SMI_READ_OPERATION BIT(26)
37#define MVMDIO_SMI_WRITE_OPERATION 0
38#define MVMDIO_SMI_READ_VALID BIT(27)
39#define MVMDIO_SMI_BUSY BIT(28)
40#define MVMDIO_ERR_INT_CAUSE 0x007C
41#define MVMDIO_ERR_INT_SMI_DONE 0x00000010
42#define MVMDIO_ERR_INT_MASK 0x0080
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010043
Antoine Ténartc0ac08f2017-06-15 16:43:23 +020044#define MVMDIO_XSMI_MGNT_REG 0x0
45#define MVMDIO_XSMI_PHYADDR_SHIFT 16
46#define MVMDIO_XSMI_DEVADDR_SHIFT 21
47#define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
48#define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
49#define MVMDIO_XSMI_READ_VALID BIT(29)
50#define MVMDIO_XSMI_BUSY BIT(30)
51#define MVMDIO_XSMI_ADDR_REG 0x8
52
Leigh Brownb70cd1c2013-10-29 09:33:31 +000053/*
54 * SMI Timeout measurements:
55 * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
56 * - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled)
57 */
Antoine Ténart2040ef22017-06-15 16:43:17 +020058#define MVMDIO_SMI_TIMEOUT 1000 /* 1000us = 1ms */
59#define MVMDIO_SMI_POLL_INTERVAL_MIN 45
60#define MVMDIO_SMI_POLL_INTERVAL_MAX 55
Leigh Brownb70cd1c2013-10-29 09:33:31 +000061
Antoine Ténartc0ac08f2017-06-15 16:43:23 +020062#define MVMDIO_XSMI_POLL_INTERVAL_MIN 150
63#define MVMDIO_XSMI_POLL_INTERVAL_MAX 160
64
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010065struct orion_mdio_dev {
Florian Fainelli3712b712013-03-22 03:39:26 +000066 void __iomem *regs;
Russell King96cb4342017-04-10 16:28:31 +010067 struct clk *clk[3];
Florian Fainelli2ec98522013-03-22 03:39:27 +000068 /*
69 * If we have access to the error interrupt pin (which is
70 * somewhat misnamed as it not only reflects internal errors
71 * but also reflects SMI completion), use that to wait for
72 * SMI access completion instead of polling the SMI busy bit.
73 */
74 int err_interrupt;
75 wait_queue_head_t smi_busy_wait;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010076};
77
Antoine Ténartc0ac08f2017-06-15 16:43:23 +020078enum orion_mdio_bus_type {
79 BUS_TYPE_SMI,
80 BUS_TYPE_XSMI
81};
82
Antoine Ténartb0b7fa42017-06-15 16:43:20 +020083struct orion_mdio_ops {
84 int (*is_done)(struct orion_mdio_dev *);
Antoine Ténart19557962017-06-15 16:43:21 +020085 unsigned int poll_interval_min;
86 unsigned int poll_interval_max;
Antoine Ténartb0b7fa42017-06-15 16:43:20 +020087};
Florian Fainelli2ec98522013-03-22 03:39:27 +000088
Thomas Petazzonib07812f2012-11-19 11:40:15 +010089/* Wait for the SMI unit to be ready for another operation
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010090 */
Antoine Ténartb0b7fa42017-06-15 16:43:20 +020091static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops,
92 struct mii_bus *bus)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010093{
94 struct orion_mdio_dev *dev = bus->priv;
Leigh Brownb70cd1c2013-10-29 09:33:31 +000095 unsigned long timeout = usecs_to_jiffies(MVMDIO_SMI_TIMEOUT);
96 unsigned long end = jiffies + timeout;
97 int timedout = 0;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010098
Leigh Brownb70cd1c2013-10-29 09:33:31 +000099 while (1) {
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200100 if (ops->is_done(dev))
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000101 return 0;
102 else if (timedout)
103 break;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100104
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000105 if (dev->err_interrupt <= 0) {
Antoine Ténart19557962017-06-15 16:43:21 +0200106 usleep_range(ops->poll_interval_min,
107 ops->poll_interval_max);
Florian Fainelli2ec98522013-03-22 03:39:27 +0000108
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000109 if (time_is_before_jiffies(end))
110 ++timedout;
111 } else {
Leigh Brown1a1f20b2013-12-19 13:09:48 +0000112 /* wait_event_timeout does not guarantee a delay of at
113 * least one whole jiffie, so timeout must be no less
114 * than two.
115 */
116 if (timeout < 2)
117 timeout = 2;
Florian Fainelli2ec98522013-03-22 03:39:27 +0000118 wait_event_timeout(dev->smi_busy_wait,
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200119 ops->is_done(dev), timeout);
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000120
121 ++timedout;
122 }
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100123 }
124
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000125 dev_err(bus->parent, "Timeout: SMI busy for too long\n");
126 return -ETIMEDOUT;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100127}
128
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200129static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)
130{
131 return !(readl(dev->regs) & MVMDIO_SMI_BUSY);
132}
133
134static const struct orion_mdio_ops orion_mdio_smi_ops = {
135 .is_done = orion_mdio_smi_is_done,
Antoine Ténart19557962017-06-15 16:43:21 +0200136 .poll_interval_min = MVMDIO_SMI_POLL_INTERVAL_MIN,
137 .poll_interval_max = MVMDIO_SMI_POLL_INTERVAL_MAX,
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200138};
139
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200140static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,
141 int regnum)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100142{
143 struct orion_mdio_dev *dev = bus->priv;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100144 u32 val;
145 int ret;
146
Antoine Ténart440ea772017-06-15 16:43:22 +0200147 if (regnum & MII_ADDR_C45)
148 return -EOPNOTSUPP;
149
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200150 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
Leigh Brown839f46b2013-10-29 09:33:32 +0000151 if (ret < 0)
152 goto out;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100153
154 writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
155 (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
156 MVMDIO_SMI_READ_OPERATION),
Florian Fainelli3712b712013-03-22 03:39:26 +0000157 dev->regs);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100158
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200159 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
Leigh Brown839f46b2013-10-29 09:33:32 +0000160 if (ret < 0)
161 goto out;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100162
Leigh Brown839f46b2013-10-29 09:33:32 +0000163 val = readl(dev->regs);
164 if (!(val & MVMDIO_SMI_READ_VALID)) {
165 dev_err(bus->parent, "SMI bus read not valid\n");
166 ret = -ENODEV;
167 goto out;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100168 }
169
Antoine Ténartfd3ebd82017-06-15 16:43:18 +0200170 ret = val & GENMASK(15, 0);
Leigh Brown839f46b2013-10-29 09:33:32 +0000171out:
Leigh Brown839f46b2013-10-29 09:33:32 +0000172 return ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100173}
174
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200175static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id,
176 int regnum, u16 value)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100177{
178 struct orion_mdio_dev *dev = bus->priv;
179 int ret;
180
Antoine Ténart440ea772017-06-15 16:43:22 +0200181 if (regnum & MII_ADDR_C45)
182 return -EOPNOTSUPP;
183
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200184 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
Leigh Brown526edcf2013-10-29 09:33:33 +0000185 if (ret < 0)
186 goto out;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100187
188 writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
189 (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
190 MVMDIO_SMI_WRITE_OPERATION |
191 (value << MVMDIO_SMI_DATA_SHIFT)),
Florian Fainelli3712b712013-03-22 03:39:26 +0000192 dev->regs);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100193
Leigh Brown526edcf2013-10-29 09:33:33 +0000194out:
Leigh Brown526edcf2013-10-29 09:33:33 +0000195 return ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100196}
197
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200198static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev)
199{
200 return !(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & MVMDIO_XSMI_BUSY);
201}
202
203static const struct orion_mdio_ops orion_mdio_xsmi_ops = {
204 .is_done = orion_mdio_xsmi_is_done,
205 .poll_interval_min = MVMDIO_XSMI_POLL_INTERVAL_MIN,
206 .poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX,
207};
208
209static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id,
210 int regnum)
211{
212 struct orion_mdio_dev *dev = bus->priv;
213 u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
214 int ret;
215
216 if (!(regnum & MII_ADDR_C45))
217 return -EOPNOTSUPP;
218
219 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
220 if (ret < 0)
221 return ret;
222
223 writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
224 writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
225 (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
226 MVMDIO_XSMI_READ_OPERATION,
227 dev->regs + MVMDIO_XSMI_MGNT_REG);
228
229 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
230 if (ret < 0)
231 return ret;
232
233 if (!(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) &
234 MVMDIO_XSMI_READ_VALID)) {
235 dev_err(bus->parent, "XSMI bus read not valid\n");
236 return -ENODEV;
237 }
238
239 return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
240}
241
242static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id,
243 int regnum, u16 value)
244{
245 struct orion_mdio_dev *dev = bus->priv;
246 u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
247 int ret;
248
249 if (!(regnum & MII_ADDR_C45))
250 return -EOPNOTSUPP;
251
252 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
253 if (ret < 0)
254 return ret;
255
256 writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
257 writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
258 (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
259 MVMDIO_XSMI_WRITE_OPERATION | value,
260 dev->regs + MVMDIO_XSMI_MGNT_REG);
261
262 return 0;
263}
264
Florian Fainelli2ec98522013-03-22 03:39:27 +0000265static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)
266{
267 struct orion_mdio_dev *dev = dev_id;
268
269 if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) &
270 MVMDIO_ERR_INT_SMI_DONE) {
271 writel(~MVMDIO_ERR_INT_SMI_DONE,
272 dev->regs + MVMDIO_ERR_INT_CAUSE);
273 wake_up(&dev->smi_busy_wait);
274 return IRQ_HANDLED;
275 }
276
277 return IRQ_NONE;
278}
279
Greg KH03ce7582012-12-21 13:42:15 +0000280static int orion_mdio_probe(struct platform_device *pdev)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100281{
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200282 enum orion_mdio_bus_type type;
Florian Fainelli7111b712013-03-22 03:39:25 +0000283 struct resource *r;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100284 struct mii_bus *bus;
285 struct orion_mdio_dev *dev;
Russell King96cb4342017-04-10 16:28:31 +0100286 int i, ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100287
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200288 type = (enum orion_mdio_bus_type)of_device_get_match_data(&pdev->dev);
289
Florian Fainelli7111b712013-03-22 03:39:25 +0000290 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
291 if (!r) {
292 dev_err(&pdev->dev, "No SMI register address given\n");
293 return -ENODEV;
294 }
295
Ezequiel Garcia56ecd2c2014-05-22 20:07:02 -0300296 bus = devm_mdiobus_alloc_size(&pdev->dev,
297 sizeof(struct orion_mdio_dev));
298 if (!bus)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100299 return -ENOMEM;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100300
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200301 switch (type) {
302 case BUS_TYPE_SMI:
303 bus->read = orion_mdio_smi_read;
304 bus->write = orion_mdio_smi_write;
305 break;
306 case BUS_TYPE_XSMI:
307 bus->read = orion_mdio_xsmi_read;
308 bus->write = orion_mdio_xsmi_write;
309 break;
310 }
311
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100312 bus->name = "orion_mdio_bus";
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100313 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
314 dev_name(&pdev->dev));
315 bus->parent = &pdev->dev;
316
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100317 dev = bus->priv;
Florian Fainelli3712b712013-03-22 03:39:26 +0000318 dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
319 if (!dev->regs) {
Florian Fainelli7111b712013-03-22 03:39:25 +0000320 dev_err(&pdev->dev, "Unable to remap SMI register\n");
Alexey Khoroshilovf814bfd2016-10-01 00:56:37 +0300321 return -ENODEV;
Florian Fainelli2ec98522013-03-22 03:39:27 +0000322 }
323
324 init_waitqueue_head(&dev->smi_busy_wait);
325
Russell King96cb4342017-04-10 16:28:31 +0100326 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
327 dev->clk[i] = of_clk_get(pdev->dev.of_node, i);
328 if (IS_ERR(dev->clk[i]))
329 break;
330 clk_prepare_enable(dev->clk[i]);
331 }
Sebastian Hesselbarth3d604da2013-04-07 01:09:47 +0000332
Florian Fainelli2ec98522013-03-22 03:39:27 +0000333 dev->err_interrupt = platform_get_irq(pdev, 0);
Russell Kinga51e2c92017-04-10 16:28:20 +0100334 if (dev->err_interrupt > 0 &&
335 resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {
336 dev_err(&pdev->dev,
337 "disabling interrupt, resource size is too small\n");
338 dev->err_interrupt = 0;
339 }
Ezequiel Garcia39076b02014-04-30 13:28:51 -0300340 if (dev->err_interrupt > 0) {
Florian Fainelli2ec98522013-03-22 03:39:27 +0000341 ret = devm_request_irq(&pdev->dev, dev->err_interrupt,
342 orion_mdio_err_irq,
343 IRQF_SHARED, pdev->name, dev);
344 if (ret)
345 goto out_mdio;
346
347 writel(MVMDIO_ERR_INT_SMI_DONE,
348 dev->regs + MVMDIO_ERR_INT_MASK);
Ezequiel Garcia39076b02014-04-30 13:28:51 -0300349
350 } else if (dev->err_interrupt == -EPROBE_DEFER) {
351 return -EPROBE_DEFER;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100352 }
353
Florian Fainelli7111b712013-03-22 03:39:25 +0000354 if (pdev->dev.of_node)
355 ret = of_mdiobus_register(bus, pdev->dev.of_node);
356 else
357 ret = mdiobus_register(bus);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100358 if (ret < 0) {
359 dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
Florian Fainelli2ec98522013-03-22 03:39:27 +0000360 goto out_mdio;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100361 }
362
363 platform_set_drvdata(pdev, bus);
364
365 return 0;
Florian Fainelli2ec98522013-03-22 03:39:27 +0000366
367out_mdio:
Russell King37282482017-04-10 16:28:04 +0100368 if (dev->err_interrupt > 0)
369 writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
Russell King96cb4342017-04-10 16:28:31 +0100370
371 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
372 if (IS_ERR(dev->clk[i]))
373 break;
374 clk_disable_unprepare(dev->clk[i]);
375 clk_put(dev->clk[i]);
376 }
377
Florian Fainelli2ec98522013-03-22 03:39:27 +0000378 return ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100379}
380
Greg KH03ce7582012-12-21 13:42:15 +0000381static int orion_mdio_remove(struct platform_device *pdev)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100382{
383 struct mii_bus *bus = platform_get_drvdata(pdev);
Florian Fainelli2ec98522013-03-22 03:39:27 +0000384 struct orion_mdio_dev *dev = bus->priv;
Russell King96cb4342017-04-10 16:28:31 +0100385 int i;
Florian Fainelli2ec98522013-03-22 03:39:27 +0000386
Russell King7093a972017-04-10 16:28:09 +0100387 if (dev->err_interrupt > 0)
388 writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100389 mdiobus_unregister(bus);
Russell King96cb4342017-04-10 16:28:31 +0100390
391 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
392 if (IS_ERR(dev->clk[i]))
393 break;
394 clk_disable_unprepare(dev->clk[i]);
395 clk_put(dev->clk[i]);
396 }
Sebastian Hesselbarth3d604da2013-04-07 01:09:47 +0000397
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100398 return 0;
399}
400
401static const struct of_device_id orion_mdio_match[] = {
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200402 { .compatible = "marvell,orion-mdio", .data = (void *)BUS_TYPE_SMI },
403 { .compatible = "marvell,xmdio", .data = (void *)BUS_TYPE_XSMI },
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100404 { }
405};
406MODULE_DEVICE_TABLE(of, orion_mdio_match);
407
408static struct platform_driver orion_mdio_driver = {
409 .probe = orion_mdio_probe,
Greg KH03ce7582012-12-21 13:42:15 +0000410 .remove = orion_mdio_remove,
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100411 .driver = {
412 .name = "orion-mdio",
413 .of_match_table = orion_mdio_match,
414 },
415};
416
417module_platform_driver(orion_mdio_driver);
418
419MODULE_DESCRIPTION("Marvell MDIO interface driver");
420MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
421MODULE_LICENSE("GPL");
Simon Baatz404b8be2013-03-24 10:33:59 +0000422MODULE_ALIAS("platform:orion-mdio");