blob: 7eb1c21d2d2110d9b69c6e336dce6d24a402dee4 [file] [log] [blame]
Marc Zyngier08dcbfd2015-10-21 10:09:49 +01001/*
2 * Copyright (C) 2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ARM_KVM_HYP_H__
19#define __ARM_KVM_HYP_H__
20
21#include <linux/compiler.h>
22#include <linux/kvm_host.h>
23#include <asm/kvm_mmu.h>
24
25#define __hyp_text __section(.hyp.text) notrace
26
27#define kern_hyp_va(v) (v)
28#define hyp_kern_va(v) (v)
29
Marc Zyngier3c295682016-01-02 15:07:13 +000030#define __ACCESS_CP15(CRn, Op1, CRm, Op2) \
31 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
32#define __ACCESS_CP15_64(Op1, CRm) \
33 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
34
35#define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
36#define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
37
38#define __read_sysreg(r, w, c, t) ({ \
39 t __val; \
40 asm volatile(r " " c : "=r" (__val)); \
41 __val; \
42})
43#define read_sysreg(...) __read_sysreg(__VA_ARGS__)
44
Marc Zyngierc7ce6c62016-01-03 12:55:01 +000045#define TTBR0 __ACCESS_CP15_64(0, c2)
46#define TTBR1 __ACCESS_CP15_64(1, c2)
Marc Zyngier1d58d2c2016-01-02 15:09:54 +000047#define VTTBR __ACCESS_CP15_64(6, c2)
Marc Zyngierc7ce6c62016-01-03 12:55:01 +000048#define PAR __ACCESS_CP15_64(0, c7)
Marc Zyngiere59bff9b2016-01-04 08:54:50 +000049#define CNTV_CVAL __ACCESS_CP15_64(3, c14)
50#define CNTVOFF __ACCESS_CP15_64(4, c14)
51
Marc Zyngierc7ce6c62016-01-03 12:55:01 +000052#define CSSELR __ACCESS_CP15(c0, 2, c0, 0)
53#define VMPIDR __ACCESS_CP15(c0, 4, c0, 5)
54#define SCTLR __ACCESS_CP15(c1, 0, c0, 0)
55#define CPACR __ACCESS_CP15(c1, 0, c0, 2)
56#define TTBCR __ACCESS_CP15(c2, 0, c0, 2)
57#define DACR __ACCESS_CP15(c3, 0, c0, 0)
58#define DFSR __ACCESS_CP15(c5, 0, c0, 0)
59#define IFSR __ACCESS_CP15(c5, 0, c0, 1)
60#define ADFSR __ACCESS_CP15(c5, 0, c1, 0)
61#define AIFSR __ACCESS_CP15(c5, 0, c1, 1)
62#define DFAR __ACCESS_CP15(c6, 0, c0, 0)
63#define IFAR __ACCESS_CP15(c6, 0, c0, 2)
Marc Zyngier1d58d2c2016-01-02 15:09:54 +000064#define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0)
65#define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0)
66#define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4)
Marc Zyngierc7ce6c62016-01-03 12:55:01 +000067#define PRRR __ACCESS_CP15(c10, 0, c2, 0)
68#define NMRR __ACCESS_CP15(c10, 0, c2, 1)
69#define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0)
70#define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1)
71#define VBAR __ACCESS_CP15(c12, 0, c0, 0)
72#define CID __ACCESS_CP15(c13, 0, c0, 1)
73#define TID_URW __ACCESS_CP15(c13, 0, c0, 2)
74#define TID_URO __ACCESS_CP15(c13, 0, c0, 3)
75#define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4)
76#define CNTKCTL __ACCESS_CP15(c14, 0, c1, 0)
Marc Zyngiere59bff9b2016-01-04 08:54:50 +000077#define CNTV_CTL __ACCESS_CP15(c14, 0, c3, 1)
78#define CNTHCTL __ACCESS_CP15(c14, 4, c1, 0)
79
80void __timer_save_state(struct kvm_vcpu *vcpu);
81void __timer_restore_state(struct kvm_vcpu *vcpu);
Marc Zyngierc7ce6c62016-01-03 12:55:01 +000082
Marc Zyngierc0c2cdb2016-01-04 09:06:11 +000083void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
84void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
85
Marc Zyngierc7ce6c62016-01-03 12:55:01 +000086void __sysreg_save_state(struct kvm_cpu_context *ctxt);
87void __sysreg_restore_state(struct kvm_cpu_context *ctxt);
Marc Zyngier1d58d2c2016-01-02 15:09:54 +000088
Marc Zyngier08dcbfd2015-10-21 10:09:49 +010089#endif /* __ARM_KVM_HYP_H__ */