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gerrit-public.fairphone.software / kernel / msm-5.4 / c538d20c7f437e56c5301357c492230d1d6d1b80 / . / arch / arm / plat-omap / include / plat / omap-serial.h
blob: 70e7738dd3a0babc1daef3002d1aa5276568061d [file] [log] [blame]
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __OMAP_SERIAL_H__
18#define __OMAP_SERIAL_H__
19
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]23#include <plat/mux.h>
24
Benoit Cousson374b8cf2010-12-09 14:24:17 +0000[diff] [blame]25#define DRIVER_NAME "omap_uart"
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]26
27/*
28 * Use tty device name as ttyO, [O -> OMAP]
29 * in bootargs we specify as console=ttyO0 if uart1
30 * is used as console uart.
31 */
32#define OMAP_SERIAL_NAME "ttyO"
33
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]34#define OMAP_MODE13X_SPEED 230400
35
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]36/* WER = 0x7F
37 * Enable module level wakeup in WER reg
38 */
39#define OMAP_UART_WER_MOD_WKUP 0X7F
40
41/* Enable XON/XOFF flow control on output */
42#define OMAP_UART_SW_TX 0x04
43
44/* Enable XON/XOFF flow control on input */
45#define OMAP_UART_SW_RX 0x04
46
47#define OMAP_UART_SYSC_RESET 0X07
48#define OMAP_UART_TCR_TRIG 0X0F
49#define OMAP_UART_SW_CLR 0XF0
50#define OMAP_UART_FIFO_CLR 0X06
51
52#define OMAP_UART_DMA_CH_FREE -1
53
54#define RX_TIMEOUT (3 * HZ)
55#define OMAP_MAX_HSUART_PORTS 4
56
57#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
58
59struct omap_uart_port_info {
60 bool dma_enabled; /* To specify DMA Mode */
61 unsigned int uartclk; /* UART clock rate */
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]62 upf_t flags; /* UPF_* flags */
63};
64
65struct uart_omap_dma {
66 u8 uart_dma_tx;
67 u8 uart_dma_rx;
68 int rx_dma_channel;
69 int tx_dma_channel;
70 dma_addr_t rx_buf_dma_phys;
71 dma_addr_t tx_buf_dma_phys;
72 unsigned int uart_base;
73 /*
74 * Buffer for rx dma.It is not required for tx because the buffer
75 * comes from port structure.
76 */
77 unsigned char *rx_buf;
78 unsigned int prev_rx_dma_pos;
79 int tx_buf_size;
80 int tx_dma_used;
81 int rx_dma_used;
82 spinlock_t tx_lock;
83 spinlock_t rx_lock;
84 /* timer to poll activity on rx dma */
85 struct timer_list rx_timer;
86 int rx_buf_size;
87 int rx_timeout;
88};
89
90struct uart_omap_port {
91 struct uart_port port;
92 struct uart_omap_dma uart_dma;
93 struct platform_device *pdev;
94
95 unsigned char ier;
96 unsigned char lcr;
97 unsigned char mcr;
98 unsigned char fcr;
99 unsigned char efr;
Govindraj.Rc538d202011-11-07 18:57:03 +0530[diff] [blame^]100 unsigned char dll;
101 unsigned char dlh;
102 unsigned char mdr1;
103 unsigned char scr;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]104
105 int use_dma;
106 /*
107 * Some bits in registers are cleared on a read, so they must
108 * be saved whenever the register is read but the bits will not
109 * be immediately processed.
110 */
111 unsigned int lsr_break_flag;
112 unsigned char msr_saved_flags;
113 char name[20];
114 unsigned long port_activity;
115};
116
117#endif /* __OMAP_SERIAL_H__ */