blob: f2e538aaddadc55d43c5463375c4de36ab37bc83 [file] [log] [blame]
Andy Shevchenko3d588f82014-09-23 17:18:11 +03001/*
2 * Driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
Andy Shevchenko2a52f6e2014-09-23 17:18:15 +03006 * Copyright (C) 2014 Intel Corporation
Andy Shevchenko3d588f82014-09-23 17:18:11 +03007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef _DMA_DW_H
13#define _DMA_DW_H
14
Andy Shevchenko2a52f6e2014-09-23 17:18:15 +030015#include <linux/clk.h>
16#include <linux/device.h>
Andy Shevchenko3d588f82014-09-23 17:18:11 +030017#include <linux/dmaengine.h>
18
Andy Shevchenko2a52f6e2014-09-23 17:18:15 +030019#include <linux/platform_data/dma-dw.h>
20
21struct dw_dma;
22
23/**
24 * struct dw_dma_chip - representation of DesignWare DMA controller hardware
25 * @dev: struct device of the DMA controller
26 * @irq: irq line
27 * @regs: memory mapped I/O space
28 * @clk: hclk clock
29 * @dw: struct dw_dma that is filed by dw_dma_probe()
Andy Shevchenko3a14c662016-04-27 14:15:40 +030030 * @pdata: pointer to platform data
Andy Shevchenko2a52f6e2014-09-23 17:18:15 +030031 */
32struct dw_dma_chip {
33 struct device *dev;
34 int irq;
35 void __iomem *regs;
36 struct clk *clk;
37 struct dw_dma *dw;
Andy Shevchenko3a14c662016-04-27 14:15:40 +030038
39 const struct dw_dma_platform_data *pdata;
Andy Shevchenko2a52f6e2014-09-23 17:18:15 +030040};
41
42/* Export to the platform drivers */
Andy Shevchenko3a14c662016-04-27 14:15:40 +030043int dw_dma_probe(struct dw_dma_chip *chip);
Andy Shevchenko2a52f6e2014-09-23 17:18:15 +030044int dw_dma_remove(struct dw_dma_chip *chip);
45
Andy Shevchenko3d588f82014-09-23 17:18:11 +030046/* DMA API extensions */
47struct dw_desc;
48
49struct dw_cyclic_desc {
50 struct dw_desc **desc;
51 unsigned long periods;
52 void (*period_callback)(void *param);
53 void *period_callback_param;
54};
55
56struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
57 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
58 enum dma_transfer_direction direction);
59void dw_dma_cyclic_free(struct dma_chan *chan);
60int dw_dma_cyclic_start(struct dma_chan *chan);
61void dw_dma_cyclic_stop(struct dma_chan *chan);
62
63dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
64
65dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
66
67#endif /* _DMA_DW_H */