blob: e79ccd6aada1a9acf10bb2860e76ddb444415d52 [file] [log] [blame]
Sam bobroff96d01612014-06-05 16:19:22 +10001/* Test context switching to see if the DSCR SPR is correctly preserved
2 * when within a transaction.
3 *
4 * Note: We assume that the DSCR has been left at the default value (0)
5 * for all CPUs.
6 *
7 * Method:
8 *
9 * Set a value into the DSCR.
10 *
11 * Start a transaction, and suspend it (*).
12 *
13 * Hard loop checking to see if the transaction has become doomed.
14 *
15 * Now that we *may* have been preempted, record the DSCR and TEXASR SPRS.
16 *
17 * If the abort was because of a context switch, check the DSCR value.
18 * Otherwise, try again.
19 *
20 * (*) If the transaction is not suspended we can't see the problem because
21 * the transaction abort handler will restore the DSCR to it's checkpointed
22 * value before we regain control.
23 */
24
25#include <inttypes.h>
26#include <stdio.h>
27#include <stdlib.h>
28#include <assert.h>
29#include <asm/tm.h>
30
Michael Ellermanaa83f3d2014-06-13 21:16:04 +100031#include "utils.h"
Michael Ellermanb319ee82015-12-02 16:00:04 +110032#include "tm.h"
Michael Ellermanaa83f3d2014-06-13 21:16:04 +100033
Sam bobroff96d01612014-06-05 16:19:22 +100034#define SPRN_DSCR 0x03
35
Michael Ellermanaa83f3d2014-06-13 21:16:04 +100036int test_body(void)
37{
Sam bobroff96d01612014-06-05 16:19:22 +100038 uint64_t rv, dscr1 = 1, dscr2, texasr;
39
Michael Ellermanb319ee82015-12-02 16:00:04 +110040 SKIP_IF(!have_htm());
41
Sam bobroff96d01612014-06-05 16:19:22 +100042 printf("Check DSCR TM context switch: ");
43 fflush(stdout);
44 for (;;) {
Sam bobroff96d01612014-06-05 16:19:22 +100045 asm __volatile__ (
46 /* set a known value into the DSCR */
47 "ld 3, %[dscr1];"
48 "mtspr %[sprn_dscr], 3;"
49
Michael Ellermanfe06fe82017-05-19 11:29:04 +100050 "li %[rv], 1;"
Sam bobroff96d01612014-06-05 16:19:22 +100051 /* start and suspend a transaction */
Rashmica Guptada3ddc32015-12-23 16:49:51 +110052 "tbegin.;"
Sam bobroff96d01612014-06-05 16:19:22 +100053 "beq 1f;"
Rashmica Guptada3ddc32015-12-23 16:49:51 +110054 "tsuspend.;"
Sam bobroff96d01612014-06-05 16:19:22 +100055
56 /* hard loop until the transaction becomes doomed */
57 "2: ;"
Rashmica Guptada3ddc32015-12-23 16:49:51 +110058 "tcheck 0;"
Sam bobroff96d01612014-06-05 16:19:22 +100059 "bc 4, 0, 2b;"
60
61 /* record DSCR and TEXASR */
62 "mfspr 3, %[sprn_dscr];"
63 "std 3, %[dscr2];"
64 "mfspr 3, %[sprn_texasr];"
65 "std 3, %[texasr];"
66
Rashmica Guptada3ddc32015-12-23 16:49:51 +110067 "tresume.;"
68 "tend.;"
Sam bobroff96d01612014-06-05 16:19:22 +100069 "li %[rv], 0;"
70 "1: ;"
71 : [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr)
72 : [dscr1]"m"(dscr1)
73 , [sprn_dscr]"i"(SPRN_DSCR), [sprn_texasr]"i"(SPRN_TEXASR)
74 : "memory", "r3"
75 );
76 assert(rv); /* make sure the transaction aborted */
77 if ((texasr >> 56) != TM_CAUSE_RESCHED) {
78 putchar('.');
79 fflush(stdout);
80 continue;
81 }
82 if (dscr2 != dscr1) {
83 printf(" FAIL\n");
Michael Ellermanaa83f3d2014-06-13 21:16:04 +100084 return 1;
Sam bobroff96d01612014-06-05 16:19:22 +100085 } else {
86 printf(" OK\n");
Michael Ellermanaa83f3d2014-06-13 21:16:04 +100087 return 0;
Sam bobroff96d01612014-06-05 16:19:22 +100088 }
89 }
90}
Michael Ellermanaa83f3d2014-06-13 21:16:04 +100091
92int main(void)
93{
94 return test_harness(test_body, "tm_resched_dscr");
95}