blob: 717625d003efe9fdc0e83f2bdf62ab88001b52dc [file] [log] [blame]
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +08001/*
2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +080011#include "skeleton.dtsi"
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +080012#include <dt-bindings/gpio/gpio.h>
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080013
14/ {
15 model = "Atmel AT91SAM9260 family SoC";
16 compatible = "atmel,at91sam9260";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 serial4 = &usart3;
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +080025 serial5 = &uart0;
26 serial6 = &uart1;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080027 gpio0 = &pioA;
28 gpio1 = &pioB;
29 gpio2 = &pioC;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020032 i2c0 = &i2c0;
Bo Shen099343c2012-11-07 11:41:41 +080033 ssc0 = &ssc0;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080034 };
35 cpus {
36 cpu@0 {
37 compatible = "arm,arm926ejs";
38 };
39 };
40
41 memory {
42 reg = <0x20000000 0x04000000>;
43 };
44
45 ahb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
51 apb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020058 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080059 compatible = "atmel,at91rm9200-aic";
60 interrupt-controller;
61 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080062 atmel,external-irqs = <29 30 31>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080063 };
64
65 ramc0: ramc@ffffea00 {
66 compatible = "atmel,at91sam9260-sdramc";
67 reg = <0xffffea00 0x200>;
68 };
69
70 pmc: pmc@fffffc00 {
71 compatible = "atmel,at91rm9200-pmc";
72 reg = <0xfffffc00 0x100>;
73 };
74
75 rstc@fffffd00 {
76 compatible = "atmel,at91sam9260-rstc";
77 reg = <0xfffffd00 0x10>;
78 };
79
80 shdwc@fffffd10 {
81 compatible = "atmel,at91sam9260-shdwc";
82 reg = <0xfffffd10 0x10>;
83 };
84
85 pit: timer@fffffd30 {
86 compatible = "atmel,at91sam9260-pit";
87 reg = <0xfffffd30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020088 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080089 };
90
91 tcb0: timer@fffa0000 {
92 compatible = "atmel,at91rm9200-tcb";
93 reg = <0xfffa0000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020094 interrupts = <17 4 0 18 4 0 19 4 0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080095 };
96
97 tcb1: timer@fffdc000 {
98 compatible = "atmel,at91rm9200-tcb";
99 reg = <0xfffdc000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200100 interrupts = <26 4 0 27 4 0 28 4 0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800101 };
102
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800103 pinctrl@fffff400 {
104 #address-cells = <1>;
105 #size-cells = <1>;
106 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
107 ranges = <0xfffff400 0xfffff400 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800108
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800109 atmel,mux-mask = <
110 /* A B */
111 0xffffffff 0xffc00c3b /* pioA */
112 0xffffffff 0x7fff3ccf /* pioB */
113 0xffffffff 0x007fffff /* pioC */
114 >;
115
116 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800117 dbgu {
118 pinctrl_dbgu: dbgu-0 {
119 atmel,pins =
120 <1 14 0x1 0x0 /* PB14 periph A */
121 1 15 0x1 0x1>; /* PB15 periph with pullup */
122 };
123 };
124
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800125 usart0 {
126 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800127 atmel,pins =
128 <1 4 0x1 0x0 /* PB4 periph A */
129 1 5 0x1 0x0>; /* PB5 periph A */
130 };
131
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800132 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800133 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800134 <1 26 0x1 0x0>; /* PB26 periph A */
135 };
136
137 pinctrl_usart0_cts: usart0_cts-0 {
138 atmel,pins =
139 <1 27 0x1 0x0>; /* PB27 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800140 };
141
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800142 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800143 atmel,pins =
144 <1 24 0x1 0x0 /* PB24 periph A */
145 1 22 0x1 0x0>; /* PB22 periph A */
146 };
147
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800148 pinctrl_usart0_dcd: usart0_dcd-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800149 atmel,pins =
150 <1 23 0x1 0x0>; /* PB23 periph A */
151 };
152
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800153 pinctrl_usart0_ri: usart0_ri-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800154 atmel,pins =
155 <1 25 0x1 0x0>; /* PB25 periph A */
156 };
157 };
158
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800159 usart1 {
160 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800161 atmel,pins =
Douglas Gilbertf10491f2013-04-04 18:19:55 +0200162 <1 6 0x1 0x1 /* PB6 periph A with pullup */
163 1 7 0x1 0x0>; /* PB7 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800164 };
165
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800166 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800167 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800168 <1 28 0x1 0x0>; /* PB28 periph A */
169 };
170
171 pinctrl_usart1_cts: usart1_cts-0 {
172 atmel,pins =
173 <1 29 0x1 0x0>; /* PB29 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800174 };
175 };
176
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800177 usart2 {
178 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800179 atmel,pins =
180 <1 8 0x1 0x1 /* PB8 periph A with pullup */
181 1 9 0x1 0x0>; /* PB9 periph A */
182 };
183
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800184 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800185 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800186 <0 4 0x1 0x0>; /* PA4 periph A */
187 };
188
189 pinctrl_usart2_cts: usart2_cts-0 {
190 atmel,pins =
191 <0 5 0x1 0x0>; /* PA5 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800192 };
193 };
194
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800195 usart3 {
196 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800197 atmel,pins =
Douglas Gilbertf10491f2013-04-04 18:19:55 +0200198 <1 10 0x1 0x1 /* PB10 periph A with pullup */
199 1 11 0x1 0x0>; /* PB11 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800200 };
201
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800202 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800203 atmel,pins =
Douglas Gilbertf10491f2013-04-04 18:19:55 +0200204 <2 8 0x2 0x0>; /* PC8 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800205 };
206
207 pinctrl_usart3_cts: usart3_cts-0 {
208 atmel,pins =
Douglas Gilbertf10491f2013-04-04 18:19:55 +0200209 <2 10 0x2 0x0>; /* PC10 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800210 };
211 };
212
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800213 uart0 {
214 pinctrl_uart0: uart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800215 atmel,pins =
216 <0 31 0x2 0x1 /* PA31 periph B with pullup */
217 0 30 0x2 0x0>; /* PA30 periph B */
218 };
219 };
220
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800221 uart1 {
222 pinctrl_uart1: uart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800223 atmel,pins =
Douglas Gilbertf10491f2013-04-04 18:19:55 +0200224 <1 12 0x1 0x1 /* PB12 periph A with pullup */
225 1 13 0x1 0x0>; /* PB13 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800226 };
227 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800228
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800229 nand {
230 pinctrl_nand: nand-0 {
231 atmel,pins =
232 <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
233 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
234 };
235 };
236
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800237 macb {
238 pinctrl_macb_rmii: macb_rmii-0 {
239 atmel,pins =
240 <0 12 0x1 0x0 /* PA12 periph A */
241 0 13 0x1 0x0 /* PA13 periph A */
242 0 14 0x1 0x0 /* PA14 periph A */
243 0 15 0x1 0x0 /* PA15 periph A */
244 0 16 0x1 0x0 /* PA16 periph A */
245 0 17 0x1 0x0 /* PA17 periph A */
246 0 18 0x1 0x0 /* PA18 periph A */
247 0 19 0x1 0x0 /* PA19 periph A */
248 0 20 0x1 0x0 /* PA20 periph A */
249 0 21 0x1 0x0>; /* PA21 periph A */
250 };
251
252 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
253 atmel,pins =
254 <0 22 0x2 0x0 /* PA22 periph B */
255 0 23 0x2 0x0 /* PA23 periph B */
256 0 24 0x2 0x0 /* PA24 periph B */
257 0 25 0x2 0x0 /* PA25 periph B */
258 0 26 0x2 0x0 /* PA26 periph B */
259 0 27 0x2 0x0 /* PA27 periph B */
260 0 28 0x2 0x0 /* PA28 periph B */
261 0 29 0x2 0x0>; /* PA29 periph B */
262 };
263
264 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
265 atmel,pins =
266 <0 10 0x2 0x0 /* PA10 periph B */
267 0 11 0x2 0x0 /* PA11 periph B */
268 0 24 0x2 0x0 /* PA24 periph B */
269 0 25 0x2 0x0 /* PA25 periph B */
270 0 26 0x2 0x0 /* PA26 periph B */
271 0 27 0x2 0x0 /* PA27 periph B */
272 0 28 0x2 0x0 /* PA28 periph B */
273 0 29 0x2 0x0>; /* PA29 periph B */
274 };
275 };
276
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800277 mmc0 {
278 pinctrl_mmc0_clk: mmc0_clk-0 {
279 atmel,pins =
280 <0 8 0x1 0x0>; /* PA8 periph A */
281 };
282
283 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
284 atmel,pins =
285 <0 7 0x1 0x1 /* PA7 periph A with pullup */
286 0 6 0x1 0x1>; /* PA6 periph A with pullup */
287 };
288
289 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
290 atmel,pins =
291 <0 9 0x1 0x1 /* PA9 periph A with pullup */
292 0 10 0x1 0x1 /* PA10 periph A with pullup */
293 0 11 0x1 0x1>; /* PA11 periph A with pullup */
294 };
295
296 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
297 atmel,pins =
298 <0 1 0x2 0x1 /* PA1 periph B with pullup */
299 0 0 0x2 0x1>; /* PA0 periph B with pullup */
300 };
301
302 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
303 atmel,pins =
304 <0 5 0x2 0x1 /* PA5 periph B with pullup */
305 0 4 0x2 0x1 /* PA4 periph B with pullup */
306 0 3 0x2 0x1>; /* PA3 periph B with pullup */
307 };
308 };
309
Bo Shen544ae6b2013-01-11 15:08:30 +0100310 ssc0 {
311 pinctrl_ssc0_tx: ssc0_tx-0 {
312 atmel,pins =
313 <1 16 0x1 0x0 /* PB16 periph A */
314 1 17 0x1 0x0 /* PB17 periph A */
315 1 18 0x1 0x0>; /* PB18 periph A */
316 };
317
318 pinctrl_ssc0_rx: ssc0_rx-0 {
319 atmel,pins =
320 <1 19 0x1 0x0 /* PB19 periph A */
321 1 20 0x1 0x0 /* PB20 periph A */
322 1 21 0x1 0x0>; /* PB21 periph A */
323 };
324 };
325
Wenyou Yanga68b7282013-04-03 14:03:52 +0800326 spi0 {
327 pinctrl_spi0: spi0-0 {
328 atmel,pins =
329 <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */
330 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */
331 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */
332 };
333 };
334
335 spi1 {
336 pinctrl_spi1: spi1-0 {
337 atmel,pins =
338 <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */
339 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */
340 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */
341 };
342 };
343
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800344 pioA: gpio@fffff400 {
345 compatible = "atmel,at91rm9200-gpio";
346 reg = <0xfffff400 0x200>;
347 interrupts = <2 4 1>;
348 #gpio-cells = <2>;
349 gpio-controller;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800353
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800354 pioB: gpio@fffff600 {
355 compatible = "atmel,at91rm9200-gpio";
356 reg = <0xfffff600 0x200>;
357 interrupts = <3 4 1>;
358 #gpio-cells = <2>;
359 gpio-controller;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 };
363
364 pioC: gpio@fffff800 {
365 compatible = "atmel,at91rm9200-gpio";
366 reg = <0xfffff800 0x200>;
367 interrupts = <4 4 1>;
368 #gpio-cells = <2>;
369 gpio-controller;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800373 };
374
375 dbgu: serial@fffff200 {
376 compatible = "atmel,at91sam9260-usart";
377 reg = <0xfffff200 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200378 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800381 status = "disabled";
382 };
383
384 usart0: serial@fffb0000 {
385 compatible = "atmel,at91sam9260-usart";
386 reg = <0xfffb0000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200387 interrupts = <6 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800388 atmel,use-dma-rx;
389 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800390 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800391 pinctrl-0 = <&pinctrl_usart0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800392 status = "disabled";
393 };
394
395 usart1: serial@fffb4000 {
396 compatible = "atmel,at91sam9260-usart";
397 reg = <0xfffb4000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200398 interrupts = <7 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800399 atmel,use-dma-rx;
400 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800401 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800402 pinctrl-0 = <&pinctrl_usart1>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800403 status = "disabled";
404 };
405
406 usart2: serial@fffb8000 {
407 compatible = "atmel,at91sam9260-usart";
408 reg = <0xfffb8000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200409 interrupts = <8 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800410 atmel,use-dma-rx;
411 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800412 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800413 pinctrl-0 = <&pinctrl_usart2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800414 status = "disabled";
415 };
416
417 usart3: serial@fffd0000 {
418 compatible = "atmel,at91sam9260-usart";
419 reg = <0xfffd0000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200420 interrupts = <23 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800421 atmel,use-dma-rx;
422 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800423 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800424 pinctrl-0 = <&pinctrl_usart3>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800425 status = "disabled";
426 };
427
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800428 uart0: serial@fffd4000 {
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800429 compatible = "atmel,at91sam9260-usart";
430 reg = <0xfffd4000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200431 interrupts = <24 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800432 atmel,use-dma-rx;
433 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800434 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800435 pinctrl-0 = <&pinctrl_uart0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800436 status = "disabled";
437 };
438
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800439 uart1: serial@fffd8000 {
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800440 compatible = "atmel,at91sam9260-usart";
441 reg = <0xfffd8000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200442 interrupts = <25 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800443 atmel,use-dma-rx;
444 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800445 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800446 pinctrl-0 = <&pinctrl_uart1>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800447 status = "disabled";
448 };
449
450 macb0: ethernet@fffc4000 {
451 compatible = "cdns,at32ap7000-macb", "cdns,macb";
452 reg = <0xfffc4000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200453 interrupts = <21 4 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_macb_rmii>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800456 status = "disabled";
457 };
458
459 usb1: gadget@fffa4000 {
460 compatible = "atmel,at91rm9200-udc";
461 reg = <0xfffa4000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200462 interrupts = <10 4 2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800463 status = "disabled";
464 };
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200465
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200466 i2c0: i2c@fffac000 {
467 compatible = "atmel,at91sam9260-i2c";
468 reg = <0xfffac000 0x100>;
469 interrupts = <11 4 6>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 status = "disabled";
473 };
474
Ludovic Desroches98731372012-11-19 12:23:36 +0100475 mmc0: mmc@fffa8000 {
476 compatible = "atmel,hsmci";
477 reg = <0xfffa8000 0x600>;
478 interrupts = <9 4 0>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 status = "disabled";
482 };
483
Bo Shen099343c2012-11-07 11:41:41 +0800484 ssc0: ssc@fffbc000 {
485 compatible = "atmel,at91rm9200-ssc";
486 reg = <0xfffbc000 0x4000>;
487 interrupts = <14 4 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
Linus Torvalds046e7d62012-12-13 11:51:23 -0800490 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800491 };
492
Richard Genoudd50f88a2013-04-03 14:02:18 +0800493 spi0: spi@fffc8000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "atmel,at91rm9200-spi";
497 reg = <0xfffc8000 0x200>;
498 interrupts = <12 4 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_spi0>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800501 status = "disabled";
502 };
503
504 spi1: spi@fffcc000 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "atmel,at91rm9200-spi";
508 reg = <0xfffcc000 0x200>;
509 interrupts = <13 4 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_spi1>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800512 status = "disabled";
513 };
514
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200515 adc0: adc@fffe0000 {
516 compatible = "atmel,at91sam9260-adc";
517 reg = <0xfffe0000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200518 interrupts = <5 4 0>;
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200519 atmel,adc-use-external-triggers;
520 atmel,adc-channels-used = <0xf>;
521 atmel,adc-vref = <3300>;
522 atmel,adc-num-channels = <4>;
523 atmel,adc-startup-time = <15>;
524 atmel,adc-channel-base = <0x30>;
525 atmel,adc-drdy-mask = <0x10000>;
526 atmel,adc-status-register = <0x1c>;
527 atmel,adc-trigger-register = <0x04>;
Ludovic Desroches4b50da652013-03-29 10:13:19 +0100528 atmel,adc-res = <8 10>;
529 atmel,adc-res-names = "lowres", "highres";
530 atmel,adc-use-res = "highres";
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200531
532 trigger@0 {
533 trigger-name = "timer-counter-0";
534 trigger-value = <0x1>;
535 };
536 trigger@1 {
537 trigger-name = "timer-counter-1";
538 trigger-value = <0x3>;
539 };
540
541 trigger@2 {
542 trigger-name = "timer-counter-2";
543 trigger-value = <0x5>;
544 };
545
546 trigger@3 {
547 trigger-name = "external";
548 trigger-value = <0x13>;
549 trigger-external;
550 };
551 };
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100552
553 watchdog@fffffd40 {
554 compatible = "atmel,at91sam9260-wdt";
555 reg = <0xfffffd40 0x10>;
556 status = "disabled";
557 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800558 };
559
560 nand0: nand@40000000 {
561 compatible = "atmel,at91rm9200-nand";
562 #address-cells = <1>;
563 #size-cells = <1>;
564 reg = <0x40000000 0x10000000
565 0xffffe800 0x200
566 >;
567 atmel,nand-addr-offset = <21>;
568 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800571 gpios = <&pioC 13 GPIO_ACTIVE_HIGH
572 &pioC 14 GPIO_ACTIVE_HIGH
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800573 0
574 >;
575 status = "disabled";
576 };
577
578 usb0: ohci@00500000 {
579 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
580 reg = <0x00500000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200581 interrupts = <20 4 2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800582 status = "disabled";
583 };
584 };
585
586 i2c@0 {
587 compatible = "i2c-gpio";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800588 gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
589 &pioA 24 GPIO_ACTIVE_HIGH /* scl */
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800590 >;
591 i2c-gpio,sda-open-drain;
592 i2c-gpio,scl-open-drain;
593 i2c-gpio,delay-us = <2>; /* ~100 kHz */
594 #address-cells = <1>;
595 #size-cells = <0>;
596 status = "disabled";
597 };
598};