Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 1 | /* |
| 2 | * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Atmel, |
| 5 | * 2012 Hong Xu <hong.xu@atmel.com> |
| 6 | * |
| 7 | * Licensed under GPLv2 or later. |
| 8 | */ |
| 9 | |
Jean-Christophe PLAGNIOL-VILLARD | 6db64d2 | 2013-05-15 01:21:50 +0800 | [diff] [blame] | 10 | #include "skeleton.dtsi" |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 11 | #include <dt-bindings/pinctrl/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 12 | #include <dt-bindings/gpio/gpio.h> |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 13 | |
| 14 | / { |
| 15 | model = "Atmel AT91SAM9N12 SoC"; |
| 16 | compatible = "atmel,at91sam9n12"; |
| 17 | interrupt-parent = <&aic>; |
| 18 | |
| 19 | aliases { |
| 20 | serial0 = &dbgu; |
| 21 | serial1 = &usart0; |
| 22 | serial2 = &usart1; |
| 23 | serial3 = &usart2; |
| 24 | serial4 = &usart3; |
| 25 | gpio0 = &pioA; |
| 26 | gpio1 = &pioB; |
| 27 | gpio2 = &pioC; |
| 28 | gpio3 = &pioD; |
| 29 | tcb0 = &tcb0; |
| 30 | tcb1 = &tcb1; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 31 | i2c0 = &i2c0; |
| 32 | i2c1 = &i2c1; |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 33 | ssc0 = &ssc0; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 34 | }; |
| 35 | cpus { |
| 36 | cpu@0 { |
| 37 | compatible = "arm,arm926ejs"; |
| 38 | }; |
| 39 | }; |
| 40 | |
| 41 | memory { |
| 42 | reg = <0x20000000 0x10000000>; |
| 43 | }; |
| 44 | |
| 45 | ahb { |
| 46 | compatible = "simple-bus"; |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <1>; |
| 49 | ranges; |
| 50 | |
| 51 | apb { |
| 52 | compatible = "simple-bus"; |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <1>; |
| 55 | ranges; |
| 56 | |
| 57 | aic: interrupt-controller@fffff000 { |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 58 | #interrupt-cells = <3>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 59 | compatible = "atmel,at91rm9200-aic"; |
| 60 | interrupt-controller; |
| 61 | reg = <0xfffff000 0x200>; |
| 62 | }; |
| 63 | |
| 64 | ramc0: ramc@ffffe800 { |
| 65 | compatible = "atmel,at91sam9g45-ddramc"; |
| 66 | reg = <0xffffe800 0x200>; |
| 67 | }; |
| 68 | |
| 69 | pmc: pmc@fffffc00 { |
| 70 | compatible = "atmel,at91rm9200-pmc"; |
| 71 | reg = <0xfffffc00 0x100>; |
| 72 | }; |
| 73 | |
| 74 | rstc@fffffe00 { |
| 75 | compatible = "atmel,at91sam9g45-rstc"; |
| 76 | reg = <0xfffffe00 0x10>; |
| 77 | }; |
| 78 | |
| 79 | pit: timer@fffffe30 { |
| 80 | compatible = "atmel,at91sam9260-pit"; |
| 81 | reg = <0xfffffe30 0xf>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 82 | interrupts = <1 4 7>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 83 | }; |
| 84 | |
| 85 | shdwc@fffffe10 { |
| 86 | compatible = "atmel,at91sam9x5-shdwc"; |
| 87 | reg = <0xfffffe10 0x10>; |
| 88 | }; |
| 89 | |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 90 | mmc0: mmc@f0008000 { |
| 91 | compatible = "atmel,hsmci"; |
| 92 | reg = <0xf0008000 0x600>; |
| 93 | interrupts = <12 4 0>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 94 | dmas = <&dma 1 0>; |
| 95 | dma-names = "rxtx"; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 96 | #address-cells = <1>; |
| 97 | #size-cells = <0>; |
| 98 | status = "disabled"; |
| 99 | }; |
| 100 | |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 101 | tcb0: timer@f8008000 { |
| 102 | compatible = "atmel,at91sam9x5-tcb"; |
| 103 | reg = <0xf8008000 0x100>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 104 | interrupts = <17 4 0>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 105 | }; |
| 106 | |
| 107 | tcb1: timer@f800c000 { |
| 108 | compatible = "atmel,at91sam9x5-tcb"; |
| 109 | reg = <0xf800c000 0x100>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 110 | interrupts = <17 4 0>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 111 | }; |
| 112 | |
| 113 | dma: dma-controller@ffffec00 { |
| 114 | compatible = "atmel,at91sam9g45-dma"; |
| 115 | reg = <0xffffec00 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 116 | interrupts = <20 4 0>; |
Ludovic Desroches | 980ce7d | 2013-04-16 15:03:06 +0200 | [diff] [blame] | 117 | #dma-cells = <2>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 118 | }; |
| 119 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 120 | pinctrl@fffff400 { |
| 121 | #address-cells = <1>; |
| 122 | #size-cells = <1>; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 123 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 124 | ranges = <0xfffff400 0xfffff400 0x800>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 126 | atmel,mux-mask = < |
| 127 | /* A B C */ |
| 128 | 0xffffffff 0xffe07983 0x00000000 /* pioA */ |
| 129 | 0x00040000 0x00047e0f 0x00000000 /* pioB */ |
| 130 | 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ |
| 131 | 0x003fffff 0x003f8000 0x00000000 /* pioD */ |
| 132 | >; |
| 133 | |
| 134 | /* shared pinctrl settings */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 135 | dbgu { |
| 136 | pinctrl_dbgu: dbgu-0 { |
| 137 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 138 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ |
| 139 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 140 | }; |
| 141 | }; |
| 142 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 143 | usart0 { |
| 144 | pinctrl_usart0: usart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 145 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 146 | <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| 147 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 148 | }; |
| 149 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 150 | pinctrl_usart0_rts: usart0_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 151 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 152 | <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 153 | }; |
| 154 | |
| 155 | pinctrl_usart0_cts: usart0_cts-0 { |
| 156 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 157 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 158 | }; |
| 159 | }; |
| 160 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 161 | usart1 { |
| 162 | pinctrl_usart1: usart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 163 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 164 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ |
| 165 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 166 | }; |
| 167 | }; |
| 168 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 169 | usart2 { |
| 170 | pinctrl_usart2: usart2-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 171 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 172 | <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ |
| 173 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 174 | }; |
| 175 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 176 | pinctrl_usart2_rts: usart2_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 177 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 178 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | pinctrl_usart2_cts: usart2_cts-0 { |
| 182 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 183 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 184 | }; |
| 185 | }; |
| 186 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 187 | usart3 { |
| 188 | pinctrl_usart3: usart3-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 189 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 190 | <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ |
| 191 | AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 192 | }; |
| 193 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 194 | pinctrl_usart3_rts: usart3_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 195 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 196 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 197 | }; |
| 198 | |
| 199 | pinctrl_usart3_cts: usart3_cts-0 { |
| 200 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 201 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 202 | }; |
| 203 | }; |
| 204 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 205 | uart0 { |
| 206 | pinctrl_uart0: uart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 207 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 208 | <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ |
| 209 | AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 210 | }; |
| 211 | }; |
| 212 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 213 | uart1 { |
| 214 | pinctrl_uart1: uart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 215 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 216 | <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ |
| 217 | AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 218 | }; |
| 219 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 220 | |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 221 | nand { |
| 222 | pinctrl_nand: nand-0 { |
| 223 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 224 | <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ |
| 225 | AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 226 | }; |
| 227 | }; |
| 228 | |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 229 | mmc0 { |
| 230 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 231 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 232 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 233 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
| 234 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 235 | }; |
| 236 | |
| 237 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 238 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 239 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| 240 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ |
| 241 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 242 | }; |
| 243 | |
| 244 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { |
| 245 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 246 | <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ |
| 247 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ |
| 248 | AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ |
| 249 | AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 250 | }; |
| 251 | }; |
| 252 | |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 253 | ssc0 { |
| 254 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 255 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 256 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 257 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 258 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 262 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 263 | <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 264 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 265 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 266 | }; |
| 267 | }; |
| 268 | |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 269 | spi0 { |
| 270 | pinctrl_spi0: spi0-0 { |
| 271 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 272 | <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ |
| 273 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ |
| 274 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 275 | }; |
| 276 | }; |
| 277 | |
| 278 | spi1 { |
| 279 | pinctrl_spi1: spi1-0 { |
| 280 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame^] | 281 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ |
| 282 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ |
| 283 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 284 | }; |
| 285 | }; |
| 286 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 287 | pioA: gpio@fffff400 { |
| 288 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 289 | reg = <0xfffff400 0x200>; |
| 290 | interrupts = <2 4 1>; |
| 291 | #gpio-cells = <2>; |
| 292 | gpio-controller; |
| 293 | interrupt-controller; |
| 294 | #interrupt-cells = <2>; |
| 295 | }; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 296 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 297 | pioB: gpio@fffff600 { |
| 298 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 299 | reg = <0xfffff600 0x200>; |
| 300 | interrupts = <2 4 1>; |
| 301 | #gpio-cells = <2>; |
| 302 | gpio-controller; |
| 303 | interrupt-controller; |
| 304 | #interrupt-cells = <2>; |
| 305 | }; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 306 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 307 | pioC: gpio@fffff800 { |
| 308 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 309 | reg = <0xfffff800 0x200>; |
| 310 | interrupts = <3 4 1>; |
| 311 | #gpio-cells = <2>; |
| 312 | gpio-controller; |
| 313 | interrupt-controller; |
| 314 | #interrupt-cells = <2>; |
| 315 | }; |
| 316 | |
| 317 | pioD: gpio@fffffa00 { |
| 318 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 319 | reg = <0xfffffa00 0x200>; |
| 320 | interrupts = <3 4 1>; |
| 321 | #gpio-cells = <2>; |
| 322 | gpio-controller; |
| 323 | interrupt-controller; |
| 324 | #interrupt-cells = <2>; |
| 325 | }; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 326 | }; |
| 327 | |
| 328 | dbgu: serial@fffff200 { |
| 329 | compatible = "atmel,at91sam9260-usart"; |
| 330 | reg = <0xfffff200 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 331 | interrupts = <1 4 7>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 332 | pinctrl-names = "default"; |
| 333 | pinctrl-0 = <&pinctrl_dbgu>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 334 | status = "disabled"; |
| 335 | }; |
| 336 | |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 337 | ssc0: ssc@f0010000 { |
| 338 | compatible = "atmel,at91sam9g45-ssc"; |
| 339 | reg = <0xf0010000 0x4000>; |
| 340 | interrupts = <28 4 5>; |
| 341 | pinctrl-names = "default"; |
| 342 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 343 | status = "disabled"; |
| 344 | }; |
| 345 | |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 346 | usart0: serial@f801c000 { |
| 347 | compatible = "atmel,at91sam9260-usart"; |
| 348 | reg = <0xf801c000 0x4000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 349 | interrupts = <5 4 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 350 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 351 | pinctrl-0 = <&pinctrl_usart0>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 352 | status = "disabled"; |
| 353 | }; |
| 354 | |
| 355 | usart1: serial@f8020000 { |
| 356 | compatible = "atmel,at91sam9260-usart"; |
| 357 | reg = <0xf8020000 0x4000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 358 | interrupts = <6 4 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 359 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 360 | pinctrl-0 = <&pinctrl_usart1>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 361 | status = "disabled"; |
| 362 | }; |
| 363 | |
| 364 | usart2: serial@f8024000 { |
| 365 | compatible = "atmel,at91sam9260-usart"; |
| 366 | reg = <0xf8024000 0x4000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 367 | interrupts = <7 4 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 368 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 369 | pinctrl-0 = <&pinctrl_usart2>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 370 | status = "disabled"; |
| 371 | }; |
| 372 | |
| 373 | usart3: serial@f8028000 { |
| 374 | compatible = "atmel,at91sam9260-usart"; |
| 375 | reg = <0xf8028000 0x4000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 376 | interrupts = <8 4 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 377 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 378 | pinctrl-0 = <&pinctrl_usart3>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 379 | status = "disabled"; |
| 380 | }; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 381 | |
| 382 | i2c0: i2c@f8010000 { |
| 383 | compatible = "atmel,at91sam9x5-i2c"; |
| 384 | reg = <0xf8010000 0x100>; |
| 385 | interrupts = <9 4 6>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 386 | dmas = <&dma 1 13>, |
| 387 | <&dma 1 14>; |
| 388 | dma-names = "tx", "rx"; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 389 | #address-cells = <1>; |
| 390 | #size-cells = <0>; |
| 391 | status = "disabled"; |
| 392 | }; |
| 393 | |
| 394 | i2c1: i2c@f8014000 { |
| 395 | compatible = "atmel,at91sam9x5-i2c"; |
| 396 | reg = <0xf8014000 0x100>; |
| 397 | interrupts = <10 4 6>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 398 | dmas = <&dma 1 15>, |
| 399 | <&dma 1 16>; |
| 400 | dma-names = "tx", "rx"; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 401 | #address-cells = <1>; |
| 402 | #size-cells = <0>; |
| 403 | status = "disabled"; |
| 404 | }; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 405 | |
| 406 | spi0: spi@f0000000 { |
| 407 | #address-cells = <1>; |
| 408 | #size-cells = <0>; |
| 409 | compatible = "atmel,at91rm9200-spi"; |
| 410 | reg = <0xf0000000 0x100>; |
| 411 | interrupts = <13 4 3>; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 412 | pinctrl-names = "default"; |
| 413 | pinctrl-0 = <&pinctrl_spi0>; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 414 | status = "disabled"; |
| 415 | }; |
| 416 | |
| 417 | spi1: spi@f0004000 { |
| 418 | #address-cells = <1>; |
| 419 | #size-cells = <0>; |
| 420 | compatible = "atmel,at91rm9200-spi"; |
| 421 | reg = <0xf0004000 0x100>; |
| 422 | interrupts = <14 4 3>; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 423 | pinctrl-names = "default"; |
| 424 | pinctrl-0 = <&pinctrl_spi1>; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 425 | status = "disabled"; |
| 426 | }; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 427 | }; |
| 428 | |
| 429 | nand0: nand@40000000 { |
| 430 | compatible = "atmel,at91rm9200-nand"; |
| 431 | #address-cells = <1>; |
| 432 | #size-cells = <1>; |
| 433 | reg = < 0x40000000 0x10000000 |
| 434 | 0xffffe000 0x00000600 |
| 435 | 0xffffe600 0x00000200 |
Josh Wu | c18c6b2 | 2013-01-23 20:47:10 +0800 | [diff] [blame] | 436 | 0x00108000 0x00018000 |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 437 | >; |
Josh Wu | c18c6b2 | 2013-01-23 20:47:10 +0800 | [diff] [blame] | 438 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 439 | atmel,nand-addr-offset = <21>; |
| 440 | atmel,nand-cmd-offset = <22>; |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 441 | pinctrl-names = "default"; |
| 442 | pinctrl-0 = <&pinctrl_nand>; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 443 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
| 444 | &pioD 4 GPIO_ACTIVE_HIGH |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 445 | 0 |
| 446 | >; |
| 447 | status = "disabled"; |
| 448 | }; |
| 449 | |
| 450 | usb0: ohci@00500000 { |
| 451 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 452 | reg = <0x00500000 0x00100000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 453 | interrupts = <22 4 2>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 454 | status = "disabled"; |
| 455 | }; |
| 456 | }; |
| 457 | |
| 458 | i2c@0 { |
| 459 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 460 | gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ |
| 461 | &pioA 31 GPIO_ACTIVE_HIGH /* scl */ |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 462 | >; |
| 463 | i2c-gpio,sda-open-drain; |
| 464 | i2c-gpio,scl-open-drain; |
| 465 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 466 | #address-cells = <1>; |
| 467 | #size-cells = <0>; |
| 468 | status = "disabled"; |
| 469 | }; |
| 470 | }; |