| Geoff Levand | 9065762 | 2007-06-16 08:06:51 +1000 | [diff] [blame] | 1 | /* |
| 2 | * PS3 Game Console device tree. |
| 3 | * |
| 4 | * Copyright (C) 2007 Sony Computer Entertainment Inc. |
| 5 | * Copyright 2007 Sony Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | / { |
| 22 | model = "SonyPS3"; |
| 23 | compatible = "sony,ps3"; |
| 24 | #size-cells = <2>; |
| 25 | #address-cells = <2>; |
| 26 | |
| 27 | chosen { |
| 28 | }; |
| 29 | |
| 30 | /* |
| 31 | * We'll get the size of the bootmem block from lv1 after startup, |
| 32 | * so we'll put a null entry here. |
| 33 | */ |
| 34 | |
| 35 | memory { |
| 36 | device_type = "memory"; |
| 37 | reg = <0 0 0 0>; |
| 38 | }; |
| 39 | |
| 40 | /* |
| 41 | * The boot cpu is always zero for PS3. |
| 42 | * |
| 43 | * dtc expects a clock-frequency and timebase-frequency entries, so |
| 44 | * we'll put a null entries here. These will be initialized after |
| 45 | * startup with data from lv1. |
| 46 | * |
| 47 | * Seems the only way currently to indicate a processor has multiple |
| 48 | * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one |
| 49 | * here so we can bring up both of ours. See smp_setup_cpu_maps(). |
| 50 | */ |
| 51 | |
| 52 | cpus { |
| 53 | #size-cells = <0>; |
| 54 | #address-cells = <1>; |
| 55 | |
| 56 | cpu@0 { |
| 57 | device_type = "cpu"; |
| 58 | reg = <0>; |
| 59 | ibm,ppc-interrupt-server#s = <0 1>; |
| 60 | clock-frequency = <0>; |
| 61 | timebase-frequency = <0>; |
| 62 | i-cache-size = <8000>; |
| 63 | d-cache-size = <8000>; |
| 64 | i-cache-line-size = <80>; |
| 65 | d-cache-line-size = <80>; |
| 66 | }; |
| 67 | }; |
| 68 | }; |