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Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030031 */
32
Yuval Mintz36558c32016-05-11 16:36:17 +030033#include <linux/crc32.h>
Yuval Mintzeff16962016-05-11 16:36:21 +030034#include <linux/etherdevice.h>
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030035#include "qed.h"
36#include "qed_sriov.h"
37#include "qed_vf.h"
38
39static void *qed_vf_pf_prep(struct qed_hwfn *p_hwfn, u16 type, u16 length)
40{
41 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
42 void *p_tlv;
43
44 /* This lock is released when we receive PF's response
45 * in qed_send_msg2pf().
46 * So, qed_vf_pf_prep() and qed_send_msg2pf()
47 * must come in sequence.
48 */
49 mutex_lock(&(p_iov->mutex));
50
51 DP_VERBOSE(p_hwfn,
52 QED_MSG_IOV,
53 "preparing to send 0x%04x tlv over vf pf channel\n",
54 type);
55
56 /* Reset Requst offset */
57 p_iov->offset = (u8 *)p_iov->vf2pf_request;
58
59 /* Clear mailbox - both request and reply */
60 memset(p_iov->vf2pf_request, 0, sizeof(union vfpf_tlvs));
61 memset(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs));
62
63 /* Init type and length */
64 p_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, type, length);
65
66 /* Init first tlv header */
67 ((struct vfpf_first_tlv *)p_tlv)->reply_address =
68 (u64)p_iov->pf2vf_reply_phys;
69
70 return p_tlv;
71}
72
Yuval Mintzb0bccb62016-08-22 13:25:12 +030073static void qed_vf_pf_req_end(struct qed_hwfn *p_hwfn, int req_status)
74{
75 union pfvf_tlvs *resp = p_hwfn->vf_iov_info->pf2vf_reply;
76
77 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
78 "VF request status = 0x%x, PF reply status = 0x%x\n",
79 req_status, resp->default_resp.hdr.status);
80
81 mutex_unlock(&(p_hwfn->vf_iov_info->mutex));
82}
83
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030084static int qed_send_msg2pf(struct qed_hwfn *p_hwfn, u8 *done, u32 resp_size)
85{
86 union vfpf_tlvs *p_req = p_hwfn->vf_iov_info->vf2pf_request;
87 struct ustorm_trigger_vf_zone trigger;
88 struct ustorm_vf_zone *zone_data;
89 int rc = 0, time = 100;
90
91 zone_data = (struct ustorm_vf_zone *)PXP_VF_BAR0_START_USDM_ZONE_B;
92
93 /* output tlvs list */
94 qed_dp_tlv_list(p_hwfn, p_req);
95
96 /* need to add the END TLV to the message size */
97 resp_size += sizeof(struct channel_list_end_tlv);
98
99 /* Send TLVs over HW channel */
100 memset(&trigger, 0, sizeof(struct ustorm_trigger_vf_zone));
101 trigger.vf_pf_msg_valid = 1;
102
103 DP_VERBOSE(p_hwfn,
104 QED_MSG_IOV,
105 "VF -> PF [%02x] message: [%08x, %08x] --> %p, %08x --> %p\n",
106 GET_FIELD(p_hwfn->hw_info.concrete_fid,
107 PXP_CONCRETE_FID_PFID),
108 upper_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys),
109 lower_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys),
110 &zone_data->non_trigger.vf_pf_msg_addr,
111 *((u32 *)&trigger), &zone_data->trigger);
112
113 REG_WR(p_hwfn,
114 (uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.lo,
115 lower_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys));
116
117 REG_WR(p_hwfn,
118 (uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.hi,
119 upper_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys));
120
121 /* The message data must be written first, to prevent trigger before
122 * data is written.
123 */
124 wmb();
125
126 REG_WR(p_hwfn, (uintptr_t)&zone_data->trigger, *((u32 *)&trigger));
127
128 /* When PF would be done with the response, it would write back to the
129 * `done' address. Poll until then.
130 */
131 while ((!*done) && time) {
132 msleep(25);
133 time--;
134 }
135
136 if (!*done) {
Mintz, Yuval81e64ef2017-03-19 13:08:12 +0200137 DP_NOTICE(p_hwfn,
138 "VF <-- PF Timeout [Type %d]\n",
139 p_req->first_tlv.tl.type);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300140 rc = -EBUSY;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300141 } else {
Mintz, Yuval81e64ef2017-03-19 13:08:12 +0200142 if ((*done != PFVF_STATUS_SUCCESS) &&
143 (*done != PFVF_STATUS_NO_RESOURCE))
144 DP_NOTICE(p_hwfn,
145 "PF response: %d [Type %d]\n",
146 *done, p_req->first_tlv.tl.type);
147 else
148 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
149 "PF response: %d [Type %d]\n",
150 *done, p_req->first_tlv.tl.type);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300151 }
152
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300153 return rc;
154}
155
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300156static void qed_vf_pf_add_qid(struct qed_hwfn *p_hwfn,
157 struct qed_queue_cid *p_cid)
158{
159 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
160 struct vfpf_qid_tlv *p_qid_tlv;
161
162 /* Only add QIDs for the queue if it was negotiated with PF */
163 if (!(p_iov->acquire_resp.pfdev_info.capabilities &
164 PFVF_ACQUIRE_CAP_QUEUE_QIDS))
165 return;
166
167 p_qid_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
168 CHANNEL_TLV_QID, sizeof(*p_qid_tlv));
169 p_qid_tlv->qid = p_cid->qid_usage_idx;
170}
171
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300172int _qed_vf_pf_release(struct qed_hwfn *p_hwfn, bool b_final)
173{
174 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
175 struct pfvf_def_resp_tlv *resp;
176 struct vfpf_first_tlv *req;
177 u32 size;
178 int rc;
179
180 /* clear mailbox and prep first tlv */
181 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_RELEASE, sizeof(*req));
182
183 /* add list termination tlv */
184 qed_add_tlv(p_hwfn, &p_iov->offset,
185 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
186
187 resp = &p_iov->pf2vf_reply->default_resp;
188 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
189
190 if (!rc && resp->hdr.status != PFVF_STATUS_SUCCESS)
191 rc = -EAGAIN;
192
193 qed_vf_pf_req_end(p_hwfn, rc);
194 if (!b_final)
195 return rc;
196
197 p_hwfn->b_int_enabled = 0;
198
199 if (p_iov->vf2pf_request)
200 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
201 sizeof(union vfpf_tlvs),
202 p_iov->vf2pf_request,
203 p_iov->vf2pf_request_phys);
204 if (p_iov->pf2vf_reply)
205 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
206 sizeof(union pfvf_tlvs),
207 p_iov->pf2vf_reply, p_iov->pf2vf_reply_phys);
208
209 if (p_iov->bulletin.p_virt) {
210 size = sizeof(struct qed_bulletin_content);
211 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
212 size,
213 p_iov->bulletin.p_virt, p_iov->bulletin.phys);
214 }
215
216 kfree(p_hwfn->vf_iov_info);
217 p_hwfn->vf_iov_info = NULL;
218
219 return rc;
220}
221
222int qed_vf_pf_release(struct qed_hwfn *p_hwfn)
223{
224 return _qed_vf_pf_release(p_hwfn, true);
225}
226
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300227#define VF_ACQUIRE_THRESH 3
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300228static void qed_vf_pf_acquire_reduce_resc(struct qed_hwfn *p_hwfn,
229 struct vf_pf_resc_request *p_req,
230 struct pf_vf_resc *p_resp)
231{
232 DP_VERBOSE(p_hwfn,
233 QED_MSG_IOV,
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300234 "PF unwilling to fullill resource request: rxq [%02x/%02x] txq [%02x/%02x] sbs [%02x/%02x] mac [%02x/%02x] vlan [%02x/%02x] mc [%02x/%02x] cids [%02x/%02x]. Try PF recommended amount\n",
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300235 p_req->num_rxqs,
236 p_resp->num_rxqs,
237 p_req->num_rxqs,
238 p_resp->num_txqs,
239 p_req->num_sbs,
240 p_resp->num_sbs,
241 p_req->num_mac_filters,
242 p_resp->num_mac_filters,
243 p_req->num_vlan_filters,
244 p_resp->num_vlan_filters,
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300245 p_req->num_mc_filters,
246 p_resp->num_mc_filters, p_req->num_cids, p_resp->num_cids);
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300247
248 /* humble our request */
249 p_req->num_txqs = p_resp->num_txqs;
250 p_req->num_rxqs = p_resp->num_rxqs;
251 p_req->num_sbs = p_resp->num_sbs;
252 p_req->num_mac_filters = p_resp->num_mac_filters;
253 p_req->num_vlan_filters = p_resp->num_vlan_filters;
254 p_req->num_mc_filters = p_resp->num_mc_filters;
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300255 p_req->num_cids = p_resp->num_cids;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300256}
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300257
258static int qed_vf_pf_acquire(struct qed_hwfn *p_hwfn)
259{
260 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
261 struct pfvf_acquire_resp_tlv *resp = &p_iov->pf2vf_reply->acquire_resp;
262 struct pf_vf_pfdev_info *pfdev_info = &resp->pfdev_info;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300263 struct vf_pf_resc_request *p_resc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300264 bool resources_acquired = false;
265 struct vfpf_acquire_tlv *req;
266 int rc = 0, attempts = 0;
267
268 /* clear mailbox and prep first tlv */
269 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_ACQUIRE, sizeof(*req));
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300270 p_resc = &req->resc_request;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300271
272 /* starting filling the request */
273 req->vfdev_info.opaque_fid = p_hwfn->hw_info.opaque_fid;
274
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300275 p_resc->num_rxqs = QED_MAX_VF_CHAINS_PER_PF;
276 p_resc->num_txqs = QED_MAX_VF_CHAINS_PER_PF;
277 p_resc->num_sbs = QED_MAX_VF_CHAINS_PER_PF;
278 p_resc->num_mac_filters = QED_ETH_VF_NUM_MAC_FILTERS;
279 p_resc->num_vlan_filters = QED_ETH_VF_NUM_VLAN_FILTERS;
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300280 p_resc->num_cids = QED_ETH_VF_DEFAULT_NUM_CIDS;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300281
282 req->vfdev_info.os_type = VFPF_ACQUIRE_OS_LINUX;
283 req->vfdev_info.fw_major = FW_MAJOR_VERSION;
284 req->vfdev_info.fw_minor = FW_MINOR_VERSION;
285 req->vfdev_info.fw_revision = FW_REVISION_VERSION;
286 req->vfdev_info.fw_engineering = FW_ENGINEERING_VERSION;
Yuval Mintz1fe614d2016-06-05 13:11:11 +0300287 req->vfdev_info.eth_fp_hsi_major = ETH_HSI_VER_MAJOR;
288 req->vfdev_info.eth_fp_hsi_minor = ETH_HSI_VER_MINOR;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300289
290 /* Fill capability field with any non-deprecated config we support */
291 req->vfdev_info.capabilities |= VFPF_ACQUIRE_CAP_100G;
292
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300293 /* If we've mapped the doorbell bar, try using queue qids */
294 if (p_iov->b_doorbell_bar)
295 req->vfdev_info.capabilities |= VFPF_ACQUIRE_CAP_PHYSICAL_BAR |
296 VFPF_ACQUIRE_CAP_QUEUE_QIDS;
297
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300298 /* pf 2 vf bulletin board address */
299 req->bulletin_addr = p_iov->bulletin.phys;
300 req->bulletin_size = p_iov->bulletin.size;
301
302 /* add list termination tlv */
303 qed_add_tlv(p_hwfn, &p_iov->offset,
304 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
305
306 while (!resources_acquired) {
307 DP_VERBOSE(p_hwfn,
308 QED_MSG_IOV, "attempting to acquire resources\n");
309
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300310 /* Clear response buffer, as this might be a re-send */
311 memset(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs));
312
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300313 /* send acquire request */
314 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
315 if (rc)
Dan Carpenter66117a92017-04-28 15:56:09 +0300316 goto exit;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300317
318 /* copy acquire response from buffer to p_hwfn */
319 memcpy(&p_iov->acquire_resp, resp, sizeof(p_iov->acquire_resp));
320
321 attempts++;
322
323 if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
324 /* PF agrees to allocate our resources */
325 if (!(resp->pfdev_info.capabilities &
326 PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE)) {
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300327 /* It's possible legacy PF mistakenly accepted;
328 * but we don't care - simply mark it as
329 * legacy and continue.
330 */
331 req->vfdev_info.capabilities |=
332 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300333 }
334 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "resources acquired\n");
335 resources_acquired = true;
336 } else if (resp->hdr.status == PFVF_STATUS_NO_RESOURCE &&
337 attempts < VF_ACQUIRE_THRESH) {
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300338 qed_vf_pf_acquire_reduce_resc(p_hwfn, p_resc,
339 &resp->resc);
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300340 } else if (resp->hdr.status == PFVF_STATUS_NOT_SUPPORTED) {
341 if (pfdev_info->major_fp_hsi &&
342 (pfdev_info->major_fp_hsi != ETH_HSI_VER_MAJOR)) {
343 DP_NOTICE(p_hwfn,
344 "PF uses an incompatible fastpath HSI %02x.%02x [VF requires %02x.%02x]. Please change to a VF driver using %02x.xx.\n",
345 pfdev_info->major_fp_hsi,
346 pfdev_info->minor_fp_hsi,
347 ETH_HSI_VER_MAJOR,
348 ETH_HSI_VER_MINOR,
349 pfdev_info->major_fp_hsi);
350 rc = -EINVAL;
351 goto exit;
352 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300353
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300354 if (!pfdev_info->major_fp_hsi) {
355 if (req->vfdev_info.capabilities &
356 VFPF_ACQUIRE_CAP_PRE_FP_HSI) {
357 DP_NOTICE(p_hwfn,
358 "PF uses very old drivers. Please change to a VF driver using no later than 8.8.x.x.\n");
359 rc = -EINVAL;
360 goto exit;
361 } else {
362 DP_INFO(p_hwfn,
363 "PF is old - try re-acquire to see if it supports FW-version override\n");
364 req->vfdev_info.capabilities |=
365 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
366 continue;
367 }
368 }
369
370 /* If PF/VF are using same Major, PF must have had
371 * it's reasons. Simply fail.
372 */
373 DP_NOTICE(p_hwfn, "PF rejected acquisition by VF\n");
374 rc = -EINVAL;
375 goto exit;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300376 } else {
377 DP_ERR(p_hwfn,
378 "PF returned error %d to VF acquisition request\n",
379 resp->hdr.status);
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300380 rc = -EAGAIN;
381 goto exit;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300382 }
383 }
384
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300385 /* Mark the PF as legacy, if needed */
386 if (req->vfdev_info.capabilities & VFPF_ACQUIRE_CAP_PRE_FP_HSI)
387 p_iov->b_pre_fp_hsi = true;
388
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300389 /* In case PF doesn't support multi-queue Tx, update the number of
390 * CIDs to reflect the number of queues [older PFs didn't fill that
391 * field].
392 */
393 if (!(resp->pfdev_info.capabilities & PFVF_ACQUIRE_CAP_QUEUE_QIDS))
394 resp->resc.num_cids = resp->resc.num_rxqs + resp->resc.num_txqs;
395
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300396 /* Update bulletin board size with response from PF */
397 p_iov->bulletin.size = resp->bulletin_size;
398
399 /* get HW info */
400 p_hwfn->cdev->type = resp->pfdev_info.dev_type;
401 p_hwfn->cdev->chip_rev = resp->pfdev_info.chip_rev;
402
403 p_hwfn->cdev->chip_num = pfdev_info->chip_num & 0xffff;
404
405 /* Learn of the possibility of CMT */
406 if (IS_LEAD_HWFN(p_hwfn)) {
407 if (resp->pfdev_info.capabilities & PFVF_ACQUIRE_CAP_100G) {
408 DP_NOTICE(p_hwfn, "100g VF\n");
409 p_hwfn->cdev->num_hwfns = 2;
410 }
411 }
412
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300413 if (!p_iov->b_pre_fp_hsi &&
414 ETH_HSI_VER_MINOR &&
Yuval Mintz1fe614d2016-06-05 13:11:11 +0300415 (resp->pfdev_info.minor_fp_hsi < ETH_HSI_VER_MINOR)) {
416 DP_INFO(p_hwfn,
417 "PF is using older fastpath HSI; %02x.%02x is configured\n",
418 ETH_HSI_VER_MAJOR, resp->pfdev_info.minor_fp_hsi);
419 }
420
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300421exit:
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300422 qed_vf_pf_req_end(p_hwfn, rc);
423
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300424 return rc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300425}
426
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300427u32 qed_vf_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
428{
429 u32 bar_size;
430
431 /* Regview size is fixed */
432 if (bar_id == BAR_ID_0)
433 return 1 << 17;
434
435 /* Doorbell is received from PF */
436 bar_size = p_hwfn->vf_iov_info->acquire_resp.pfdev_info.bar_size;
437 if (bar_size)
438 return 1 << bar_size;
439 return 0;
440}
441
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300442int qed_vf_hw_prepare(struct qed_hwfn *p_hwfn)
443{
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300444 struct qed_hwfn *p_lead = QED_LEADING_HWFN(p_hwfn->cdev);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300445 struct qed_vf_iov *p_iov;
446 u32 reg;
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300447 int rc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300448
449 /* Set number of hwfns - might be overriden once leading hwfn learns
450 * actual configuration from PF.
451 */
452 if (IS_LEAD_HWFN(p_hwfn))
453 p_hwfn->cdev->num_hwfns = 1;
454
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300455 reg = PXP_VF_BAR0_ME_OPAQUE_ADDRESS;
456 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);
457
458 reg = PXP_VF_BAR0_ME_CONCRETE_ADDRESS;
459 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);
460
461 /* Allocate vf sriov info */
462 p_iov = kzalloc(sizeof(*p_iov), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700463 if (!p_iov)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300464 return -ENOMEM;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300465
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300466 /* Doorbells are tricky; Upper-layer has alreday set the hwfn doorbell
467 * value, but there are several incompatibily scenarios where that
468 * would be incorrect and we'd need to override it.
469 */
470 if (!p_hwfn->doorbells) {
471 p_hwfn->doorbells = (u8 __iomem *)p_hwfn->regview +
472 PXP_VF_BAR0_START_DQ;
473 } else if (p_hwfn == p_lead) {
474 /* For leading hw-function, value is always correct, but need
475 * to handle scenario where legacy PF would not support 100g
476 * mapped bars later.
477 */
478 p_iov->b_doorbell_bar = true;
479 } else {
480 /* here, value would be correct ONLY if the leading hwfn
481 * received indication that mapped-bars are supported.
482 */
483 if (p_lead->vf_iov_info->b_doorbell_bar)
484 p_iov->b_doorbell_bar = true;
485 else
486 p_hwfn->doorbells = (u8 __iomem *)
487 p_hwfn->regview + PXP_VF_BAR0_START_DQ;
488 }
489
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300490 /* Allocate vf2pf msg */
491 p_iov->vf2pf_request = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
492 sizeof(union vfpf_tlvs),
493 &p_iov->vf2pf_request_phys,
494 GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700495 if (!p_iov->vf2pf_request)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300496 goto free_p_iov;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300497
498 p_iov->pf2vf_reply = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
499 sizeof(union pfvf_tlvs),
500 &p_iov->pf2vf_reply_phys,
501 GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700502 if (!p_iov->pf2vf_reply)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300503 goto free_vf2pf_request;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300504
505 DP_VERBOSE(p_hwfn,
506 QED_MSG_IOV,
507 "VF's Request mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys]\n",
508 p_iov->vf2pf_request,
509 (u64) p_iov->vf2pf_request_phys,
510 p_iov->pf2vf_reply, (u64)p_iov->pf2vf_reply_phys);
511
512 /* Allocate Bulletin board */
513 p_iov->bulletin.size = sizeof(struct qed_bulletin_content);
514 p_iov->bulletin.p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
515 p_iov->bulletin.size,
516 &p_iov->bulletin.phys,
517 GFP_KERNEL);
518 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
519 "VF's bulletin Board [%p virt 0x%llx phys 0x%08x bytes]\n",
520 p_iov->bulletin.p_virt,
521 (u64)p_iov->bulletin.phys, p_iov->bulletin.size);
522
523 mutex_init(&p_iov->mutex);
524
525 p_hwfn->vf_iov_info = p_iov;
526
527 p_hwfn->hw_info.personality = QED_PCI_ETH;
528
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300529 rc = qed_vf_pf_acquire(p_hwfn);
530
531 /* If VF is 100g using a mapped bar and PF is too old to support that,
532 * acquisition would succeed - but the VF would have no way knowing
533 * the size of the doorbell bar configured in HW and thus will not
534 * know how to split it for 2nd hw-function.
535 * In this case we re-try without the indication of the mapped
536 * doorbell.
537 */
538 if (!rc && p_iov->b_doorbell_bar &&
539 !qed_vf_hw_bar_size(p_hwfn, BAR_ID_1) &&
540 (p_hwfn->cdev->num_hwfns > 1)) {
541 rc = _qed_vf_pf_release(p_hwfn, false);
542 if (rc)
543 return rc;
544
545 p_iov->b_doorbell_bar = false;
546 p_hwfn->doorbells = (u8 __iomem *)p_hwfn->regview +
547 PXP_VF_BAR0_START_DQ;
548 rc = qed_vf_pf_acquire(p_hwfn);
549 }
550
551 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
552 "Regview [%p], Doorbell [%p], Device-doorbell [%p]\n",
553 p_hwfn->regview, p_hwfn->doorbells, p_hwfn->cdev->doorbells);
554
555 return rc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300556
557free_vf2pf_request:
558 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
559 sizeof(union vfpf_tlvs),
560 p_iov->vf2pf_request, p_iov->vf2pf_request_phys);
561free_p_iov:
562 kfree(p_iov);
563
564 return -ENOMEM;
565}
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300566#define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
567#define MSTORM_QZONE_START(dev) (TSTORM_QZONE_START + \
568 (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300569
Chopra, Manisheaf3c0c2017-04-24 10:00:49 -0700570static void
571__qed_vf_prep_tunn_req_tlv(struct vfpf_update_tunn_param_tlv *p_req,
572 struct qed_tunn_update_type *p_src,
573 enum qed_tunn_clss mask, u8 *p_cls)
574{
575 if (p_src->b_update_mode) {
576 p_req->tun_mode_update_mask |= BIT(mask);
577
578 if (p_src->b_mode_enabled)
579 p_req->tunn_mode |= BIT(mask);
580 }
581
582 *p_cls = p_src->tun_cls;
583}
584
585static void
586qed_vf_prep_tunn_req_tlv(struct vfpf_update_tunn_param_tlv *p_req,
587 struct qed_tunn_update_type *p_src,
588 enum qed_tunn_clss mask,
589 u8 *p_cls, struct qed_tunn_update_udp_port *p_port,
590 u8 *p_update_port, u16 *p_udp_port)
591{
592 if (p_port->b_update_port) {
593 *p_update_port = 1;
594 *p_udp_port = p_port->port;
595 }
596
597 __qed_vf_prep_tunn_req_tlv(p_req, p_src, mask, p_cls);
598}
599
600void qed_vf_set_vf_start_tunn_update_param(struct qed_tunnel_info *p_tun)
601{
602 if (p_tun->vxlan.b_mode_enabled)
603 p_tun->vxlan.b_update_mode = true;
604 if (p_tun->l2_geneve.b_mode_enabled)
605 p_tun->l2_geneve.b_update_mode = true;
606 if (p_tun->ip_geneve.b_mode_enabled)
607 p_tun->ip_geneve.b_update_mode = true;
608 if (p_tun->l2_gre.b_mode_enabled)
609 p_tun->l2_gre.b_update_mode = true;
610 if (p_tun->ip_gre.b_mode_enabled)
611 p_tun->ip_gre.b_update_mode = true;
612
613 p_tun->b_update_rx_cls = true;
614 p_tun->b_update_tx_cls = true;
615}
616
617static void
618__qed_vf_update_tunn_param(struct qed_tunn_update_type *p_tun,
619 u16 feature_mask, u8 tunn_mode,
620 u8 tunn_cls, enum qed_tunn_mode val)
621{
622 if (feature_mask & BIT(val)) {
623 p_tun->b_mode_enabled = tunn_mode;
624 p_tun->tun_cls = tunn_cls;
625 } else {
626 p_tun->b_mode_enabled = false;
627 }
628}
629
630static void qed_vf_update_tunn_param(struct qed_hwfn *p_hwfn,
631 struct qed_tunnel_info *p_tun,
632 struct pfvf_update_tunn_param_tlv *p_resp)
633{
634 /* Update mode and classes provided by PF */
635 u16 feat_mask = p_resp->tunn_feature_mask;
636
637 __qed_vf_update_tunn_param(&p_tun->vxlan, feat_mask,
638 p_resp->vxlan_mode, p_resp->vxlan_clss,
639 QED_MODE_VXLAN_TUNN);
640 __qed_vf_update_tunn_param(&p_tun->l2_geneve, feat_mask,
641 p_resp->l2geneve_mode,
642 p_resp->l2geneve_clss,
643 QED_MODE_L2GENEVE_TUNN);
644 __qed_vf_update_tunn_param(&p_tun->ip_geneve, feat_mask,
645 p_resp->ipgeneve_mode,
646 p_resp->ipgeneve_clss,
647 QED_MODE_IPGENEVE_TUNN);
648 __qed_vf_update_tunn_param(&p_tun->l2_gre, feat_mask,
649 p_resp->l2gre_mode, p_resp->l2gre_clss,
650 QED_MODE_L2GRE_TUNN);
651 __qed_vf_update_tunn_param(&p_tun->ip_gre, feat_mask,
652 p_resp->ipgre_mode, p_resp->ipgre_clss,
653 QED_MODE_IPGRE_TUNN);
654 p_tun->geneve_port.port = p_resp->geneve_udp_port;
655 p_tun->vxlan_port.port = p_resp->vxlan_udp_port;
656
657 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
658 "tunn mode: vxlan=0x%x, l2geneve=0x%x, ipgeneve=0x%x, l2gre=0x%x, ipgre=0x%x",
659 p_tun->vxlan.b_mode_enabled, p_tun->l2_geneve.b_mode_enabled,
660 p_tun->ip_geneve.b_mode_enabled,
661 p_tun->l2_gre.b_mode_enabled, p_tun->ip_gre.b_mode_enabled);
662}
663
664int qed_vf_pf_tunnel_param_update(struct qed_hwfn *p_hwfn,
665 struct qed_tunnel_info *p_src)
666{
667 struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;
668 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
669 struct pfvf_update_tunn_param_tlv *p_resp;
670 struct vfpf_update_tunn_param_tlv *p_req;
671 int rc;
672
673 p_req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_UPDATE_TUNN_PARAM,
674 sizeof(*p_req));
675
676 if (p_src->b_update_rx_cls && p_src->b_update_tx_cls)
677 p_req->update_tun_cls = 1;
678
679 qed_vf_prep_tunn_req_tlv(p_req, &p_src->vxlan, QED_MODE_VXLAN_TUNN,
680 &p_req->vxlan_clss, &p_src->vxlan_port,
681 &p_req->update_vxlan_port,
682 &p_req->vxlan_port);
683 qed_vf_prep_tunn_req_tlv(p_req, &p_src->l2_geneve,
684 QED_MODE_L2GENEVE_TUNN,
685 &p_req->l2geneve_clss, &p_src->geneve_port,
686 &p_req->update_geneve_port,
687 &p_req->geneve_port);
688 __qed_vf_prep_tunn_req_tlv(p_req, &p_src->ip_geneve,
689 QED_MODE_IPGENEVE_TUNN,
690 &p_req->ipgeneve_clss);
691 __qed_vf_prep_tunn_req_tlv(p_req, &p_src->l2_gre,
692 QED_MODE_L2GRE_TUNN, &p_req->l2gre_clss);
693 __qed_vf_prep_tunn_req_tlv(p_req, &p_src->ip_gre,
694 QED_MODE_IPGRE_TUNN, &p_req->ipgre_clss);
695
696 /* add list termination tlv */
697 qed_add_tlv(p_hwfn, &p_iov->offset,
698 CHANNEL_TLV_LIST_END,
699 sizeof(struct channel_list_end_tlv));
700
701 p_resp = &p_iov->pf2vf_reply->tunn_param_resp;
702 rc = qed_send_msg2pf(p_hwfn, &p_resp->hdr.status, sizeof(*p_resp));
703
704 if (rc)
705 goto exit;
706
707 if (p_resp->hdr.status != PFVF_STATUS_SUCCESS) {
708 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
709 "Failed to update tunnel parameters\n");
710 rc = -EINVAL;
711 }
712
713 qed_vf_update_tunn_param(p_hwfn, p_tun, p_resp);
714exit:
715 qed_vf_pf_req_end(p_hwfn, rc);
716 return rc;
717}
718
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200719int
720qed_vf_pf_rxq_start(struct qed_hwfn *p_hwfn,
721 struct qed_queue_cid *p_cid,
722 u16 bd_max_bytes,
723 dma_addr_t bd_chain_phys_addr,
724 dma_addr_t cqe_pbl_addr,
725 u16 cqe_pbl_size, void __iomem **pp_prod)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300726{
727 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
728 struct pfvf_start_queue_resp_tlv *resp;
729 struct vfpf_start_rxq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200730 u8 rx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300731 int rc;
732
733 /* clear mailbox and prep first tlv */
734 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_RXQ, sizeof(*req));
735
736 req->rx_qid = rx_qid;
737 req->cqe_pbl_addr = cqe_pbl_addr;
738 req->cqe_pbl_size = cqe_pbl_size;
739 req->rxq_addr = bd_chain_phys_addr;
Mintz, Yuvalf604b172017-06-04 13:31:01 +0300740 req->hw_sb = p_cid->sb_igu_id;
741 req->sb_index = p_cid->sb_idx;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300742 req->bd_max_bytes = bd_max_bytes;
743 req->stat_id = -1;
744
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300745 /* If PF is legacy, we'll need to calculate producers ourselves
746 * as well as clean them.
747 */
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200748 if (p_iov->b_pre_fp_hsi) {
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300749 u8 hw_qid = p_iov->acquire_resp.resc.hw_qid[rx_qid];
750 u32 init_prod_val = 0;
751
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200752 *pp_prod = (u8 __iomem *)
753 p_hwfn->regview +
754 MSTORM_QZONE_START(p_hwfn->cdev) +
755 hw_qid * MSTORM_QZONE_SIZE;
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300756
757 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
758 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
759 (u32 *)(&init_prod_val));
760 }
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300761
762 qed_vf_pf_add_qid(p_hwfn, p_cid);
763
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300764 /* add list termination tlv */
765 qed_add_tlv(p_hwfn, &p_iov->offset,
766 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
767
768 resp = &p_iov->pf2vf_reply->queue_start;
769 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
770 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300771 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300772
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300773 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
774 rc = -EINVAL;
775 goto exit;
776 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300777
778 /* Learn the address of the producer from the response */
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200779 if (!p_iov->b_pre_fp_hsi) {
Yuval Mintzb21290b2016-07-27 14:45:21 +0300780 u32 init_prod_val = 0;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300781
782 *pp_prod = (u8 __iomem *)p_hwfn->regview + resp->offset;
783 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
784 "Rxq[0x%02x]: producer at %p [offset 0x%08x]\n",
785 rx_qid, *pp_prod, resp->offset);
786
787 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
Yuval Mintzb21290b2016-07-27 14:45:21 +0300788 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300789 (u32 *)&init_prod_val);
790 }
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300791exit:
792 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300793
794 return rc;
795}
796
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200797int qed_vf_pf_rxq_stop(struct qed_hwfn *p_hwfn,
798 struct qed_queue_cid *p_cid, bool cqe_completion)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300799{
800 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
801 struct vfpf_stop_rxqs_tlv *req;
802 struct pfvf_def_resp_tlv *resp;
803 int rc;
804
805 /* clear mailbox and prep first tlv */
806 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_RXQS, sizeof(*req));
807
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200808 req->rx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300809 req->num_rxqs = 1;
810 req->cqe_completion = cqe_completion;
811
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300812 qed_vf_pf_add_qid(p_hwfn, p_cid);
813
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300814 /* add list termination tlv */
815 qed_add_tlv(p_hwfn, &p_iov->offset,
816 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
817
818 resp = &p_iov->pf2vf_reply->default_resp;
819 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
820 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300821 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300822
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300823 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
824 rc = -EINVAL;
825 goto exit;
826 }
827
828exit:
829 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300830
831 return rc;
832}
833
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200834int
835qed_vf_pf_txq_start(struct qed_hwfn *p_hwfn,
836 struct qed_queue_cid *p_cid,
837 dma_addr_t pbl_addr,
838 u16 pbl_size, void __iomem **pp_doorbell)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300839{
840 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
Yuval Mintz5040acf2016-06-05 13:11:14 +0300841 struct pfvf_start_queue_resp_tlv *resp;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300842 struct vfpf_start_txq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200843 u16 qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300844 int rc;
845
846 /* clear mailbox and prep first tlv */
847 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_TXQ, sizeof(*req));
848
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200849 req->tx_qid = qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300850
851 /* Tx */
852 req->pbl_addr = pbl_addr;
853 req->pbl_size = pbl_size;
Mintz, Yuvalf604b172017-06-04 13:31:01 +0300854 req->hw_sb = p_cid->sb_igu_id;
855 req->sb_index = p_cid->sb_idx;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300856
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300857 qed_vf_pf_add_qid(p_hwfn, p_cid);
858
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300859 /* add list termination tlv */
860 qed_add_tlv(p_hwfn, &p_iov->offset,
861 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
862
Yuval Mintz5040acf2016-06-05 13:11:14 +0300863 resp = &p_iov->pf2vf_reply->queue_start;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300864 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
865 if (rc)
Yuval Mintz5040acf2016-06-05 13:11:14 +0300866 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300867
Yuval Mintz5040acf2016-06-05 13:11:14 +0300868 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
869 rc = -EINVAL;
870 goto exit;
871 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300872
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200873 /* Modern PFs provide the actual offsets, while legacy
874 * provided only the queue id.
875 */
876 if (!p_iov->b_pre_fp_hsi) {
877 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells + resp->offset;
878 } else {
879 u8 cid = p_iov->acquire_resp.resc.cid[qid];
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300880
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200881 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
882 qed_db_addr_vf(cid,
883 DQ_DEMS_LEGACY);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300884 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200885
886 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
887 "Txq[0x%02x]: doorbell at %p [offset 0x%08x]\n",
888 qid, *pp_doorbell, resp->offset);
Yuval Mintz5040acf2016-06-05 13:11:14 +0300889exit:
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300890 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300891
892 return rc;
893}
894
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200895int qed_vf_pf_txq_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300896{
897 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
898 struct vfpf_stop_txqs_tlv *req;
899 struct pfvf_def_resp_tlv *resp;
900 int rc;
901
902 /* clear mailbox and prep first tlv */
903 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_TXQS, sizeof(*req));
904
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200905 req->tx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300906 req->num_txqs = 1;
907
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300908 qed_vf_pf_add_qid(p_hwfn, p_cid);
909
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300910 /* add list termination tlv */
911 qed_add_tlv(p_hwfn, &p_iov->offset,
912 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
913
914 resp = &p_iov->pf2vf_reply->default_resp;
915 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
916 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300917 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300918
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300919 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
920 rc = -EINVAL;
921 goto exit;
922 }
923
924exit:
925 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300926
927 return rc;
928}
929
930int qed_vf_pf_vport_start(struct qed_hwfn *p_hwfn,
931 u8 vport_id,
932 u16 mtu,
933 u8 inner_vlan_removal,
934 enum qed_tpa_mode tpa_mode,
Yuval Mintz08feecd2016-05-11 16:36:20 +0300935 u8 max_buffers_per_cqe, u8 only_untagged)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300936{
937 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
938 struct vfpf_vport_start_tlv *req;
939 struct pfvf_def_resp_tlv *resp;
940 int rc, i;
941
942 /* clear mailbox and prep first tlv */
943 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_START, sizeof(*req));
944
945 req->mtu = mtu;
946 req->vport_id = vport_id;
947 req->inner_vlan_removal = inner_vlan_removal;
948 req->tpa_mode = tpa_mode;
949 req->max_buffers_per_cqe = max_buffers_per_cqe;
Yuval Mintz08feecd2016-05-11 16:36:20 +0300950 req->only_untagged = only_untagged;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300951
952 /* status blocks */
Mintz, Yuval50a20712017-06-01 15:29:09 +0300953 for (i = 0; i < p_hwfn->vf_iov_info->acquire_resp.resc.num_sbs; i++) {
954 struct qed_sb_info *p_sb = p_hwfn->vf_iov_info->sbs_info[i];
955
956 if (p_sb)
957 req->sb_addr[i] = p_sb->sb_phys;
958 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300959
960 /* add list termination tlv */
961 qed_add_tlv(p_hwfn, &p_iov->offset,
962 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
963
964 resp = &p_iov->pf2vf_reply->default_resp;
965 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
966 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300967 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300968
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300969 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
970 rc = -EINVAL;
971 goto exit;
972 }
973
974exit:
975 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300976
977 return rc;
978}
979
980int qed_vf_pf_vport_stop(struct qed_hwfn *p_hwfn)
981{
982 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
983 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
984 int rc;
985
986 /* clear mailbox and prep first tlv */
987 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_TEARDOWN,
988 sizeof(struct vfpf_first_tlv));
989
990 /* add list termination tlv */
991 qed_add_tlv(p_hwfn, &p_iov->offset,
992 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
993
994 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
995 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300996 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300997
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300998 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
999 rc = -EINVAL;
1000 goto exit;
1001 }
1002
1003exit:
1004 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001005
1006 return rc;
1007}
1008
1009static bool
1010qed_vf_handle_vp_update_is_needed(struct qed_hwfn *p_hwfn,
1011 struct qed_sp_vport_update_params *p_data,
1012 u16 tlv)
1013{
1014 switch (tlv) {
1015 case CHANNEL_TLV_VPORT_UPDATE_ACTIVATE:
1016 return !!(p_data->update_vport_active_rx_flg ||
1017 p_data->update_vport_active_tx_flg);
Yuval Mintz17b235c2016-05-11 16:36:18 +03001018 case CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH:
1019 return !!p_data->update_tx_switching_flg;
1020 case CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP:
1021 return !!p_data->update_inner_vlan_removal_flg;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001022 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN:
1023 return !!p_data->update_accept_any_vlan_flg;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001024 case CHANNEL_TLV_VPORT_UPDATE_MCAST:
1025 return !!p_data->update_approx_mcast_flg;
1026 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM:
1027 return !!(p_data->accept_flags.update_rx_mode_config ||
1028 p_data->accept_flags.update_tx_mode_config);
1029 case CHANNEL_TLV_VPORT_UPDATE_RSS:
1030 return !!p_data->rss_params;
Yuval Mintz17b235c2016-05-11 16:36:18 +03001031 case CHANNEL_TLV_VPORT_UPDATE_SGE_TPA:
1032 return !!p_data->sge_tpa_params;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001033 default:
1034 DP_INFO(p_hwfn, "Unexpected vport-update TLV[%d]\n",
1035 tlv);
1036 return false;
1037 }
1038}
1039
1040static void
1041qed_vf_handle_vp_update_tlvs_resp(struct qed_hwfn *p_hwfn,
1042 struct qed_sp_vport_update_params *p_data)
1043{
1044 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1045 struct pfvf_def_resp_tlv *p_resp;
1046 u16 tlv;
1047
1048 for (tlv = CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
1049 tlv < CHANNEL_TLV_VPORT_UPDATE_MAX; tlv++) {
1050 if (!qed_vf_handle_vp_update_is_needed(p_hwfn, p_data, tlv))
1051 continue;
1052
1053 p_resp = (struct pfvf_def_resp_tlv *)
1054 qed_iov_search_list_tlvs(p_hwfn, p_iov->pf2vf_reply,
1055 tlv);
1056 if (p_resp && p_resp->hdr.status)
1057 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1058 "TLV[%d] Configuration %s\n",
1059 tlv,
1060 (p_resp && p_resp->hdr.status) ? "succeeded"
1061 : "failed");
1062 }
1063}
1064
1065int qed_vf_pf_vport_update(struct qed_hwfn *p_hwfn,
1066 struct qed_sp_vport_update_params *p_params)
1067{
1068 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1069 struct vfpf_vport_update_tlv *req;
1070 struct pfvf_def_resp_tlv *resp;
1071 u8 update_rx, update_tx;
1072 u32 resp_size = 0;
1073 u16 size, tlv;
1074 int rc;
1075
1076 resp = &p_iov->pf2vf_reply->default_resp;
1077 resp_size = sizeof(*resp);
1078
1079 update_rx = p_params->update_vport_active_rx_flg;
1080 update_tx = p_params->update_vport_active_tx_flg;
1081
1082 /* clear mailbox and prep header tlv */
1083 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_UPDATE, sizeof(*req));
1084
1085 /* Prepare extended tlvs */
1086 if (update_rx || update_tx) {
1087 struct vfpf_vport_update_activate_tlv *p_act_tlv;
1088
1089 size = sizeof(struct vfpf_vport_update_activate_tlv);
1090 p_act_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
1091 CHANNEL_TLV_VPORT_UPDATE_ACTIVATE,
1092 size);
1093 resp_size += sizeof(struct pfvf_def_resp_tlv);
1094
1095 if (update_rx) {
1096 p_act_tlv->update_rx = update_rx;
1097 p_act_tlv->active_rx = p_params->vport_active_rx_flg;
1098 }
1099
1100 if (update_tx) {
1101 p_act_tlv->update_tx = update_tx;
1102 p_act_tlv->active_tx = p_params->vport_active_tx_flg;
1103 }
1104 }
1105
Yuval Mintz831bfb0e2016-05-11 16:36:25 +03001106 if (p_params->update_tx_switching_flg) {
1107 struct vfpf_vport_update_tx_switch_tlv *p_tx_switch_tlv;
1108
1109 size = sizeof(struct vfpf_vport_update_tx_switch_tlv);
1110 tlv = CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
1111 p_tx_switch_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
1112 tlv, size);
1113 resp_size += sizeof(struct pfvf_def_resp_tlv);
1114
1115 p_tx_switch_tlv->tx_switching = p_params->tx_switching_flg;
1116 }
1117
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001118 if (p_params->update_approx_mcast_flg) {
1119 struct vfpf_vport_update_mcast_bin_tlv *p_mcast_tlv;
1120
1121 size = sizeof(struct vfpf_vport_update_mcast_bin_tlv);
1122 p_mcast_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
1123 CHANNEL_TLV_VPORT_UPDATE_MCAST, size);
1124 resp_size += sizeof(struct pfvf_def_resp_tlv);
1125
1126 memcpy(p_mcast_tlv->bins, p_params->bins,
1127 sizeof(unsigned long) * ETH_MULTICAST_MAC_BINS_IN_REGS);
1128 }
1129
1130 update_rx = p_params->accept_flags.update_rx_mode_config;
1131 update_tx = p_params->accept_flags.update_tx_mode_config;
1132
1133 if (update_rx || update_tx) {
1134 struct vfpf_vport_update_accept_param_tlv *p_accept_tlv;
1135
1136 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
1137 size = sizeof(struct vfpf_vport_update_accept_param_tlv);
1138 p_accept_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, tlv, size);
1139 resp_size += sizeof(struct pfvf_def_resp_tlv);
1140
1141 if (update_rx) {
1142 p_accept_tlv->update_rx_mode = update_rx;
1143 p_accept_tlv->rx_accept_filter =
1144 p_params->accept_flags.rx_accept_filter;
1145 }
1146
1147 if (update_tx) {
1148 p_accept_tlv->update_tx_mode = update_tx;
1149 p_accept_tlv->tx_accept_filter =
1150 p_params->accept_flags.tx_accept_filter;
1151 }
1152 }
1153
1154 if (p_params->rss_params) {
1155 struct qed_rss_params *rss_params = p_params->rss_params;
1156 struct vfpf_vport_update_rss_tlv *p_rss_tlv;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02001157 int i, table_size;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001158
1159 size = sizeof(struct vfpf_vport_update_rss_tlv);
1160 p_rss_tlv = qed_add_tlv(p_hwfn,
1161 &p_iov->offset,
1162 CHANNEL_TLV_VPORT_UPDATE_RSS, size);
1163 resp_size += sizeof(struct pfvf_def_resp_tlv);
1164
1165 if (rss_params->update_rss_config)
1166 p_rss_tlv->update_rss_flags |=
1167 VFPF_UPDATE_RSS_CONFIG_FLAG;
1168 if (rss_params->update_rss_capabilities)
1169 p_rss_tlv->update_rss_flags |=
1170 VFPF_UPDATE_RSS_CAPS_FLAG;
1171 if (rss_params->update_rss_ind_table)
1172 p_rss_tlv->update_rss_flags |=
1173 VFPF_UPDATE_RSS_IND_TABLE_FLAG;
1174 if (rss_params->update_rss_key)
1175 p_rss_tlv->update_rss_flags |= VFPF_UPDATE_RSS_KEY_FLAG;
1176
1177 p_rss_tlv->rss_enable = rss_params->rss_enable;
1178 p_rss_tlv->rss_caps = rss_params->rss_caps;
1179 p_rss_tlv->rss_table_size_log = rss_params->rss_table_size_log;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02001180
1181 table_size = min_t(int, T_ETH_INDIRECTION_TABLE_SIZE,
1182 1 << p_rss_tlv->rss_table_size_log);
1183 for (i = 0; i < table_size; i++) {
1184 struct qed_queue_cid *p_queue;
1185
1186 p_queue = rss_params->rss_ind_table[i];
1187 p_rss_tlv->rss_ind_table[i] = p_queue->rel.queue_id;
1188 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001189 memcpy(p_rss_tlv->rss_key, rss_params->rss_key,
1190 sizeof(rss_params->rss_key));
1191 }
1192
Yuval Mintz08feecd2016-05-11 16:36:20 +03001193 if (p_params->update_accept_any_vlan_flg) {
1194 struct vfpf_vport_update_accept_any_vlan_tlv *p_any_vlan_tlv;
1195
1196 size = sizeof(struct vfpf_vport_update_accept_any_vlan_tlv);
1197 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
1198 p_any_vlan_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, tlv, size);
1199
1200 resp_size += sizeof(struct pfvf_def_resp_tlv);
1201 p_any_vlan_tlv->accept_any_vlan = p_params->accept_any_vlan;
1202 p_any_vlan_tlv->update_accept_any_vlan_flg =
1203 p_params->update_accept_any_vlan_flg;
1204 }
1205
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001206 /* add list termination tlv */
1207 qed_add_tlv(p_hwfn, &p_iov->offset,
1208 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1209
1210 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, resp_size);
1211 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001212 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001213
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001214 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1215 rc = -EINVAL;
1216 goto exit;
1217 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001218
1219 qed_vf_handle_vp_update_tlvs_resp(p_hwfn, p_params);
1220
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001221exit:
1222 qed_vf_pf_req_end(p_hwfn, rc);
1223
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001224 return rc;
1225}
1226
Yuval Mintz0b55e272016-05-11 16:36:15 +03001227int qed_vf_pf_reset(struct qed_hwfn *p_hwfn)
1228{
1229 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1230 struct pfvf_def_resp_tlv *resp;
1231 struct vfpf_first_tlv *req;
1232 int rc;
1233
1234 /* clear mailbox and prep first tlv */
1235 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_CLOSE, sizeof(*req));
1236
1237 /* add list termination tlv */
1238 qed_add_tlv(p_hwfn, &p_iov->offset,
1239 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1240
1241 resp = &p_iov->pf2vf_reply->default_resp;
1242 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1243 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001244 goto exit;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001245
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001246 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1247 rc = -EAGAIN;
1248 goto exit;
1249 }
Yuval Mintz0b55e272016-05-11 16:36:15 +03001250
1251 p_hwfn->b_int_enabled = 0;
1252
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001253exit:
1254 qed_vf_pf_req_end(p_hwfn, rc);
1255
1256 return rc;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001257}
1258
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001259void qed_vf_pf_filter_mcast(struct qed_hwfn *p_hwfn,
1260 struct qed_filter_mcast *p_filter_cmd)
1261{
1262 struct qed_sp_vport_update_params sp_params;
1263 int i;
1264
1265 memset(&sp_params, 0, sizeof(sp_params));
1266 sp_params.update_approx_mcast_flg = 1;
1267
1268 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1269 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1270 u32 bit;
1271
1272 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1273 __set_bit(bit, sp_params.bins);
1274 }
1275 }
1276
1277 qed_vf_pf_vport_update(p_hwfn, &sp_params);
1278}
1279
1280int qed_vf_pf_filter_ucast(struct qed_hwfn *p_hwfn,
1281 struct qed_filter_ucast *p_ucast)
1282{
1283 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1284 struct vfpf_ucast_filter_tlv *req;
1285 struct pfvf_def_resp_tlv *resp;
1286 int rc;
1287
1288 /* clear mailbox and prep first tlv */
1289 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_UCAST_FILTER, sizeof(*req));
1290 req->opcode = (u8) p_ucast->opcode;
1291 req->type = (u8) p_ucast->type;
1292 memcpy(req->mac, p_ucast->mac, ETH_ALEN);
1293 req->vlan = p_ucast->vlan;
1294
1295 /* add list termination tlv */
1296 qed_add_tlv(p_hwfn, &p_iov->offset,
1297 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1298
1299 resp = &p_iov->pf2vf_reply->default_resp;
1300 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1301 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001302 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001303
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001304 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1305 rc = -EAGAIN;
1306 goto exit;
1307 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001308
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001309exit:
1310 qed_vf_pf_req_end(p_hwfn, rc);
1311
1312 return rc;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001313}
1314
Yuval Mintz0b55e272016-05-11 16:36:15 +03001315int qed_vf_pf_int_cleanup(struct qed_hwfn *p_hwfn)
1316{
1317 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1318 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
1319 int rc;
1320
1321 /* clear mailbox and prep first tlv */
1322 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_INT_CLEANUP,
1323 sizeof(struct vfpf_first_tlv));
1324
1325 /* add list termination tlv */
1326 qed_add_tlv(p_hwfn, &p_iov->offset,
1327 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1328
1329 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1330 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001331 goto exit;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001332
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001333 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1334 rc = -EINVAL;
1335 goto exit;
1336 }
Yuval Mintz0b55e272016-05-11 16:36:15 +03001337
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001338exit:
1339 qed_vf_pf_req_end(p_hwfn, rc);
1340
1341 return rc;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001342}
1343
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001344u16 qed_vf_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
1345{
1346 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1347
1348 if (!p_iov) {
1349 DP_NOTICE(p_hwfn, "vf_sriov_info isn't initialized\n");
1350 return 0;
1351 }
1352
1353 return p_iov->acquire_resp.resc.hw_sbs[sb_id].hw_sb_id;
1354}
1355
Mintz, Yuval50a20712017-06-01 15:29:09 +03001356void qed_vf_set_sb_info(struct qed_hwfn *p_hwfn,
1357 u16 sb_id, struct qed_sb_info *p_sb)
1358{
1359 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1360
1361 if (!p_iov) {
1362 DP_NOTICE(p_hwfn, "vf_sriov_info isn't initialized\n");
1363 return;
1364 }
1365
1366 if (sb_id >= PFVF_MAX_SBS_PER_VF) {
1367 DP_NOTICE(p_hwfn, "Can't configure SB %04x\n", sb_id);
1368 return;
1369 }
1370
1371 p_iov->sbs_info[sb_id] = p_sb;
1372}
1373
Yuval Mintz36558c32016-05-11 16:36:17 +03001374int qed_vf_read_bulletin(struct qed_hwfn *p_hwfn, u8 *p_change)
1375{
1376 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1377 struct qed_bulletin_content shadow;
1378 u32 crc, crc_size;
1379
1380 crc_size = sizeof(p_iov->bulletin.p_virt->crc);
1381 *p_change = 0;
1382
1383 /* Need to guarantee PF is not in the middle of writing it */
1384 memcpy(&shadow, p_iov->bulletin.p_virt, p_iov->bulletin.size);
1385
1386 /* If version did not update, no need to do anything */
1387 if (shadow.version == p_iov->bulletin_shadow.version)
1388 return 0;
1389
1390 /* Verify the bulletin we see is valid */
1391 crc = crc32(0, (u8 *)&shadow + crc_size,
1392 p_iov->bulletin.size - crc_size);
1393 if (crc != shadow.crc)
1394 return -EAGAIN;
1395
1396 /* Set the shadow bulletin and process it */
1397 memcpy(&p_iov->bulletin_shadow, &shadow, p_iov->bulletin.size);
1398
1399 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1400 "Read a bulletin update %08x\n", shadow.version);
1401
1402 *p_change = 1;
1403
1404 return 0;
1405}
1406
1407void __qed_vf_get_link_params(struct qed_hwfn *p_hwfn,
1408 struct qed_mcp_link_params *p_params,
1409 struct qed_bulletin_content *p_bulletin)
1410{
1411 memset(p_params, 0, sizeof(*p_params));
1412
1413 p_params->speed.autoneg = p_bulletin->req_autoneg;
1414 p_params->speed.advertised_speeds = p_bulletin->req_adv_speed;
1415 p_params->speed.forced_speed = p_bulletin->req_forced_speed;
1416 p_params->pause.autoneg = p_bulletin->req_autoneg_pause;
1417 p_params->pause.forced_rx = p_bulletin->req_forced_rx;
1418 p_params->pause.forced_tx = p_bulletin->req_forced_tx;
1419 p_params->loopback_mode = p_bulletin->req_loopback;
1420}
1421
1422void qed_vf_get_link_params(struct qed_hwfn *p_hwfn,
1423 struct qed_mcp_link_params *params)
1424{
1425 __qed_vf_get_link_params(p_hwfn, params,
1426 &(p_hwfn->vf_iov_info->bulletin_shadow));
1427}
1428
1429void __qed_vf_get_link_state(struct qed_hwfn *p_hwfn,
1430 struct qed_mcp_link_state *p_link,
1431 struct qed_bulletin_content *p_bulletin)
1432{
1433 memset(p_link, 0, sizeof(*p_link));
1434
1435 p_link->link_up = p_bulletin->link_up;
1436 p_link->speed = p_bulletin->speed;
1437 p_link->full_duplex = p_bulletin->full_duplex;
1438 p_link->an = p_bulletin->autoneg;
1439 p_link->an_complete = p_bulletin->autoneg_complete;
1440 p_link->parallel_detection = p_bulletin->parallel_detection;
1441 p_link->pfc_enabled = p_bulletin->pfc_enabled;
1442 p_link->partner_adv_speed = p_bulletin->partner_adv_speed;
1443 p_link->partner_tx_flow_ctrl_en = p_bulletin->partner_tx_flow_ctrl_en;
1444 p_link->partner_rx_flow_ctrl_en = p_bulletin->partner_rx_flow_ctrl_en;
1445 p_link->partner_adv_pause = p_bulletin->partner_adv_pause;
1446 p_link->sfp_tx_fault = p_bulletin->sfp_tx_fault;
1447}
1448
1449void qed_vf_get_link_state(struct qed_hwfn *p_hwfn,
1450 struct qed_mcp_link_state *link)
1451{
1452 __qed_vf_get_link_state(p_hwfn, link,
1453 &(p_hwfn->vf_iov_info->bulletin_shadow));
1454}
1455
1456void __qed_vf_get_link_caps(struct qed_hwfn *p_hwfn,
1457 struct qed_mcp_link_capabilities *p_link_caps,
1458 struct qed_bulletin_content *p_bulletin)
1459{
1460 memset(p_link_caps, 0, sizeof(*p_link_caps));
1461 p_link_caps->speed_capabilities = p_bulletin->capability_speed;
1462}
1463
1464void qed_vf_get_link_caps(struct qed_hwfn *p_hwfn,
1465 struct qed_mcp_link_capabilities *p_link_caps)
1466{
1467 __qed_vf_get_link_caps(p_hwfn, p_link_caps,
1468 &(p_hwfn->vf_iov_info->bulletin_shadow));
1469}
1470
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001471void qed_vf_get_num_rxqs(struct qed_hwfn *p_hwfn, u8 *num_rxqs)
1472{
1473 *num_rxqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_rxqs;
1474}
1475
Mintz, Yuval0db711b2017-06-04 13:31:00 +03001476void qed_vf_get_num_txqs(struct qed_hwfn *p_hwfn, u8 *num_txqs)
1477{
1478 *num_txqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_txqs;
1479}
1480
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001481void qed_vf_get_port_mac(struct qed_hwfn *p_hwfn, u8 *port_mac)
1482{
1483 memcpy(port_mac,
1484 p_hwfn->vf_iov_info->acquire_resp.pfdev_info.port_mac, ETH_ALEN);
1485}
1486
1487void qed_vf_get_num_vlan_filters(struct qed_hwfn *p_hwfn, u8 *num_vlan_filters)
1488{
1489 struct qed_vf_iov *p_vf;
1490
1491 p_vf = p_hwfn->vf_iov_info;
1492 *num_vlan_filters = p_vf->acquire_resp.resc.num_vlan_filters;
1493}
1494
Mintz, Yuvalb0fca312016-10-31 22:26:54 +02001495void qed_vf_get_num_mac_filters(struct qed_hwfn *p_hwfn, u8 *num_mac_filters)
1496{
1497 struct qed_vf_iov *p_vf = p_hwfn->vf_iov_info;
1498
1499 *num_mac_filters = p_vf->acquire_resp.resc.num_mac_filters;
1500}
1501
Yuval Mintzeff16962016-05-11 16:36:21 +03001502bool qed_vf_check_mac(struct qed_hwfn *p_hwfn, u8 *mac)
1503{
1504 struct qed_bulletin_content *bulletin;
1505
1506 bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1507 if (!(bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)))
1508 return true;
1509
1510 /* Forbid VF from changing a MAC enforced by PF */
1511 if (ether_addr_equal(bulletin->mac, mac))
1512 return false;
1513
1514 return false;
1515}
1516
Baoyou Xieba569472016-09-09 09:21:15 +08001517static bool qed_vf_bulletin_get_forced_mac(struct qed_hwfn *hwfn,
1518 u8 *dst_mac, u8 *p_is_forced)
Yuval Mintzeff16962016-05-11 16:36:21 +03001519{
1520 struct qed_bulletin_content *bulletin;
1521
1522 bulletin = &hwfn->vf_iov_info->bulletin_shadow;
1523
1524 if (bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)) {
1525 if (p_is_forced)
1526 *p_is_forced = 1;
1527 } else if (bulletin->valid_bitmap & (1 << VFPF_BULLETIN_MAC_ADDR)) {
1528 if (p_is_forced)
1529 *p_is_forced = 0;
1530 } else {
1531 return false;
1532 }
1533
1534 ether_addr_copy(dst_mac, bulletin->mac);
1535
1536 return true;
1537}
1538
Chopra, Manish97379f12017-04-24 10:00:48 -07001539static void
1540qed_vf_bulletin_get_udp_ports(struct qed_hwfn *p_hwfn,
1541 u16 *p_vxlan_port, u16 *p_geneve_port)
1542{
1543 struct qed_bulletin_content *p_bulletin;
1544
1545 p_bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1546
1547 *p_vxlan_port = p_bulletin->vxlan_udp_port;
1548 *p_geneve_port = p_bulletin->geneve_udp_port;
1549}
1550
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001551void qed_vf_get_fw_version(struct qed_hwfn *p_hwfn,
1552 u16 *fw_major, u16 *fw_minor,
1553 u16 *fw_rev, u16 *fw_eng)
1554{
1555 struct pf_vf_pfdev_info *info;
1556
1557 info = &p_hwfn->vf_iov_info->acquire_resp.pfdev_info;
1558
1559 *fw_major = info->fw_major;
1560 *fw_minor = info->fw_minor;
1561 *fw_rev = info->fw_rev;
1562 *fw_eng = info->fw_eng;
1563}
Yuval Mintz36558c32016-05-11 16:36:17 +03001564
1565static void qed_handle_bulletin_change(struct qed_hwfn *hwfn)
1566{
Yuval Mintzeff16962016-05-11 16:36:21 +03001567 struct qed_eth_cb_ops *ops = hwfn->cdev->protocol_ops.eth;
1568 u8 mac[ETH_ALEN], is_mac_exist, is_mac_forced;
1569 void *cookie = hwfn->cdev->ops_cookie;
Chopra, Manish97379f12017-04-24 10:00:48 -07001570 u16 vxlan_port, geneve_port;
Yuval Mintzeff16962016-05-11 16:36:21 +03001571
Chopra, Manish97379f12017-04-24 10:00:48 -07001572 qed_vf_bulletin_get_udp_ports(hwfn, &vxlan_port, &geneve_port);
Yuval Mintzeff16962016-05-11 16:36:21 +03001573 is_mac_exist = qed_vf_bulletin_get_forced_mac(hwfn, mac,
1574 &is_mac_forced);
Yuval Mintzc3aaa402016-10-14 05:19:17 -04001575 if (is_mac_exist && cookie)
1576 ops->force_mac(cookie, mac, !!is_mac_forced);
Yuval Mintzeff16962016-05-11 16:36:21 +03001577
Chopra, Manish97379f12017-04-24 10:00:48 -07001578 ops->ports_update(cookie, vxlan_port, geneve_port);
1579
Yuval Mintz36558c32016-05-11 16:36:17 +03001580 /* Always update link configuration according to bulletin */
1581 qed_link_update(hwfn);
1582}
1583
1584void qed_iov_vf_task(struct work_struct *work)
1585{
1586 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
1587 iov_task.work);
1588 u8 change = 0;
1589
1590 if (test_and_clear_bit(QED_IOV_WQ_STOP_WQ_FLAG, &hwfn->iov_task_flags))
1591 return;
1592
1593 /* Handle bulletin board changes */
1594 qed_vf_read_bulletin(hwfn, &change);
Mintz, Yuval65ed2ff2017-02-20 22:43:39 +02001595 if (test_and_clear_bit(QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG,
1596 &hwfn->iov_task_flags))
1597 change = 1;
Yuval Mintz36558c32016-05-11 16:36:17 +03001598 if (change)
1599 qed_handle_bulletin_change(hwfn);
1600
1601 /* As VF is polling bulletin board, need to constantly re-schedule */
1602 queue_delayed_work(hwfn->iov_wq, &hwfn->iov_task, HZ);
1603}