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Catalin Marinas9cce7a42012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/include/asm/processor.h
3 *
4 * Copyright (C) 1995-1999 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASM_PROCESSOR_H
20#define __ASM_PROCESSOR_H
21
22/*
23 * Default implementation of macro that returns current
24 * instruction pointer ("program counter").
25 */
26#define current_text_addr() ({ __label__ _l; _l: &&_l;})
27
28#ifdef __KERNEL__
29
30#include <linux/string.h>
31
Will Deaconcd5e10b2016-02-02 12:46:23 +000032#include <asm/alternative.h>
Catalin Marinas9cce7a42012-03-05 11:49:28 +000033#include <asm/fpsimd.h>
34#include <asm/hw_breakpoint.h>
Paul Walmsley2ec45602015-01-05 17:38:41 -070035#include <asm/pgtable-hwdef.h>
Catalin Marinas9cce7a42012-03-05 11:49:28 +000036#include <asm/ptrace.h>
37#include <asm/types.h>
38
39#ifdef __KERNEL__
40#define STACK_TOP_MAX TASK_SIZE_64
41#ifdef CONFIG_COMPAT
42#define AARCH32_VECTORS_BASE 0xffff0000
43#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
44 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
45#else
46#define STACK_TOP STACK_TOP_MAX
47#endif /* CONFIG_COMPAT */
Will Deaconf483a852012-11-08 16:00:16 +000048
Catalin Marinasa1e50a82015-02-05 18:01:53 +000049extern phys_addr_t arm64_dma_phys_limit;
50#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
Catalin Marinas9cce7a42012-03-05 11:49:28 +000051#endif /* __KERNEL__ */
52
53struct debug_info {
54 /* Have we suspended stepping by a debugger? */
55 int suspended_step;
56 /* Allow breakpoints and watchpoints to be disabled for this thread. */
57 int bps_disabled;
58 int wps_disabled;
59 /* Hardware breakpoints pinned to this task. */
60 struct perf_event *hbp_break[ARM_MAX_BRP];
61 struct perf_event *hbp_watch[ARM_MAX_WRP];
62};
63
64struct cpu_context {
65 unsigned long x19;
66 unsigned long x20;
67 unsigned long x21;
68 unsigned long x22;
69 unsigned long x23;
70 unsigned long x24;
71 unsigned long x25;
72 unsigned long x26;
73 unsigned long x27;
74 unsigned long x28;
75 unsigned long fp;
76 unsigned long sp;
77 unsigned long pc;
78};
79
80struct thread_struct {
81 struct cpu_context cpu_context; /* cpu context */
Will Deacond00a3812015-05-27 15:39:40 +010082 unsigned long tp_value; /* TLS register */
83#ifdef CONFIG_COMPAT
84 unsigned long tp2_value;
85#endif
Catalin Marinas9cce7a42012-03-05 11:49:28 +000086 struct fpsimd_state fpsimd_state;
87 unsigned long fault_address; /* fault info */
Catalin Marinas91413002014-04-06 23:04:12 +010088 unsigned long fault_code; /* ESR_EL1 value */
Catalin Marinas9cce7a42012-03-05 11:49:28 +000089 struct debug_info debug; /* debugging */
90};
91
Will Deacond00a3812015-05-27 15:39:40 +010092#ifdef CONFIG_COMPAT
93#define task_user_tls(t) \
94({ \
95 unsigned long *__tls; \
96 if (is_compat_thread(task_thread_info(t))) \
97 __tls = &(t)->thread.tp2_value; \
98 else \
99 __tls = &(t)->thread.tp_value; \
100 __tls; \
101 })
102#else
103#define task_user_tls(t) (&(t)->thread.tp_value)
104#endif
105
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000106#define INIT_THREAD { }
107
108static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
109{
110 memset(regs, 0, sizeof(*regs));
111 regs->syscallno = ~0UL;
112 regs->pc = pc;
113}
114
115static inline void start_thread(struct pt_regs *regs, unsigned long pc,
116 unsigned long sp)
117{
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000118 start_thread_common(regs, pc);
119 regs->pstate = PSR_MODE_EL0t;
120 regs->sp = sp;
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000121}
122
123#ifdef CONFIG_COMPAT
124static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
125 unsigned long sp)
126{
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000127 start_thread_common(regs, pc);
128 regs->pstate = COMPAT_PSR_MODE_USR;
129 if (pc & 1)
130 regs->pstate |= COMPAT_PSR_T_BIT;
Will Deacona795a382013-10-11 14:52:12 +0100131
132#ifdef __AARCH64EB__
133 regs->pstate |= COMPAT_PSR_E_BIT;
134#endif
135
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000136 regs->compat_sp = sp;
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000137}
138#endif
139
140/* Forward declaration, a strange C thing */
141struct task_struct;
142
143/* Free all resources held by a thread. */
144extern void release_thread(struct task_struct *);
145
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000146unsigned long get_wchan(struct task_struct *p);
147
Peter Crosthwaite1baa82f2015-03-02 19:19:14 +0000148static inline void cpu_relax(void)
149{
150 asm volatile("yield" ::: "memory");
151}
152
Davidlohr Bueso3a6bfbc2014-06-29 15:09:33 -0700153#define cpu_relax_lowlatency() cpu_relax()
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000154
155/* Thread switching */
156extern struct task_struct *cpu_switch_to(struct task_struct *prev,
157 struct task_struct *next);
158
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000159#define task_pt_regs(p) \
160 ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
161
Catalin Marinasebe61522014-07-10 11:37:40 +0100162#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
Will Deacon3168a742014-08-29 16:11:10 +0100163#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000164
165/*
166 * Prefetching support
167 */
168#define ARCH_HAS_PREFETCH
169static inline void prefetch(const void *ptr)
170{
171 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
172}
173
174#define ARCH_HAS_PREFETCHW
175static inline void prefetchw(const void *ptr)
176{
177 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
178}
179
180#define ARCH_HAS_SPINLOCK_PREFETCH
Will Deaconcd5e10b2016-02-02 12:46:23 +0000181static inline void spin_lock_prefetch(const void *ptr)
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000182{
Will Deaconcd5e10b2016-02-02 12:46:23 +0000183 asm volatile(ARM64_LSE_ATOMIC_INSN(
184 "prfm pstl1strm, %a0",
185 "nop") : : "p" (ptr));
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000186}
187
188#define HAVE_ARCH_PICK_MMAP_LAYOUT
189
190#endif
191
Suzuki K. Poulosedbb4e152015-10-19 14:24:50 +0100192void cpu_enable_pan(void *__unused);
James Morse338d4f42015-07-22 19:05:54 +0100193
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000194#endif /* __ASM_PROCESSOR_H */