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gerrit-public.fairphone.software / kernel / msm-5.4 / cd622017eb3e0ab841502df88fb7fda3c3a58eb9 / . / drivers / pinctrl / sh-pfc / pfc-r8a7778.c
blob: f9039102bb433fc16c3d0899ee3187fbba9e516f [file] [log] [blame]
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1/*
2 * r8a7778 processor support - PFC hardware block
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Vladimir Barinov2d7cd392013-05-09 03:14:35 +0400[diff] [blame]6 * Copyright (C) 2013 Cogent Embedded, Inc.
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]7 *
8 * based on
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 * Copyright (C) 2011 Magnus Damm
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/platform_data/gpio-rcar.h>
23#include <linux/kernel.h>
24#include "sh_pfc.h"
25
26#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
27
28#define PORT_GP_32(bank, fn, sfx) \
29 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
30 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
31 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
32 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
33 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
34 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
35 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
36 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
37 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
38 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
39 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
40 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
41 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
42 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
43 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
44 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
45
46#define PORT_GP_27(bank, fn, sfx) \
47 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
48 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
49 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
50 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
51 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
52 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
53 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
54 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
55 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
56 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
57 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
58 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
59 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
60 PORT_GP_1(bank, 26, fn, sfx)
61
62#define CPU_ALL_PORT(fn, sfx) \
63 PORT_GP_32(0, fn, sfx), \
64 PORT_GP_32(1, fn, sfx), \
65 PORT_GP_32(2, fn, sfx), \
66 PORT_GP_32(3, fn, sfx), \
67 PORT_GP_27(4, fn, sfx)
68
69#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
70
71#define _GP_GPIO(bank, pin, _name, sfx) \
72 [RCAR_GP_PIN(bank, pin)] = { \
73 .name = __stringify(_name), \
74 .enum_id = _name##_DATA, \
75 }
76
77#define _GP_DATA(bank, pin, name, sfx) \
78 PINMUX_DATA(name##_DATA, name##_FN)
79
80#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
81#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
82#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
83
84#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn)
85#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
86#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
87#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
88
89enum {
90 PINMUX_RESERVED = 0,
91
92 PINMUX_DATA_BEGIN,
93 GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
94 PINMUX_DATA_END,
95
96 PINMUX_FUNCTION_BEGIN,
97 GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
98
99 /* GPSR0 */
100 FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2,
101 FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1,
102 FN_A2, FN_A3, FN_IP0_15, FN_IP0_16,
103 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20,
104 FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24,
105 FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28,
106 FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1,
107 FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11,
108
109 /* GPSR1 */
110 FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25,
111 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6,
112 FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17,
113 FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2,
114 FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13,
115 FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24,
116 FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30,
117 FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4,
118
119 /* GPSR2 */
120 FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11,
121 FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21,
122 FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0,
123 FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7,
124 FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13,
125 FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB,
126 FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29,
127 FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7,
128
129 /* GPSR3 */
130 FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10,
131 FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16,
132 FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22,
133 FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30,
134 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6,
135 FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
136 FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29,
137 FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9,
138
139 /* GPSR4 */
140 FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19,
141 FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0,
142 FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12,
143 FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24,
144 FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6,
145 FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19,
146 FN_IP10_24_22, FN_AVS1, FN_AVS2,
147
148 /* IPSR0 */
149 FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0,
150 FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B,
151 FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C,
152 FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A,
153 FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A,
154 FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0,
155 FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5,
156 FN_A6, FN_A7, FN_A8, FN_A9,
157 FN_A10, FN_A11, FN_A12, FN_A13,
158 FN_A14, FN_A15, FN_A16, FN_A17,
159 FN_A18, FN_A19,
160
161 /* IPSR1 */
162 FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B,
163 FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
164 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
165 FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24,
166 FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A,
167 FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A,
168 FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT,
169 FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B,
170 FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
171 FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR,
172 FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0,
173 FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1,
174 FN_MMC_D4,
175
176 /* IPSR2 */
177 FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2,
178 FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3,
179 FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4,
180 FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A,
181 FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A,
182 FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0,
183 FN_PWM0_C, FN_D0, FN_D1, FN_D2,
184 FN_D3, FN_D4, FN_D5, FN_D6,
185 FN_D7, FN_D8, FN_D9, FN_D10,
186 FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK,
187 FN_IRQ1_A,
188
189 /* IPSR3 */
190 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
191 FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
192 FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B,
193 FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A,
194 FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A,
195 FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
196 FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B,
197 FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0,
198 FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2,
199 FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4,
200 FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3,
201 FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
202 FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3,
203 FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5,
204 FN_DU0_DR6, FN_LCDOUT6,
205
206 /* IPSR4 */
207 FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
208 FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D,
209 FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9,
210 FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D,
211 FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10,
212 FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12,
213 FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B,
214 FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7,
215 FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B,
216 FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6,
217 FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B,
218 FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
219 FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A,
220 FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2,
221 FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19,
222 FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20,
223
224 /* IPSR5 */
225 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B,
226 FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B,
227 FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN,
228 FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK,
229 FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A,
230 FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
231 FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
232 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
233 FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP,
234 FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK,
235 FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB,
236 FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D,
237 FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
238 FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
239 FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B,
240 FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B,
241 FN_RX2_A, FN_CAN0_RX_B,
242
243 /* IPSR6 */
244 FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B,
245 FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B,
246 FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5,
247 FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5,
248 FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8,
249 FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9,
250 FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
251 FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
252 FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12,
253 FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13,
254 FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
255 FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0,
256 FN_ARM_TRACEDATA_15,
257 FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST,
258 FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK,
259 FN_SD0_DAT2, FN_SUB_TDI,
260
261 /* IPSR7 */
262 FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A,
263 FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A,
264 FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A,
265 FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A,
266 FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC,
267 FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C,
268 FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C,
269 FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A,
270 FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
271 FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B,
272 FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A,
273 FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2,
274 FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B,
275
276 /* IPSR8 */
277 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
278 FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0,
279 FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1,
280 FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2,
281 FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3,
282 FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4,
283 FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5,
284 FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B,
285 FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A,
286 FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
287 FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4,
288 FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B,
289 FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B,
290
291 /* IPSR9 */
292 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
293 FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7,
294 FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK,
295 FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A,
296 FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2,
297 FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7,
298 FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV,
299 FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN,
300 FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER,
301 FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A,
302 FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C,
303 FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A,
304 FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C,
305 FN_RX2_D, FN_SCL2_C,
306
307 /* IPSR10 */
308 FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1,
309 FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A,
310 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1,
311 FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP,
312 FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A,
313 FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
314 FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A,
315 FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B,
316 FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B,
317 FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A,
318 FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B,
319 FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B,
320 FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C,
321
322 /* SEL */
323 FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
324 FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
325 FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
326 FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
327 FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
328 FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
329 FN_SEL_SSI2_A, FN_SEL_SSI2_B,
330 FN_SEL_SSI1_A, FN_SEL_SSI1_B,
331 FN_SEL_VI1_A, FN_SEL_VI1_B,
332 FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D,
333 FN_SEL_SD2_A, FN_SEL_SD2_B,
334 FN_SEL_SD1_A, FN_SEL_SD1_B,
335 FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
336 FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C,
337 FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
338 FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
339 FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
340 FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
341 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
342 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
343 FN_SEL_CAN1_A, FN_SEL_CAN1_B,
344 FN_SEL_CAN0_A, FN_SEL_CAN0_B,
345 FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
346 FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
347 FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
348 FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
349 FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C,
350 FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D,
351 FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C,
352 FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
353 FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
354 FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
355 FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
356 FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C,
357 FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C,
358 FN_SEL_I2C1_A, FN_SEL_I2C1_B,
359 PINMUX_FUNCTION_END,
360
361 PINMUX_MARK_BEGIN,
362
363 /* GPSR0 */
364 PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK,
365
366 /* GPSR1 */
367 WE0_MARK,
368
369 /* GPSR2 */
370 AUDIO_CLKA_MARK,
371 AUDIO_CLKB_MARK,
372
373 /* GPSR3 */
374 SSI_SCK34_MARK,
375
376 /* GPSR4 */
377 AVS1_MARK,
378 AVS2_MARK,
379
Laurent Pinchart0eef12d72013-04-23 11:08:05 +0000[diff] [blame]380 VI0_R0_C_MARK, /* see sel_vi0 */
381 VI0_R1_C_MARK, /* see sel_vi0 */
382 VI0_R2_C_MARK, /* see sel_vi0 */
383 /* VI0_R3_C_MARK, */
384 VI0_R4_C_MARK, /* see sel_vi0 */
385 VI0_R5_C_MARK, /* see sel_vi0 */
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]386
Laurent Pinchart0eef12d72013-04-23 11:08:05 +0000[diff] [blame]387 VI0_R0_D_MARK, /* see sel_vi0 */
388 VI0_R1_D_MARK, /* see sel_vi0 */
389 VI0_R2_D_MARK, /* see sel_vi0 */
390 VI0_R3_D_MARK, /* see sel_vi0 */
391 VI0_R4_D_MARK, /* see sel_vi0 */
392 VI0_R5_D_MARK, /* see sel_vi0 */
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]393
394 /* IPSR0 */
395 PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK,
396 ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK,
397 TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK,
398 GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK,
399 SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK,
400 ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK,
401 MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK,
402 A4_MARK, A5_MARK, A6_MARK, A7_MARK,
403 A8_MARK, A9_MARK, A10_MARK, A11_MARK,
404 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
405 A16_MARK, A17_MARK, A18_MARK, A19_MARK,
406
407 /* IPSR1 */
408 A20_MARK, HSPI_CS1_B_MARK, A21_MARK,
409 HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK,
410 RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK,
411 TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK,
412 SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK,
413 HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK,
414 MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK,
415 RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK,
416 HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK,
417 HSPI_RX1_B_MARK, SSI_SCK1_B_MARK,
418 ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK,
419 MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK,
420 ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK,
421 TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK,
422
423 /* IPSR2 */
424 SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK,
425 SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK,
426 SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK,
427 EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK,
428 MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK,
429 DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK,
430 DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK,
431 D1_MARK, D2_MARK, D3_MARK, D4_MARK,
432 D5_MARK, D6_MARK, D7_MARK, D8_MARK,
433 D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK,
434 IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK,
435
436 /* IPSR3 */
437 MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK,
438 MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK,
439 SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK,
440 CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK,
441 TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK,
442 RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK,
443 SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK,
444 HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK,
445 HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK,
446 DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK,
447 SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK,
448 SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK,
449 ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK,
450 TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
451 DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
452 DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
453
454 /* IPSR4 */
455 DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
456 AUDATA4_MARK, ARM_TRACEDATA_4_MARK,
457 TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK,
458 LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK,
459 RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK,
460 LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK,
461 LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK,
462 TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK,
463 DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK,
464 VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK,
465 ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK,
466 ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK,
467 VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK,
468 ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK,
469 TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
470 VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK,
471 DU0_DB4_MARK, LCDOUT20_MARK,
472
473 /* IPSR5 */
474 VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK,
475 DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK,
476 DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK,
477 QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
478 QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK,
479 AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK,
480 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
481 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
482 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
483 QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK,
484 DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK,
485 BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK,
486 AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK,
487 SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK,
488 TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK,
489 RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK,
490 SSI_SCK2_A_MARK, HSPI_CS0_B_MARK,
491 TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK,
492 HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK,
493
494 /* IPSR6 */
495 SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK,
496 CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK,
497 BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK,
498 HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK,
499 RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK,
500 RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK,
501 SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
502 SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK,
503 SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK,
504 TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
505 SSI_SDATA2_MARK, HSPI_CS2_A_MARK,
506 ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK,
507 ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK,
508 SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK,
509 SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK,
510 SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK,
511 SD0_DAT2_MARK, SUB_TDI_MARK,
512
513 /* IPSR7 */
514 SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK,
515 SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK,
516 HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK,
517 HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK,
518 HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK,
519 VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK,
520 TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK,
521 IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK,
522 CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK,
523 VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK,
524 RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK,
525 VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK,
526 TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK,
527 DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK,
528
529 /* IPSR8 */
530 VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK,
531 HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK,
532 DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK,
533 DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK,
534 DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK,
535 DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK,
536 DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK,
537 DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK,
538 VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK,
539 PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK,
540 RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK,
541 DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK,
542 VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK,
543
544 /* IPSR9 */
545 VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK,
546 DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK,
547 VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK,
548 VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK,
549 VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK,
550 PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK,
551 DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK,
552 ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK,
553 VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK,
554 TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK,
555 IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK,
556 DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK,
557 BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK,
558 DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK,
559 RX2_D_MARK, SCL2_C_MARK,
560
561 /* IPSR10 */
562 SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK,
563 ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK,
564 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK,
565 ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK,
566 DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK,
567 CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK,
568 ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK,
569 PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK,
570 DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK,
571 GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK,
572 DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK,
573 GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK,
574 EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK,
575 REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK,
576 EX_WAIT2_B_MARK, DACK0_B_MARK,
577 HSPI_TX2_B_MARK, CAN_CLK_C_MARK,
578
579 PINMUX_MARK_END,
580};
581
582static const pinmux_enum_t pinmux_data[] = {
583 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
584
585 PINMUX_DATA(PENC0_MARK, FN_PENC0),
586 PINMUX_DATA(PENC1_MARK, FN_PENC1),
587 PINMUX_DATA(A1_MARK, FN_A1),
588 PINMUX_DATA(A2_MARK, FN_A2),
589 PINMUX_DATA(A3_MARK, FN_A3),
590 PINMUX_DATA(WE0_MARK, FN_WE0),
591 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
592 PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB),
593 PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34),
594 PINMUX_DATA(AVS1_MARK, FN_AVS1),
595 PINMUX_DATA(AVS2_MARK, FN_AVS2),
596
597 /* IPSR0 */
598 PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT),
599 PINMUX_IPSR_DATA(IP0_1_0, PWM1),
600
601 PINMUX_IPSR_DATA(IP0_4_2, AUDATA0),
602 PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0),
603 PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C),
604 PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0),
605 PINMUX_IPSR_DATA(IP0_4_2, TX2_E),
606 PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B),
607
608 PINMUX_IPSR_DATA(IP0_7_5, AUDATA1),
609 PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1),
610 PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C),
611 PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1),
612 PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E),
613 PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B),
614
615 PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A),
616 PINMUX_IPSR_DATA(IP0_11_8, MMC_D2),
617 PINMUX_IPSR_DATA(IP0_11_8, BS),
618 PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A),
619 PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A),
620 PINMUX_IPSR_DATA(IP0_11_8, PWM4_B),
621
622 PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A),
623 PINMUX_IPSR_DATA(IP0_14_12, MMC_D3),
624 PINMUX_IPSR_DATA(IP0_14_12, A0),
625 PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A),
626 PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B),
627
628 PINMUX_IPSR_DATA(IP0_15, A4),
629 PINMUX_IPSR_DATA(IP0_16, A5),
630 PINMUX_IPSR_DATA(IP0_17, A6),
631 PINMUX_IPSR_DATA(IP0_18, A7),
632 PINMUX_IPSR_DATA(IP0_19, A8),
633 PINMUX_IPSR_DATA(IP0_20, A9),
634 PINMUX_IPSR_DATA(IP0_21, A10),
635 PINMUX_IPSR_DATA(IP0_22, A11),
636 PINMUX_IPSR_DATA(IP0_23, A12),
637 PINMUX_IPSR_DATA(IP0_24, A13),
638 PINMUX_IPSR_DATA(IP0_25, A14),
639 PINMUX_IPSR_DATA(IP0_26, A15),
640 PINMUX_IPSR_DATA(IP0_27, A16),
641 PINMUX_IPSR_DATA(IP0_28, A17),
642 PINMUX_IPSR_DATA(IP0_29, A18),
643 PINMUX_IPSR_DATA(IP0_30, A19),
644
645 /* IPSR1 */
646 PINMUX_IPSR_DATA(IP1_0, A20),
647 PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B),
648
649 PINMUX_IPSR_DATA(IP1_1, A21),
650 PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B),
651
652 PINMUX_IPSR_DATA(IP1_4_2, A22),
653 PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B),
654 PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B),
655 PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A),
656
657 PINMUX_IPSR_DATA(IP1_7_5, A23),
658 PINMUX_IPSR_DATA(IP1_7_5, HTX0_B),
659 PINMUX_IPSR_DATA(IP1_7_5, TX2_B),
660 PINMUX_IPSR_DATA(IP1_7_5, DACK2_A),
661 PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A),
662
663 PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A),
664 PINMUX_IPSR_DATA(IP1_10_8, MMC_D6),
665 PINMUX_IPSR_DATA(IP1_10_8, A24),
666 PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A),
667 PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B),
668 PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A),
669
670 PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A),
671 PINMUX_IPSR_DATA(IP1_14_11, MMC_D7),
672 PINMUX_IPSR_DATA(IP1_14_11, A25),
673 PINMUX_IPSR_DATA(IP1_14_11, DACK1_A),
674 PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B),
675 PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C),
676 PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A),
677
678 PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT),
679 PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B),
680 PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B),
681
682 PINMUX_IPSR_NOGP(IP1_17, CS0),
683 PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B),
684
685 PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B),
686 PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B),
687 PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26),
688 PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A),
689 PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B),
690
691 PINMUX_IPSR_DATA(IP1_23_21, MMC_D5),
692 PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B),
693 PINMUX_IPSR_DATA(IP1_23_21, RD_WR),
694
695 PINMUX_IPSR_DATA(IP1_24, WE1),
696 PINMUX_IPSR_DATA(IP1_24, ATAWR0_B),
697
698 PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B),
699 PINMUX_IPSR_DATA(IP1_27_25, EX_CS0),
700 PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A),
701 PINMUX_IPSR_DATA(IP1_27_25, TX3_C),
702 PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A),
703
704 PINMUX_IPSR_DATA(IP1_29_28, EX_CS1),
705 PINMUX_IPSR_DATA(IP1_29_28, MMC_D4),
706
707 /* IPSR2 */
708 PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A),
709 PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK),
710 PINMUX_IPSR_DATA(IP2_2_0, ATACS00),
711 PINMUX_IPSR_DATA(IP2_2_0, EX_CS2),
712
713 PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A),
714 PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD),
715 PINMUX_IPSR_DATA(IP2_5_3, ATACS10),
716 PINMUX_IPSR_DATA(IP2_5_3, EX_CS3),
717
718 PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A),
719 PINMUX_IPSR_DATA(IP2_8_6, MMC_D0),
720 PINMUX_IPSR_DATA(IP2_8_6, ATARD0),
721 PINMUX_IPSR_DATA(IP2_8_6, EX_CS4),
722 PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A),
723
724 PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A),
725 PINMUX_IPSR_DATA(IP2_11_9, MMC_D1),
726 PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A),
727 PINMUX_IPSR_DATA(IP2_11_9, EX_CS5),
728 PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A),
729
730 PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A),
731 PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A),
732
733 PINMUX_IPSR_DATA(IP2_16_14, DACK0),
734 PINMUX_IPSR_DATA(IP2_16_14, TX3_A),
735 PINMUX_IPSR_DATA(IP2_16_14, DRACK0),
736
737 PINMUX_IPSR_DATA(IP2_17, EX_WAIT0),
738 PINMUX_IPSR_DATA(IP2_17, PWM0_C),
739
740 PINMUX_IPSR_NOGP(IP2_18, D0),
741 PINMUX_IPSR_NOGP(IP2_19, D1),
742 PINMUX_IPSR_NOGP(IP2_20, D2),
743 PINMUX_IPSR_NOGP(IP2_21, D3),
744 PINMUX_IPSR_NOGP(IP2_22, D4),
745 PINMUX_IPSR_NOGP(IP2_23, D5),
746 PINMUX_IPSR_NOGP(IP2_24, D6),
747 PINMUX_IPSR_NOGP(IP2_25, D7),
748 PINMUX_IPSR_NOGP(IP2_26, D8),
749 PINMUX_IPSR_NOGP(IP2_27, D9),
750 PINMUX_IPSR_NOGP(IP2_28, D10),
751 PINMUX_IPSR_NOGP(IP2_29, D11),
752
753 PINMUX_IPSR_DATA(IP2_30, RD_WR_B),
754 PINMUX_IPSR_DATA(IP2_30, IRQ0),
755
756 PINMUX_IPSR_DATA(IP2_31, MLB_CLK),
757 PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A),
758
759 /* IPSR3 */
760 PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG),
761 PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B),
762 PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A),
763 PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A),
764
765 PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT),
766 PINMUX_IPSR_DATA(IP3_4_2, TX5_B),
767 PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A),
768 PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A),
769 PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B),
770
771 PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B),
772 PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK),
773 PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B),
774 PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B),
775 PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B),
776
777 PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B),
778 PINMUX_IPSR_DATA(IP3_9_8, HTX0_A),
779 PINMUX_IPSR_DATA(IP3_9_8, TX0_A),
780
781 PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B),
782 PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A),
783 PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A),
784
785 PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B),
786 PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A),
787 PINMUX_IPSR_DATA(IP3_15_13, SCK0),
788 PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B),
789
790 PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B),
791 PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A),
792 PINMUX_IPSR_DATA(IP3_18_16, CTS0),
793
794 PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B),
795 PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A),
796 PINMUX_IPSR_DATA(IP3_20_19, RTS0),
797
798 PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4),
799 PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0),
800 PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0),
801 PINMUX_IPSR_DATA(IP3_23_21, AUDATA2),
802 PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2),
803 PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C),
804 PINMUX_IPSR_DATA(IP3_23_21, ADICHS1),
805 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B),
806
807 PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4),
808 PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1),
809 PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1),
810 PINMUX_IPSR_DATA(IP3_26_24, AUDATA3),
811 PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3),
812 PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C),
813 PINMUX_IPSR_DATA(IP3_26_24, ADICHS2),
814 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B),
815
816 PINMUX_IPSR_DATA(IP3_27, DU0_DR2),
817 PINMUX_IPSR_DATA(IP3_27, LCDOUT2),
818
819 PINMUX_IPSR_DATA(IP3_28, DU0_DR3),
820 PINMUX_IPSR_DATA(IP3_28, LCDOUT3),
821
822 PINMUX_IPSR_DATA(IP3_29, DU0_DR4),
823 PINMUX_IPSR_DATA(IP3_29, LCDOUT4),
824
825 PINMUX_IPSR_DATA(IP3_30, DU0_DR5),
826 PINMUX_IPSR_DATA(IP3_30, LCDOUT5),
827
828 PINMUX_IPSR_DATA(IP3_31, DU0_DR6),
829 PINMUX_IPSR_DATA(IP3_31, LCDOUT6),
830
831 /* IPSR4 */
832 PINMUX_IPSR_DATA(IP4_0, DU0_DR7),
833 PINMUX_IPSR_DATA(IP4_0, LCDOUT7),
834
835 PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0),
836 PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8),
837 PINMUX_IPSR_DATA(IP4_3_1, AUDATA4),
838 PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4),
839 PINMUX_IPSR_DATA(IP4_3_1, TX1_D),
840 PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A),
841 PINMUX_IPSR_DATA(IP4_3_1, ADICHS0),
842
843 PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1),
844 PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9),
845 PINMUX_IPSR_DATA(IP4_6_4, AUDATA5),
846 PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5),
847 PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D),
848 PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A),
849 PINMUX_IPSR_DATA(IP4_6_4, ADIDATA),
850
851 PINMUX_IPSR_DATA(IP4_7, DU0_DG2),
852 PINMUX_IPSR_DATA(IP4_7, LCDOUT10),
853
854 PINMUX_IPSR_DATA(IP4_8, DU0_DG3),
855 PINMUX_IPSR_DATA(IP4_8, LCDOUT11),
856
857 PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4),
858 PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12),
859 PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B),
860
861 PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5),
862 PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13),
863 PINMUX_IPSR_DATA(IP4_12_11, TX0_B),
864
865 PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6),
866 PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14),
867 PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A),
868
869 PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7),
870 PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15),
871 PINMUX_IPSR_DATA(IP4_16_15, TX4_A),
872
873 PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B),
874 PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */
875 PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */
876 PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0),
877 PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16),
878 PINMUX_IPSR_DATA(IP4_20_17, AUDATA6),
879 PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6),
880 PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A),
881 PINMUX_IPSR_DATA(IP4_20_17, PWM0_A),
882 PINMUX_IPSR_DATA(IP4_20_17, ADICLK),
883 PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B),
884
885 PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC),
886 PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */
887 PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */
888 PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1),
889 PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17),
890 PINMUX_IPSR_DATA(IP4_24_21, AUDATA7),
891 PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7),
892 PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A),
893 PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP),
894 PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B),
895
896 PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */
897 PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */
898 PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2),
899 PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18),
900
901 PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B),
902 PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3),
903 PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19),
904
905 PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */
906 PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */
907 PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4),
908 PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20),
909
910 /* IPSR5 */
911 PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */
912 PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */
913 PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5),
914 PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21),
915
916 PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B),
917 PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6),
918 PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22),
919
920 PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B),
921 PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7),
922 PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23),
923
924 PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN),
925 PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS),
926
927 PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0),
928 PINMUX_IPSR_DATA(IP5_7, QCLK),
929
930 PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1),
931 PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE),
932 PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A),
933 PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C),
934
935 PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B),
936 PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC),
937 PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS),
938
939 PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC),
940 PINMUX_IPSR_DATA(IP5_12, QSTB_QHE),
941
942 PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE),
943 PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE),
944 PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D),
945
946 PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A),
947 PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP),
948 PINMUX_IPSR_DATA(IP5_17_15, QPOLA),
949 PINMUX_IPSR_DATA(IP5_17_15, AUDCK),
950 PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK),
951 PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D),
952
953 PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A),
954 PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE),
955 PINMUX_IPSR_DATA(IP5_20_18, QPOLB),
956 PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC),
957 PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL),
958 PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D),
959
960 PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B),
961 PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78),
962 PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B),
963 PINMUX_IPSR_DATA(IP5_22_21, TX1_B),
964
965 PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B),
966 PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78),
967 PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B),
968 PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B),
969 PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D),
970
971 PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8),
972 PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A),
973 PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B),
974 PINMUX_IPSR_DATA(IP5_28_26, TX2_A),
975 PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B),
976
977 PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7),
978 PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B),
979 PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A),
980 PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B),
981
982 /* IPSR6 */
983 PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6),
984 PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A),
985 PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B),
986 PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B),
987
988 PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6),
989 PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A),
990 PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B),
991 PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B),
992
993 PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6),
994 PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A),
995 PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B),
996
997 PINMUX_IPSR_DATA(IP6_7, SSI_SCK5),
998 PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C),
999
1000 PINMUX_IPSR_DATA(IP6_8, SSI_WS5),
1001 PINMUX_IPSR_DATA(IP6_8, TX4_C),
1002
1003 PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5),
1004 PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D),
1005
1006 PINMUX_IPSR_DATA(IP6_10, SSI_WS34),
1007 PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8),
1008
1009 PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4),
1010 PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A),
1011 PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9),
1012
1013 PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3),
1014 PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10),
1015
1016 PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012),
1017 PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11),
1018 PINMUX_IPSR_DATA(IP6_15_14, TX0_D),
1019
1020 PINMUX_IPSR_DATA(IP6_16, SSI_WS012),
1021 PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12),
1022
1023 PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2),
1024 PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A),
1025 PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13),
1026 PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A),
1027
1028 PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1),
1029 PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14),
1030 PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A),
1031 PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A),
1032
1033 PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0),
1034 PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15),
1035
1036 PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK),
1037 PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO),
1038
1039 PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD),
1040 PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST),
1041
1042 PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0),
1043 PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS),
1044
1045 PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1),
1046 PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK),
1047
1048 PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2),
1049 PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI),
1050
1051 /* IPSR7 */
1052 PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3),
1053 PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B),
1054
1055 PINMUX_IPSR_DATA(IP7_3_2, SD0_CD),
1056 PINMUX_IPSR_DATA(IP7_3_2, TX5_A),
1057
1058 PINMUX_IPSR_DATA(IP7_5_4, SD0_WP),
1059 PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A),
1060
1061 PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB),
1062 PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A),
1063 PINMUX_IPSR_DATA(IP7_8_6, HTX1_A),
1064 PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C),
1065
1066 PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD),
1067 PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A),
1068 PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A),
1069 PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C),
1070
1071 PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC),
1072 PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A),
1073 PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A),
1074 PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A),
1075 PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C),
1076
1077 PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC),
1078 PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0),
1079 PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A),
1080 PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A),
1081 PINMUX_IPSR_DATA(IP7_17_15, TX1_C),
1082
1083 PINMUX_IPSR_DATA(IP7_20_18, TCLK0),
1084 PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A),
1085 PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A),
1086 PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C),
1087 PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C),
1088 PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN),
1089
1090 PINMUX_IPSR_DATA(IP7_21, VI0_CLK),
1091 PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A),
1092
1093 PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB),
1094 PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B),
1095 PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0),
1096 PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6),
1097 PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A),
1098 PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B),
1099
1100 PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD),
1101 PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B),
1102 PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */
1103 PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */
1104 PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1),
1105 PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7),
1106 PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A),
1107 PINMUX_IPSR_DATA(IP7_28_25, TX4_B),
1108
1109 PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC),
1110 PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B),
1111 PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2),
1112 PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2),
1113 PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A),
1114 PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B),
1115
1116 /* IPSR8 */
1117 PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC),
1118 PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B),
1119 PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3),
1120 PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3),
1121 PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A),
1122 PINMUX_IPSR_DATA(IP8_2_0, TX3_B),
1123
1124 PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0),
1125 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2),
1126 PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B),
1127 PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D),
1128
1129 PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1),
1130 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3),
1131 PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B),
1132 PINMUX_IPSR_DATA(IP8_8_6, TX3_D),
1133
1134 PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2),
1135 PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4),
1136 PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C),
1137
1138 PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3),
1139 PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5),
1140 PINMUX_IPSR_DATA(IP8_13_11, TX1_A),
1141 PINMUX_IPSR_DATA(IP8_13_11, TX0_C),
1142
1143 PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4),
1144 PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2),
1145 PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A),
1146
1147 PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5),
1148 PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3),
1149 PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A),
1150 PINMUX_IPSR_DATA(IP8_18_16, PWM4),
1151 PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B),
1152
1153 PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0),
1154 PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4),
1155 PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A),
1156 PINMUX_IPSR_DATA(IP8_21_19, PWM5),
1157
1158 PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1),
1159 PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5),
1160 PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A),
1161
1162 PINMUX_IPSR_DATA(IP8_26_24, VI0_G2),
1163 PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B),
1164 PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4),
1165 PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4),
1166 PINMUX_IPSR_DATA(IP8_26_24, HTX1_B),
1167
1168 PINMUX_IPSR_DATA(IP8_29_27, VI0_G3),
1169 PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B),
1170 PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5),
1171 PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5),
1172 PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B),
1173
1174 /* IPSR9 */
1175 PINMUX_IPSR_DATA(IP9_2_0, VI0_G4),
1176 PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B),
1177 PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6),
1178 PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6),
1179 PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B),
1180
1181 PINMUX_IPSR_DATA(IP9_5_3, VI0_G5),
1182 PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B),
1183 PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7),
1184 PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7),
1185 PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B),
1186
1187 PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */
1188 PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */
1189 PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK),
1190 PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK),
1191 PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN),
1192
1193 PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */
1194 PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */
1195 PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8),
1196 PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6),
1197 PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0),
1198 PINMUX_IPSR_DATA(IP9_11_9, PWM2),
1199 PINMUX_IPSR_DATA(IP9_11_9, TCLK1),
1200
1201 PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */
1202 PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */
1203 PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9),
1204 PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7),
1205 PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1),
1206 PINMUX_IPSR_DATA(IP9_14_12, PWM3),
1207
1208 PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A),
1209 PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV),
1210 PINMUX_IPSR_DATA(IP9_17_15, IECLK),
1211 PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C),
1212
1213 PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */
1214 PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */
1215 PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN),
1216 PINMUX_IPSR_DATA(IP9_20_18, IETX),
1217 PINMUX_IPSR_DATA(IP9_20_18, TX2_C),
1218
1219 PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */
1220 PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */
1221 PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER),
1222 PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C),
1223 PINMUX_IPSR_DATA(IP9_23_21, IERX),
1224 PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C),
1225
1226 PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A),
1227 PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT),
1228 PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0),
1229 PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C),
1230 PINMUX_IPSR_DATA(IP9_26_24, TX2_D),
1231 PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C),
1232
1233 PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A),
1234 PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC),
1235 PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1),
1236 PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C),
1237 PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D),
1238 PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C),
1239
1240 /* IPSR10 */
1241 PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A),
1242 PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC),
1243 PINMUX_IPSR_DATA(IP10_2_0, ATARD1),
1244 PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC),
1245 PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B),
1246
1247 PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A),
1248 PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1249 PINMUX_IPSR_DATA(IP10_5_3, ATAWR1),
1250 PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO),
1251 PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B),
1252
1253 PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A),
1254 PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP),
1255 PINMUX_IPSR_DATA(IP10_8_6, ATACS01),
1256 PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B),
1257 PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1258 PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A),
1259
1260 PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A),
1261 PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE),
1262 PINMUX_IPSR_DATA(IP10_12_9, ATACS11),
1263 PINMUX_IPSR_DATA(IP10_12_9, DACK1_B),
1264 PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC),
1265 PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A),
1266 PINMUX_IPSR_DATA(IP10_12_9, PWM6),
1267
1268 PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A),
1269 PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12),
1270 PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B),
1271 PINMUX_IPSR_DATA(IP10_15_13, ATADIR1),
1272 PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B),
1273 PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B),
1274
1275 PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A),
1276 PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13),
1277 PINMUX_IPSR_DATA(IP10_18_16, DACK2_B),
1278 PINMUX_IPSR_DATA(IP10_18_16, ATAG1),
1279 PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B),
1280 PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B),
1281
1282 PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A),
1283 PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14),
1284 PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B),
1285 PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B),
1286 PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B),
1287 PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A),
1288
1289 PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A),
1290 PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15),
1291 PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B),
1292 PINMUX_IPSR_DATA(IP10_24_22, DACK0_B),
1293 PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B),
1294 PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
1295};
1296
1297static struct sh_pfc_pin pinmux_pins[] = {
1298 PINMUX_GPIO_GP_ALL(),
1299};
1300
1301/* Pin numbers for pins without a corresponding GPIO port number are computed
1302 * from the row and column numbers with a 1000 offset to avoid collisions with
1303 * GPIO port numbers.
1304 */
1305#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
1306
Kuninori Morimotoa10cd302013-04-18 20:07:34 -0700[diff] [blame]1307/* - macro */
1308#define SH_PFC_PINS(name, args...) \
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1309 static const unsigned int name ##_pins[] = { args }
Kuninori Morimotoa10cd302013-04-18 20:07:34 -0700[diff] [blame]1310#define SH_PFC_MUX1(name, arg1) \
1311 static const unsigned int name ##_mux[] = { arg1##_MARK }
1312#define SH_PFC_MUX2(name, arg1, arg2) \
1313 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, }
1314#define SH_PFC_MUX3(name, arg1, arg2, arg3) \
1315 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
1316 arg3##_MARK }
1317#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \
1318 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
1319 arg3##_MARK, arg4##_MARK }
Vladimir Barinov2d7cd392013-05-09 03:14:35 +0400[diff] [blame]1320#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
1321 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
1322 arg3##_MARK, arg4##_MARK, \
1323 arg5##_MARK, arg6##_MARK, \
1324 arg7##_MARK, arg8##_MARK, }
Kuninori Morimotoa10cd302013-04-18 20:07:34 -0700[diff] [blame]1325
Sergei Shtylyov3c5886d2013-05-08 23:15:50 +0000[diff] [blame]1326/* - Ether ------------------------------------------------------------------ */
1327SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1328 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9),
1329 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1330 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14),
1331 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17));
1332static const unsigned int ether_rmii_mux[] = {
1333 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1334 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1335 ETH_MDIO_MARK, ETH_MDC_MARK,
1336};
1337SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19));
1338SH_PFC_MUX1(ether_link, ETH_LINK);
1339SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20));
1340SH_PFC_MUX1(ether_magic, ETH_MAGIC);
1341
Kuninori Morimotoa10cd302013-04-18 20:07:34 -0700[diff] [blame]1342/* - SCIF macro ------------------------------------------------------------- */
1343#define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
1344#define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
1345#define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts)
1346#define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck)
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1347
1348/* - HSCIF0 ----------------------------------------------------------------- */
1349SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
1350SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A);
1351SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30));
1352SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B);
1353SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
1354SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A);
1355SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28));
1356SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B);
1357SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19));
1358SCIF_PFC_CLK(hscif0_clk, HSCK0);
1359
1360/* - HSCIF1 ----------------------------------------------------------------- */
1361SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20));
1362SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A);
1363SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
1364SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B);
1365SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
1366SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A);
1367SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7));
1368SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B);
1369SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23));
1370SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A);
1371SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2));
1372SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B);
1373
Kuninori Morimoto09cc76a2013-05-22 20:16:30 -0700[diff] [blame]1374/* - HSPI macro --------------------------------------------------------------*/
1375#define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
1376#define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx)
1377
1378/* - HSPI0 -------------------------------------------------------------------*/
1379HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
1380 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
1381HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A,
1382 HSPI_RX0_A, HSPI_TX0);
1383
1384HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1385 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27));
1386HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B,
1387 HSPI_RX0_B, HSPI_TX0_B);
1388
1389/* - HSPI1 -------------------------------------------------------------------*/
1390HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
1391 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28));
1392HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A,
1393 HSPI_RX1_A, HSPI_TX1_A);
1394
1395HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26),
1396 PIN_NUMBER(20, 1), PIN_NUMBER(25, 2));
1397HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B,
1398 HSPI_RX1_B, HSPI_TX1_B);
1399
1400/* - HSPI2 -------------------------------------------------------------------*/
1401HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8),
1402 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30));
1403HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A,
1404 HSPI_RX2_A, HSPI_TX2_A);
1405
1406HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
1407 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24));
1408HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B,
1409 HSPI_RX2_B, HSPI_TX2_B);
1410
Kuninori Morimoto0dcbc69e2013-05-22 20:15:53 -0700[diff] [blame]1411/* - I2C macro ------------------------------------------------------------- */
1412#define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
1413#define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl)
1414
1415/* - I2C1 ------------------------------------------------------------------ */
1416I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9));
1417I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A);
1418I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
1419I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B);
1420
1421/* - I2C2 ------------------------------------------------------------------ */
1422I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
1423I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A);
1424I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
1425I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B);
1426I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
1427I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C);
1428
1429/* - I2C3 ------------------------------------------------------------------ */
1430I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15));
1431I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A);
1432I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19));
1433I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B);
1434I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
1435I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C);
1436
Kuninori Morimoto3ef2a772013-05-22 20:17:04 -0700[diff] [blame]1437/* - MMC macro -------------------------------------------------------------- */
1438#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1439#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
1440#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
1441#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
1442#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
1443 SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1444
1445/* - MMC -------------------------------------------------------------------- */
1446MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
1447MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
1448MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
1449MMC_PFC_DAT1(mmc_data1, MMC_D0);
Kuninori Morimotocd622012013-06-11 19:02:20 -0700[diff] [blame^]1450MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
Kuninori Morimoto3ef2a772013-05-22 20:17:04 -0700[diff] [blame]1451 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
1452MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
1453 MMC_D2, MMC_D3);
Kuninori Morimotocd622012013-06-11 19:02:20 -0700[diff] [blame^]1454MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
Kuninori Morimoto3ef2a772013-05-22 20:17:04 -0700[diff] [blame]1455 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1456 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1457 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
1458MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1,
1459 MMC_D2, MMC_D3,
1460 MMC_D4, MMC_D5,
1461 MMC_D6, MMC_D7);
1462
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1463/* - SCIF CLOCK ------------------------------------------------------------- */
1464SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16));
1465SCIF_PFC_CLK(scif_clk, SCIF_CLK);
1466
1467/* - SCIF0 ------------------------------------------------------------------ */
1468SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
1469SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A);
1470SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2));
1471SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B);
1472SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31));
1473SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C);
1474SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1));
1475SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D);
1476SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
1477SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0);
1478SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19));
1479SCIF_PFC_CLK(scif0_clk, SCK0);
1480
1481/* - SCIF1 ------------------------------------------------------------------ */
1482SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1));
1483SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A);
1484SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
1485SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B);
1486SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
1487SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C);
1488SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
1489SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D);
1490SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
1491SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A);
1492SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19));
1493SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C);
1494SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2));
1495SCIF_PFC_CLK(scif1_clk_a, SCK1_A);
1496SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20));
1497SCIF_PFC_CLK(scif1_clk_c, SCK1_C);
1498
1499/* - SCIF2 ------------------------------------------------------------------ */
1500SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
1501SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A);
1502SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28));
1503SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B);
1504SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14));
1505SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C);
1506SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
1507SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D);
1508SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
1509SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E);
1510SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9));
1511SCIF_PFC_CLK(scif2_clk_a, SCK2_A);
1512SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20));
1513SCIF_PFC_CLK(scif2_clk_b, SCK2_B);
1514SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12));
1515SCIF_PFC_CLK(scif2_clk_c, SCK2_C);
1516
1517/* - SCIF3 ------------------------------------------------------------------ */
1518SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9));
1519SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A);
1520SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27));
1521SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B);
1522SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31));
1523SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C);
1524SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29));
1525SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D);
1526
1527/* - SCIF4 ------------------------------------------------------------------ */
1528SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4));
1529SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A);
1530SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25));
1531SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B);
1532SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31));
1533SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C);
1534
1535/* - SCIF5 ------------------------------------------------------------------ */
1536SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18));
1537SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A);
1538SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14));
1539SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B);
1540
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1541/* - SDHI macro ------------------------------------------------------------- */
1542#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1543#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
1544#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
1545#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
1546#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd)
1547#define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp)
1548
1549/* - SDHI0 ------------------------------------------------------------------ */
1550SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17));
1551SDHI_PFC_CDPN(sdhi0_cd, SD0_CD);
1552SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12));
1553SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD);
1554SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13));
1555SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0);
1556SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1557 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16));
1558SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1,
1559 SD0_DAT2, SD0_DAT3);
1560SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18));
1561SDHI_PFC_WPPN(sdhi0_wp, SD0_WP);
1562
1563/* - SDHI1 ------------------------------------------------------------------ */
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1564SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30));
1565SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A);
1566SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24));
1567SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B);
1568SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
1569SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A);
1570SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16));
1571SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B);
1572SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7));
1573SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A);
1574SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18));
1575SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B);
1576SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1577 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1578SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A,
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1579 SD1_DAT2_A, SD1_DAT3_A);
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1580SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1581 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1582SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B,
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1583 SD1_DAT2_B, SD1_DAT3_B);
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1584SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31));
1585SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A);
1586SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25));
1587SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B);
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1588
1589/* - SDH2 ------------------------------------------------------------------- */
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1590SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23));
1591SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A);
1592SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27));
1593SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B);
1594SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
1595SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A);
1596SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
1597SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B);
1598SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19));
1599SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A);
1600SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7));
1601SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B);
1602SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1603 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22));
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1604SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A,
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1605 SD2_DAT2_A, SD2_DAT3_A);
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1606SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1607 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26));
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1608SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B,
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1609 SD2_DAT2_B, SD2_DAT3_B);
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1610SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24));
1611SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
1612SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28));
1613SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B);
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1614
Sergei Shtylyov5cee53b2013-05-08 23:12:47 +0000[diff] [blame]1615/* - USB0 ------------------------------------------------------------------- */
1616SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1));
1617SH_PFC_MUX1(usb0, PENC0);
1618SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3));
1619SH_PFC_MUX1(usb0_ovc, USB_OVC0);
1620
1621/* - USB1 ------------------------------------------------------------------- */
1622SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2));
1623SH_PFC_MUX1(usb1, PENC1);
1624SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4));
1625SH_PFC_MUX1(usb1_ovc, USB_OVC1);
1626
Vladimir Barinov2d7cd392013-05-09 03:14:35 +0400[diff] [blame]1627/* - VIN macros ------------------------------------------------------------- */
1628#define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1629#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
1630 SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1631#define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
1632#define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync)
1633
1634/* - VIN0 ------------------------------------------------------------------- */
1635VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30),
1636 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0),
1637 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
1638 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
1639VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1,
1640 VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3,
1641 VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5,
1642 VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1);
1643VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24));
1644VIN_PFC_CLK(vin0_clk, VI0_CLK);
1645VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28));
1646VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC);
1647/* - VIN1 ------------------------------------------------------------------- */
1648VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1649 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1650 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
1651 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8));
1652VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1,
1653 VI1_DATA2, VI1_DATA3,
1654 VI1_DATA4, VI1_DATA5,
1655 VI1_DATA6, VI1_DATA7);
1656VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9));
1657VIN_PFC_CLK(vin1_clk, VI1_CLK);
1658VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
1659VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC);
1660
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1661static const struct sh_pfc_pin_group pinmux_groups[] = {
Sergei Shtylyov3c5886d2013-05-08 23:15:50 +0000[diff] [blame]1662 SH_PFC_PIN_GROUP(ether_rmii),
1663 SH_PFC_PIN_GROUP(ether_link),
1664 SH_PFC_PIN_GROUP(ether_magic),
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1665 SH_PFC_PIN_GROUP(hscif0_data_a),
1666 SH_PFC_PIN_GROUP(hscif0_data_b),
1667 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
1668 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
1669 SH_PFC_PIN_GROUP(hscif0_clk),
1670 SH_PFC_PIN_GROUP(hscif1_data_a),
1671 SH_PFC_PIN_GROUP(hscif1_data_b),
1672 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
1673 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
1674 SH_PFC_PIN_GROUP(hscif1_clk_a),
1675 SH_PFC_PIN_GROUP(hscif1_clk_b),
Kuninori Morimoto09cc76a2013-05-22 20:16:30 -0700[diff] [blame]1676 SH_PFC_PIN_GROUP(hspi0_a),
1677 SH_PFC_PIN_GROUP(hspi0_b),
1678 SH_PFC_PIN_GROUP(hspi1_a),
1679 SH_PFC_PIN_GROUP(hspi1_b),
1680 SH_PFC_PIN_GROUP(hspi2_a),
1681 SH_PFC_PIN_GROUP(hspi2_b),
Kuninori Morimoto0dcbc69e2013-05-22 20:15:53 -0700[diff] [blame]1682 SH_PFC_PIN_GROUP(i2c1_a),
1683 SH_PFC_PIN_GROUP(i2c1_b),
1684 SH_PFC_PIN_GROUP(i2c2_a),
1685 SH_PFC_PIN_GROUP(i2c2_b),
1686 SH_PFC_PIN_GROUP(i2c2_c),
1687 SH_PFC_PIN_GROUP(i2c3_a),
1688 SH_PFC_PIN_GROUP(i2c3_b),
1689 SH_PFC_PIN_GROUP(i2c3_c),
Kuninori Morimoto3ef2a772013-05-22 20:17:04 -0700[diff] [blame]1690 SH_PFC_PIN_GROUP(mmc_ctrl),
1691 SH_PFC_PIN_GROUP(mmc_data1),
1692 SH_PFC_PIN_GROUP(mmc_data4),
1693 SH_PFC_PIN_GROUP(mmc_data8),
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1694 SH_PFC_PIN_GROUP(scif_clk),
1695 SH_PFC_PIN_GROUP(scif0_data_a),
1696 SH_PFC_PIN_GROUP(scif0_data_b),
1697 SH_PFC_PIN_GROUP(scif0_data_c),
1698 SH_PFC_PIN_GROUP(scif0_data_d),
1699 SH_PFC_PIN_GROUP(scif0_ctrl),
1700 SH_PFC_PIN_GROUP(scif0_clk),
1701 SH_PFC_PIN_GROUP(scif1_data_a),
1702 SH_PFC_PIN_GROUP(scif1_data_b),
1703 SH_PFC_PIN_GROUP(scif1_data_c),
1704 SH_PFC_PIN_GROUP(scif1_data_d),
1705 SH_PFC_PIN_GROUP(scif1_ctrl_a),
1706 SH_PFC_PIN_GROUP(scif1_ctrl_c),
1707 SH_PFC_PIN_GROUP(scif1_clk_a),
1708 SH_PFC_PIN_GROUP(scif1_clk_c),
1709 SH_PFC_PIN_GROUP(scif2_data_a),
1710 SH_PFC_PIN_GROUP(scif2_data_b),
1711 SH_PFC_PIN_GROUP(scif2_data_c),
1712 SH_PFC_PIN_GROUP(scif2_data_d),
1713 SH_PFC_PIN_GROUP(scif2_data_e),
1714 SH_PFC_PIN_GROUP(scif2_clk_a),
1715 SH_PFC_PIN_GROUP(scif2_clk_b),
1716 SH_PFC_PIN_GROUP(scif2_clk_c),
1717 SH_PFC_PIN_GROUP(scif3_data_a),
1718 SH_PFC_PIN_GROUP(scif3_data_b),
1719 SH_PFC_PIN_GROUP(scif3_data_c),
1720 SH_PFC_PIN_GROUP(scif3_data_d),
1721 SH_PFC_PIN_GROUP(scif4_data_a),
1722 SH_PFC_PIN_GROUP(scif4_data_b),
1723 SH_PFC_PIN_GROUP(scif4_data_c),
1724 SH_PFC_PIN_GROUP(scif5_data_a),
1725 SH_PFC_PIN_GROUP(scif5_data_b),
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1726 SH_PFC_PIN_GROUP(sdhi0_cd),
1727 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1728 SH_PFC_PIN_GROUP(sdhi0_data1),
1729 SH_PFC_PIN_GROUP(sdhi0_data4),
1730 SH_PFC_PIN_GROUP(sdhi0_wp),
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1731 SH_PFC_PIN_GROUP(sdhi1_cd_a),
1732 SH_PFC_PIN_GROUP(sdhi1_cd_b),
1733 SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
1734 SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
1735 SH_PFC_PIN_GROUP(sdhi1_data1_a),
1736 SH_PFC_PIN_GROUP(sdhi1_data1_b),
1737 SH_PFC_PIN_GROUP(sdhi1_data4_a),
1738 SH_PFC_PIN_GROUP(sdhi1_data4_b),
1739 SH_PFC_PIN_GROUP(sdhi1_wp_a),
1740 SH_PFC_PIN_GROUP(sdhi1_wp_b),
1741 SH_PFC_PIN_GROUP(sdhi2_cd_a),
1742 SH_PFC_PIN_GROUP(sdhi2_cd_b),
1743 SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
1744 SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
1745 SH_PFC_PIN_GROUP(sdhi2_data1_a),
1746 SH_PFC_PIN_GROUP(sdhi2_data1_b),
1747 SH_PFC_PIN_GROUP(sdhi2_data4_a),
1748 SH_PFC_PIN_GROUP(sdhi2_data4_b),
1749 SH_PFC_PIN_GROUP(sdhi2_wp_a),
1750 SH_PFC_PIN_GROUP(sdhi2_wp_b),
Sergei Shtylyov5cee53b2013-05-08 23:12:47 +0000[diff] [blame]1751 SH_PFC_PIN_GROUP(usb0),
1752 SH_PFC_PIN_GROUP(usb0_ovc),
1753 SH_PFC_PIN_GROUP(usb1),
1754 SH_PFC_PIN_GROUP(usb1_ovc),
Vladimir Barinov2d7cd392013-05-09 03:14:35 +0400[diff] [blame]1755 SH_PFC_PIN_GROUP(vin0_data8),
1756 SH_PFC_PIN_GROUP(vin0_clk),
1757 SH_PFC_PIN_GROUP(vin0_sync),
1758 SH_PFC_PIN_GROUP(vin1_data8),
1759 SH_PFC_PIN_GROUP(vin1_clk),
1760 SH_PFC_PIN_GROUP(vin1_sync),
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1761};
1762
Sergei Shtylyov3c5886d2013-05-08 23:15:50 +0000[diff] [blame]1763static const char * const ether_groups[] = {
1764 "ether_rmii",
1765 "ether_link",
1766 "ether_magic",
1767};
1768
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1769static const char * const hscif0_groups[] = {
1770 "hscif0_data_a",
1771 "hscif0_data_b",
1772 "hscif0_ctrl_a",
1773 "hscif0_ctrl_b",
1774 "hscif0_clk",
1775};
1776
1777static const char * const hscif1_groups[] = {
1778 "hscif1_data_a",
1779 "hscif1_data_b",
1780 "hscif1_ctrl_a",
1781 "hscif1_ctrl_b",
1782 "hscif1_clk_a",
1783 "hscif1_clk_b",
1784};
1785
Kuninori Morimoto09cc76a2013-05-22 20:16:30 -0700[diff] [blame]1786static const char * const hspi0_groups[] = {
1787 "hspi0_a",
1788 "hspi0_b",
1789};
1790
1791static const char * const hspi1_groups[] = {
1792 "hspi1_a",
1793 "hspi1_b",
1794};
1795
1796static const char * const hspi2_groups[] = {
1797 "hspi2_a",
1798 "hspi2_b",
1799};
1800
Kuninori Morimoto0dcbc69e2013-05-22 20:15:53 -0700[diff] [blame]1801static const char * const i2c1_groups[] = {
1802 "i2c1_a",
1803 "i2c1_b",
1804};
1805
1806static const char * const i2c2_groups[] = {
1807 "i2c2_a",
1808 "i2c2_b",
1809 "i2c2_c",
1810};
1811
1812static const char * const i2c3_groups[] = {
1813 "i2c3_a",
1814 "i2c3_b",
1815 "i2c3_c",
1816};
1817
Kuninori Morimoto3ef2a772013-05-22 20:17:04 -0700[diff] [blame]1818static const char * const mmc_groups[] = {
1819 "mmc_ctrl",
1820 "mmc_data1",
1821 "mmc_data4",
1822 "mmc_data8",
1823};
1824
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1825static const char * const scif_clk_groups[] = {
1826 "scif_clk",
1827};
1828
1829static const char * const scif0_groups[] = {
1830 "scif0_data_a",
1831 "scif0_data_b",
1832 "scif0_data_c",
1833 "scif0_data_d",
1834 "scif0_ctrl",
1835 "scif0_clk",
1836};
1837
1838static const char * const scif1_groups[] = {
1839 "scif1_data_a",
1840 "scif1_data_b",
1841 "scif1_data_c",
1842 "scif1_data_d",
1843 "scif1_ctrl_a",
1844 "scif1_ctrl_c",
1845 "scif1_clk_a",
1846 "scif1_clk_c",
1847};
1848
1849static const char * const scif2_groups[] = {
1850 "scif2_data_a",
1851 "scif2_data_b",
1852 "scif2_data_c",
1853 "scif2_data_d",
1854 "scif2_data_e",
1855 "scif2_clk_a",
1856 "scif2_clk_b",
1857 "scif2_clk_c",
1858};
1859
1860static const char * const scif3_groups[] = {
1861 "scif3_data_a",
1862 "scif3_data_b",
1863 "scif3_data_c",
1864 "scif3_data_d",
1865};
1866
1867static const char * const scif4_groups[] = {
1868 "scif4_data_a",
1869 "scif4_data_b",
1870 "scif4_data_c",
1871};
1872
1873static const char * const scif5_groups[] = {
1874 "scif5_data_a",
1875 "scif5_data_b",
1876};
1877
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1878
1879static const char * const sdhi0_groups[] = {
1880 "sdhi0_cd",
1881 "sdhi0_ctrl",
1882 "sdhi0_data1",
1883 "sdhi0_data4",
1884 "sdhi0_wp",
1885};
1886
1887static const char * const sdhi1_groups[] = {
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1888 "sdhi1_cd_a",
1889 "sdhi1_cd_b",
1890 "sdhi1_ctrl_a",
1891 "sdhi1_ctrl_b",
1892 "sdhi1_data1_a",
1893 "sdhi1_data1_b",
1894 "sdhi1_data4_a",
1895 "sdhi1_data4_b",
1896 "sdhi1_wp_a",
1897 "sdhi1_wp_b",
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1898};
1899
1900static const char * const sdhi2_groups[] = {
Kuninori Morimoto0290df22013-04-23 04:32:32 +0000[diff] [blame]1901 "sdhi2_cd_a",
1902 "sdhi2_cd_b",
1903 "sdhi2_ctrl_a",
1904 "sdhi2_ctrl_b",
1905 "sdhi2_data1_a",
1906 "sdhi2_data1_b",
1907 "sdhi2_data4_a",
1908 "sdhi2_data4_b",
1909 "sdhi2_wp_a",
1910 "sdhi2_wp_b",
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1911};
1912
Sergei Shtylyov5cee53b2013-05-08 23:12:47 +0000[diff] [blame]1913static const char * const usb0_groups[] = {
1914 "usb0",
1915 "usb0_ovc",
1916};
1917
1918static const char * const usb1_groups[] = {
1919 "usb1",
1920 "usb1_ovc",
1921};
1922
Vladimir Barinov2d7cd392013-05-09 03:14:35 +0400[diff] [blame]1923static const char * const vin0_groups[] = {
1924 "vin0_data8",
1925 "vin0_clk",
1926 "vin0_sync",
1927};
1928
1929static const char * const vin1_groups[] = {
1930 "vin1_data8",
1931 "vin1_clk",
1932 "vin1_sync",
1933};
1934
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1935static const struct sh_pfc_function pinmux_functions[] = {
Sergei Shtylyov3c5886d2013-05-08 23:15:50 +0000[diff] [blame]1936 SH_PFC_FUNCTION(ether),
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1937 SH_PFC_FUNCTION(hscif0),
1938 SH_PFC_FUNCTION(hscif1),
Kuninori Morimoto09cc76a2013-05-22 20:16:30 -0700[diff] [blame]1939 SH_PFC_FUNCTION(hspi0),
1940 SH_PFC_FUNCTION(hspi1),
1941 SH_PFC_FUNCTION(hspi2),
Kuninori Morimoto0dcbc69e2013-05-22 20:15:53 -0700[diff] [blame]1942 SH_PFC_FUNCTION(i2c1),
1943 SH_PFC_FUNCTION(i2c2),
1944 SH_PFC_FUNCTION(i2c3),
Kuninori Morimoto3ef2a772013-05-22 20:17:04 -0700[diff] [blame]1945 SH_PFC_FUNCTION(mmc),
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1946 SH_PFC_FUNCTION(scif_clk),
1947 SH_PFC_FUNCTION(scif0),
1948 SH_PFC_FUNCTION(scif1),
1949 SH_PFC_FUNCTION(scif2),
1950 SH_PFC_FUNCTION(scif3),
1951 SH_PFC_FUNCTION(scif4),
1952 SH_PFC_FUNCTION(scif5),
Kuninori Morimoto564617d2013-04-18 20:08:23 -0700[diff] [blame]1953 SH_PFC_FUNCTION(sdhi0),
1954 SH_PFC_FUNCTION(sdhi1),
1955 SH_PFC_FUNCTION(sdhi2),
Sergei Shtylyov5cee53b2013-05-08 23:12:47 +0000[diff] [blame]1956 SH_PFC_FUNCTION(usb0),
1957 SH_PFC_FUNCTION(usb1),
Vladimir Barinov2d7cd392013-05-09 03:14:35 +0400[diff] [blame]1958 SH_PFC_FUNCTION(vin0),
1959 SH_PFC_FUNCTION(vin1),
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]1960};
1961
1962static struct pinmux_cfg_reg pinmux_config_regs[] = {
1963 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
1964 GP_0_31_FN, FN_IP1_14_11,
1965 GP_0_30_FN, FN_IP1_10_8,
1966 GP_0_29_FN, FN_IP1_7_5,
1967 GP_0_28_FN, FN_IP1_4_2,
1968 GP_0_27_FN, FN_IP1_1,
1969 GP_0_26_FN, FN_IP1_0,
1970 GP_0_25_FN, FN_IP0_30,
1971 GP_0_24_FN, FN_IP0_29,
1972 GP_0_23_FN, FN_IP0_28,
1973 GP_0_22_FN, FN_IP0_27,
1974 GP_0_21_FN, FN_IP0_26,
1975 GP_0_20_FN, FN_IP0_25,
1976 GP_0_19_FN, FN_IP0_24,
1977 GP_0_18_FN, FN_IP0_23,
1978 GP_0_17_FN, FN_IP0_22,
1979 GP_0_16_FN, FN_IP0_21,
1980 GP_0_15_FN, FN_IP0_20,
1981 GP_0_14_FN, FN_IP0_19,
1982 GP_0_13_FN, FN_IP0_18,
1983 GP_0_12_FN, FN_IP0_17,
1984 GP_0_11_FN, FN_IP0_16,
1985 GP_0_10_FN, FN_IP0_15,
1986 GP_0_9_FN, FN_A3,
1987 GP_0_8_FN, FN_A2,
1988 GP_0_7_FN, FN_A1,
1989 GP_0_6_FN, FN_IP0_14_12,
1990 GP_0_5_FN, FN_IP0_11_8,
1991 GP_0_4_FN, FN_IP0_7_5,
1992 GP_0_3_FN, FN_IP0_4_2,
1993 GP_0_2_FN, FN_PENC1,
1994 GP_0_1_FN, FN_PENC0,
1995 GP_0_0_FN, FN_IP0_1_0 }
1996 },
1997 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
1998 GP_1_31_FN, FN_IP4_6_4,
1999 GP_1_30_FN, FN_IP4_3_1,
2000 GP_1_29_FN, FN_IP4_0,
2001 GP_1_28_FN, FN_IP3_31,
2002 GP_1_27_FN, FN_IP3_30,
2003 GP_1_26_FN, FN_IP3_29,
2004 GP_1_25_FN, FN_IP3_28,
2005 GP_1_24_FN, FN_IP3_27,
2006 GP_1_23_FN, FN_IP3_26_24,
2007 GP_1_22_FN, FN_IP3_23_21,
2008 GP_1_21_FN, FN_IP3_20_19,
2009 GP_1_20_FN, FN_IP3_18_16,
2010 GP_1_19_FN, FN_IP3_15_13,
2011 GP_1_18_FN, FN_IP3_12_10,
2012 GP_1_17_FN, FN_IP3_9_8,
2013 GP_1_16_FN, FN_IP3_7_5,
2014 GP_1_15_FN, FN_IP3_4_2,
2015 GP_1_14_FN, FN_IP3_1_0,
2016 GP_1_13_FN, FN_IP2_31,
2017 GP_1_12_FN, FN_IP2_30,
2018 GP_1_11_FN, FN_IP2_17,
2019 GP_1_10_FN, FN_IP2_16_14,
2020 GP_1_9_FN, FN_IP2_13_12,
2021 GP_1_8_FN, FN_IP2_11_9,
2022 GP_1_7_FN, FN_IP2_8_6,
2023 GP_1_6_FN, FN_IP2_5_3,
2024 GP_1_5_FN, FN_IP2_2_0,
2025 GP_1_4_FN, FN_IP1_29_28,
2026 GP_1_3_FN, FN_IP1_27_25,
2027 GP_1_2_FN, FN_IP1_24,
2028 GP_1_1_FN, FN_WE0,
2029 GP_1_0_FN, FN_IP1_23_21 }
2030 },
2031 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
2032 GP_2_31_FN, FN_IP6_7,
2033 GP_2_30_FN, FN_IP6_6_5,
2034 GP_2_29_FN, FN_IP6_4_2,
2035 GP_2_28_FN, FN_IP6_1_0,
2036 GP_2_27_FN, FN_IP5_30_29,
2037 GP_2_26_FN, FN_IP5_28_26,
2038 GP_2_25_FN, FN_IP5_25_23,
2039 GP_2_24_FN, FN_IP5_22_21,
2040 GP_2_23_FN, FN_AUDIO_CLKB,
2041 GP_2_22_FN, FN_AUDIO_CLKA,
2042 GP_2_21_FN, FN_IP5_20_18,
2043 GP_2_20_FN, FN_IP5_17_15,
2044 GP_2_19_FN, FN_IP5_14_13,
2045 GP_2_18_FN, FN_IP5_12,
2046 GP_2_17_FN, FN_IP5_11_10,
2047 GP_2_16_FN, FN_IP5_9_8,
2048 GP_2_15_FN, FN_IP5_7,
2049 GP_2_14_FN, FN_IP5_6,
2050 GP_2_13_FN, FN_IP5_5_4,
2051 GP_2_12_FN, FN_IP5_3_2,
2052 GP_2_11_FN, FN_IP5_1_0,
2053 GP_2_10_FN, FN_IP4_30_29,
2054 GP_2_9_FN, FN_IP4_28_27,
2055 GP_2_8_FN, FN_IP4_26_25,
2056 GP_2_7_FN, FN_IP4_24_21,
2057 GP_2_6_FN, FN_IP4_20_17,
2058 GP_2_5_FN, FN_IP4_16_15,
2059 GP_2_4_FN, FN_IP4_14_13,
2060 GP_2_3_FN, FN_IP4_12_11,
2061 GP_2_2_FN, FN_IP4_10_9,
2062 GP_2_1_FN, FN_IP4_8,
2063 GP_2_0_FN, FN_IP4_7 }
2064 },
2065 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
2066 GP_3_31_FN, FN_IP8_10_9,
2067 GP_3_30_FN, FN_IP8_8_6,
2068 GP_3_29_FN, FN_IP8_5_3,
2069 GP_3_28_FN, FN_IP8_2_0,
2070 GP_3_27_FN, FN_IP7_31_29,
2071 GP_3_26_FN, FN_IP7_28_25,
2072 GP_3_25_FN, FN_IP7_24_22,
2073 GP_3_24_FN, FN_IP7_21,
2074 GP_3_23_FN, FN_IP7_20_18,
2075 GP_3_22_FN, FN_IP7_17_15,
2076 GP_3_21_FN, FN_IP7_14_12,
2077 GP_3_20_FN, FN_IP7_11_9,
2078 GP_3_19_FN, FN_IP7_8_6,
2079 GP_3_18_FN, FN_IP7_5_4,
2080 GP_3_17_FN, FN_IP7_3_2,
2081 GP_3_16_FN, FN_IP7_1_0,
2082 GP_3_15_FN, FN_IP6_31_30,
2083 GP_3_14_FN, FN_IP6_29_28,
2084 GP_3_13_FN, FN_IP6_27_26,
2085 GP_3_12_FN, FN_IP6_25_24,
2086 GP_3_11_FN, FN_IP6_23_22,
2087 GP_3_10_FN, FN_IP6_21,
2088 GP_3_9_FN, FN_IP6_20_19,
2089 GP_3_8_FN, FN_IP6_18_17,
2090 GP_3_7_FN, FN_IP6_16,
2091 GP_3_6_FN, FN_IP6_15_14,
2092 GP_3_5_FN, FN_IP6_13,
2093 GP_3_4_FN, FN_IP6_12_11,
2094 GP_3_3_FN, FN_IP6_10,
2095 GP_3_2_FN, FN_SSI_SCK34,
2096 GP_3_1_FN, FN_IP6_9,
2097 GP_3_0_FN, FN_IP6_8 }
2098 },
2099 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
2100 0, 0,
2101 0, 0,
2102 0, 0,
2103 0, 0,
2104 0, 0,
2105 GP_4_26_FN, FN_AVS2,
2106 GP_4_25_FN, FN_AVS1,
2107 GP_4_24_FN, FN_IP10_24_22,
2108 GP_4_23_FN, FN_IP10_21_19,
2109 GP_4_22_FN, FN_IP10_18_16,
2110 GP_4_21_FN, FN_IP10_15_13,
2111 GP_4_20_FN, FN_IP10_12_9,
2112 GP_4_19_FN, FN_IP10_8_6,
2113 GP_4_18_FN, FN_IP10_5_3,
2114 GP_4_17_FN, FN_IP10_2_0,
2115 GP_4_16_FN, FN_IP9_29_27,
2116 GP_4_15_FN, FN_IP9_26_24,
2117 GP_4_14_FN, FN_IP9_23_21,
2118 GP_4_13_FN, FN_IP9_20_18,
2119 GP_4_12_FN, FN_IP9_17_15,
2120 GP_4_11_FN, FN_IP9_14_12,
2121 GP_4_10_FN, FN_IP9_11_9,
2122 GP_4_9_FN, FN_IP9_8_6,
2123 GP_4_8_FN, FN_IP9_5_3,
2124 GP_4_7_FN, FN_IP9_2_0,
2125 GP_4_6_FN, FN_IP8_29_27,
2126 GP_4_5_FN, FN_IP8_26_24,
2127 GP_4_4_FN, FN_IP8_23_22,
2128 GP_4_3_FN, FN_IP8_21_19,
2129 GP_4_2_FN, FN_IP8_18_16,
2130 GP_4_1_FN, FN_IP8_15_14,
2131 GP_4_0_FN, FN_IP8_13_11 }
2132 },
2133
2134 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2135 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2136 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
2137 /* IP0_31 [1] */
2138 0, 0,
2139 /* IP0_30 [1] */
2140 FN_A19, 0,
2141 /* IP0_29 [1] */
2142 FN_A18, 0,
2143 /* IP0_28 [1] */
2144 FN_A17, 0,
2145 /* IP0_27 [1] */
2146 FN_A16, 0,
2147 /* IP0_26 [1] */
2148 FN_A15, 0,
2149 /* IP0_25 [1] */
2150 FN_A14, 0,
2151 /* IP0_24 [1] */
2152 FN_A13, 0,
2153 /* IP0_23 [1] */
2154 FN_A12, 0,
2155 /* IP0_22 [1] */
2156 FN_A11, 0,
2157 /* IP0_21 [1] */
2158 FN_A10, 0,
2159 /* IP0_20 [1] */
2160 FN_A9, 0,
2161 /* IP0_19 [1] */
2162 FN_A8, 0,
2163 /* IP0_18 [1] */
2164 FN_A7, 0,
2165 /* IP0_17 [1] */
2166 FN_A6, 0,
2167 /* IP0_16 [1] */
2168 FN_A5, 0,
2169 /* IP0_15 [1] */
2170 FN_A4, 0,
2171 /* IP0_14_12 [3] */
2172 FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0,
2173 FN_ATAG0_A, 0, FN_REMOCON_B, 0,
2174 /* IP0_11_8 [4] */
2175 FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,
2176 FN_ATADIR0_A, 0, FN_SDSELF_B, 0,
2177 FN_PWM4_B, 0, 0, 0,
2178 0, 0, 0, 0,
2179 /* IP0_7_5 [3] */
2180 FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1,
2181 FN_RX2_E, FN_SCL2_B, 0, 0,
2182 /* IP0_4_2 [3] */
2183 FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0,
2184 FN_TX2_E, FN_SDA2_B, 0, 0,
2185 /* IP0_1_0 [2] */
2186 FN_PRESETOUT, 0, FN_PWM1, 0,
2187 }
2188 },
2189 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2190 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
2191 /* IP1_31 [1] */
2192 0, 0,
2193 /* IP1_30 [1] */
2194 0, 0,
2195 /* IP1_29_28 [2] */
2196 FN_EX_CS1, FN_MMC_D4, 0, 0,
2197 /* IP1_27_25 [3] */
2198 FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C,
2199 FN_TS_SCK0_A, 0, 0, 0,
2200 /* IP1_24 [1] */
2201 FN_WE1, FN_ATAWR0_B,
2202 /* IP1_23_21 [3] */
2203 FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR,
2204 0, 0, 0, 0,
2205 /* IP1_20_18 [3] */
2206 FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
2207 FN_SCK2_B, 0, 0, 0,
2208 /* IP1_17 [1] */
2209 FN_CS0, FN_HSPI_RX1_B,
2210 /* IP1_16_15 [2] */
2211 FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0,
2212 /* IP1_14_11 [4] */
2213 FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25,
2214 FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C,
2215 FN_TS_SDAT0_A, 0, 0, 0,
2216 0, 0, 0, 0,
2217 /* IP1_10_8 [3] */
2218 FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24,
2219 FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,
2220 /* IP1_7_5 [3] */
2221 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
2222 FN_TS_SDEN0_A, 0, 0, 0,
2223 /* IP1_4_2 [3] */
2224 FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
2225 0, 0, 0, 0,
2226 /* IP1_1 [1] */
2227 FN_A21, FN_HSPI_CLK1_B,
2228 /* IP1_0 [1] */
2229 FN_A20, FN_HSPI_CS1_B,
2230 }
2231 },
2232 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2233 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2234 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
2235 /* IP2_31 [1] */
Kuninori Morimotod64d0052013-05-13 21:10:17 -0700[diff] [blame]2236 FN_MLB_CLK, FN_IRQ1_A,
Kuninori Morimoto87f8c982013-04-12 05:37:20 +0000[diff] [blame]2237 /* IP2_30 [1] */
2238 FN_RD_WR_B, FN_IRQ0,
2239 /* IP2_29 [1] */
2240 FN_D11, 0,
2241 /* IP2_28 [1] */
2242 FN_D10, 0,
2243 /* IP2_27 [1] */
2244 FN_D9, 0,
2245 /* IP2_26 [1] */
2246 FN_D8, 0,
2247 /* IP2_25 [1] */
2248 FN_D7, 0,
2249 /* IP2_24 [1] */
2250 FN_D6, 0,
2251 /* IP2_23 [1] */
2252 FN_D5, 0,
2253 /* IP2_22 [1] */
2254 FN_D4, 0,
2255 /* IP2_21 [1] */
2256 FN_D3, 0,
2257 /* IP2_20 [1] */
2258 FN_D2, 0,
2259 /* IP2_19 [1] */
2260 FN_D1, 0,
2261 /* IP2_18 [1] */
2262 FN_D0, 0,
2263 /* IP2_17 [1] */
2264 FN_EX_WAIT0, FN_PWM0_C,
2265 /* IP2_16_14 [3] */
2266 FN_DACK0, 0, 0, FN_TX3_A,
2267 FN_DRACK0, 0, 0, 0,
2268 /* IP2_13_12 [2] */
2269 FN_DREQ0_A, 0, 0, FN_RX3_A,
2270 /* IP2_11_9 [3] */
2271 FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A,
2272 FN_EX_CS5, FN_EX_WAIT2_A, 0, 0,
2273 /* IP2_8_6 [3] */
2274 FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0,
2275 FN_EX_CS4, FN_EX_WAIT1_A, 0, 0,
2276 /* IP2_5_3 [3] */
2277 FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10,
2278 FN_EX_CS3, 0, 0, 0,
2279 /* IP2_2_0 [3] */
2280 FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00,
2281 FN_EX_CS2, 0, 0, 0,
2282 }
2283 },
2284 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2285 1, 1, 1, 1, 1, 3, 3, 2,
2286 3, 3, 3, 2, 3, 3, 2) {
2287 /* IP3_31 [1] */
2288 FN_DU0_DR6, FN_LCDOUT6,
2289 /* IP3_30 [1] */
2290 FN_DU0_DR5, FN_LCDOUT5,
2291 /* IP3_29 [1] */
2292 FN_DU0_DR4, FN_LCDOUT4,
2293 /* IP3_28 [1] */
2294 FN_DU0_DR3, FN_LCDOUT3,
2295 /* IP3_27 [1] */
2296 FN_DU0_DR2, FN_LCDOUT2,
2297 /* IP3_26_24 [3] */
2298 FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3,
2299 FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
2300 /* IP3_23_21 [3] */
2301 FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2,
2302 FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B,
2303 /* IP3_20_19 [2] */
2304 FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0,
2305 /* IP3_18_16 [3] */
2306 FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0,
2307 0, 0, 0, 0,
2308 /* IP3_15_13 [3] */
2309 FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
2310 0, 0, 0, 0,
2311 /* IP3_12_10 [3] */
2312 FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0,
2313 0, 0, 0, 0,
2314 /* IP3_9_8 [2] */
2315 FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0,
2316 /* IP3_7_5 [3] */
2317 FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B,
2318 FN_SDA3_B, 0, 0, 0,
2319 /* IP3_4_2 [3] */
2320 FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
2321 FN_SDSELF_B, 0, 0, 0,
2322 /* IP3_1_0 [2] */
2323 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
2324 }
2325 },
2326 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2327 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
2328 /* IP4_31 [1] */
2329 0, 0,
2330 /* IP4_30_29 [2] */
2331 FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0,
2332 /* IP4_28_27 [2] */
2333 FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0,
2334 /* IP4_26_25 [2] */
2335 FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0,
2336 /* IP4_24_21 [4] */
2337 FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
2338 FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0,
2339 FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0,
2340 0, 0, 0, 0,
2341 /* IP4_20_17 [4] */
2342 FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16,
2343 FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A,
2344 FN_ADICLK, FN_TS_SDAT0_B, 0, 0,
2345 0, 0, 0, 0,
2346 /* IP4_16_15 [2] */
2347 FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0,
2348 /* IP4_14_13 [2] */
2349 FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0,
2350 /* IP4_12_11 [2] */
2351 FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0,
2352 /* IP4_10_9 [2] */
2353 FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0,
2354 /* IP4_8 [1] */
2355 FN_DU0_DG3, FN_LCDOUT11,
2356 /* IP4_7 [1] */
2357 FN_DU0_DG2, FN_LCDOUT10,
2358 /* IP4_6_4 [3] */
2359 FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5,
2360 FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0,
2361 /* IP4_3_1 [3] */
2362 FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4,
2363 FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0,
2364 /* IP4_0 [1] */
2365 FN_DU0_DR7, FN_LCDOUT7,
2366 }
2367 },
2368 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2369 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
2370
2371 /* IP5_31 [1] */
2372 0, 0,
2373 /* IP5_30_29 [2] */
2374 FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B,
2375 /* IP5_28_26 [3] */
2376 FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A,
2377 FN_CAN0_TX_B, 0, 0, 0,
2378 /* IP5_25_23 [3] */
2379 FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
2380 FN_CAN_CLK_D, 0, 0, 0,
2381 /* IP5_22_21 [2] */
2382 FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
2383 /* IP5_20_18 [3] */
2384 FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC,
2385 FN_ARM_TRACECTL, FN_FMIN_D, 0, 0,
2386 /* IP5_17_15 [3] */
2387 FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK,
2388 FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0,
2389 /* IP5_14_13 [2] */
2390 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
2391 FN_FMCLK_D, 0,
2392 /* IP5_12 [1] */
2393 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
2394 /* IP5_11_10 [2] */
2395 FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
2396 FN_QSTH_QHS, 0,
2397 /* IP5_9_8 [2] */
2398 FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE,
2399 FN_AUDIO_CLKOUT_A, FN_REMOCON_C,
2400 /* IP5_7 [1] */
2401 FN_DU0_DOTCLKO_UT0, FN_QCLK,
2402 /* IP5_6 [1] */
2403 FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
2404 /* IP5_5_4 [2] */
2405 FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0,
2406 /* IP5_3_2 [2] */
2407 FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0,
2408 /* IP5_1_0 [2] */
2409 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0,
2410 }
2411 },
2412 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2413 2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
2414 1, 2, 1, 1, 1, 1, 2, 3, 2) {
2415 /* IP6_31_30 [2] */
2416 FN_SD0_DAT2, 0, FN_SUB_TDI, 0,
2417 /* IP6_29_28 [2] */
2418 FN_SD0_DAT1, 0, FN_SUB_TCK, 0,
2419 /* IP6_27_26 [2] */
2420 FN_SD0_DAT0, 0, FN_SUB_TMS, 0,
2421 /* IP6_25_24 [2] */
2422 FN_SD0_CMD, 0, FN_SUB_TRST, 0,
2423 /* IP6_23_22 [2] */
2424 FN_SD0_CLK, 0, FN_SUB_TDO, 0,
2425 /* IP6_21 [1] */
2426 FN_SSI_SDATA0, FN_ARM_TRACEDATA_15,
2427 /* IP6_20_19 [2] */
2428 FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
2429 FN_SCL1_A, FN_SCK2_A,
2430 /* IP6_18_17 [2] */
2431 FN_SSI_SDATA2, FN_HSPI_CS2_A,
2432 FN_ARM_TRACEDATA_13, FN_SDA1_A,
2433 /* IP6_16 [1] */
2434 FN_SSI_WS012, FN_ARM_TRACEDATA_12,
2435 /* IP6_15_14 [2] */
2436 FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
2437 FN_TX0_D, 0,
2438 /* IP6_13 [1] */
2439 FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
2440 /* IP6_12_11 [2] */
2441 FN_SSI_SDATA4, FN_SSI_WS2_A,
2442 FN_ARM_TRACEDATA_9, 0,
2443 /* IP6_10 [1] */
2444 FN_SSI_WS34, FN_ARM_TRACEDATA_8,
2445 /* IP6_9 [1] */
2446 FN_SSI_SDATA5, FN_RX0_D,
2447 /* IP6_8 [1] */
2448 FN_SSI_WS5, FN_TX4_C,
2449 /* IP6_7 [1] */
2450 FN_SSI_SCK5, FN_RX4_C,
2451 /* IP6_6_5 [2] */
2452 FN_SSI_SDATA6, FN_HSPI_TX2_A,
2453 FN_FMIN_B, 0,
2454 /* IP6_4_2 [3] */
2455 FN_SSI_WS6, FN_HSPI_CLK2_A,
2456 FN_BPFCLK_B, FN_CAN1_RX_B,
2457 0, 0, 0, 0,
2458 /* IP6_1_0 [2] */
2459 FN_SSI_SCK6, FN_HSPI_RX2_A,
2460 FN_FMCLK_B, FN_CAN1_TX_B,
2461 }
2462 },
2463 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2464 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
2465
2466 /* IP7_31_29 [3] */
2467 FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2,
2468 0, FN_HSPI_CS1_A, FN_RX3_B, 0,
2469 /* IP7_28_25 [4] */
2470 FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1,
2471 FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B,
2472 0, 0, 0, 0,
2473 0, 0, 0, 0,
2474 /* IP7_24_22 [3] */
2475 FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
2476 0, FN_HSPI_RX1_A, FN_RX4_B, 0,
2477 /* IP7_21 [1] */
2478 FN_VI0_CLK, FN_CAN_CLK_A,
2479 /* IP7_20_18 [3] */
2480 FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0,
2481 FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0,
2482 /* IP7_17_15 [3] */
2483 FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A,
2484 0, FN_TX1_C, 0, 0,
2485 /* IP7_14_12 [3] */
2486 FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A,
2487 0, FN_RX1_C, 0, 0,
2488 /* IP7_11_9 [3] */
2489 FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0,
2490 FN_SCK1_C, 0, 0, 0,
2491 /* IP7_8_6 [3] */
2492 FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0,
2493 FN_RTS1_C, 0, 0, 0,
2494 /* IP7_5_4 [2] */
2495 FN_SD0_WP, 0, FN_RX5_A, 0,
2496 /* IP7_3_2 [2] */
2497 FN_SD0_CD, 0, FN_TX5_A, 0,
2498 /* IP7_1_0 [2] */
2499 FN_SD0_DAT3, 0, FN_IRQ1_B, 0,
2500 }
2501 },
2502 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2503 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
2504 /* IP8_31 [1] */
2505 0, 0,
2506 /* IP8_30 [1] */
2507 0, 0,
2508 /* IP8_29_27 [3] */
2509 FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5,
2510 0, FN_HRX1_B, 0, 0,
2511 /* IP8_26_24 [3] */
2512 FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4,
2513 0, FN_HTX1_B, 0, 0,
2514 /* IP8_23_22 [2] */
2515 FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
2516 FN_RTS1_A, 0,
2517 /* IP8_21_19 [3] */
2518 FN_VI0_DATA6_VI0_G0, FN_DU1_DB4,
2519 FN_CTS1_A, FN_PWM5,
2520 0, 0, 0, 0,
2521 /* IP8_18_16 [3] */
2522 FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4,
2523 0, FN_HSCK1_B, 0, 0,
2524 /* IP8_15_14 [2] */
2525 FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0,
2526 /* IP8_13_11 [3] */
2527 FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C,
2528 0, 0, 0, 0,
2529 /* IP8_10_9 [2] */
2530 FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0,
2531 /* IP8_8_6 [3] */
2532 FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D,
2533 0, 0, 0, 0,
2534 /* IP8_5_3 [3] */
2535 FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D,
2536 0, 0, 0, 0,
2537 /* IP8_2_0 [3] */
2538 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
2539 0, FN_HSPI_TX1_A, FN_TX3_B, 0,
2540 }
2541 },
2542 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2543 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2544 /* IP9_31 [1] */
2545 0, 0,
2546 /* IP9_30 [1] */
2547 0, 0,
2548 /* IP9_29_27 [3] */
2549 FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC,
2550 FN_ETH_RXD1, FN_FMIN_C,
2551 0, FN_RX2_D,
2552 FN_SCL2_C, 0,
2553 /* IP9_26_24 [3] */
2554 FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT,
2555 FN_ETH_RXD0, FN_BPFCLK_C,
2556 0, FN_TX2_D,
2557 FN_SDA2_C, 0,
2558 /* IP9_23_21 [3] */
2559 FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C,
2560 FN_IERX, FN_RX2_C, 0, 0,
2561 /* IP9_20_18 [3] */
2562 FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0,
2563 FN_IETX, FN_TX2_C, 0, 0,
2564 /* IP9_17_15 [3] */
2565 FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK,
2566 FN_SCK2_C, 0, 0, 0,
2567 /* IP9_14_12 [3] */
2568 FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1,
2569 0, FN_PWM3, 0, 0,
2570 /* IP9_11_9 [3] */
2571 FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0,
2572 0, FN_PWM2, FN_TCLK1, 0,
2573 /* IP9_8_6 [3] */
2574 FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
2575 0, 0, 0, 0,
2576 /* IP9_5_3 [3] */
2577 FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7,
2578 0, FN_HCTS1_B, 0, 0,
2579 /* IP9_2_0 [3] */
2580 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
2581 0, FN_HRTS1_B, 0, 0,
2582 }
2583 },
2584 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2585 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
2586
2587 /* IP10_31 [1] */
2588 0, 0,
2589 /* IP10_30 [1] */
2590 0, 0,
2591 /* IP10_29 [1] */
2592 0, 0,
2593 /* IP10_28 [1] */
2594 0, 0,
2595 /* IP10_27 [1] */
2596 0, 0,
2597 /* IP10_26 [1] */
2598 0, 0,
2599 /* IP10_25 [1] */
2600 0, 0,
2601 /* IP10_24_22 [3] */
2602 FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B,
2603 FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0,
2604 /* IP10_21_19 [3] */
2605 FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B,
2606 FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0,
2607 /* IP10_18_16 [3] */
2608 FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1,
2609 FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0,
2610 /* IP10_15_13 [3] */
2611 FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1,
2612 FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0,
2613 /* IP10_12_9 [4] */
2614 FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
2615 FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6,
2616 0, 0, 0, 0,
2617 0, 0, 0, 0,
2618 /* IP10_8_6 [3] */
2619 FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B,
2620 FN_ETH_LINK, FN_CAN1_RX_A, 0, 0,
2621 /* IP10_5_3 [3] */
2622 FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2623 FN_ATAWR1, FN_ETH_MDIO,
2624 FN_SCL1_B, 0,
2625 0, 0,
2626 /* IP10_2_0 [3] */
2627 FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC,
2628 FN_ATARD1, FN_ETH_MDC,
2629 FN_SDA1_B, 0,
2630 0, 0,
2631 }
2632 },
2633 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
2634 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
2635 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2636
2637 /* SEL 31 [1] */
2638 0, 0,
2639 /* SEL_30 (SCIF5) [1] */
2640 FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
2641 /* SEL_29_28 (SCIF4) [2] */
2642 FN_SEL_SCIF4_A, FN_SEL_SCIF4_B,
2643 FN_SEL_SCIF4_C, 0,
2644 /* SEL_27_26 (SCIF3) [2] */
2645 FN_SEL_SCIF3_A, FN_SEL_SCIF3_B,
2646 FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
2647 /* SEL_25_23 (SCIF2) [3] */
2648 FN_SEL_SCIF2_A, FN_SEL_SCIF2_B,
2649 FN_SEL_SCIF2_C, FN_SEL_SCIF2_D,
2650 FN_SEL_SCIF2_E, 0,
2651 0, 0,
2652 /* SEL_22_21 (SCIF1) [2] */
2653 FN_SEL_SCIF1_A, FN_SEL_SCIF1_B,
2654 FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
2655 /* SEL_20_19 (SCIF0) [2] */
2656 FN_SEL_SCIF0_A, FN_SEL_SCIF0_B,
2657 FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
2658 /* SEL_18 [1] */
2659 0, 0,
2660 /* SEL_17 (SSI2) [1] */
2661 FN_SEL_SSI2_A, FN_SEL_SSI2_B,
2662 /* SEL_16 (SSI1) [1] */
2663 FN_SEL_SSI1_A, FN_SEL_SSI1_B,
2664 /* SEL_15 (VI1) [1] */
2665 FN_SEL_VI1_A, FN_SEL_VI1_B,
2666 /* SEL_14_13 (VI0) [2] */
2667 FN_SEL_VI0_A, FN_SEL_VI0_B,
2668 FN_SEL_VI0_C, FN_SEL_VI0_D,
2669 /* SEL_12 [1] */
2670 0, 0,
2671 /* SEL_11 (SD2) [1] */
2672 FN_SEL_SD2_A, FN_SEL_SD2_B,
2673 /* SEL_10 (SD1) [1] */
2674 FN_SEL_SD1_A, FN_SEL_SD1_B,
2675 /* SEL_9 (IRQ3) [1] */
2676 FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
2677 /* SEL_8_7 (IRQ2) [2] */
2678 FN_SEL_IRQ2_A, FN_SEL_IRQ2_B,
2679 FN_SEL_IRQ2_C, 0,
2680 /* SEL_6 (IRQ1) [1] */
2681 FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
2682 /* SEL_5 [1] */
2683 0, 0,
2684 /* SEL_4 (DREQ2) [1] */
2685 FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
2686 /* SEL_3 (DREQ1) [1] */
2687 FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
2688 /* SEL_2 (DREQ0) [1] */
2689 FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
2690 /* SEL_1 (WAIT2) [1] */
2691 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
2692 /* SEL_0 (WAIT1) [1] */
2693 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
2694 }
2695 },
2696 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
2697 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
2698 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
2699
2700 /* SEL_31 [1] */
2701 0, 0,
2702 /* SEL_30 [1] */
2703 0, 0,
2704 /* SEL_29 [1] */
2705 0, 0,
2706 /* SEL_28 [1] */
2707 0, 0,
2708 /* SEL_27 (CAN1) [1] */
2709 FN_SEL_CAN1_A, FN_SEL_CAN1_B,
2710 /* SEL_26 (CAN0) [1] */
2711 FN_SEL_CAN0_A, FN_SEL_CAN0_B,
2712 /* SEL_25_24 (CANCLK) [2] */
2713 FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
2714 FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
2715 /* SEL_23 (HSCIF1) [1] */
2716 FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
2717 /* SEL_22 (HSCIF0) [1] */
2718 FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
2719 /* SEL_21 [1] */
2720 0, 0,
2721 /* SEL_20 [1] */
2722 0, 0,
2723 /* SEL_19 [1] */
2724 0, 0,
2725 /* SEL_18 [1] */
2726 0, 0,
2727 /* SEL_17 [1] */
2728 0, 0,
2729 /* SEL_16 [1] */
2730 0, 0,
2731 /* SEL_15 [1] */
2732 0, 0,
2733 /* SEL_14_13 (REMOCON) [2] */
2734 FN_SEL_REMOCON_A, FN_SEL_REMOCON_B,
2735 FN_SEL_REMOCON_C, 0,
2736 /* SEL_12_11 (FM) [2] */
2737 FN_SEL_FM_A, FN_SEL_FM_B,
2738 FN_SEL_FM_C, FN_SEL_FM_D,
2739 /* SEL_10_9 (GPS) [2] */
2740 FN_SEL_GPS_A, FN_SEL_GPS_B,
2741 FN_SEL_GPS_C, 0,
2742 /* SEL_8 (TSIF0) [1] */
2743 FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
2744 /* SEL_7 (HSPI2) [1] */
2745 FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
2746 /* SEL_6 (HSPI1) [1] */
2747 FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
2748 /* SEL_5 (HSPI0) [1] */
2749 FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
2750 /* SEL_4_3 (I2C3) [2] */
2751 FN_SEL_I2C3_A, FN_SEL_I2C3_B,
2752 FN_SEL_I2C3_C, 0,
2753 /* SEL_2_1 (I2C2) [2] */
2754 FN_SEL_I2C2_A, FN_SEL_I2C2_B,
2755 FN_SEL_I2C2_C, 0,
2756 /* SEL_0 (I2C1) [1] */
2757 FN_SEL_I2C1_A, FN_SEL_I2C1_B,
2758 }
2759 },
2760 { },
2761};
2762
2763const struct sh_pfc_soc_info r8a7778_pinmux_info = {
2764 .name = "r8a7778_pfc",
2765
2766 .unlock_reg = 0xfffc0000, /* PMMR */
2767
2768 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2769
2770 .pins = pinmux_pins,
2771 .nr_pins = ARRAY_SIZE(pinmux_pins),
2772
2773 .groups = pinmux_groups,
2774 .nr_groups = ARRAY_SIZE(pinmux_groups),
2775
2776 .functions = pinmux_functions,
2777 .nr_functions = ARRAY_SIZE(pinmux_functions),
2778
2779 .cfg_regs = pinmux_config_regs,
2780
2781 .gpio_data = pinmux_data,
2782 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2783};