| Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/arm/hardware/it8152.h |
| 3 | * |
| 4 | * Copyright Compulab Ltd., 2006,2007 |
| 5 | * Mike Rapoport <mike@compulab.co.il> |
| 6 | * |
| 7 | * ITE 8152 companion chip register definitions |
| 8 | */ |
| 9 | |
| 10 | #ifndef __ASM_HARDWARE_IT8152_H |
| 11 | #define __ASM_HARDWARE_IT8152_H |
| Rob Herring | bc0a151 | 2012-01-03 15:52:42 -0600 | [diff] [blame] | 12 | |
| 13 | #include <mach/irqs.h> |
| 14 | |
| Arnd Bergmann | 97b09da | 2011-10-01 22:03:45 +0200 | [diff] [blame] | 15 | extern void __iomem *it8152_base_address; |
| Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 16 | |
| 17 | #define IT8152_IO_BASE (it8152_base_address + 0x03e00000) |
| 18 | #define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000) |
| 19 | |
| 20 | #define __REG_IT8152(x) (it8152_base_address + (x)) |
| 21 | |
| 22 | #define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800) |
| 23 | #define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804) |
| 24 | |
| 25 | #define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300) |
| 26 | #define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304) |
| 27 | #define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308) |
| 28 | #define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C) |
| 29 | #define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310) |
| 30 | #define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314) |
| 31 | #define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320) |
| 32 | #define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324) |
| 33 | #define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328) |
| 34 | #define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C) |
| 35 | #define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330) |
| 36 | #define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334) |
| 37 | #define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340) |
| 38 | #define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344) |
| 39 | #define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348) |
| 40 | #define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C) |
| 41 | #define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350) |
| 42 | #define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354) |
| 43 | #define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC) |
| 44 | |
| 45 | #define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500) |
| 46 | |
| 47 | /* |
| Joe Perches | 84c0792 | 2008-02-03 16:50:59 +0200 | [diff] [blame] | 48 | Interrupt controller per register summary: |
| Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 49 | --------------------------------------- |
| 50 | LCDNIRR: |
| 51 | IT8152_LD_IRQ(8) PCICLK stop |
| 52 | IT8152_LD_IRQ(7) MCLK ready |
| 53 | IT8152_LD_IRQ(6) s/w |
| 54 | IT8152_LD_IRQ(5) UART |
| 55 | IT8152_LD_IRQ(4) GPIO |
| 56 | IT8152_LD_IRQ(3) TIMER 4 |
| 57 | IT8152_LD_IRQ(2) TIMER 3 |
| 58 | IT8152_LD_IRQ(1) TIMER 2 |
| 59 | IT8152_LD_IRQ(0) TIMER 1 |
| 60 | |
| 61 | LPCNIRR: |
| 62 | IT8152_LP_IRQ(x) serial IRQ x |
| 63 | |
| 64 | PCIDNIRR: |
| 65 | IT8152_PD_IRQ(14) PCISERR |
| 66 | IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR) |
| 67 | IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR) |
| 68 | IT8152_PD_IRQ(11) PCI INTD |
| 69 | IT8152_PD_IRQ(10) PCI INTC |
| 70 | IT8152_PD_IRQ(9) PCI INTB |
| 71 | IT8152_PD_IRQ(8) PCI INTA |
| 72 | IT8152_PD_IRQ(7) serial INTD |
| 73 | IT8152_PD_IRQ(6) serial INTC |
| 74 | IT8152_PD_IRQ(5) serial INTB |
| 75 | IT8152_PD_IRQ(4) serial INTA |
| 76 | IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR) |
| 77 | IT8152_PD_IRQ(2) chaining DMA (CDMAR) |
| 78 | IT8152_PD_IRQ(1) USB (USBR) |
| 79 | IT8152_PD_IRQ(0) Audio controller (ACR) |
| 80 | */ |
| Eric Miao | 12cdcc8 | 2010-11-02 04:53:59 +0800 | [diff] [blame] | 81 | #define IT8152_IRQ(x) (IRQ_BOARD_START + (x)) |
| Mike Rapoport | 823a2df | 2010-12-29 09:06:26 +0200 | [diff] [blame] | 82 | #define IT8152_LAST_IRQ (IRQ_BOARD_START + 40) |
| Eric Miao | 0dc726b | 2009-12-27 23:01:25 +0800 | [diff] [blame] | 83 | |
| 84 | /* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ |
| 85 | #define IT8152_LD_IRQ_COUNT 9 |
| 86 | #define IT8152_LP_IRQ_COUNT 16 |
| 87 | #define IT8152_PD_IRQ_COUNT 15 |
| 88 | |
| 89 | /* Priorities: */ |
| 90 | #define IT8152_PD_IRQ(i) IT8152_IRQ(i) |
| 91 | #define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) |
| 92 | #define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) |
| 93 | |
| Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 94 | /* frequently used interrupts */ |
| 95 | #define IT8152_PCISERR IT8152_PD_IRQ(14) |
| 96 | #define IT8152_H2PTADR IT8152_PD_IRQ(13) |
| 97 | #define IT8152_H2PMAR IT8152_PD_IRQ(12) |
| 98 | #define IT8152_PCI_INTD IT8152_PD_IRQ(11) |
| 99 | #define IT8152_PCI_INTC IT8152_PD_IRQ(10) |
| 100 | #define IT8152_PCI_INTB IT8152_PD_IRQ(9) |
| 101 | #define IT8152_PCI_INTA IT8152_PD_IRQ(8) |
| 102 | #define IT8152_CDMA_INT IT8152_PD_IRQ(2) |
| 103 | #define IT8152_USB_INT IT8152_PD_IRQ(1) |
| 104 | #define IT8152_AUDIO_INT IT8152_PD_IRQ(0) |
| 105 | |
| 106 | struct pci_dev; |
| 107 | struct pci_sys_data; |
| 108 | |
| 109 | extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc); |
| 110 | extern void it8152_init_irq(void); |
| Ralf Baechle | d534194 | 2011-06-10 15:30:21 +0100 | [diff] [blame] | 111 | extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); |
| Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 112 | extern int it8152_pci_setup(int nr, struct pci_sys_data *sys); |
| 113 | extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys); |
| 114 | |
| 115 | #endif /* __ASM_HARDWARE_IT8152_H */ |