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gerrit-public.fairphone.software / kernel / msm-5.4 / cee4d26448c1000ccc1711eb5e6ed4c15f18fa83 / . / drivers / net / ethernet / qlogic / qed / qed_hsi.h
blob: 5909823463abdc11d8a4578e77e5846cb0dd4ef1 [file] [log] [blame]
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200[diff] [blame]1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#ifndef _QED_HSI_H
10#define _QED_HSI_H
11
12#include <linux/types.h>
13#include <linux/io.h>
14#include <linux/bitops.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/list.h>
18#include <linux/slab.h>
19#include <linux/qed/common_hsi.h>
Yuval Mintz25c089d2015-10-26 11:02:26 +0200[diff] [blame]20#include <linux/qed/eth_common.h>
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200[diff] [blame]21
22struct qed_hwfn;
23struct qed_ptt;
24/********************************/
25/* Add include to common target */
26/********************************/
27
28/* opcodes for the event ring */
29enum common_event_opcode {
30 COMMON_EVENT_PF_START,
31 COMMON_EVENT_PF_STOP,
32 COMMON_EVENT_RESERVED,
33 COMMON_EVENT_RESERVED2,
34 COMMON_EVENT_RESERVED3,
35 COMMON_EVENT_RESERVED4,
36 COMMON_EVENT_RESERVED5,
37 MAX_COMMON_EVENT_OPCODE
38};
39
40/* Common Ramrod Command IDs */
41enum common_ramrod_cmd_id {
42 COMMON_RAMROD_UNUSED,
43 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
44 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
45 COMMON_RAMROD_RESERVED,
46 COMMON_RAMROD_RESERVED2,
47 COMMON_RAMROD_RESERVED3,
48 MAX_COMMON_RAMROD_CMD_ID
49};
50
51/* The core storm context for the Ystorm */
52struct ystorm_core_conn_st_ctx {
53 __le32 reserved[4];
54};
55
56/* The core storm context for the Pstorm */
57struct pstorm_core_conn_st_ctx {
58 __le32 reserved[4];
59};
60
61/* Core Slowpath Connection storm context of Xstorm */
62struct xstorm_core_conn_st_ctx {
63 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
64 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
65 struct regpair consolid_base_addr;
66 __le16 spq_cons /* SPQ Ring Consumer */;
67 __le16 consolid_cons /* Consolidation Ring Consumer */;
68 __le32 reserved0[55] /* Pad to 15 cycles */;
69};
70
71struct xstorm_core_conn_ag_ctx {
72 u8 reserved0 /* cdu_validation */;
73 u8 core_state /* state */;
74 u8 flags0;
75#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
76#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
77#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
78#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
79#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
80#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
81#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
82#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
83#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
84#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
85#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
86#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
87#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
88#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
89#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
90#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
91 u8 flags1;
92#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
93#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
94#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
95#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
96#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
97#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
98#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
99#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
100#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
101#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
102#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
103#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
104#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
105#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
106#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
107#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
108 u8 flags2;
109#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
110#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
111#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
112#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
113#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
114#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
115#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
116#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
117 u8 flags3;
118#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
119#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
120#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
121#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
122#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
123#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
124#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
125#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
126 u8 flags4;
127#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
128#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
129#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
130#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
131#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
132#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
133#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
134#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
135 u8 flags5;
136#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
137#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
138#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
139#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
140#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
141#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
142#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
143#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
144 u8 flags6;
145#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */
146#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
147#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
148#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
149#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
150#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
151#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
152#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
153 u8 flags7;
154#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
155#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
156#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
157#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
158#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
159#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
160#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
161#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
162#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
163#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
164 u8 flags8;
165#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
166#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
167#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
168#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
169#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
170#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
171#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
172#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
173#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
174#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
175#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
176#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
177#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
178#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
179#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
180#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
181 u8 flags9;
182#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
183#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
184#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
185#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
186#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
187#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
188#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
189#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
190#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
191#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
192#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
193#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
194#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */
195#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
196#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
197#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
198 u8 flags10;
199#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
200#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
201#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
202#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
203#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
204#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
205#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
206#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
207#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
208#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
209#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
210#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
211#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
212#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
213#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
214#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
215 u8 flags11;
216#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
217#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
218#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
219#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
220#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
221#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
222#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
223#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
224#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
225#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
226#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
227#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
228#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
229#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
230#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
231#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
232 u8 flags12;
233#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
234#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
235#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
236#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
237#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
238#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
239#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
240#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
241#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
242#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
243#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
244#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
245#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
246#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
247#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
248#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
249 u8 flags13;
250#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
251#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
252#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
253#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
254#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
255#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
256#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
257#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
258#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
259#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
260#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
261#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
262#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
263#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
264#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
265#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
266 u8 flags14;
267#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
268#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
269#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
270#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
271#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
272#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
273#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
274#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
275#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
276#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
277#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
278#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
279#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
280#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
281 u8 byte2 /* byte2 */;
282 __le16 physical_q0 /* physical_q0 */;
283 __le16 consolid_prod /* physical_q1 */;
284 __le16 reserved16 /* physical_q2 */;
285 __le16 tx_bd_cons /* word3 */;
286 __le16 tx_bd_or_spq_prod /* word4 */;
287 __le16 word5 /* word5 */;
288 __le16 conn_dpi /* conn_dpi */;
289 u8 byte3 /* byte3 */;
290 u8 byte4 /* byte4 */;
291 u8 byte5 /* byte5 */;
292 u8 byte6 /* byte6 */;
293 __le32 reg0 /* reg0 */;
294 __le32 reg1 /* reg1 */;
295 __le32 reg2 /* reg2 */;
296 __le32 reg3 /* reg3 */;
297 __le32 reg4 /* reg4 */;
298 __le32 reg5 /* cf_array0 */;
299 __le32 reg6 /* cf_array1 */;
300 __le16 word7 /* word7 */;
301 __le16 word8 /* word8 */;
302 __le16 word9 /* word9 */;
303 __le16 word10 /* word10 */;
304 __le32 reg7 /* reg7 */;
305 __le32 reg8 /* reg8 */;
306 __le32 reg9 /* reg9 */;
307 u8 byte7 /* byte7 */;
308 u8 byte8 /* byte8 */;
309 u8 byte9 /* byte9 */;
310 u8 byte10 /* byte10 */;
311 u8 byte11 /* byte11 */;
312 u8 byte12 /* byte12 */;
313 u8 byte13 /* byte13 */;
314 u8 byte14 /* byte14 */;
315 u8 byte15 /* byte15 */;
316 u8 byte16 /* byte16 */;
317 __le16 word11 /* word11 */;
318 __le32 reg10 /* reg10 */;
319 __le32 reg11 /* reg11 */;
320 __le32 reg12 /* reg12 */;
321 __le32 reg13 /* reg13 */;
322 __le32 reg14 /* reg14 */;
323 __le32 reg15 /* reg15 */;
324 __le32 reg16 /* reg16 */;
325 __le32 reg17 /* reg17 */;
326 __le32 reg18 /* reg18 */;
327 __le32 reg19 /* reg19 */;
328 __le16 word12 /* word12 */;
329 __le16 word13 /* word13 */;
330 __le16 word14 /* word14 */;
331 __le16 word15 /* word15 */;
332};
333
334/* The core storm context for the Mstorm */
335struct mstorm_core_conn_st_ctx {
336 __le32 reserved[24];
337};
338
339/* The core storm context for the Ustorm */
340struct ustorm_core_conn_st_ctx {
341 __le32 reserved[4];
342};
343
344/* core connection context */
345struct core_conn_context {
346 struct ystorm_core_conn_st_ctx ystorm_st_context;
347 struct regpair ystorm_st_padding[2] /* padding */;
348 struct pstorm_core_conn_st_ctx pstorm_st_context;
349 struct regpair pstorm_st_padding[2];
350 struct xstorm_core_conn_st_ctx xstorm_st_context;
351 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
352 struct mstorm_core_conn_st_ctx mstorm_st_context;
353 struct regpair mstorm_st_padding[2];
354 struct ustorm_core_conn_st_ctx ustorm_st_context;
355 struct regpair ustorm_st_padding[2] /* padding */;
356};
357
358/* Event Ring Next Page Address */
359struct event_ring_next_addr {
360 struct regpair addr /* Next Page Address */;
361 __le32 reserved[2] /* Reserved */;
362};
363
364union event_ring_element {
365 struct event_ring_entry entry /* Event Ring Entry */;
366 struct event_ring_next_addr next_addr;
367};
368
369enum personality_type {
370 PERSONALITY_RESERVED,
371 PERSONALITY_RESERVED2,
372 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp */,
373 PERSONALITY_RESERVED3,
374 PERSONALITY_ETH /* Ethernet */,
375 PERSONALITY_RESERVED4,
376 MAX_PERSONALITY_TYPE
377};
378
379struct pf_start_tunnel_config {
380 u8 set_vxlan_udp_port_flg;
381 u8 set_geneve_udp_port_flg;
382 u8 tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
383 u8 tx_enable_l2geneve;
384 u8 tx_enable_ipgeneve;
385 u8 tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
386 u8 tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
387 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
388 u8 tunnel_clss_l2geneve;
389 u8 tunnel_clss_ipgeneve;
390 u8 tunnel_clss_l2gre;
391 u8 tunnel_clss_ipgre;
392 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
393 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
394};
395
396/* Ramrod data for PF start ramrod */
397struct pf_start_ramrod_data {
398 struct regpair event_ring_pbl_addr;
399 struct regpair consolid_q_pbl_addr;
400 struct pf_start_tunnel_config tunnel_config;
401 __le16 event_ring_sb_id;
402 u8 base_vf_id;
403 u8 num_vfs;
404 u8 event_ring_num_pages;
405 u8 event_ring_sb_index;
406 u8 path_id;
407 u8 warning_as_error;
408 u8 dont_log_ramrods;
409 u8 personality;
410 __le16 log_type_mask;
411 u8 mf_mode /* Multi function mode */;
412 u8 integ_phase /* Integration phase */;
413 u8 allow_npar_tx_switching;
414 u8 inner_to_outer_pri_map[8];
415 u8 pri_map_valid;
416 u32 outer_tag;
417 u8 reserved0[4];
418};
419
420enum ports_mode {
421 ENGX2_PORTX1 /* 2 engines x 1 port */,
422 ENGX2_PORTX2 /* 2 engines x 2 ports */,
423 ENGX1_PORTX1 /* 1 engine x 1 port */,
424 ENGX1_PORTX2 /* 1 engine x 2 ports */,
425 ENGX1_PORTX4 /* 1 engine x 4 ports */,
426 MAX_PORTS_MODE
427};
428
429/* Ramrod Header of SPQE */
430struct ramrod_header {
431 __le32 cid /* Slowpath Connection CID */;
432 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */;
433 u8 protocol_id /* Ramrod Protocol ID */;
434 __le16 echo /* Ramrod echo */;
435};
436
437/* Slowpath Element (SPQE) */
438struct slow_path_element {
439 struct ramrod_header hdr /* Ramrod Header */;
440 struct regpair data_ptr;
441};
442
443struct tstorm_per_port_stat {
444 struct regpair trunc_error_discard;
445 struct regpair mac_error_discard;
446 struct regpair mftag_filter_discard;
447 struct regpair eth_mac_filter_discard;
448 struct regpair ll2_mac_filter_discard;
449 struct regpair ll2_conn_disabled_discard;
450 struct regpair iscsi_irregular_pkt;
451 struct regpair fcoe_irregular_pkt;
452 struct regpair roce_irregular_pkt;
453 struct regpair eth_irregular_pkt;
454 struct regpair toe_irregular_pkt;
455 struct regpair preroce_irregular_pkt;
456};
457
458struct atten_status_block {
459 __le32 atten_bits;
460 __le32 atten_ack;
461 __le16 reserved0;
462 __le16 sb_index /* status block running index */;
463 __le32 reserved1;
464};
465
466enum block_addr {
467 GRCBASE_GRC = 0x50000,
468 GRCBASE_MISCS = 0x9000,
469 GRCBASE_MISC = 0x8000,
470 GRCBASE_DBU = 0xa000,
471 GRCBASE_PGLUE_B = 0x2a8000,
472 GRCBASE_CNIG = 0x218000,
473 GRCBASE_CPMU = 0x30000,
474 GRCBASE_NCSI = 0x40000,
475 GRCBASE_OPTE = 0x53000,
476 GRCBASE_BMB = 0x540000,
477 GRCBASE_PCIE = 0x54000,
478 GRCBASE_MCP = 0xe00000,
479 GRCBASE_MCP2 = 0x52000,
480 GRCBASE_PSWHST = 0x2a0000,
481 GRCBASE_PSWHST2 = 0x29e000,
482 GRCBASE_PSWRD = 0x29c000,
483 GRCBASE_PSWRD2 = 0x29d000,
484 GRCBASE_PSWWR = 0x29a000,
485 GRCBASE_PSWWR2 = 0x29b000,
486 GRCBASE_PSWRQ = 0x280000,
487 GRCBASE_PSWRQ2 = 0x240000,
488 GRCBASE_PGLCS = 0x0,
489 GRCBASE_PTU = 0x560000,
490 GRCBASE_DMAE = 0xc000,
491 GRCBASE_TCM = 0x1180000,
492 GRCBASE_MCM = 0x1200000,
493 GRCBASE_UCM = 0x1280000,
494 GRCBASE_XCM = 0x1000000,
495 GRCBASE_YCM = 0x1080000,
496 GRCBASE_PCM = 0x1100000,
497 GRCBASE_QM = 0x2f0000,
498 GRCBASE_TM = 0x2c0000,
499 GRCBASE_DORQ = 0x100000,
500 GRCBASE_BRB = 0x340000,
501 GRCBASE_SRC = 0x238000,
502 GRCBASE_PRS = 0x1f0000,
503 GRCBASE_TSDM = 0xfb0000,
504 GRCBASE_MSDM = 0xfc0000,
505 GRCBASE_USDM = 0xfd0000,
506 GRCBASE_XSDM = 0xf80000,
507 GRCBASE_YSDM = 0xf90000,
508 GRCBASE_PSDM = 0xfa0000,
509 GRCBASE_TSEM = 0x1700000,
510 GRCBASE_MSEM = 0x1800000,
511 GRCBASE_USEM = 0x1900000,
512 GRCBASE_XSEM = 0x1400000,
513 GRCBASE_YSEM = 0x1500000,
514 GRCBASE_PSEM = 0x1600000,
515 GRCBASE_RSS = 0x238800,
516 GRCBASE_TMLD = 0x4d0000,
517 GRCBASE_MULD = 0x4e0000,
518 GRCBASE_YULD = 0x4c8000,
519 GRCBASE_XYLD = 0x4c0000,
520 GRCBASE_PRM = 0x230000,
521 GRCBASE_PBF_PB1 = 0xda0000,
522 GRCBASE_PBF_PB2 = 0xda4000,
523 GRCBASE_RPB = 0x23c000,
524 GRCBASE_BTB = 0xdb0000,
525 GRCBASE_PBF = 0xd80000,
526 GRCBASE_RDIF = 0x300000,
527 GRCBASE_TDIF = 0x310000,
528 GRCBASE_CDU = 0x580000,
529 GRCBASE_CCFC = 0x2e0000,
530 GRCBASE_TCFC = 0x2d0000,
531 GRCBASE_IGU = 0x180000,
532 GRCBASE_CAU = 0x1c0000,
533 GRCBASE_UMAC = 0x51000,
534 GRCBASE_XMAC = 0x210000,
535 GRCBASE_DBG = 0x10000,
536 GRCBASE_NIG = 0x500000,
537 GRCBASE_WOL = 0x600000,
538 GRCBASE_BMBN = 0x610000,
539 GRCBASE_IPC = 0x20000,
540 GRCBASE_NWM = 0x800000,
541 GRCBASE_NWS = 0x700000,
542 GRCBASE_MS = 0x6a0000,
543 GRCBASE_PHY_PCIE = 0x618000,
544 GRCBASE_MISC_AEU = 0x8000,
545 GRCBASE_BAR0_MAP = 0x1c00000,
546 MAX_BLOCK_ADDR
547};
548
549enum block_id {
550 BLOCK_GRC,
551 BLOCK_MISCS,
552 BLOCK_MISC,
553 BLOCK_DBU,
554 BLOCK_PGLUE_B,
555 BLOCK_CNIG,
556 BLOCK_CPMU,
557 BLOCK_NCSI,
558 BLOCK_OPTE,
559 BLOCK_BMB,
560 BLOCK_PCIE,
561 BLOCK_MCP,
562 BLOCK_MCP2,
563 BLOCK_PSWHST,
564 BLOCK_PSWHST2,
565 BLOCK_PSWRD,
566 BLOCK_PSWRD2,
567 BLOCK_PSWWR,
568 BLOCK_PSWWR2,
569 BLOCK_PSWRQ,
570 BLOCK_PSWRQ2,
571 BLOCK_PGLCS,
572 BLOCK_PTU,
573 BLOCK_DMAE,
574 BLOCK_TCM,
575 BLOCK_MCM,
576 BLOCK_UCM,
577 BLOCK_XCM,
578 BLOCK_YCM,
579 BLOCK_PCM,
580 BLOCK_QM,
581 BLOCK_TM,
582 BLOCK_DORQ,
583 BLOCK_BRB,
584 BLOCK_SRC,
585 BLOCK_PRS,
586 BLOCK_TSDM,
587 BLOCK_MSDM,
588 BLOCK_USDM,
589 BLOCK_XSDM,
590 BLOCK_YSDM,
591 BLOCK_PSDM,
592 BLOCK_TSEM,
593 BLOCK_MSEM,
594 BLOCK_USEM,
595 BLOCK_XSEM,
596 BLOCK_YSEM,
597 BLOCK_PSEM,
598 BLOCK_RSS,
599 BLOCK_TMLD,
600 BLOCK_MULD,
601 BLOCK_YULD,
602 BLOCK_XYLD,
603 BLOCK_PRM,
604 BLOCK_PBF_PB1,
605 BLOCK_PBF_PB2,
606 BLOCK_RPB,
607 BLOCK_BTB,
608 BLOCK_PBF,
609 BLOCK_RDIF,
610 BLOCK_TDIF,
611 BLOCK_CDU,
612 BLOCK_CCFC,
613 BLOCK_TCFC,
614 BLOCK_IGU,
615 BLOCK_CAU,
616 BLOCK_UMAC,
617 BLOCK_XMAC,
618 BLOCK_DBG,
619 BLOCK_NIG,
620 BLOCK_WOL,
621 BLOCK_BMBN,
622 BLOCK_IPC,
623 BLOCK_NWM,
624 BLOCK_NWS,
625 BLOCK_MS,
626 BLOCK_PHY_PCIE,
627 BLOCK_MISC_AEU,
628 BLOCK_BAR0_MAP,
629 MAX_BLOCK_ID
630};
631
632enum command_type_bit {
633 IGU_COMMAND_TYPE_NOP = 0,
634 IGU_COMMAND_TYPE_SET = 1,
635 MAX_COMMAND_TYPE_BIT
636};
637
638struct dmae_cmd {
639 __le32 opcode;
640#define DMAE_CMD_SRC_MASK 0x1
641#define DMAE_CMD_SRC_SHIFT 0
642#define DMAE_CMD_DST_MASK 0x3
643#define DMAE_CMD_DST_SHIFT 1
644#define DMAE_CMD_C_DST_MASK 0x1
645#define DMAE_CMD_C_DST_SHIFT 3
646#define DMAE_CMD_CRC_RESET_MASK 0x1
647#define DMAE_CMD_CRC_RESET_SHIFT 4
648#define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
649#define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
650#define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
651#define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
652#define DMAE_CMD_COMP_FUNC_MASK 0x1
653#define DMAE_CMD_COMP_FUNC_SHIFT 7
654#define DMAE_CMD_COMP_WORD_EN_MASK 0x1
655#define DMAE_CMD_COMP_WORD_EN_SHIFT 8
656#define DMAE_CMD_COMP_CRC_EN_MASK 0x1
657#define DMAE_CMD_COMP_CRC_EN_SHIFT 9
658#define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
659#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
660#define DMAE_CMD_RESERVED1_MASK 0x1
661#define DMAE_CMD_RESERVED1_SHIFT 13
662#define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
663#define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
664#define DMAE_CMD_ERR_HANDLING_MASK 0x3
665#define DMAE_CMD_ERR_HANDLING_SHIFT 16
666#define DMAE_CMD_PORT_ID_MASK 0x3
667#define DMAE_CMD_PORT_ID_SHIFT 18
668#define DMAE_CMD_SRC_PF_ID_MASK 0xF
669#define DMAE_CMD_SRC_PF_ID_SHIFT 20
670#define DMAE_CMD_DST_PF_ID_MASK 0xF
671#define DMAE_CMD_DST_PF_ID_SHIFT 24
672#define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
673#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
674#define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
675#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
676#define DMAE_CMD_RESERVED2_MASK 0x3
677#define DMAE_CMD_RESERVED2_SHIFT 30
678 __le32 src_addr_lo;
679 __le32 src_addr_hi;
680 __le32 dst_addr_lo;
681 __le32 dst_addr_hi;
682 __le16 length /* Length in DW */;
683 __le16 opcode_b;
684#define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */
685#define DMAE_CMD_SRC_VF_ID_SHIFT 0
686#define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */
687#define DMAE_CMD_DST_VF_ID_SHIFT 8
688 __le32 comp_addr_lo /* PCIe completion address low or grc address */;
689 __le32 comp_addr_hi;
690 __le32 comp_val /* Value to write to copmletion address */;
691 __le32 crc32 /* crc16 result */;
692 __le32 crc_32_c /* crc32_c result */;
693 __le16 crc16 /* crc16 result */;
694 __le16 crc16_c /* crc16_c result */;
695 __le16 crc10 /* crc_t10 result */;
696 __le16 reserved;
697 __le16 xsum16 /* checksum16 result */;
698 __le16 xsum8 /* checksum8 result */;
699};
700
701struct igu_cleanup {
702 __le32 sb_id_and_flags;
703#define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
704#define IGU_CLEANUP_RESERVED0_SHIFT 0
705#define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 /* cleanup clear - 0, set - 1 */
706#define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
707#define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
708#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
709#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
710#define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
711 __le32 reserved1;
712};
713
714union igu_command {
715 struct igu_prod_cons_update prod_cons_update;
716 struct igu_cleanup cleanup;
717};
718
719struct igu_command_reg_ctrl {
720 __le16 opaque_fid;
721 __le16 igu_command_reg_ctrl_fields;
722#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
723#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
724#define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
725#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
726#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
727#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
728};
729
730struct igu_mapping_line {
731 __le32 igu_mapping_line_fields;
732#define IGU_MAPPING_LINE_VALID_MASK 0x1
733#define IGU_MAPPING_LINE_VALID_SHIFT 0
734#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
735#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
736#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
737#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
738#define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */
739#define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
740#define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
741#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
742#define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
743#define IGU_MAPPING_LINE_RESERVED_SHIFT 24
744};
745
746struct igu_msix_vector {
747 struct regpair address;
748 __le32 data;
749 __le32 msix_vector_fields;
750#define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
751#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
752#define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
753#define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
754#define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
755#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
756#define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
757#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
758};
759
760enum init_modes {
761 MODE_BB_A0,
762 MODE_RESERVED,
763 MODE_RESERVED2,
764 MODE_ASIC,
765 MODE_RESERVED3,
766 MODE_RESERVED4,
767 MODE_RESERVED5,
768 MODE_SF,
769 MODE_MF_SD,
770 MODE_MF_SI,
771 MODE_PORTS_PER_ENG_1,
772 MODE_PORTS_PER_ENG_2,
773 MODE_PORTS_PER_ENG_4,
774 MODE_40G,
775 MODE_100G,
776 MODE_EAGLE_ENG1_WORKAROUND,
777 MAX_INIT_MODES
778};
779
780enum init_phases {
781 PHASE_ENGINE,
782 PHASE_PORT,
783 PHASE_PF,
784 PHASE_RESERVED,
785 PHASE_QM_PF,
786 MAX_INIT_PHASES
787};
788
789struct mstorm_core_conn_ag_ctx {
790 u8 byte0 /* cdu_validation */;
791 u8 byte1 /* state */;
792 u8 flags0;
793#define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
794#define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
795#define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
796#define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
797#define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
798#define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
799#define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
800#define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
801#define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
802#define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
803 u8 flags1;
804#define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
805#define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
806#define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
807#define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
808#define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
809#define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
810#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
811#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
812#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
813#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
814#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
815#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
816#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
817#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
818#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
819#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
820 __le16 word0 /* word0 */;
821 __le16 word1 /* word1 */;
822 __le32 reg0 /* reg0 */;
823 __le32 reg1 /* reg1 */;
824};
825
826/* per encapsulation type enabling flags */
827struct prs_reg_encapsulation_type_en {
828 u8 flags;
829#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
830#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
831#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
832#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
833#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
834#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
835#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
836#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
837#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
838#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
839#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
840#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
841#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
842#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
843};
844
845enum pxp_tph_st_hint {
846 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
847 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
848 TPH_ST_HINT_TARGET,
849 TPH_ST_HINT_TARGET_PRIO,
850 MAX_PXP_TPH_ST_HINT
851};
852
853/* QM hardware structure of enable bypass credit mask */
854struct qm_rf_bypass_mask {
855 u8 flags;
856#define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
857#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
858#define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
859#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
860#define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
861#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
862#define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
863#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
864#define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
865#define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
866#define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
867#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
868#define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
869#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
870#define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
871#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
872};
873
874/* QM hardware structure of opportunistic credit mask */
875struct qm_rf_opportunistic_mask {
876 __le16 flags;
877#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
878#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
879#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
880#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
881#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
882#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
883#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
884#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
885#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
886#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
887#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
888#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
889#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
890#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
891#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
892#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
893#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
894#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
895#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
896#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
897};
898
899/* QM hardware structure of QM map memory */
900struct qm_rf_pq_map {
901 u32 reg;
902#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */
903#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
904#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */
905#define QM_RF_PQ_MAP_RL_ID_SHIFT 1
906#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
907#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
908#define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */
909#define QM_RF_PQ_MAP_VOQ_SHIFT 18
910#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
911#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
912#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */
913#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
914#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
915#define QM_RF_PQ_MAP_RESERVED_SHIFT 26
916};
917
918/* SDM operation gen command (generate aggregative interrupt) */
919struct sdm_op_gen {
920 __le32 command;
921#define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF /* completion parameters 0-15 */
922#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
923#define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */
924#define SDM_OP_GEN_COMP_TYPE_SHIFT 16
925#define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */
926#define SDM_OP_GEN_RESERVED_SHIFT 20
927};
928
929struct tstorm_core_conn_ag_ctx {
930 u8 byte0 /* cdu_validation */;
931 u8 byte1 /* state */;
932 u8 flags0;
933#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
934#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
935#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
936#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
937#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
938#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
939#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
940#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
941#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
942#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
943#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
944#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
945#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
946#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
947 u8 flags1;
948#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
949#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
950#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
951#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
952#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
953#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
954#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
955#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
956 u8 flags2;
957#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
958#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
959#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
960#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
961#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
962#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
963#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
964#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
965 u8 flags3;
966#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
967#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
968#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
969#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
970#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
971#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
972#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
973#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
974#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
975#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
976#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
977#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
978 u8 flags4;
979#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
980#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
981#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
982#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
983#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
984#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
985#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
986#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
987#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
988#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
989#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
990#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
991#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
992#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
993#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
994#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
995 u8 flags5;
996#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
997#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
998#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
999#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
1000#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1001#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
1002#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1003#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
1004#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1005#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
1006#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1007#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
1008#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1009#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
1010#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1011#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
1012 __le32 reg0 /* reg0 */;
1013 __le32 reg1 /* reg1 */;
1014 __le32 reg2 /* reg2 */;
1015 __le32 reg3 /* reg3 */;
1016 __le32 reg4 /* reg4 */;
1017 __le32 reg5 /* reg5 */;
1018 __le32 reg6 /* reg6 */;
1019 __le32 reg7 /* reg7 */;
1020 __le32 reg8 /* reg8 */;
1021 u8 byte2 /* byte2 */;
1022 u8 byte3 /* byte3 */;
1023 __le16 word0 /* word0 */;
1024 u8 byte4 /* byte4 */;
1025 u8 byte5 /* byte5 */;
1026 __le16 word1 /* word1 */;
1027 __le16 word2 /* conn_dpi */;
1028 __le16 word3 /* word3 */;
1029 __le32 reg9 /* reg9 */;
1030 __le32 reg10 /* reg10 */;
1031};
1032
1033struct ustorm_core_conn_ag_ctx {
1034 u8 reserved /* cdu_validation */;
1035 u8 byte1 /* state */;
1036 u8 flags0;
1037#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1038#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1039#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1040#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1041#define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1042#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1043#define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1044#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1045#define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1046#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1047 u8 flags1;
1048#define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1049#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
1050#define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1051#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
1052#define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1053#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
1054#define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1055#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
1056 u8 flags2;
1057#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1058#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1059#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1060#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1061#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1062#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1063#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1064#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
1065#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1066#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
1067#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1068#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
1069#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1070#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
1071#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1072#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
1073 u8 flags3;
1074#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1075#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
1076#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1077#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
1078#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1079#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
1080#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1081#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
1082#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1083#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
1084#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1085#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
1086#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1087#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
1088#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1089#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
1090 u8 byte2 /* byte2 */;
1091 u8 byte3 /* byte3 */;
1092 __le16 word0 /* conn_dpi */;
1093 __le16 word1 /* word1 */;
1094 __le32 rx_producers /* reg0 */;
1095 __le32 reg1 /* reg1 */;
1096 __le32 reg2 /* reg2 */;
1097 __le32 reg3 /* reg3 */;
1098 __le16 word2 /* word2 */;
1099 __le16 word3 /* word3 */;
1100};
1101
1102struct ystorm_core_conn_ag_ctx {
1103 u8 byte0 /* cdu_validation */;
1104 u8 byte1 /* state */;
1105 u8 flags0;
1106#define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1107#define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1108#define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1109#define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1110#define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1111#define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1112#define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1113#define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1114#define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1115#define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1116 u8 flags1;
1117#define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1118#define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1119#define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1120#define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1121#define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1122#define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1123#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1124#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1125#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1126#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1127#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1128#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1129#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1130#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1131#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1132#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1133 u8 byte2 /* byte2 */;
1134 u8 byte3 /* byte3 */;
1135 __le16 word0 /* word0 */;
1136 __le32 reg0 /* reg0 */;
1137 __le32 reg1 /* reg1 */;
1138 __le16 word1 /* word1 */;
1139 __le16 word2 /* word2 */;
1140 __le16 word3 /* word3 */;
1141 __le16 word4 /* word4 */;
1142 __le32 reg2 /* reg2 */;
1143 __le32 reg3 /* reg3 */;
1144};
1145
1146/*********************************** Init ************************************/
1147
1148/* Width of GRC address in bits (addresses are specified in dwords) */
1149#define GRC_ADDR_BITS 23
1150#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
1151
1152/* indicates an init that should be applied to any phase ID */
1153#define ANY_PHASE_ID 0xffff
1154
1155/* init pattern size in bytes */
1156#define INIT_PATTERN_SIZE_BITS 4
1157#define MAX_INIT_PATTERN_SIZE BIT(INIT_PATTERN_SIZE_BITS)
1158
1159/* Max size in dwords of a zipped array */
1160#define MAX_ZIPPED_SIZE 8192
1161
1162/* Global PXP window */
1163#define NUM_OF_PXP_WIN 19
1164#define PXP_WIN_DWORD_SIZE_BITS 10
1165#define PXP_WIN_DWORD_SIZE BIT(PXP_WIN_DWORD_SIZE_BITS)
1166#define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2)
1167#define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4)
1168
1169/********************************* GRC Dump **********************************/
1170
1171/* width of GRC dump register sequence length in bits */
1172#define DUMP_SEQ_LEN_BITS 8
1173#define DUMP_SEQ_LEN_MAX_VAL ((1 << DUMP_SEQ_LEN_BITS) - 1)
1174
1175/* width of GRC dump memory length in bits */
1176#define DUMP_MEM_LEN_BITS 18
1177#define DUMP_MEM_LEN_MAX_VAL ((1 << DUMP_MEM_LEN_BITS) - 1)
1178
1179/* width of register type ID in bits */
1180#define REG_TYPE_ID_BITS 6
1181#define REG_TYPE_ID_MAX_VAL ((1 << REG_TYPE_ID_BITS) - 1)
1182
1183/* width of block ID in bits */
1184#define BLOCK_ID_BITS 8
1185#define BLOCK_ID_MAX_VAL ((1 << BLOCK_ID_BITS) - 1)
1186
1187/******************************** Idle Check *********************************/
1188
1189/* max number of idle check predicate immediates */
1190#define MAX_IDLE_CHK_PRED_IMM 3
1191
1192/* max number of idle check argument registers */
1193#define MAX_IDLE_CHK_READ_REGS 3
1194
1195/* max number of idle check loops */
1196#define MAX_IDLE_CHK_LOOPS 0x10000
1197
1198/* max idle check address increment */
1199#define MAX_IDLE_CHK_INCREMENT 0x10000
1200
1201/* inicates an undefined idle check line index */
1202#define IDLE_CHK_UNDEFINED_LINE_IDX 0xffffff
1203
1204/* max number of register values following the idle check header */
1205#define IDLE_CHK_MAX_DUMP_REGS 2
1206
1207/* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
1208#define IDLE_CHK_QM_RD_WR_PTR 0
1209#define IDLE_CHK_QM_RD_WR_BANK 1
1210
1211/**************************************/
1212/* HSI Functions constants and macros */
1213/**************************************/
1214
1215/* Number of VLAN priorities */
1216#define NUM_OF_VLAN_PRIORITIES 8
1217
1218/* the MCP Trace meta data signautre is duplicated in the perl script that
1219 * generats the NVRAM images.
1220 */
1221#define MCP_TRACE_META_IMAGE_SIGNATURE 0x669955aa
1222
1223/* Binary buffer header */
1224struct bin_buffer_hdr {
1225 u32 offset;
1226 u32 length /* buffer length in bytes */;
1227};
1228
1229/* binary buffer types */
1230enum bin_buffer_type {
1231 BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
1232 BIN_BUF_INIT_CMD /* init commands */,
1233 BIN_BUF_INIT_VAL /* init data */,
1234 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
1235 BIN_BUF_IRO /* internal RAM offsets array */,
1236 MAX_BIN_BUFFER_TYPE
1237};
1238
1239/* Chip IDs */
1240enum chip_ids {
1241 CHIP_BB_A0 /* BB A0 chip ID */,
1242 CHIP_BB_B0 /* BB B0 chip ID */,
1243 CHIP_K2 /* AH chip ID */,
1244 MAX_CHIP_IDS
1245};
1246
1247enum idle_chk_severity_types {
1248 IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */,
1249 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
1250 IDLE_CHK_SEVERITY_WARNING,
1251 MAX_IDLE_CHK_SEVERITY_TYPES
1252};
1253
1254struct init_array_raw_hdr {
1255 __le32 data;
1256#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
1257#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
1258#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */
1259#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1260};
1261
1262struct init_array_standard_hdr {
1263 __le32 data;
1264#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
1265#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
1266#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
1267#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
1268};
1269
1270struct init_array_zipped_hdr {
1271 __le32 data;
1272#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
1273#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
1274#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
1275#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1276};
1277
1278struct init_array_pattern_hdr {
1279 __le32 data;
1280#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
1281#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
1282#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
1283#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
1284#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
1285#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
1286};
1287
1288union init_array_hdr {
1289 struct init_array_raw_hdr raw /* raw init array header */;
1290 struct init_array_standard_hdr standard;
1291 struct init_array_zipped_hdr zipped /* zipped init array header */;
1292 struct init_array_pattern_hdr pattern /* pattern init array header */;
1293};
1294
1295enum init_array_types {
1296 INIT_ARR_STANDARD /* standard init array */,
1297 INIT_ARR_ZIPPED /* zipped init array */,
1298 INIT_ARR_PATTERN /* a repeated pattern */,
1299 MAX_INIT_ARRAY_TYPES
1300};
1301
1302/* init operation: callback */
1303struct init_callback_op {
1304 __le32 op_data;
1305#define INIT_CALLBACK_OP_OP_MASK 0xF
1306#define INIT_CALLBACK_OP_OP_SHIFT 0
1307#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
1308#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1309 __le16 callback_id /* Callback ID */;
1310 __le16 block_id /* Blocks ID */;
1311};
1312
1313/* init comparison types */
1314enum init_comparison_types {
1315 INIT_COMPARISON_EQ /* init value is included in the init command */,
1316 INIT_COMPARISON_OR /* init value is all zeros */,
1317 INIT_COMPARISON_AND /* init value is an array of values */,
1318 MAX_INIT_COMPARISON_TYPES
1319};
1320
1321/* init operation: delay */
1322struct init_delay_op {
1323 __le32 op_data;
1324#define INIT_DELAY_OP_OP_MASK 0xF
1325#define INIT_DELAY_OP_OP_SHIFT 0
1326#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
1327#define INIT_DELAY_OP_RESERVED_SHIFT 4
1328 __le32 delay /* delay in us */;
1329};
1330
1331/* init operation: if_mode */
1332struct init_if_mode_op {
1333 __le32 op_data;
1334#define INIT_IF_MODE_OP_OP_MASK 0xF
1335#define INIT_IF_MODE_OP_OP_SHIFT 0
1336#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
1337#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
1338#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
1339#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
1340 __le16 reserved2;
1341 __le16 modes_buf_offset;
1342};
1343
1344/* init operation: if_phase */
1345struct init_if_phase_op {
1346 __le32 op_data;
1347#define INIT_IF_PHASE_OP_OP_MASK 0xF
1348#define INIT_IF_PHASE_OP_OP_SHIFT 0
1349#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
1350#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
1351#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
1352#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
1353#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
1354#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
1355 __le32 phase_data;
1356#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
1357#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
1358#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
1359#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
1360#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
1361#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
1362};
1363
1364/* init mode operators */
1365enum init_mode_ops {
1366 INIT_MODE_OP_NOT /* init mode not operator */,
1367 INIT_MODE_OP_OR /* init mode or operator */,
1368 INIT_MODE_OP_AND /* init mode and operator */,
1369 MAX_INIT_MODE_OPS
1370};
1371
1372/* init operation: raw */
1373struct init_raw_op {
1374 __le32 op_data;
1375#define INIT_RAW_OP_OP_MASK 0xF
1376#define INIT_RAW_OP_OP_SHIFT 0
1377#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
1378#define INIT_RAW_OP_PARAM1_SHIFT 4
1379 __le32 param2 /* Init param 2 */;
1380};
1381
1382/* init array params */
1383struct init_op_array_params {
1384 __le16 size /* array size in dwords */;
1385 __le16 offset /* array start offset in dwords */;
1386};
1387
1388/* Write init operation arguments */
1389union init_write_args {
1390 __le32 inline_val;
1391 __le32 zeros_count;
1392 __le32 array_offset;
1393 struct init_op_array_params runtime;
1394};
1395
1396/* init operation: write */
1397struct init_write_op {
1398 __le32 data;
1399#define INIT_WRITE_OP_OP_MASK 0xF
1400#define INIT_WRITE_OP_OP_SHIFT 0
1401#define INIT_WRITE_OP_SOURCE_MASK 0x7
1402#define INIT_WRITE_OP_SOURCE_SHIFT 4
1403#define INIT_WRITE_OP_RESERVED_MASK 0x1
1404#define INIT_WRITE_OP_RESERVED_SHIFT 7
1405#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
1406#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
1407#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
1408#define INIT_WRITE_OP_ADDRESS_SHIFT 9
1409 union init_write_args args /* Write init operation arguments */;
1410};
1411
1412/* init operation: read */
1413struct init_read_op {
1414 __le32 op_data;
1415#define INIT_READ_OP_OP_MASK 0xF
1416#define INIT_READ_OP_OP_SHIFT 0
1417#define INIT_READ_OP_POLL_COMP_MASK 0x7
1418#define INIT_READ_OP_POLL_COMP_SHIFT 4
1419#define INIT_READ_OP_RESERVED_MASK 0x1
1420#define INIT_READ_OP_RESERVED_SHIFT 7
1421#define INIT_READ_OP_POLL_MASK 0x1
1422#define INIT_READ_OP_POLL_SHIFT 8
1423#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
1424#define INIT_READ_OP_ADDRESS_SHIFT 9
1425 __le32 expected_val;
1426};
1427
1428/* Init operations union */
1429union init_op {
1430 struct init_raw_op raw /* raw init operation */;
1431 struct init_write_op write /* write init operation */;
1432 struct init_read_op read /* read init operation */;
1433 struct init_if_mode_op if_mode /* if_mode init operation */;
1434 struct init_if_phase_op if_phase /* if_phase init operation */;
1435 struct init_callback_op callback /* callback init operation */;
1436 struct init_delay_op delay /* delay init operation */;
1437};
1438
1439/* Init command operation types */
1440enum init_op_types {
1441 INIT_OP_READ /* GRC read init command */,
1442 INIT_OP_WRITE /* GRC write init command */,
1443 INIT_OP_IF_MODE,
1444 INIT_OP_IF_PHASE,
1445 INIT_OP_DELAY /* delay init command */,
1446 INIT_OP_CALLBACK /* callback init command */,
1447 MAX_INIT_OP_TYPES
1448};
1449
1450/* init source types */
1451enum init_source_types {
1452 INIT_SRC_INLINE /* init value is included in the init command */,
1453 INIT_SRC_ZEROS /* init value is all zeros */,
1454 INIT_SRC_ARRAY /* init value is an array of values */,
1455 INIT_SRC_RUNTIME /* init value is provided during runtime */,
1456 MAX_INIT_SOURCE_TYPES
1457};
1458
1459/* Internal RAM Offsets macro data */
1460struct iro {
1461 u32 base /* RAM field offset */;
1462 u16 m1 /* multiplier 1 */;
1463 u16 m2 /* multiplier 2 */;
1464 u16 m3 /* multiplier 3 */;
1465 u16 size /* RAM field size */;
1466};
1467
1468/* QM per-port init parameters */
1469struct init_qm_port_params {
1470 u8 active /* Indicates if this port is active */;
1471 u8 num_active_phys_tcs;
1472 u16 num_pbf_cmd_lines;
1473 u16 num_btb_blocks;
1474 __le16 reserved;
1475};
1476
1477/* QM per-PQ init parameters */
1478struct init_qm_pq_params {
1479 u8 vport_id /* VPORT ID */;
1480 u8 tc_id /* TC ID */;
1481 u8 wrr_group /* WRR group */;
1482 u8 reserved;
1483};
1484
1485/* QM per-vport init parameters */
1486struct init_qm_vport_params {
1487 u32 vport_rl;
1488 u16 vport_wfq;
1489 u16 first_tx_pq_id[NUM_OF_TCS];
1490};
1491
1492/* Win 2 */
1493#define GTT_BAR0_MAP_REG_IGU_CMD \
1494 0x00f000UL
1495/* Win 3 */
1496#define GTT_BAR0_MAP_REG_TSDM_RAM \
1497 0x010000UL
1498/* Win 4 */
1499#define GTT_BAR0_MAP_REG_MSDM_RAM \
1500 0x011000UL
1501/* Win 5 */
1502#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1503 0x012000UL
1504/* Win 6 */
1505#define GTT_BAR0_MAP_REG_USDM_RAM \
1506 0x013000UL
1507/* Win 7 */
1508#define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1509 0x014000UL
1510/* Win 8 */
1511#define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1512 0x015000UL
1513/* Win 9 */
1514#define GTT_BAR0_MAP_REG_XSDM_RAM \
1515 0x016000UL
1516/* Win 10 */
1517#define GTT_BAR0_MAP_REG_YSDM_RAM \
1518 0x017000UL
1519/* Win 11 */
1520#define GTT_BAR0_MAP_REG_PSDM_RAM \
1521 0x018000UL
1522
1523/**
1524 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
1525 *
1526 * Returns the required host memory size in 4KB units.
1527 * Must be called before all QM init HSI functions.
1528 *
1529 * @param pf_id - physical function ID
1530 * @param num_pf_cids - number of connections used by this PF
1531 * @param num_vf_cids - number of connections used by VFs of this PF
1532 * @param num_tids - number of tasks used by this PF
1533 * @param num_pf_pqs - number of PQs used by this PF
1534 * @param num_vf_pqs - number of PQs used by VFs of this PF
1535 *
1536 * @return The required host memory size in 4KB units.
1537 */
1538u32 qed_qm_pf_mem_size(u8 pf_id,
1539 u32 num_pf_cids,
1540 u32 num_vf_cids,
1541 u32 num_tids,
1542 u16 num_pf_pqs,
1543 u16 num_vf_pqs);
1544
1545struct qed_qm_common_rt_init_params {
1546 u8 max_ports_per_engine;
1547 u8 max_phys_tcs_per_port;
1548 bool pf_rl_en;
1549 bool pf_wfq_en;
1550 bool vport_rl_en;
1551 bool vport_wfq_en;
1552 struct init_qm_port_params *port_params;
1553};
1554
1555/**
1556 * @brief qed_qm_common_rt_init - Prepare QM runtime init values for the
1557 * engine phase.
1558 *
1559 * @param p_hwfn
1560 * @param max_ports_per_engine - max number of ports per engine in HW
1561 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
1562 * @param pf_rl_en - enable per-PF rate limiters
1563 * @param pf_wfq_en - enable per-PF WFQ
1564 * @param vport_rl_en - enable per-VPORT rate limiters
1565 * @param vport_wfq_en - enable per-VPORT WFQ
1566 * @param port_params - array of size MAX_NUM_PORTS with
1567 * arameters for each port
1568 *
1569 * @return 0 on success, -1 on error.
1570 */
1571int qed_qm_common_rt_init(
1572 struct qed_hwfn *p_hwfn,
1573 struct qed_qm_common_rt_init_params *p_params);
1574
1575struct qed_qm_pf_rt_init_params {
1576 u8 port_id;
1577 u8 pf_id;
1578 u8 max_phys_tcs_per_port;
1579 bool is_first_pf;
1580 u32 num_pf_cids;
1581 u32 num_vf_cids;
1582 u32 num_tids;
1583 u16 start_pq;
1584 u16 num_pf_pqs;
1585 u16 num_vf_pqs;
1586 u8 start_vport;
1587 u8 num_vports;
1588 u8 pf_wfq;
1589 u32 pf_rl;
1590 struct init_qm_pq_params *pq_params;
1591 struct init_qm_vport_params *vport_params;
1592};
1593
1594int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
1595 struct qed_ptt *p_ptt,
1596 struct qed_qm_pf_rt_init_params *p_params);
1597
1598/**
1599 * @brief qed_init_pf_rl Initializes the rate limit of the specified PF
1600 *
1601 * @param p_hwfn
1602 * @param p_ptt - ptt window used for writing the registers
1603 * @param pf_id - PF ID
1604 * @param pf_rl - rate limit in Mb/sec units
1605 *
1606 * @return 0 on success, -1 on error.
1607 */
1608int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
1609 struct qed_ptt *p_ptt,
1610 u8 pf_id,
1611 u32 pf_rl);
1612
1613/**
1614 * @brief qed_init_vport_rl Initializes the rate limit of the specified VPORT
1615 *
1616 * @param p_hwfn
1617 * @param p_ptt - ptt window used for writing the registers
1618 * @param vport_id - VPORT ID
1619 * @param vport_rl - rate limit in Mb/sec units
1620 *
1621 * @return 0 on success, -1 on error.
1622 */
1623
1624int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
1625 struct qed_ptt *p_ptt,
1626 u8 vport_id,
1627 u32 vport_rl);
1628/**
1629 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
1630 *
1631 * @param p_hwfn
1632 * @param p_ptt - ptt window used for writing the registers
1633 * @param is_release_cmd - true for release, false for stop.
1634 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
1635 * @param start_pq - first PQ ID to stop
1636 * @param num_pqs - Number of PQs to stop, starting from start_pq.
1637 *
1638 * @return bool, true if successful, false if timeout occurred while waiting
1639 * for QM command done.
1640 */
1641
1642bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
1643 struct qed_ptt *p_ptt,
1644 bool is_release_cmd,
1645 bool is_tx_pq,
1646 u16 start_pq,
1647 u16 num_pqs);
1648
1649/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
1650#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
1651#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
1652/* Tstorm port statistics */
1653#define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + \
1654 ((port_id) * \
1655 IRO[1].m1))
1656#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
1657/* Ustorm VF-PF Channel ready flag */
1658#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) (IRO[2].base + \
1659 ((vf_id) * \
1660 IRO[2].m1))
1661#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[2].size)
1662/* Ustorm Final flr cleanup ack */
1663#define USTORM_FLR_FINAL_ACK_OFFSET (IRO[3].base)
1664#define USTORM_FLR_FINAL_ACK_SIZE (IRO[3].size)
1665/* Ustorm Event ring consumer */
1666#define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[4].base + \
1667 ((pf_id) * \
1668 IRO[4].m1))
1669#define USTORM_EQE_CONS_SIZE (IRO[4].size)
1670/* Ustorm Completion ring consumer */
1671#define USTORM_CQ_CONS_OFFSET(global_queue_id) (IRO[5].base + \
1672 ((global_queue_id) * \
1673 IRO[5].m1))
1674#define USTORM_CQ_CONS_SIZE (IRO[5].size)
1675/* Xstorm Integration Test Data */
1676#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[6].base)
1677#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[6].size)
1678/* Ystorm Integration Test Data */
1679#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[7].base)
1680#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[7].size)
1681/* Pstorm Integration Test Data */
1682#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
1683#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
1684/* Tstorm Integration Test Data */
1685#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
1686#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
1687/* Mstorm Integration Test Data */
1688#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
1689#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
1690/* Ustorm Integration Test Data */
1691#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
1692#define USTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
1693/* Tstorm producers */
1694#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) (IRO[12].base + \
1695 ((core_rx_queue_id) * \
1696 IRO[12].m1))
1697#define TSTORM_LL2_RX_PRODS_SIZE (IRO[12].size)
1698/* Tstorm LiteL2 queue statistics */
1699#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_q_id) (IRO[13].base + \
1700 ((core_rx_q_id) * \
1701 IRO[13].m1))
1702#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[13].size)
1703/* Ustorm LiteL2 queue statistics */
1704#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_q_id) (IRO[14].base + \
1705 ((core_rx_q_id) * \
1706 IRO[14].m1))
1707#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[14].size)
1708/* Pstorm LiteL2 queue statistics */
1709#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_txst_id) (IRO[15].base + \
1710 ((core_txst_id) * \
1711 IRO[15].m1))
1712#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
1713/* Mstorm queue statistics */
1714#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[16].base + \
1715 ((stat_counter_id) * \
1716 IRO[16].m1))
1717#define MSTORM_QUEUE_STAT_SIZE (IRO[16].size)
1718/* Mstorm producers */
1719#define MSTORM_PRODS_OFFSET(queue_id) (IRO[17].base + \
1720 ((queue_id) * \
1721 IRO[17].m1))
1722#define MSTORM_PRODS_SIZE (IRO[17].size)
1723/* TPA agregation timeout in us resolution (on ASIC) */
1724#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[18].base)
1725#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[18].size)
1726/* Ustorm queue statistics */
1727#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[19].base + \
1728 ((stat_counter_id) * \
1729 IRO[19].m1))
1730#define USTORM_QUEUE_STAT_SIZE (IRO[19].size)
1731/* Ustorm queue zone */
1732#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[20].base + \
1733 ((queue_id) * \
1734 IRO[20].m1))
1735#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[20].size)
1736/* Pstorm queue statistics */
1737#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[21].base + \
1738 ((stat_counter_id) * \
1739 IRO[21].m1))
1740#define PSTORM_QUEUE_STAT_SIZE (IRO[21].size)
1741/* Tstorm last parser message */
1742#define TSTORM_ETH_PRS_INPUT_OFFSET(pf_id) (IRO[22].base + \
1743 ((pf_id) * \
1744 IRO[22].m1))
1745#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[22].size)
1746/* Ystorm queue zone */
1747#define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[23].base + \
1748 ((queue_id) * \
1749 IRO[23].m1))
1750#define YSTORM_ETH_QUEUE_ZONE_SIZE (IRO[23].size)
1751/* Ystorm cqe producer */
1752#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[24].base + \
1753 ((rss_id) * \
1754 IRO[24].m1))
1755#define YSTORM_TOE_CQ_PROD_SIZE (IRO[24].size)
1756/* Ustorm cqe producer */
1757#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[25].base + \
1758 ((rss_id) * \
1759 IRO[25].m1))
1760#define USTORM_TOE_CQ_PROD_SIZE (IRO[25].size)
1761/* Ustorm grq producer */
1762#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[26].base + \
1763 ((pf_id) * \
1764 IRO[26].m1))
1765#define USTORM_TOE_GRQ_PROD_SIZE (IRO[26].size)
1766/* Tstorm cmdq-cons of given command queue-id */
1767#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) (IRO[27].base + \
1768 ((cmdq_queue_id) * \
1769 IRO[27].m1))
1770#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[27].size)
1771/* Mstorm rq-cons of given queue-id */
1772#define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id) (IRO[28].base + \
1773 ((rq_queue_id) * \
1774 IRO[28].m1))
1775#define MSTORM_SCSI_RQ_CONS_SIZE (IRO[28].size)
1776/* Pstorm RoCE statistics */
1777#define PSTORM_ROCE_STAT_OFFSET(stat_counter_id) (IRO[29].base + \
1778 ((stat_counter_id) * \
1779 IRO[29].m1))
1780#define PSTORM_ROCE_STAT_SIZE (IRO[29].size)
1781/* Tstorm RoCE statistics */
1782#define TSTORM_ROCE_STAT_OFFSET(stat_counter_id) (IRO[30].base + \
1783 ((stat_counter_id) * \
1784 IRO[30].m1))
1785#define TSTORM_ROCE_STAT_SIZE (IRO[30].size)
1786
1787static const struct iro iro_arr[31] = {
1788 { 0x10, 0x0, 0x0, 0x0, 0x8 },
1789 { 0x4448, 0x60, 0x0, 0x0, 0x60 },
1790 { 0x498, 0x8, 0x0, 0x0, 0x4 },
1791 { 0x494, 0x0, 0x0, 0x0, 0x4 },
1792 { 0x10, 0x8, 0x0, 0x0, 0x2 },
1793 { 0x90, 0x8, 0x0, 0x0, 0x2 },
1794 { 0x4540, 0x0, 0x0, 0x0, 0xf8 },
1795 { 0x39e0, 0x0, 0x0, 0x0, 0xf8 },
1796 { 0x2598, 0x0, 0x0, 0x0, 0xf8 },
1797 { 0x4350, 0x0, 0x0, 0x0, 0xf8 },
1798 { 0x52d0, 0x0, 0x0, 0x0, 0xf8 },
1799 { 0x7a48, 0x0, 0x0, 0x0, 0xf8 },
1800 { 0x100, 0x8, 0x0, 0x0, 0x8 },
1801 { 0x5808, 0x10, 0x0, 0x0, 0x10 },
1802 { 0xb100, 0x30, 0x0, 0x0, 0x30 },
1803 { 0x95c0, 0x30, 0x0, 0x0, 0x30 },
1804 { 0x54f8, 0x40, 0x0, 0x0, 0x40 },
1805 { 0x200, 0x10, 0x0, 0x0, 0x8 },
1806 { 0x9e70, 0x0, 0x0, 0x0, 0x4 },
1807 { 0x7ca0, 0x40, 0x0, 0x0, 0x30 },
1808 { 0xd00, 0x8, 0x0, 0x0, 0x8 },
1809 { 0x2790, 0x80, 0x0, 0x0, 0x38 },
1810 { 0xa520, 0xf0, 0x0, 0x0, 0xf0 },
1811 { 0x80, 0x8, 0x0, 0x0, 0x8 },
1812 { 0xac0, 0x8, 0x0, 0x0, 0x8 },
1813 { 0x2580, 0x8, 0x0, 0x0, 0x8 },
1814 { 0x2500, 0x8, 0x0, 0x0, 0x8 },
1815 { 0x440, 0x8, 0x0, 0x0, 0x2 },
1816 { 0x1800, 0x8, 0x0, 0x0, 0x2 },
1817 { 0x27c8, 0x80, 0x0, 0x0, 0x10 },
1818 { 0x4710, 0x10, 0x0, 0x0, 0x10 },
1819};
1820
1821/* Runtime array offsets */
1822#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
1823#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
1824#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
1825#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
1826#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
1827#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
1828#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
1829#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
1830#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
1831#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
1832#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
1833#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
1834#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
1835#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
1836#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
1837#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
1838#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
1839#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 17
1840#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 18
1841#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 19
1842#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 20
1843#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 21
1844#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 22
1845#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 23
1846#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 760
1847#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
1848#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 760
1849#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
1850#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1496
1851#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
1852#define CAU_REG_PI_MEMORY_RT_OFFSET 2232
1853#define CAU_REG_PI_MEMORY_RT_SIZE 4416
1854#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6648
1855#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6649
1856#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6650
1857#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6651
1858#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6652
1859#define PRS_REG_SEARCH_TCP_RT_OFFSET 6653
1860#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6654
1861#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6655
1862#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6656
1863#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6657
1864#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6658
1865#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6659
1866#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6660
1867#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6661
1868#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6662
1869#define SRC_REG_FIRSTFREE_RT_OFFSET 6663
1870#define SRC_REG_FIRSTFREE_RT_SIZE 2
1871#define SRC_REG_LASTFREE_RT_OFFSET 6665
1872#define SRC_REG_LASTFREE_RT_SIZE 2
1873#define SRC_REG_COUNTFREE_RT_OFFSET 6667
1874#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6668
1875#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6669
1876#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6670
1877#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6671
1878#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6672
1879#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6673
1880#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6674
1881#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6675
1882#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6676
1883#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6677
1884#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6678
1885#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6679
1886#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6680
1887#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6681
1888#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6682
1889#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6683
1890#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6684
1891#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6685
1892#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6686
1893#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6687
1894#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6688
1895#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6689
1896#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6690
1897#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6691
1898#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6692
1899#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6693
1900#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6694
1901#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6695
1902#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6696
1903#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6697
1904#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6698
1905#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6699
1906#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6700
1907#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6701
1908#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
1909#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28701
1910#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28702
1911#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28703
1912#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28704
1913#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28705
1914#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28706
1915#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28707
1916#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28708
1917#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28709
1918#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28710
1919#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28711
1920#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
1921#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29127
1922#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
1923#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29639
1924#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29640
1925#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29641
1926#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29642
1927#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29643
1928#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29644
1929#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29645
1930#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29646
1931#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29647
1932#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29648
1933#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29649
1934#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29650
1935#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29651
1936#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29652
1937#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29653
1938#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29654
1939#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29655
1940#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29656
1941#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29657
1942#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29658
1943#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29659
1944#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29660
1945#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29661
1946#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29662
1947#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29663
1948#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29664
1949#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29665
1950#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29666
1951#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29667
1952#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29668
1953#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29669
1954#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29670
1955#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29671
1956#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29672
1957#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29673
1958#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29674
1959#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29675
1960#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29676
1961#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29677
1962#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29678
1963#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29679
1964#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29680
1965#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29681
1966#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29682
1967#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29683
1968#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29684
1969#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29685
1970#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29686
1971#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29687
1972#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29688
1973#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29689
1974#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29690
1975#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29691
1976#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29692
1977#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29693
1978#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29694
1979#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29695
1980#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29696
1981#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29697
1982#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29698
1983#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29699
1984#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29700
1985#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29701
1986#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29702
1987#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29703
1988#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29704
1989#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29705
1990#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29706
1991#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
1992#define QM_REG_VOQCRDLINE_RT_OFFSET 29834
1993#define QM_REG_VOQCRDLINE_RT_SIZE 20
1994#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29854
1995#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
1996#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29874
1997#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29875
1998#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29876
1999#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29877
2000#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29878
2001#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29879
2002#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29880
2003#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29881
2004#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29882
2005#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29883
2006#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29884
2007#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29885
2008#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29886
2009#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29887
2010#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29888
2011#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29889
2012#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29890
2013#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29891
2014#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29892
2015#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29893
2016#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29894
2017#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29895
2018#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29896
2019#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29897
2020#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29898
2021#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29899
2022#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29900
2023#define QM_REG_PQTX2PF_0_RT_OFFSET 29901
2024#define QM_REG_PQTX2PF_1_RT_OFFSET 29902
2025#define QM_REG_PQTX2PF_2_RT_OFFSET 29903
2026#define QM_REG_PQTX2PF_3_RT_OFFSET 29904
2027#define QM_REG_PQTX2PF_4_RT_OFFSET 29905
2028#define QM_REG_PQTX2PF_5_RT_OFFSET 29906
2029#define QM_REG_PQTX2PF_6_RT_OFFSET 29907
2030#define QM_REG_PQTX2PF_7_RT_OFFSET 29908
2031#define QM_REG_PQTX2PF_8_RT_OFFSET 29909
2032#define QM_REG_PQTX2PF_9_RT_OFFSET 29910
2033#define QM_REG_PQTX2PF_10_RT_OFFSET 29911
2034#define QM_REG_PQTX2PF_11_RT_OFFSET 29912
2035#define QM_REG_PQTX2PF_12_RT_OFFSET 29913
2036#define QM_REG_PQTX2PF_13_RT_OFFSET 29914
2037#define QM_REG_PQTX2PF_14_RT_OFFSET 29915
2038#define QM_REG_PQTX2PF_15_RT_OFFSET 29916
2039#define QM_REG_PQTX2PF_16_RT_OFFSET 29917
2040#define QM_REG_PQTX2PF_17_RT_OFFSET 29918
2041#define QM_REG_PQTX2PF_18_RT_OFFSET 29919
2042#define QM_REG_PQTX2PF_19_RT_OFFSET 29920
2043#define QM_REG_PQTX2PF_20_RT_OFFSET 29921
2044#define QM_REG_PQTX2PF_21_RT_OFFSET 29922
2045#define QM_REG_PQTX2PF_22_RT_OFFSET 29923
2046#define QM_REG_PQTX2PF_23_RT_OFFSET 29924
2047#define QM_REG_PQTX2PF_24_RT_OFFSET 29925
2048#define QM_REG_PQTX2PF_25_RT_OFFSET 29926
2049#define QM_REG_PQTX2PF_26_RT_OFFSET 29927
2050#define QM_REG_PQTX2PF_27_RT_OFFSET 29928
2051#define QM_REG_PQTX2PF_28_RT_OFFSET 29929
2052#define QM_REG_PQTX2PF_29_RT_OFFSET 29930
2053#define QM_REG_PQTX2PF_30_RT_OFFSET 29931
2054#define QM_REG_PQTX2PF_31_RT_OFFSET 29932
2055#define QM_REG_PQTX2PF_32_RT_OFFSET 29933
2056#define QM_REG_PQTX2PF_33_RT_OFFSET 29934
2057#define QM_REG_PQTX2PF_34_RT_OFFSET 29935
2058#define QM_REG_PQTX2PF_35_RT_OFFSET 29936
2059#define QM_REG_PQTX2PF_36_RT_OFFSET 29937
2060#define QM_REG_PQTX2PF_37_RT_OFFSET 29938
2061#define QM_REG_PQTX2PF_38_RT_OFFSET 29939
2062#define QM_REG_PQTX2PF_39_RT_OFFSET 29940
2063#define QM_REG_PQTX2PF_40_RT_OFFSET 29941
2064#define QM_REG_PQTX2PF_41_RT_OFFSET 29942
2065#define QM_REG_PQTX2PF_42_RT_OFFSET 29943
2066#define QM_REG_PQTX2PF_43_RT_OFFSET 29944
2067#define QM_REG_PQTX2PF_44_RT_OFFSET 29945
2068#define QM_REG_PQTX2PF_45_RT_OFFSET 29946
2069#define QM_REG_PQTX2PF_46_RT_OFFSET 29947
2070#define QM_REG_PQTX2PF_47_RT_OFFSET 29948
2071#define QM_REG_PQTX2PF_48_RT_OFFSET 29949
2072#define QM_REG_PQTX2PF_49_RT_OFFSET 29950
2073#define QM_REG_PQTX2PF_50_RT_OFFSET 29951
2074#define QM_REG_PQTX2PF_51_RT_OFFSET 29952
2075#define QM_REG_PQTX2PF_52_RT_OFFSET 29953
2076#define QM_REG_PQTX2PF_53_RT_OFFSET 29954
2077#define QM_REG_PQTX2PF_54_RT_OFFSET 29955
2078#define QM_REG_PQTX2PF_55_RT_OFFSET 29956
2079#define QM_REG_PQTX2PF_56_RT_OFFSET 29957
2080#define QM_REG_PQTX2PF_57_RT_OFFSET 29958
2081#define QM_REG_PQTX2PF_58_RT_OFFSET 29959
2082#define QM_REG_PQTX2PF_59_RT_OFFSET 29960
2083#define QM_REG_PQTX2PF_60_RT_OFFSET 29961
2084#define QM_REG_PQTX2PF_61_RT_OFFSET 29962
2085#define QM_REG_PQTX2PF_62_RT_OFFSET 29963
2086#define QM_REG_PQTX2PF_63_RT_OFFSET 29964
2087#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29965
2088#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29966
2089#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29967
2090#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29968
2091#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29969
2092#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29970
2093#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29971
2094#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29972
2095#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29973
2096#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29974
2097#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29975
2098#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29976
2099#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29977
2100#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29978
2101#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29979
2102#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29980
2103#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29981
2104#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29982
2105#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29983
2106#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29984
2107#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29985
2108#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29986
2109#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29987
2110#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29988
2111#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29989
2112#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29990
2113#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29991
2114#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29992
2115#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29993
2116#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
2117#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30249
2118#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
2119#define QM_REG_RLGLBLCRD_RT_OFFSET 30505
2120#define QM_REG_RLGLBLCRD_RT_SIZE 256
2121#define QM_REG_RLGLBLENABLE_RT_OFFSET 30761
2122#define QM_REG_RLPFPERIOD_RT_OFFSET 30762
2123#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30763
2124#define QM_REG_RLPFINCVAL_RT_OFFSET 30764
2125#define QM_REG_RLPFINCVAL_RT_SIZE 16
2126#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30780
2127#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
2128#define QM_REG_RLPFCRD_RT_OFFSET 30796
2129#define QM_REG_RLPFCRD_RT_SIZE 16
2130#define QM_REG_RLPFENABLE_RT_OFFSET 30812
2131#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30813
2132#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30814
2133#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
2134#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30830
2135#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
2136#define QM_REG_WFQPFCRD_RT_OFFSET 30846
2137#define QM_REG_WFQPFCRD_RT_SIZE 160
2138#define QM_REG_WFQPFENABLE_RT_OFFSET 31006
2139#define QM_REG_WFQVPENABLE_RT_OFFSET 31007
2140#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31008
2141#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
2142#define QM_REG_TXPQMAP_RT_OFFSET 31520
2143#define QM_REG_TXPQMAP_RT_SIZE 512
2144#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32032
2145#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
2146#define QM_REG_WFQVPUPPERBOUND_RT_OFFSET 32544
2147#define QM_REG_WFQVPUPPERBOUND_RT_SIZE 512
2148#define QM_REG_WFQVPCRD_RT_OFFSET 33056
2149#define QM_REG_WFQVPCRD_RT_SIZE 512
2150#define QM_REG_WFQVPMAP_RT_OFFSET 33568
2151#define QM_REG_WFQVPMAP_RT_SIZE 512
2152#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34080
2153#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
2154#define NIG_REG_LLH_CLS_TYPE_DUALMODE_RT_OFFSET 34240
2155#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34241
2156#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34242
2157#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34243
2158#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34244
2159#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34245
2160#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34246
2161#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34247
2162#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
2163#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34251
2164#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
2165#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34255
2166#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
2167#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34259
2168#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34260
2169#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
2170#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34292
2171#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
2172#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34308
2173#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
2174#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34324
2175#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
2176#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34340
2177#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
2178#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34356
2179#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34357
2180#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34358
2181#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34359
2182#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34360
2183#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34361
2184#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34362
2185#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34363
2186#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34364
2187#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34365
2188#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34366
2189#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34367
2190#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34368
2191#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34369
2192#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34370
2193#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34371
2194#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34372
2195#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34373
2196#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34374
2197#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34375
2198#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34376
2199#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34377
2200#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34378
2201#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34379
2202#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34380
2203#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34381
2204#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34382
2205#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34383
2206#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34384
2207#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34385
2208#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34386
2209#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34387
2210#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34388
2211#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34389
2212#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34390
2213#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34391
2214#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34392
2215#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34393
2216#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34394
2217#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34395
2218#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34396
2219#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34397
2220#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34398
2221#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34399
2222#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34400
2223#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34401
2224#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34402
2225#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34403
2226#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34404
2227#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34405
2228#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34406
2229#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34407
2230#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34408
2231#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34409
2232#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34410
2233#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34411
2234#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34412
2235#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34413
2236#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34414
2237#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34415
2238#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34416
2239#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34417
2240#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34418
2241#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34419
2242#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34420
2243#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34421
2244#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34422
2245#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34423
2246#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34424
2247#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34425
2248#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34426
2249#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34427
2250#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34428
2251#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34429
2252#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34430
2253#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34431
2254
2255#define RUNTIME_ARRAY_SIZE 34432
2256
2257/* The eth storm context for the Ystorm */
2258struct ystorm_eth_conn_st_ctx {
2259 __le32 reserved[4];
2260};
2261
2262/* The eth storm context for the Pstorm */
2263struct pstorm_eth_conn_st_ctx {
2264 __le32 reserved[8];
2265};
2266
2267/* The eth storm context for the Xstorm */
2268struct xstorm_eth_conn_st_ctx {
2269 __le32 reserved[60];
2270};
2271
2272struct xstorm_eth_conn_ag_ctx {
2273 u8 reserved0 /* cdu_validation */;
2274 u8 eth_state /* state */;
2275 u8 flags0;
2276#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
2277#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2278#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
2279#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
2280#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
2281#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
2282#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
2283#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
2284#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
2285#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
2286#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
2287#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
2288#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
2289#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
2290#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
2291#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
2292 u8 flags1;
2293#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
2294#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
2295#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
2296#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
2297#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
2298#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
2299#define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
2300#define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
2301#define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
2302#define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
2303#define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
2304#define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
2305#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
2306#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
2307#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
2308#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
2309 u8 flags2;
2310#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2311#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
2312#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2313#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
2314#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2315#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
2316#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
2317#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
2318 u8 flags3;
2319#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2320#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
2321#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2322#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
2323#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2324#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
2325#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
2326#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
2327 u8 flags4;
2328#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2329#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
2330#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2331#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
2332#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2333#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
2334#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
2335#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
2336 u8 flags5;
2337#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
2338#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
2339#define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
2340#define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
2341#define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
2342#define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
2343#define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
2344#define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
2345 u8 flags6;
2346#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */
2347#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
2348#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
2349#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
2350#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
2351#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
2352#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
2353#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
2354 u8 flags7;
2355#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
2356#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
2357#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
2358#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
2359#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2360#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2361#define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2362#define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
2363#define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2364#define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
2365 u8 flags8;
2366#define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2367#define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
2368#define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2369#define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
2370#define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2371#define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
2372#define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2373#define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
2374#define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2375#define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
2376#define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
2377#define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
2378#define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2379#define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
2380#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2381#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
2382 u8 flags9;
2383#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2384#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
2385#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
2386#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
2387#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
2388#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
2389#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
2390#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
2391#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
2392#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
2393#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
2394#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
2395#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */
2396#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2397#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2398#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2399 u8 flags10;
2400#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
2401#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2402#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
2403#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2404#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
2405#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2406#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
2407#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
2408#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
2409#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2410#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */
2411#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2412#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
2413#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
2414#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
2415#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
2416 u8 flags11;
2417#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
2418#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
2419#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
2420#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
2421#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
2422#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2423#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2424#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
2425#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2426#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
2427#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2428#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
2429#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
2430#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2431#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
2432#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
2433 u8 flags12;
2434#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
2435#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
2436#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
2437#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
2438#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
2439#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2440#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
2441#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2442#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
2443#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
2444#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
2445#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
2446#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
2447#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
2448#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
2449#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
2450 u8 flags13;
2451#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
2452#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
2453#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
2454#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
2455#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
2456#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2457#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
2458#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2459#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
2460#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2461#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
2462#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2463#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
2464#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2465#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
2466#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2467 u8 flags14;
2468#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */
2469#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2470#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */
2471#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2472#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */
2473#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2474#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */
2475#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2476#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */
2477#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2478#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
2479#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2480#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */
2481#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2482 u8 edpm_event_id /* byte2 */;
2483 __le16 physical_q0 /* physical_q0 */;
2484 __le16 word1 /* physical_q1 */;
2485 __le16 edpm_num_bds /* physical_q2 */;
2486 __le16 tx_bd_cons /* word3 */;
2487 __le16 tx_bd_prod /* word4 */;
2488 __le16 go_to_bd_cons /* word5 */;
2489 __le16 conn_dpi /* conn_dpi */;
2490 u8 byte3 /* byte3 */;
2491 u8 byte4 /* byte4 */;
2492 u8 byte5 /* byte5 */;
2493 u8 byte6 /* byte6 */;
2494 __le32 reg0 /* reg0 */;
2495 __le32 reg1 /* reg1 */;
2496 __le32 reg2 /* reg2 */;
2497 __le32 reg3 /* reg3 */;
2498 __le32 reg4 /* reg4 */;
2499 __le32 reg5 /* cf_array0 */;
2500 __le32 reg6 /* cf_array1 */;
2501 __le16 word7 /* word7 */;
2502 __le16 word8 /* word8 */;
2503 __le16 word9 /* word9 */;
2504 __le16 word10 /* word10 */;
2505 __le32 reg7 /* reg7 */;
2506 __le32 reg8 /* reg8 */;
2507 __le32 reg9 /* reg9 */;
2508 u8 byte7 /* byte7 */;
2509 u8 byte8 /* byte8 */;
2510 u8 byte9 /* byte9 */;
2511 u8 byte10 /* byte10 */;
2512 u8 byte11 /* byte11 */;
2513 u8 byte12 /* byte12 */;
2514 u8 byte13 /* byte13 */;
2515 u8 byte14 /* byte14 */;
2516 u8 byte15 /* byte15 */;
2517 u8 byte16 /* byte16 */;
2518 __le16 word11 /* word11 */;
2519 __le32 reg10 /* reg10 */;
2520 __le32 reg11 /* reg11 */;
2521 __le32 reg12 /* reg12 */;
2522 __le32 reg13 /* reg13 */;
2523 __le32 reg14 /* reg14 */;
2524 __le32 reg15 /* reg15 */;
2525 __le32 reg16 /* reg16 */;
2526 __le32 reg17 /* reg17 */;
2527 __le32 reg18 /* reg18 */;
2528 __le32 reg19 /* reg19 */;
2529 __le16 word12 /* word12 */;
2530 __le16 word13 /* word13 */;
2531 __le16 word14 /* word14 */;
2532 __le16 word15 /* word15 */;
2533};
2534
2535/* The eth storm context for the Tstorm */
2536struct tstorm_eth_conn_st_ctx {
2537 __le32 reserved[4];
2538};
2539
2540/* The eth storm context for the Mstorm */
2541struct mstorm_eth_conn_st_ctx {
2542 __le32 reserved[8];
2543};
2544
2545/* The eth storm context for the Ustorm */
2546struct ustorm_eth_conn_st_ctx {
2547 __le32 reserved[40];
2548};
2549
2550/* eth connection context */
2551struct eth_conn_context {
2552 struct ystorm_eth_conn_st_ctx ystorm_st_context;
2553 struct regpair ystorm_st_padding[2] /* padding */;
2554 struct pstorm_eth_conn_st_ctx pstorm_st_context;
2555 struct regpair pstorm_st_padding[2] /* padding */;
2556 struct xstorm_eth_conn_st_ctx xstorm_st_context;
2557 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
2558 struct tstorm_eth_conn_st_ctx tstorm_st_context;
2559 struct regpair tstorm_st_padding[2] /* padding */;
2560 struct mstorm_eth_conn_st_ctx mstorm_st_context;
2561 struct ustorm_eth_conn_st_ctx ustorm_st_context;
2562};
2563
Manish Chopracee4d262015-10-26 11:02:28 +0200[diff] [blame^]2564enum eth_filter_action {
2565 ETH_FILTER_ACTION_REMOVE,
2566 ETH_FILTER_ACTION_ADD,
2567 ETH_FILTER_ACTION_REPLACE,
2568 MAX_ETH_FILTER_ACTION
2569};
2570
2571struct eth_filter_cmd {
2572 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
2573 u8 vport_id /* the vport id */;
2574 u8 action /* filter command action: add/remove/replace */;
2575 u8 reserved0;
2576 __le32 vni;
2577 __le16 mac_lsb;
2578 __le16 mac_mid;
2579 __le16 mac_msb;
2580 __le16 vlan_id;
2581};
2582
2583struct eth_filter_cmd_header {
2584 u8 rx;
2585 u8 tx;
2586 u8 cmd_cnt;
2587 u8 assert_on_error;
2588 u8 reserved1[4];
2589};
2590
2591enum eth_filter_type {
2592 ETH_FILTER_TYPE_MAC,
2593 ETH_FILTER_TYPE_VLAN,
2594 ETH_FILTER_TYPE_PAIR,
2595 ETH_FILTER_TYPE_INNER_MAC,
2596 ETH_FILTER_TYPE_INNER_VLAN,
2597 ETH_FILTER_TYPE_INNER_PAIR,
2598 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
2599 ETH_FILTER_TYPE_MAC_VNI_PAIR,
2600 ETH_FILTER_TYPE_VNI,
2601 MAX_ETH_FILTER_TYPE
2602};
2603
2604enum eth_ramrod_cmd_id {
2605 ETH_RAMROD_UNUSED,
2606 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
2607 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
2608 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
2609 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
2610 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
2611 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
2612 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
2613 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
2614 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
2615 ETH_RAMROD_RESERVED,
2616 ETH_RAMROD_RESERVED2,
2617 ETH_RAMROD_RESERVED3,
2618 ETH_RAMROD_RESERVED4,
2619 ETH_RAMROD_RESERVED5,
2620 ETH_RAMROD_RESERVED6,
2621 ETH_RAMROD_RESERVED7,
2622 ETH_RAMROD_RESERVED8,
2623 MAX_ETH_RAMROD_CMD_ID
2624};
2625
2626struct eth_vport_rss_config {
2627 __le16 capabilities;
2628#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
2629#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
2630#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
2631#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
2632#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
2633#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
2634#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
2635#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
2636#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
2637#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
2638#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
2639#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
2640#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
2641#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
2642#define ETH_VPORT_RSS_CONFIG_CALC_4TUP_TCP_FRAG_MASK 0x1
2643#define ETH_VPORT_RSS_CONFIG_CALC_4TUP_TCP_FRAG_SHIFT 7
2644#define ETH_VPORT_RSS_CONFIG_CALC_4TUP_UDP_FRAG_MASK 0x1
2645#define ETH_VPORT_RSS_CONFIG_CALC_4TUP_UDP_FRAG_SHIFT 8
2646#define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x7F
2647#define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 9
2648 u8 rss_id;
2649 u8 rss_mode;
2650 u8 update_rss_key;
2651 u8 update_rss_ind_table;
2652 u8 update_rss_capabilities;
2653 u8 tbl_size;
2654 __le32 reserved2[2];
2655 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
2656 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
2657 __le32 reserved3[2];
2658};
2659
2660enum eth_vport_rss_mode {
2661 ETH_VPORT_RSS_MODE_DISABLED,
2662 ETH_VPORT_RSS_MODE_REGULAR,
2663 MAX_ETH_VPORT_RSS_MODE
2664};
2665
2666struct eth_vport_rx_mode {
2667 __le16 state;
2668#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
2669#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
2670#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2671#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2672#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
2673#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
2674#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
2675#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
2676#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2677#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
2678#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2679#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
2680#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
2681#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
2682 __le16 reserved2[3];
2683};
2684
2685struct eth_vport_tpa_param {
2686 u64 reserved[2];
2687};
2688
2689struct eth_vport_tx_mode {
2690 __le16 state;
2691#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
2692#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
2693#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2694#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2695#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
2696#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
2697#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2698#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
2699#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2700#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
2701#define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
2702#define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
2703 __le16 reserved2[3];
2704};
2705
2706struct rx_queue_start_ramrod_data {
2707 __le16 rx_queue_id;
2708 __le16 num_of_pbl_pages;
2709 __le16 bd_max_bytes;
2710 __le16 sb_id;
2711 u8 sb_index;
2712 u8 vport_id;
2713 u8 default_rss_queue_flg;
2714 u8 complete_cqe_flg;
2715 u8 complete_event_flg;
2716 u8 stats_counter_id;
2717 u8 pin_context;
2718 u8 pxp_tph_valid_bd;
2719 u8 pxp_tph_valid_pkt;
2720 u8 pxp_st_hint;
2721 __le16 pxp_st_index;
2722 u8 reserved[4];
2723 struct regpair cqe_pbl_addr;
2724 struct regpair bd_base;
2725 struct regpair sge_base;
2726};
2727
2728struct rx_queue_stop_ramrod_data {
2729 __le16 rx_queue_id;
2730 u8 complete_cqe_flg;
2731 u8 complete_event_flg;
2732 u8 vport_id;
2733 u8 reserved[3];
2734};
2735
2736struct rx_queue_update_ramrod_data {
2737 __le16 rx_queue_id;
2738 u8 complete_cqe_flg;
2739 u8 complete_event_flg;
2740 u8 init_sge_ring_flg;
2741 u8 vport_id;
2742 u8 pxp_tph_valid_sge;
2743 u8 pxp_st_hint;
2744 __le16 pxp_st_index;
2745 u8 reserved[6];
2746 struct regpair sge_base;
2747};
2748
2749struct tx_queue_start_ramrod_data {
2750 __le16 sb_id;
2751 u8 sb_index;
2752 u8 vport_id;
2753 u8 tc;
2754 u8 stats_counter_id;
2755 __le16 qm_pq_id;
2756 u8 flags;
2757#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
2758#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
2759#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
2760#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
2761#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
2762#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
2763#define TX_QUEUE_START_RAMROD_DATA_RESERVED0_MASK 0x1F
2764#define TX_QUEUE_START_RAMROD_DATA_RESERVED0_SHIFT 3
2765 u8 pin_context;
2766 u8 pxp_tph_valid_bd;
2767 u8 pxp_tph_valid_pkt;
2768 __le16 pxp_st_index;
2769 u8 pxp_st_hint;
2770 u8 reserved1[3];
2771 __le16 queue_zone_id;
2772 __le16 test_dup_count;
2773 __le16 pbl_size;
2774 struct regpair pbl_base_addr;
2775};
2776
2777struct tx_queue_stop_ramrod_data {
2778 __le16 reserved[4];
2779};
2780
2781struct vport_filter_update_ramrod_data {
2782 struct eth_filter_cmd_header filter_cmd_hdr;
2783 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
2784};
2785
2786struct vport_start_ramrod_data {
2787 u8 vport_id;
2788 u8 sw_fid;
2789 __le16 mtu;
2790 u8 drop_ttl0_en;
2791 u8 inner_vlan_removal_en;
2792 struct eth_vport_rx_mode rx_mode;
2793 struct eth_vport_tx_mode tx_mode;
2794 struct eth_vport_tpa_param tpa_param;
2795 __le16 sge_buff_size;
2796 u8 max_sges_num;
2797 u8 tx_switching_en;
2798 u8 anti_spoofing_en;
2799 u8 default_vlan_en;
2800 u8 handle_ptp_pkts;
2801 u8 silent_vlan_removal_en;
2802 __le16 default_vlan;
2803 u8 untagged;
2804 u8 reserved[7];
2805};
2806
2807struct vport_stop_ramrod_data {
2808 u8 vport_id;
2809 u8 reserved[7];
2810};
2811
2812struct vport_update_ramrod_data_cmn {
2813 u8 vport_id;
2814 u8 update_rx_active_flg;
2815 u8 rx_active_flg;
2816 u8 update_tx_active_flg;
2817 u8 tx_active_flg;
2818 u8 update_rx_mode_flg;
2819 u8 update_tx_mode_flg;
2820 u8 update_approx_mcast_flg;
2821 u8 update_rss_flg;
2822 u8 update_inner_vlan_removal_en_flg;
2823 u8 inner_vlan_removal_en;
2824 u8 update_tpa_param_flg;
2825 u8 update_tpa_en_flg;
2826 u8 update_sge_param_flg;
2827 __le16 sge_buff_size;
2828 u8 max_sges_num;
2829 u8 update_tx_switching_en_flg;
2830 u8 tx_switching_en;
2831 u8 update_anti_spoofing_en_flg;
2832 u8 anti_spoofing_en;
2833 u8 update_handle_ptp_pkts;
2834 u8 handle_ptp_pkts;
2835 u8 update_default_vlan_en_flg;
2836 u8 default_vlan_en;
2837 u8 update_default_vlan_flg;
2838 __le16 default_vlan;
2839 u8 update_accept_any_vlan_flg;
2840 u8 accept_any_vlan;
2841 u8 silent_vlan_removal_en;
2842 u8 reserved;
2843};
2844
2845struct vport_update_ramrod_mcast {
2846 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
2847};
2848
2849struct vport_update_ramrod_data {
2850 struct vport_update_ramrod_data_cmn common;
2851 struct eth_vport_rx_mode rx_mode;
2852 struct eth_vport_tx_mode tx_mode;
2853 struct eth_vport_tpa_param tpa_param;
2854 struct vport_update_ramrod_mcast approx_mcast;
2855 struct eth_vport_rss_config rss_config;
2856};
2857
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200[diff] [blame]2858struct mstorm_eth_conn_ag_ctx {
2859 u8 byte0 /* cdu_validation */;
2860 u8 byte1 /* state */;
2861 u8 flags0;
2862#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
2863#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2864#define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2865#define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2866#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2867#define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
2868#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2869#define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
2870#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2871#define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
2872 u8 flags1;
2873#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2874#define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
2875#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2876#define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
2877#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2878#define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2879#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2880#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
2881#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2882#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
2883#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2884#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
2885#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2886#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
2887#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2888#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
2889 __le16 word0 /* word0 */;
2890 __le16 word1 /* word1 */;
2891 __le32 reg0 /* reg0 */;
2892 __le32 reg1 /* reg1 */;
2893};
2894
2895struct tstorm_eth_conn_ag_ctx {
2896 u8 byte0 /* cdu_validation */;
2897 u8 byte1 /* state */;
2898 u8 flags0;
2899#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2900#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2901#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2902#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2903#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
2904#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
2905#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
2906#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
2907#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
2908#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
2909#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
2910#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
2911#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2912#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
2913 u8 flags1;
2914#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2915#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
2916#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2917#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
2918#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2919#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
2920#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2921#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
2922 u8 flags2;
2923#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2924#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
2925#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2926#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
2927#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
2928#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
2929#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2930#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
2931 u8 flags3;
2932#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2933#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
2934#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2935#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
2936#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2937#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
2938#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2939#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
2940#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2941#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
2942#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2943#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
2944 u8 flags4;
2945#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2946#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
2947#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2948#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
2949#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2950#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
2951#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
2952#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
2953#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2954#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
2955#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2956#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
2957#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2958#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
2959#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2960#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
2961 u8 flags5;
2962#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2963#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2964#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2965#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2966#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2967#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2968#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2969#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2970#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2971#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2972#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */
2973#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
2974#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2975#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2976#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2977#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
2978 __le32 reg0 /* reg0 */;
2979 __le32 reg1 /* reg1 */;
2980 __le32 reg2 /* reg2 */;
2981 __le32 reg3 /* reg3 */;
2982 __le32 reg4 /* reg4 */;
2983 __le32 reg5 /* reg5 */;
2984 __le32 reg6 /* reg6 */;
2985 __le32 reg7 /* reg7 */;
2986 __le32 reg8 /* reg8 */;
2987 u8 byte2 /* byte2 */;
2988 u8 byte3 /* byte3 */;
2989 __le16 rx_bd_cons /* word0 */;
2990 u8 byte4 /* byte4 */;
2991 u8 byte5 /* byte5 */;
2992 __le16 rx_bd_prod /* word1 */;
2993 __le16 word2 /* conn_dpi */;
2994 __le16 word3 /* word3 */;
2995 __le32 reg9 /* reg9 */;
2996 __le32 reg10 /* reg10 */;
2997};
2998
2999struct ustorm_eth_conn_ag_ctx {
3000 u8 byte0 /* cdu_validation */;
3001 u8 byte1 /* state */;
3002 u8 flags0;
3003#define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3004#define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3005#define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3006#define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
3007#define USTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
3008#define USTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
3009#define USTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
3010#define USTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
3011#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
3012#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
3013 u8 flags1;
3014#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3015#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
3016#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */
3017#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
3018#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */
3019#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
3020#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */
3021#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
3022 u8 flags2;
3023#define USTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
3024#define USTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
3025#define USTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
3026#define USTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
3027#define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
3028#define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
3029#define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
3030#define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
3031#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */
3032#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
3033#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */
3034#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
3035#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */
3036#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
3037#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
3038#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
3039 u8 flags3;
3040#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
3041#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
3042#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
3043#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
3044#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
3045#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
3046#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
3047#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
3048#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
3049#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
3050#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
3051#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
3052#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
3053#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
3054#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
3055#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
3056 u8 byte2 /* byte2 */;
3057 u8 byte3 /* byte3 */;
3058 __le16 word0 /* conn_dpi */;
3059 __le16 tx_bd_cons /* word1 */;
3060 __le32 reg0 /* reg0 */;
3061 __le32 reg1 /* reg1 */;
3062 __le32 reg2 /* reg2 */;
3063 __le32 reg3 /* reg3 */;
3064 __le16 tx_drv_bd_cons /* word2 */;
3065 __le16 rx_drv_cqe_cons /* word3 */;
3066};
3067
3068struct xstorm_eth_hw_conn_ag_ctx {
3069 u8 reserved0 /* cdu_validation */;
3070 u8 eth_state /* state */;
3071 u8 flags0;
3072#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
3073#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
3074#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
3075#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
3076#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
3077#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
3078#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
3079#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
3080#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
3081#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
3082#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
3083#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
3084#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
3085#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
3086#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
3087#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
3088 u8 flags1;
3089#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
3090#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
3091#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
3092#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
3093#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
3094#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
3095#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
3096#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
3097#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
3098#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
3099#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
3100#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
3101#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
3102#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
3103#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
3104#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
3105 u8 flags2;
3106#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
3107#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
3108#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
3109#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
3110#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
3111#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
3112#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
3113#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
3114 u8 flags3;
3115#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
3116#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
3117#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
3118#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
3119#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
3120#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
3121#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
3122#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
3123 u8 flags4;
3124#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
3125#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
3126#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
3127#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
3128#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
3129#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
3130#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
3131#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
3132 u8 flags5;
3133#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
3134#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
3135#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
3136#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
3137#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
3138#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
3139#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
3140#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
3141 u8 flags6;
3142#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
3143#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
3144#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
3145#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
3146#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
3147#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
3148#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
3149#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
3150 u8 flags7;
3151#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
3152#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
3153#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
3154#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
3155#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
3156#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
3157#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
3158#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
3159#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
3160#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
3161 u8 flags8;
3162#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
3163#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
3164#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
3165#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
3166#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
3167#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
3168#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
3169#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
3170#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
3171#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
3172#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
3173#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
3174#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
3175#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
3176#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
3177#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
3178 u8 flags9;
3179#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
3180#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
3181#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
3182#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
3183#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
3184#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
3185#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
3186#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
3187#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
3188#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
3189#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
3190#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
3191#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
3192#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
3193#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
3194#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
3195 u8 flags10;
3196#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
3197#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
3198#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
3199#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
3200#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
3201#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
3202#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
3203#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
3204#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
3205#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
3206#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
3207#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
3208#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
3209#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
3210#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
3211#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
3212 u8 flags11;
3213#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
3214#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
3215#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
3216#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
3217#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
3218#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
3219#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
3220#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
3221#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
3222#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
3223#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
3224#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
3225#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
3226#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
3227#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
3228#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
3229 u8 flags12;
3230#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
3231#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
3232#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
3233#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
3234#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
3235#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
3236#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
3237#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
3238#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
3239#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
3240#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
3241#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
3242#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
3243#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
3244#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
3245#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
3246 u8 flags13;
3247#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
3248#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
3249#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
3250#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
3251#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
3252#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
3253#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
3254#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
3255#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
3256#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
3257#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
3258#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
3259#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
3260#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
3261#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
3262#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
3263 u8 flags14;
3264#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
3265#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
3266#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
3267#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
3268#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
3269#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
3270#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
3271#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
3272#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
3273#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
3274#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
3275#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
3276#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
3277#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
3278 u8 edpm_event_id /* byte2 */;
3279 __le16 physical_q0 /* physical_q0 */;
3280 __le16 word1 /* physical_q1 */;
3281 __le16 edpm_num_bds /* physical_q2 */;
3282 __le16 tx_bd_cons /* word3 */;
3283 __le16 tx_bd_prod /* word4 */;
3284 __le16 go_to_bd_cons /* word5 */;
3285 __le16 conn_dpi /* conn_dpi */;
3286};
3287
3288#define VF_MAX_STATIC 192 /* In case of K2 */
3289
3290#define MCP_GLOB_PATH_MAX 2
3291#define MCP_PORT_MAX 2 /* Global */
3292#define MCP_GLOB_PORT_MAX 4 /* Global */
3293#define MCP_GLOB_FUNC_MAX 16 /* Global */
3294
3295typedef u32 offsize_t; /* In DWORDS !!! */
3296/* Offset from the beginning of the MCP scratchpad */
3297#define OFFSIZE_OFFSET_SHIFT 0
3298#define OFFSIZE_OFFSET_MASK 0x0000ffff
3299/* Size of specific element (not the whole array if any) */
3300#define OFFSIZE_SIZE_SHIFT 16
3301#define OFFSIZE_SIZE_MASK 0xffff0000
3302
3303/* SECTION_OFFSET is calculating the offset in bytes out of offsize */
3304#define SECTION_OFFSET(_offsize) ((((_offsize & \
3305 OFFSIZE_OFFSET_MASK) >> \
3306 OFFSIZE_OFFSET_SHIFT) << 2))
3307
3308/* QED_SECTION_SIZE is calculating the size in bytes out of offsize */
3309#define QED_SECTION_SIZE(_offsize) (((_offsize & \
3310 OFFSIZE_SIZE_MASK) >> \
3311 OFFSIZE_SIZE_SHIFT) << 2)
3312
3313/* SECTION_ADDR returns the GRC addr of a section, given offsize and index
3314 * within section.
3315 */
3316#define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
3317 SECTION_OFFSET(_offsize) + \
3318 (QED_SECTION_SIZE(_offsize) * idx))
3319
3320/* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address.
3321 * Use offsetof, since the OFFSETUP collide with the firmware definition
3322 */
3323#define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + \
3324 offsetof(struct \
3325 mcp_public_data, \
3326 sections[_section]))
3327/* PHY configuration */
3328struct pmm_phy_cfg {
3329 u32 speed;
3330#define PMM_SPEED_AUTONEG 0
3331
3332 u32 pause; /* bitmask */
3333#define PMM_PAUSE_NONE 0x0
3334#define PMM_PAUSE_AUTONEG 0x1
3335#define PMM_PAUSE_RX 0x2
3336#define PMM_PAUSE_TX 0x4
3337
3338 u32 adv_speed; /* Default should be the speed_cap_mask */
3339 u32 loopback_mode;
3340#define PMM_LOOPBACK_NONE 0
3341#define PMM_LOOPBACK_INT_PHY 1
3342#define PMM_LOOPBACK_EXT_PHY 2
3343#define PMM_LOOPBACK_EXT 3
3344#define PMM_LOOPBACK_MAC 4
3345
3346 /* features */
3347 u32 feature_config_flags;
3348};
3349
3350struct port_mf_cfg {
3351 u32 dynamic_cfg; /* device control channel */
3352#define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
3353#define PORT_MF_CFG_OV_TAG_SHIFT 0
3354#define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
3355
3356 u32 reserved[1];
3357};
3358
3359/* DO NOT add new fields in the middle
3360 * MUST be synced with struct pmm_stats_map
3361 */
3362struct pmm_stats {
3363 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
3364 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
3365 u64 r255;
3366 u64 r511;
3367 u64 r1023;
3368 u64 r1518;
3369 u64 r1522;
3370 u64 r2047;
3371 u64 r4095;
3372 u64 r9216;
3373 u64 r16383;
3374 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
3375 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
3376 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
3377 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
3378 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
3379 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
3380 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
3381 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
3382 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
3383 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
3384 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
3385 u64 t127;
3386 u64 t255;
3387 u64 t511;
3388 u64 t1023;
3389 u64 t1518;
3390 u64 t2047;
3391 u64 t4095;
3392 u64 t9216;
3393 u64 t16383;
3394 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
3395 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
3396 u64 tlpiec;
3397 u64 tncl;
3398 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
3399 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
3400 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
3401 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
3402 u64 rxpok;
3403 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
3404 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
3405 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
3406 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
3407 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
3408};
3409
3410struct brb_stats {
3411 u64 brb_truncate[8];
3412 u64 brb_discard[8];
3413};
3414
3415struct port_stats {
3416 struct brb_stats brb;
3417 struct pmm_stats pmm;
3418};
3419
3420#define CMT_TEAM0 0
3421#define CMT_TEAM1 1
3422#define CMT_TEAM_MAX 2
3423
3424struct couple_mode_teaming {
3425 u8 port_cmt[MCP_GLOB_PORT_MAX];
3426#define PORT_CMT_IN_TEAM BIT(0)
3427
3428#define PORT_CMT_PORT_ROLE BIT(1)
3429#define PORT_CMT_PORT_INACTIVE (0 << 1)
3430#define PORT_CMT_PORT_ACTIVE BIT(1)
3431
3432#define PORT_CMT_TEAM_MASK BIT(2)
3433#define PORT_CMT_TEAM0 (0 << 2)
3434#define PORT_CMT_TEAM1 BIT(2)
3435};
3436
3437/**************************************
3438* LLDP and DCBX HSI structures
3439**************************************/
3440#define LLDP_CHASSIS_ID_STAT_LEN 4
3441#define LLDP_PORT_ID_STAT_LEN 4
3442#define DCBX_MAX_APP_PROTOCOL 32
3443#define MAX_SYSTEM_LLDP_TLV_DATA 32
3444
3445enum lldp_agent_e {
3446 LLDP_NEAREST_BRIDGE = 0,
3447 LLDP_NEAREST_NON_TPMR_BRIDGE,
3448 LLDP_NEAREST_CUSTOMER_BRIDGE,
3449 LLDP_MAX_LLDP_AGENTS
3450};
3451
3452struct lldp_config_params_s {
3453 u32 config;
3454#define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
3455#define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
3456#define LLDP_CONFIG_HOLD_MASK 0x00000f00
3457#define LLDP_CONFIG_HOLD_SHIFT 8
3458#define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
3459#define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
3460#define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
3461#define LLDP_CONFIG_ENABLE_RX_SHIFT 30
3462#define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
3463#define LLDP_CONFIG_ENABLE_TX_SHIFT 31
3464 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3465 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
3466};
3467
3468struct lldp_status_params_s {
3469 u32 prefix_seq_num;
3470 u32 status; /* TBD */
3471
3472 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
3473 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3474
3475 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
3476 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
3477 u32 suffix_seq_num;
3478};
3479
3480struct dcbx_ets_feature {
3481 u32 flags;
3482#define DCBX_ETS_ENABLED_MASK 0x00000001
3483#define DCBX_ETS_ENABLED_SHIFT 0
3484#define DCBX_ETS_WILLING_MASK 0x00000002
3485#define DCBX_ETS_WILLING_SHIFT 1
3486#define DCBX_ETS_ERROR_MASK 0x00000004
3487#define DCBX_ETS_ERROR_SHIFT 2
3488#define DCBX_ETS_CBS_MASK 0x00000008
3489#define DCBX_ETS_CBS_SHIFT 3
3490#define DCBX_ETS_MAX_TCS_MASK 0x000000f0
3491#define DCBX_ETS_MAX_TCS_SHIFT 4
3492 u32 pri_tc_tbl[1];
3493#define DCBX_ISCSI_OOO_TC 4
3494#define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
3495 u32 tc_bw_tbl[2];
3496 u32 tc_tsa_tbl[2];
3497#define DCBX_ETS_TSA_STRICT 0
3498#define DCBX_ETS_TSA_CBS 1
3499#define DCBX_ETS_TSA_ETS 2
3500};
3501
3502struct dcbx_app_priority_entry {
3503 u32 entry;
3504#define DCBX_APP_PRI_MAP_MASK 0x000000ff
3505#define DCBX_APP_PRI_MAP_SHIFT 0
3506#define DCBX_APP_PRI_0 0x01
3507#define DCBX_APP_PRI_1 0x02
3508#define DCBX_APP_PRI_2 0x04
3509#define DCBX_APP_PRI_3 0x08
3510#define DCBX_APP_PRI_4 0x10
3511#define DCBX_APP_PRI_5 0x20
3512#define DCBX_APP_PRI_6 0x40
3513#define DCBX_APP_PRI_7 0x80
3514#define DCBX_APP_SF_MASK 0x00000300
3515#define DCBX_APP_SF_SHIFT 8
3516#define DCBX_APP_SF_ETHTYPE 0
3517#define DCBX_APP_SF_PORT 1
3518#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
3519#define DCBX_APP_PROTOCOL_ID_SHIFT 16
3520};
3521
3522/* FW structure in BE */
3523struct dcbx_app_priority_feature {
3524 u32 flags;
3525#define DCBX_APP_ENABLED_MASK 0x00000001
3526#define DCBX_APP_ENABLED_SHIFT 0
3527#define DCBX_APP_WILLING_MASK 0x00000002
3528#define DCBX_APP_WILLING_SHIFT 1
3529#define DCBX_APP_ERROR_MASK 0x00000004
3530#define DCBX_APP_ERROR_SHIFT 2
3531/* Not in use
3532 * #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
3533 * #define DCBX_APP_DEFAULT_PRI_SHIFT 8
3534 */
3535#define DCBX_APP_MAX_TCS_MASK 0x0000f000
3536#define DCBX_APP_MAX_TCS_SHIFT 12
3537#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
3538#define DCBX_APP_NUM_ENTRIES_SHIFT 16
3539 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
3540};
3541
3542/* FW structure in BE */
3543struct dcbx_features {
3544 /* PG feature */
3545 struct dcbx_ets_feature ets;
3546
3547 /* PFC feature */
3548 u32 pfc;
3549#define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
3550#define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
3551#define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
3552#define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
3553#define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
3554#define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
3555#define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
3556#define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
3557#define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
3558#define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
3559
3560#define DCBX_PFC_FLAGS_MASK 0x0000ff00
3561#define DCBX_PFC_FLAGS_SHIFT 8
3562#define DCBX_PFC_CAPS_MASK 0x00000f00
3563#define DCBX_PFC_CAPS_SHIFT 8
3564#define DCBX_PFC_MBC_MASK 0x00004000
3565#define DCBX_PFC_MBC_SHIFT 14
3566#define DCBX_PFC_WILLING_MASK 0x00008000
3567#define DCBX_PFC_WILLING_SHIFT 15
3568#define DCBX_PFC_ENABLED_MASK 0x00010000
3569#define DCBX_PFC_ENABLED_SHIFT 16
3570#define DCBX_PFC_ERROR_MASK 0x00020000
3571#define DCBX_PFC_ERROR_SHIFT 17
3572
3573 /* APP feature */
3574 struct dcbx_app_priority_feature app;
3575};
3576
3577struct dcbx_local_params {
3578 u32 config;
3579#define DCBX_CONFIG_VERSION_MASK 0x00000003
3580#define DCBX_CONFIG_VERSION_SHIFT 0
3581#define DCBX_CONFIG_VERSION_DISABLED 0
3582#define DCBX_CONFIG_VERSION_IEEE 1
3583#define DCBX_CONFIG_VERSION_CEE 2
3584
3585 u32 flags;
3586 struct dcbx_features features;
3587};
3588
3589struct dcbx_mib {
3590 u32 prefix_seq_num;
3591 u32 flags;
3592 struct dcbx_features features;
3593 u32 suffix_seq_num;
3594};
3595
3596struct lldp_system_tlvs_buffer_s {
3597 u16 valid;
3598 u16 length;
3599 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
3600};
3601
3602/**************************************/
3603/* */
3604/* P U B L I C G L O B A L */
3605/* */
3606/**************************************/
3607struct public_global {
3608 u32 max_path;
3609#define MAX_PATH_BIG_BEAR 2
3610#define MAX_PATH_K2 1
3611 u32 max_ports;
3612#define MODE_1P 1
3613#define MODE_2P 2
3614#define MODE_3P 3
3615#define MODE_4P 4
3616 u32 debug_mb_offset;
3617 u32 phymod_dbg_mb_offset;
3618 struct couple_mode_teaming cmt;
3619 s32 internal_temperature;
3620 u32 mfw_ver;
3621 u32 running_bundle_id;
3622};
3623
3624/**************************************/
3625/* */
3626/* P U B L I C P A T H */
3627/* */
3628/**************************************/
3629
3630/****************************************************************************
3631* Shared Memory 2 Region *
3632****************************************************************************/
3633/* The fw_flr_ack is actually built in the following way: */
3634/* 8 bit: PF ack */
3635/* 128 bit: VF ack */
3636/* 8 bit: ios_dis_ack */
3637/* In order to maintain endianity in the mailbox hsi, we want to keep using */
3638/* u32. The fw must have the VF right after the PF since this is how it */
3639/* access arrays(it expects always the VF to reside after the PF, and that */
3640/* makes the calculation much easier for it. ) */
3641/* In order to answer both limitations, and keep the struct small, the code */
3642/* will abuse the structure defined here to achieve the actual partition */
3643/* above */
3644/****************************************************************************/
3645struct fw_flr_mb {
3646 u32 aggint;
3647 u32 opgen_addr;
3648 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
3649#define ACCUM_ACK_PF_BASE 0
3650#define ACCUM_ACK_PF_SHIFT 0
3651
3652#define ACCUM_ACK_VF_BASE 8
3653#define ACCUM_ACK_VF_SHIFT 3
3654
3655#define ACCUM_ACK_IOV_DIS_BASE 256
3656#define ACCUM_ACK_IOV_DIS_SHIFT 8
3657};
3658
3659struct public_path {
3660 struct fw_flr_mb flr_mb;
3661 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
3662
3663 u32 process_kill;
3664#define PROCESS_KILL_COUNTER_MASK 0x0000ffff
3665#define PROCESS_KILL_COUNTER_SHIFT 0
3666#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
3667#define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
3668#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
3669};
3670
3671/**************************************/
3672/* */
3673/* P U B L I C P O R T */
3674/* */
3675/**************************************/
3676
3677/****************************************************************************
3678* Driver <-> FW Mailbox *
3679****************************************************************************/
3680
3681struct public_port {
3682 u32 validity_map; /* 0x0 (4*2 = 0x8) */
3683
3684 /* validity bits */
3685#define MCP_VALIDITY_PCI_CFG 0x00100000
3686#define MCP_VALIDITY_MB 0x00200000
3687#define MCP_VALIDITY_DEV_INFO 0x00400000
3688#define MCP_VALIDITY_RESERVED 0x00000007
3689
3690 /* One licensing bit should be set */
3691#define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
3692#define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
3693#define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
3694#define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
3695
3696 /* Active MFW */
3697#define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
3698#define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
3699#define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
3700#define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
3701
3702 u32 link_status;
3703#define LINK_STATUS_LINK_UP \
3704 0x00000001
3705#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
3706#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD BIT(1)
3707#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
3708#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
3709#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
3710#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
3711#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
3712#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
3713#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
3714
3715#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
3716
3717#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
3718#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
3719
3720#define LINK_STATUS_PFC_ENABLED \
3721 0x00000100
3722#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
3723#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
3724#define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
3725#define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
3726#define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
3727#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
3728#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
3729#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
3730
3731#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
3732#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
3733#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE BIT(18)
3734#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
3735#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
3736
3737#define LINK_STATUS_SFP_TX_FAULT \
3738 0x00100000
3739#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
3740#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
3741
3742 u32 link_status1;
3743 u32 ext_phy_fw_version;
3744 u32 drv_phy_cfg_addr;
3745
3746 u32 port_stx;
3747
3748 u32 stat_nig_timer;
3749
3750 struct port_mf_cfg port_mf_config;
3751 struct port_stats stats;
3752
3753 u32 media_type;
3754#define MEDIA_UNSPECIFIED 0x0
3755#define MEDIA_SFPP_10G_FIBER 0x1
3756#define MEDIA_XFP_FIBER 0x2
3757#define MEDIA_DA_TWINAX 0x3
3758#define MEDIA_BASE_T 0x4
3759#define MEDIA_SFP_1G_FIBER 0x5
3760#define MEDIA_KR 0xf0
3761#define MEDIA_NOT_PRESENT 0xff
3762
3763 u32 lfa_status;
3764#define LFA_LINK_FLAP_REASON_OFFSET 0
3765#define LFA_LINK_FLAP_REASON_MASK 0x000000ff
3766#define LFA_NO_REASON (0 << 0)
3767#define LFA_LINK_DOWN BIT(0)
3768#define LFA_FORCE_INIT BIT(1)
3769#define LFA_LOOPBACK_MISMATCH BIT(2)
3770#define LFA_SPEED_MISMATCH BIT(3)
3771#define LFA_FLOW_CTRL_MISMATCH BIT(4)
3772#define LFA_ADV_SPEED_MISMATCH BIT(5)
3773#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
3774#define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
3775#define LINK_FLAP_COUNT_OFFSET 16
3776#define LINK_FLAP_COUNT_MASK 0x00ff0000
3777
3778 u32 link_change_count;
3779
3780 /* LLDP params */
3781 struct lldp_config_params_s lldp_config_params[
3782 LLDP_MAX_LLDP_AGENTS];
3783 struct lldp_status_params_s lldp_status_params[
3784 LLDP_MAX_LLDP_AGENTS];
3785 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
3786
3787 /* DCBX related MIB */
3788 struct dcbx_local_params local_admin_dcbx_mib;
3789 struct dcbx_mib remote_dcbx_mib;
3790 struct dcbx_mib operational_dcbx_mib;
3791};
3792
3793/**************************************/
3794/* */
3795/* P U B L I C F U N C */
3796/* */
3797/**************************************/
3798
3799struct public_func {
3800 u32 iscsi_boot_signature;
3801 u32 iscsi_boot_block_offset;
3802
3803 u32 reserved[8];
3804
3805 u32 config;
3806
3807 /* E/R/I/D */
3808 /* function 0 of each port cannot be hidden */
3809#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
3810#define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
3811#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
3812
3813#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
3814#define FUNC_MF_CFG_PROTOCOL_SHIFT 4
3815#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
3816#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
3817#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
3818#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
3819#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
3820
3821 /* MINBW, MAXBW */
3822 /* value range - 0..100, increments in 1 % */
3823#define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
3824#define FUNC_MF_CFG_MIN_BW_SHIFT 8
3825#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
3826#define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
3827#define FUNC_MF_CFG_MAX_BW_SHIFT 16
3828#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
3829
3830 u32 status;
3831#define FUNC_STATUS_VLINK_DOWN 0x00000001
3832
3833 u32 mac_upper; /* MAC */
3834#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
3835#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
3836#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
3837 u32 mac_lower;
3838#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
3839
3840 u32 fcoe_wwn_port_name_upper;
3841 u32 fcoe_wwn_port_name_lower;
3842
3843 u32 fcoe_wwn_node_name_upper;
3844 u32 fcoe_wwn_node_name_lower;
3845
3846 u32 ovlan_stag; /* tags */
3847#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
3848#define FUNC_MF_CFG_OV_STAG_SHIFT 0
3849#define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
3850
3851 u32 pf_allocation; /* vf per pf */
3852
3853 u32 preserve_data; /* Will be used bt CCM */
3854
3855 u32 driver_last_activity_ts;
3856
3857 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
3858
3859 u32 drv_id;
3860#define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
3861#define DRV_ID_PDA_COMP_VER_SHIFT 0
3862
3863#define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
3864#define DRV_ID_MCP_HSI_VER_SHIFT 16
3865#define DRV_ID_MCP_HSI_VER_CURRENT BIT(DRV_ID_MCP_HSI_VER_SHIFT)
3866
3867#define DRV_ID_DRV_TYPE_MASK 0xff000000
3868#define DRV_ID_DRV_TYPE_SHIFT 24
3869#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
3870#define DRV_ID_DRV_TYPE_LINUX BIT(DRV_ID_DRV_TYPE_SHIFT)
3871#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
3872#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
3873#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
3874#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
3875#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
3876#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
3877#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
3878};
3879
3880/**************************************/
3881/* */
3882/* P U B L I C M B */
3883/* */
3884/**************************************/
3885/* This is the only section that the driver can write to, and each */
3886/* Basically each driver request to set feature parameters,
3887 * will be done using a different command, which will be linked
3888 * to a specific data structure from the union below.
3889 * For huge strucuture, the common blank structure should be used.
3890 */
3891
3892struct mcp_mac {
3893 u32 mac_upper; /* Upper 16 bits are always zeroes */
3894 u32 mac_lower;
3895};
3896
3897struct mcp_val64 {
3898 u32 lo;
3899 u32 hi;
3900};
3901
3902struct mcp_file_att {
3903 u32 nvm_start_addr;
3904 u32 len;
3905};
3906
3907#define MCP_DRV_VER_STR_SIZE 16
3908#define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
3909#define MCP_DRV_NVM_BUF_LEN 32
3910struct drv_version_stc {
3911 u32 version;
3912 u8 name[MCP_DRV_VER_STR_SIZE - 4];
3913};
3914
3915union drv_union_data {
3916 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
3917 struct mcp_mac wol_mac;
3918
3919 struct pmm_phy_cfg drv_phy_cfg;
3920
3921 struct mcp_val64 val64; /* For PHY / AVS commands */
3922
3923 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
3924
3925 struct mcp_file_att file_att;
3926
3927 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
3928
3929 struct drv_version_stc drv_version;
3930};
3931
3932struct public_drv_mb {
3933 u32 drv_mb_header;
3934#define DRV_MSG_CODE_MASK 0xffff0000
3935#define DRV_MSG_CODE_LOAD_REQ 0x10000000
3936#define DRV_MSG_CODE_LOAD_DONE 0x11000000
3937#define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
3938#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
3939#define DRV_MSG_CODE_INIT_PHY 0x22000000
3940 /* Params - FORCE - Reinitialize the link regardless of LFA */
3941 /* - DONT_CARE - Don't flap the link if up */
3942#define DRV_MSG_CODE_LINK_RESET 0x23000000
3943
3944#define DRV_MSG_CODE_SET_LLDP 0x24000000
3945#define DRV_MSG_CODE_SET_DCBX 0x25000000
3946
3947#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
3948
3949#define DRV_MSG_CODE_INITIATE_FLR 0x02000000
3950#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
3951#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
3952#define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
3953#define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
3954#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
3955#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
3956#define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
3957#define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
3958#define DRV_MSG_CODE_MCP_RESET 0x00090000
3959#define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
3960#define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
3961#define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
3962#define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
3963#define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
3964#define DRV_MSG_CODE_SET_VERSION 0x000f0000
3965
3966#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
3967
3968 u32 drv_mb_param;
3969
3970 /* UNLOAD_REQ params */
3971#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
3972#define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
3973#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
3974#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
3975
3976 /* UNLOAD_DONE_params */
3977#define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
3978
3979 /* INIT_PHY params */
3980#define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
3981#define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
3982
3983 /* LLDP / DCBX params*/
3984#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
3985#define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
3986#define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
3987#define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
3988#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
3989#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
3990
3991#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
3992#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
3993
3994#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
3995#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
3996
3997#define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
3998#define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
3999#define DRV_MB_PARAM_NVM_LEN_SHIFT 24
4000#define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
4001
4002#define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
4003#define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
4004#define DRV_MB_PARAM_PHY_LANE_SHIFT 16
4005#define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
4006#define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
4007#define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
4008#define DRV_MB_PARAM_PHY_PORT_SHIFT 30
4009#define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
4010
4011/* configure vf MSIX params*/
4012#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
4013#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
4014#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
4015#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
4016
4017 u32 fw_mb_header;
4018#define FW_MSG_CODE_MASK 0xffff0000
4019#define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
4020#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
4021#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
4022#define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
4023#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
4024#define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
4025#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
4026#define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
4027#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
4028#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
4029#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
4030#define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
4031#define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
4032#define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
4033#define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
4034#define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
4035#define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
4036#define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
4037#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
4038#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
4039#define FW_MSG_CODE_FLR_ACK 0x02000000
4040#define FW_MSG_CODE_FLR_NACK 0x02100000
4041
4042#define FW_MSG_CODE_NVM_OK 0x00010000
4043#define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
4044#define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
4045#define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
4046#define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
4047#define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
4048#define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
4049#define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
4050#define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
4051#define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
4052#define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
4053#define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
4054#define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
4055#define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
4056#define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
4057#define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
4058#define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
4059#define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
4060#define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
4061#define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
4062#define FW_MSG_CODE_PHY_OK 0x00110000
4063#define FW_MSG_CODE_PHY_ERROR 0x00120000
4064#define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
4065#define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
4066#define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
4067
4068#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
4069
4070 u32 fw_mb_param;
4071
4072 u32 drv_pulse_mb;
4073#define DRV_PULSE_SEQ_MASK 0x00007fff
4074#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
4075#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
4076 u32 mcp_pulse_mb;
4077#define MCP_PULSE_SEQ_MASK 0x00007fff
4078#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
4079#define MCP_EVENT_MASK 0xffff0000
4080#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
4081
4082 union drv_union_data union_data;
4083};
4084
4085/* MFW - DRV MB */
4086/**********************************************************************
4087* Description
4088* Incremental Aggregative
4089* 8-bit MFW counter per message
4090* 8-bit ack-counter per message
4091* Capabilities
4092* Provides up to 256 aggregative message per type
4093* Provides 4 message types in dword
4094* Message type pointers to byte offset
4095* Backward Compatibility by using sizeof for the counters.
4096* No lock requires for 32bit messages
4097* Limitations:
4098* In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
4099* is required to prevent data corruption.
4100**********************************************************************/
4101enum MFW_DRV_MSG_TYPE {
4102 MFW_DRV_MSG_LINK_CHANGE,
4103 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
4104 MFW_DRV_MSG_VF_DISABLED,
4105 MFW_DRV_MSG_LLDP_DATA_UPDATED,
4106 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
4107 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
4108 MFW_DRV_MSG_ERROR_RECOVERY,
4109 MFW_DRV_MSG_MAX
4110};
4111
4112#define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
4113#define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
4114#define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
4115#define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
4116
4117struct public_mfw_mb {
4118 u32 sup_msgs;
4119 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4120 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4121};
4122
4123/**************************************/
4124/* */
4125/* P U B L I C D A T A */
4126/* */
4127/**************************************/
4128enum public_sections {
4129 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
4130 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
4131 PUBLIC_GLOBAL,
4132 PUBLIC_PATH,
4133 PUBLIC_PORT,
4134 PUBLIC_FUNC,
4135 PUBLIC_MAX_SECTIONS
4136};
4137
4138struct drv_ver_info_stc {
4139 u32 ver;
4140 u8 name[32];
4141};
4142
4143struct mcp_public_data {
4144 /* The sections fields is an array */
4145 u32 num_sections;
4146 offsize_t sections[PUBLIC_MAX_SECTIONS];
4147 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
4148 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
4149 struct public_global global;
4150 struct public_path path[MCP_GLOB_PATH_MAX];
4151 struct public_port port[MCP_GLOB_PORT_MAX];
4152 struct public_func func[MCP_GLOB_FUNC_MAX];
4153 struct drv_ver_info_stc drv_info;
4154};
4155
4156struct nvm_cfg_mac_address {
4157 u32 mac_addr_hi;
4158#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
4159#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
4160
4161 u32 mac_addr_lo;
4162};
4163
4164/******************************************
4165* nvm_cfg1 structs
4166******************************************/
4167
4168struct nvm_cfg1_glob {
4169 u32 generic_cont0; /* 0x0 */
4170#define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
4171#define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
4172#define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
4173#define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
4174#define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
4175#define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
4176#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
4177#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
4178#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
4179#define NVM_CFG1_GLOB_MF_MODE_FORCED_SF 0x1
4180#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
4181#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
4182#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
4183#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
4184#define NVM_CFG1_GLOB_MF_MODE_BD 0x6
4185#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
4186#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
4187#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
4188#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
4189#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
4190#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
4191#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
4192#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
4193#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
4194#define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
4195#define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
4196#define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
4197#define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
4198#define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
4199#define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
4200#define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
4201#define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
4202#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
4203#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
4204#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
4205#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
4206
4207 u32 engineering_change[3]; /* 0x4 */
4208
4209 u32 manufacturing_id; /* 0x10 */
4210
4211 u32 serial_number[4]; /* 0x14 */
4212
4213 u32 pcie_cfg; /* 0x24 */
4214#define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
4215#define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
4216#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
4217#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
4218#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
4219#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
4220#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
4221#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
4222#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
4223#define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
4224#define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
4225#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
4226#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
4227#define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
4228#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
4229#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_MASK 0x00000020
4230#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_OFFSET 5
4231#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_DISABLED 0x0
4232#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_ENABLED 0x1
4233#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
4234#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
4235#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
4236#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
4237#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
4238#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
4239#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
4240#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
4241#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
4242#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
4243#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
4244#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
4245#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
4246#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
4247
4248 u32 mgmt_traffic; /* 0x28 */
4249#define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
4250#define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
4251#define NVM_CFG1_GLOB_RESERVED60_100KHZ 0x0
4252#define NVM_CFG1_GLOB_RESERVED60_400KHZ 0x1
4253#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
4254#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
4255#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
4256#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
4257#define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
4258#define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
4259#define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
4260#define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
4261#define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
4262#define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
4263#define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
4264
4265 u32 core_cfg; /* 0x2C */
4266#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
4267#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
4268#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0
4269#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1
4270#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2
4271#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F 0x3
4272#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E 0x4
4273#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G 0x5
4274#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G 0xB
4275#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G 0xC
4276#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G 0xD
4277#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK 0x00000100
4278#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET 8
4279#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4280#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4281#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK 0x00000200
4282#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET 9
4283#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4284#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4285#define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK 0x0003FC00
4286#define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10
4287#define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000
4288#define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18
4289#define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
4290#define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
4291#define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
4292#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP 0x1
4293#define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
4294#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
4295#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
4296#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
4297#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
4298
4299 u32 e_lane_cfg1; /* 0x30 */
4300#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4301#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4302#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4303#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4304#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4305#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4306#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4307#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4308#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4309#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4310#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4311#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4312#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4313#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4314#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4315#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4316
4317 u32 e_lane_cfg2; /* 0x34 */
4318#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4319#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4320#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4321#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4322#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4323#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4324#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4325#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4326#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4327#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4328#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4329#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4330#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4331#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4332#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4333#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4334#define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
4335#define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
4336#define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
4337#define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
4338#define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
4339#define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
4340#define NVM_CFG1_GLOB_NCSI_OFFSET 12
4341#define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
4342#define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
4343
4344 u32 f_lane_cfg1; /* 0x38 */
4345#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4346#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4347#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4348#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4349#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4350#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4351#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4352#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4353#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4354#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4355#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4356#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4357#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4358#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4359#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4360#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4361
4362 u32 f_lane_cfg2; /* 0x3C */
4363#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4364#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4365#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4366#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4367#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4368#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4369#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4370#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4371#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4372#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4373#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4374#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4375#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4376#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4377#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4378#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4379
4380 u32 eagle_preemphasis; /* 0x40 */
4381#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4382#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4383#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4384#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4385#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4386#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4387#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4388#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4389
4390 u32 eagle_driver_current; /* 0x44 */
4391#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4392#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4393#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4394#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4395#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4396#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4397#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4398#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4399
4400 u32 falcon_preemphasis; /* 0x48 */
4401#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4402#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4403#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4404#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4405#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4406#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4407#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4408#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4409
4410 u32 falcon_driver_current; /* 0x4C */
4411#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4412#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4413#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4414#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4415#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4416#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4417#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4418#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4419
4420 u32 pci_id; /* 0x50 */
4421#define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
4422#define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
4423
4424 u32 pci_subsys_id; /* 0x54 */
4425#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
4426#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
4427#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
4428#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
4429
4430 u32 bar; /* 0x58 */
4431#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
4432#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
4433#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
4434#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
4435#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
4436#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
4437#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
4438#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
4439#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
4440#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
4441#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
4442#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
4443#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
4444#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
4445#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
4446#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
4447#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
4448#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
4449#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
4450#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
4451#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
4452#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
4453#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
4454#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
4455#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
4456#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
4457#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
4458#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
4459#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
4460#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
4461#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
4462#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
4463#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
4464#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
4465#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
4466#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
4467#define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
4468#define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
4469#define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
4470#define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
4471#define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
4472#define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
4473#define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
4474#define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
4475#define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
4476#define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
4477#define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
4478#define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
4479#define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
4480#define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
4481#define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
4482#define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
4483#define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
4484#define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
4485
4486 u32 eagle_txfir_main; /* 0x5C */
4487#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4488#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4489#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4490#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4491#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4492#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4493#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4494#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4495
4496 u32 eagle_txfir_post; /* 0x60 */
4497#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4498#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4499#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4500#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4501#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4502#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4503#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4504#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4505
4506 u32 falcon_txfir_main; /* 0x64 */
4507#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4508#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4509#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4510#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4511#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4512#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4513#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4514#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4515
4516 u32 falcon_txfir_post; /* 0x68 */
4517#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4518#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4519#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4520#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4521#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4522#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4523#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4524#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4525
4526 u32 manufacture_ver; /* 0x6C */
4527#define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
4528#define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
4529#define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
4530#define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
4531#define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
4532#define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
4533#define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
4534#define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
4535#define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
4536#define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
4537
4538 u32 manufacture_time; /* 0x70 */
4539#define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
4540#define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
4541#define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
4542#define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
4543#define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
4544#define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
4545
4546 u32 led_global_settings; /* 0x74 */
4547#define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
4548#define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
4549#define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
4550#define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
4551#define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
4552#define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
4553#define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
4554#define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
4555
4556 u32 generic_cont1; /* 0x78 */
4557#define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
4558#define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
4559
4560 u32 mbi_version; /* 0x7C */
4561#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
4562#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
4563#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
4564#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
4565#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
4566#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
4567
4568 u32 mbi_date; /* 0x80 */
4569
4570 u32 misc_sig; /* 0x84 */
4571
4572 /* Define the GPIO mapping to switch i2c mux */
4573#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
4574#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
4575#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
4576#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
4577#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
4578#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
4579#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
4580#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
4581#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
4582#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
4583#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
4584#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
4585#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
4586#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
4587#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
4588#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
4589#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
4590#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
4591#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
4592#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
4593#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
4594#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
4595#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
4596#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
4597#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
4598#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
4599#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
4600#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
4601#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
4602#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
4603#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
4604#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
4605#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
4606#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
4607#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
4608#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
4609#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
4610
4611 u32 reserved[46]; /* 0x88 */
4612};
4613
4614struct nvm_cfg1_path {
4615 u32 reserved[30]; /* 0x0 */
4616};
4617
4618struct nvm_cfg1_port {
4619 u32 power_dissipated; /* 0x0 */
4620#define NVM_CFG1_PORT_POWER_DIS_D0_MASK 0x000000FF
4621#define NVM_CFG1_PORT_POWER_DIS_D0_OFFSET 0
4622#define NVM_CFG1_PORT_POWER_DIS_D1_MASK 0x0000FF00
4623#define NVM_CFG1_PORT_POWER_DIS_D1_OFFSET 8
4624#define NVM_CFG1_PORT_POWER_DIS_D2_MASK 0x00FF0000
4625#define NVM_CFG1_PORT_POWER_DIS_D2_OFFSET 16
4626#define NVM_CFG1_PORT_POWER_DIS_D3_MASK 0xFF000000
4627#define NVM_CFG1_PORT_POWER_DIS_D3_OFFSET 24
4628
4629 u32 power_consumed; /* 0x4 */
4630#define NVM_CFG1_PORT_POWER_CONS_D0_MASK 0x000000FF
4631#define NVM_CFG1_PORT_POWER_CONS_D0_OFFSET 0
4632#define NVM_CFG1_PORT_POWER_CONS_D1_MASK 0x0000FF00
4633#define NVM_CFG1_PORT_POWER_CONS_D1_OFFSET 8
4634#define NVM_CFG1_PORT_POWER_CONS_D2_MASK 0x00FF0000
4635#define NVM_CFG1_PORT_POWER_CONS_D2_OFFSET 16
4636#define NVM_CFG1_PORT_POWER_CONS_D3_MASK 0xFF000000
4637#define NVM_CFG1_PORT_POWER_CONS_D3_OFFSET 24
4638
4639 u32 generic_cont0; /* 0x8 */
4640#define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
4641#define NVM_CFG1_PORT_LED_MODE_OFFSET 0
4642#define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
4643#define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
4644#define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
4645#define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
4646#define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
4647#define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
4648#define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
4649#define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
4650#define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
4651#define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
4652#define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
4653#define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
4654#define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
4655#define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
4656#define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
4657#define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
4658#define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
4659#define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
4660#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
4661#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
4662#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
4663#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
4664#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
4665#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
4666
4667 u32 pcie_cfg; /* 0xC */
4668#define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
4669#define NVM_CFG1_PORT_RESERVED15_OFFSET 0
4670
4671 u32 features; /* 0x10 */
4672#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
4673#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
4674#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
4675#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
4676#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
4677#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
4678#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
4679#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
4680
4681 u32 speed_cap_mask; /* 0x14 */
4682#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
4683#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
4684#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
4685#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
4686#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
4687#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
4688#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
4689#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40
4690#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
4691#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
4692#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
4693#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
4694#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
4695#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
4696#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
4697#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40
4698
4699 u32 link_settings; /* 0x18 */
4700#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
4701#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
4702#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
4703#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
4704#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
4705#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
4706#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
4707#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
4708#define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7
4709#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
4710#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
4711#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
4712#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
4713#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
4714#define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
4715#define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
4716#define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
4717#define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
4718#define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
4719#define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
4720#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
4721#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
4722#define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7
4723#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
4724#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
4725#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
4726#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
4727#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
4728#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
4729#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
4730#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
4731#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
4732
4733 u32 phy_cfg; /* 0x1C */
4734#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
4735#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
4736#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
4737#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
4738#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
4739#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
4740#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
4741#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
4742#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
4743#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
4744#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
4745#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
4746#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
4747#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
4748#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
4749#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
4750#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
4751#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0xD
4752#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0xE
4753#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0xF
4754#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x10
4755#define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
4756#define NVM_CFG1_PORT_AN_MODE_OFFSET 24
4757#define NVM_CFG1_PORT_AN_MODE_NONE 0x0
4758#define NVM_CFG1_PORT_AN_MODE_CL73 0x1
4759#define NVM_CFG1_PORT_AN_MODE_CL37 0x2
4760#define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
4761#define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4
4762#define NVM_CFG1_PORT_AN_MODE_HPAM 0x5
4763#define NVM_CFG1_PORT_AN_MODE_SGMII 0x6
4764
4765 u32 mgmt_traffic; /* 0x20 */
4766#define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
4767#define NVM_CFG1_PORT_RESERVED61_OFFSET 0
4768#define NVM_CFG1_PORT_RESERVED61_DISABLED 0x0
4769#define NVM_CFG1_PORT_RESERVED61_NCSI_OVER_RMII 0x1
4770#define NVM_CFG1_PORT_RESERVED61_NCSI_OVER_SMBUS 0x2
4771
4772 u32 ext_phy; /* 0x24 */
4773#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
4774#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
4775#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
4776#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1
4777#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
4778#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
4779
4780 u32 mba_cfg1; /* 0x28 */
4781#define NVM_CFG1_PORT_MBA_MASK 0x00000001
4782#define NVM_CFG1_PORT_MBA_OFFSET 0
4783#define NVM_CFG1_PORT_MBA_DISABLED 0x0
4784#define NVM_CFG1_PORT_MBA_ENABLED 0x1
4785#define NVM_CFG1_PORT_MBA_BOOT_TYPE_MASK 0x00000006
4786#define NVM_CFG1_PORT_MBA_BOOT_TYPE_OFFSET 1
4787#define NVM_CFG1_PORT_MBA_BOOT_TYPE_AUTO 0x0
4788#define NVM_CFG1_PORT_MBA_BOOT_TYPE_BBS 0x1
4789#define NVM_CFG1_PORT_MBA_BOOT_TYPE_INT18H 0x2
4790#define NVM_CFG1_PORT_MBA_BOOT_TYPE_INT19H 0x3
4791#define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
4792#define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
4793#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
4794#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
4795#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
4796#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
4797#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
4798#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
4799#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
4800#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
4801#define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
4802#define NVM_CFG1_PORT_RESERVED5_OFFSET 9
4803#define NVM_CFG1_PORT_RESERVED5_DISABLED 0x0
4804#define NVM_CFG1_PORT_RESERVED5_2K 0x1
4805#define NVM_CFG1_PORT_RESERVED5_4K 0x2
4806#define NVM_CFG1_PORT_RESERVED5_8K 0x3
4807#define NVM_CFG1_PORT_RESERVED5_16K 0x4
4808#define NVM_CFG1_PORT_RESERVED5_32K 0x5
4809#define NVM_CFG1_PORT_RESERVED5_64K 0x6
4810#define NVM_CFG1_PORT_RESERVED5_128K 0x7
4811#define NVM_CFG1_PORT_RESERVED5_256K 0x8
4812#define NVM_CFG1_PORT_RESERVED5_512K 0x9
4813#define NVM_CFG1_PORT_RESERVED5_1M 0xA
4814#define NVM_CFG1_PORT_RESERVED5_2M 0xB
4815#define NVM_CFG1_PORT_RESERVED5_4M 0xC
4816#define NVM_CFG1_PORT_RESERVED5_8M 0xD
4817#define NVM_CFG1_PORT_RESERVED5_16M 0xE
4818#define NVM_CFG1_PORT_RESERVED5_32M 0xF
4819#define NVM_CFG1_PORT_MBA_LINK_SPEED_MASK 0x001E0000
4820#define NVM_CFG1_PORT_MBA_LINK_SPEED_OFFSET 17
4821#define NVM_CFG1_PORT_MBA_LINK_SPEED_AUTONEG 0x0
4822#define NVM_CFG1_PORT_MBA_LINK_SPEED_1G 0x1
4823#define NVM_CFG1_PORT_MBA_LINK_SPEED_10G 0x2
4824#define NVM_CFG1_PORT_MBA_LINK_SPEED_25G 0x4
4825#define NVM_CFG1_PORT_MBA_LINK_SPEED_40G 0x5
4826#define NVM_CFG1_PORT_MBA_LINK_SPEED_50G 0x6
4827#define NVM_CFG1_PORT_MBA_LINK_SPEED_100G 0x7
4828#define NVM_CFG1_PORT_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
4829#define NVM_CFG1_PORT_MBA_BOOT_RETRY_COUNT_OFFSET 21
4830
4831 u32 mba_cfg2; /* 0x2C */
4832#define NVM_CFG1_PORT_MBA_VLAN_VALUE_MASK 0x0000FFFF
4833#define NVM_CFG1_PORT_MBA_VLAN_VALUE_OFFSET 0
4834#define NVM_CFG1_PORT_MBA_VLAN_MASK 0x00010000
4835#define NVM_CFG1_PORT_MBA_VLAN_OFFSET 16
4836
4837 u32 vf_cfg; /* 0x30 */
4838#define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
4839#define NVM_CFG1_PORT_RESERVED8_OFFSET 0
4840#define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
4841#define NVM_CFG1_PORT_RESERVED6_OFFSET 16
4842#define NVM_CFG1_PORT_RESERVED6_DISABLED 0x0
4843#define NVM_CFG1_PORT_RESERVED6_4K 0x1
4844#define NVM_CFG1_PORT_RESERVED6_8K 0x2
4845#define NVM_CFG1_PORT_RESERVED6_16K 0x3
4846#define NVM_CFG1_PORT_RESERVED6_32K 0x4
4847#define NVM_CFG1_PORT_RESERVED6_64K 0x5
4848#define NVM_CFG1_PORT_RESERVED6_128K 0x6
4849#define NVM_CFG1_PORT_RESERVED6_256K 0x7
4850#define NVM_CFG1_PORT_RESERVED6_512K 0x8
4851#define NVM_CFG1_PORT_RESERVED6_1M 0x9
4852#define NVM_CFG1_PORT_RESERVED6_2M 0xA
4853#define NVM_CFG1_PORT_RESERVED6_4M 0xB
4854#define NVM_CFG1_PORT_RESERVED6_8M 0xC
4855#define NVM_CFG1_PORT_RESERVED6_16M 0xD
4856#define NVM_CFG1_PORT_RESERVED6_32M 0xE
4857#define NVM_CFG1_PORT_RESERVED6_64M 0xF
4858
4859 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
4860
4861 u32 led_port_settings; /* 0x3C */
4862#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
4863#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
4864#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
4865#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
4866#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
4867#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
4868#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
4869#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
4870#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
4871#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
4872#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
4873#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40
4874
4875 u32 transceiver_00; /* 0x40 */
4876
4877 /* Define for mapping of transceiver signal module absent */
4878#define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
4879#define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
4880#define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
4881#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
4882#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
4883#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
4884#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
4885#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
4886#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
4887#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
4888#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
4889#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
4890#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
4891#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
4892#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
4893#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
4894#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
4895#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
4896#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
4897#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
4898#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
4899#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
4900#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
4901#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
4902#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
4903#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
4904#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
4905#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
4906#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
4907#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
4908#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
4909#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
4910#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
4911#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
4912#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
4913 /* Define the GPIO mux settings to switch i2c mux to this port */
4914#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
4915#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
4916#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
4917#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
4918
4919 u32 reserved[133]; /* 0x44 */
4920};
4921
4922struct nvm_cfg1_func {
4923 struct nvm_cfg_mac_address mac_address; /* 0x0 */
4924
4925 u32 rsrv1; /* 0x8 */
4926#define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
4927#define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
4928#define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
4929#define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
4930
4931 u32 rsrv2; /* 0xC */
4932#define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
4933#define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
4934#define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
4935#define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
4936
4937 u32 device_id; /* 0x10 */
4938#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
4939#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
4940#define NVM_CFG1_FUNC_VENDOR_DEVICE_ID_MASK 0xFFFF0000
4941#define NVM_CFG1_FUNC_VENDOR_DEVICE_ID_OFFSET 16
4942
4943 u32 cmn_cfg; /* 0x14 */
4944#define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_MASK 0x00000007
4945#define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_OFFSET 0
4946#define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_PXE 0x0
4947#define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_RPL 0x1
4948#define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_BOOTP 0x2
4949#define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_ISCSI_BOOT 0x3
4950#define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_FCOE_BOOT 0x4
4951#define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_NONE 0x7
4952#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
4953#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
4954#define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
4955#define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
4956#define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
4957#define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
4958#define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
4959#define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
4960#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
4961#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
4962#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
4963#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
4964#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
4965#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
4966
4967 u32 pci_cfg; /* 0x18 */
4968#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
4969#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
4970#define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80
4971#define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7
4972#define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
4973#define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
4974#define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
4975#define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
4976#define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
4977#define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
4978#define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
4979#define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
4980#define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
4981#define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
4982#define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
4983#define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
4984#define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
4985#define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
4986#define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
4987#define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
4988#define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
4989#define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
4990#define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
4991#define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
4992
4993 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
4994
4995 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
4996
4997 u32 reserved[9]; /* 0x2C */
4998};
4999
5000struct nvm_cfg1 {
5001 struct nvm_cfg1_glob glob; /* 0x0 */
5002
5003 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */
5004
5005 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
5006
5007 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
5008};
5009
5010/******************************************
5011* nvm_cfg structs
5012******************************************/
5013
5014enum nvm_cfg_sections {
5015 NVM_CFG_SECTION_NVM_CFG1,
5016 NVM_CFG_SECTION_MAX
5017};
5018
5019struct nvm_cfg {
5020 u32 num_sections;
5021 u32 sections_offset[NVM_CFG_SECTION_MAX];
5022 struct nvm_cfg1 cfg1;
5023};
5024
5025#define PORT_0 0
5026#define PORT_1 1
5027#define PORT_2 2
5028#define PORT_3 3
5029
5030extern struct spad_layout g_spad;
5031
5032#define MCP_SPAD_SIZE 0x00028000 /* 160 KB */
5033
5034#define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
5035
5036#define TO_OFFSIZE(_offset, _size) \
5037 (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
5038 (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
5039
5040enum spad_sections {
5041 SPAD_SECTION_TRACE,
5042 SPAD_SECTION_NVM_CFG,
5043 SPAD_SECTION_PUBLIC,
5044 SPAD_SECTION_PRIVATE,
5045 SPAD_SECTION_MAX
5046};
5047
5048struct spad_layout {
5049 struct nvm_cfg nvm_cfg;
5050 struct mcp_public_data public_data;
5051};
5052
5053#define CRC_MAGIC_VALUE 0xDEBB20E3
5054#define CRC32_POLYNOMIAL 0xEDB88320
5055#define NVM_CRC_SIZE (sizeof(u32))
5056
5057enum nvm_sw_arbitrator {
5058 NVM_SW_ARB_HOST,
5059 NVM_SW_ARB_MCP,
5060 NVM_SW_ARB_UART,
5061 NVM_SW_ARB_RESERVED
5062};
5063
5064/****************************************************************************
5065* Boot Strap Region *
5066****************************************************************************/
5067struct legacy_bootstrap_region {
5068 u32 magic_value;
5069#define NVM_MAGIC_VALUE 0x669955aa
5070 u32 sram_start_addr;
5071 u32 code_len; /* boot code length (in dwords) */
5072 u32 code_start_addr;
5073 u32 crc; /* 32-bit CRC */
5074};
5075
5076/****************************************************************************
5077* Directories Region *
5078****************************************************************************/
5079struct nvm_code_entry {
5080 u32 image_type; /* Image type */
5081 u32 nvm_start_addr; /* NVM address of the image */
5082 u32 len; /* Include CRC */
5083 u32 sram_start_addr;
5084 u32 sram_run_addr; /* Relevant in case of MIM only */
5085};
5086
5087enum nvm_image_type {
5088 NVM_TYPE_TIM1 = 0x01,
5089 NVM_TYPE_TIM2 = 0x02,
5090 NVM_TYPE_MIM1 = 0x03,
5091 NVM_TYPE_MIM2 = 0x04,
5092 NVM_TYPE_MBA = 0x05,
5093 NVM_TYPE_MODULES_PN = 0x06,
5094 NVM_TYPE_VPD = 0x07,
5095 NVM_TYPE_MFW_TRACE1 = 0x08,
5096 NVM_TYPE_MFW_TRACE2 = 0x09,
5097 NVM_TYPE_NVM_CFG1 = 0x0a,
5098 NVM_TYPE_L2B = 0x0b,
5099 NVM_TYPE_DIR1 = 0x0c,
5100 NVM_TYPE_EAGLE_FW1 = 0x0d,
5101 NVM_TYPE_FALCON_FW1 = 0x0e,
5102 NVM_TYPE_PCIE_FW1 = 0x0f,
5103 NVM_TYPE_HW_SET = 0x10,
5104 NVM_TYPE_LIM = 0x11,
5105 NVM_TYPE_AVS_FW1 = 0x12,
5106 NVM_TYPE_DIR2 = 0x13,
5107 NVM_TYPE_CCM = 0x14,
5108 NVM_TYPE_EAGLE_FW2 = 0x15,
5109 NVM_TYPE_FALCON_FW2 = 0x16,
5110 NVM_TYPE_PCIE_FW2 = 0x17,
5111 NVM_TYPE_AVS_FW2 = 0x18,
5112
5113 NVM_TYPE_MAX,
5114};
5115
5116#define MAX_NVM_DIR_ENTRIES 200
5117
5118struct nvm_dir {
5119 s32 seq;
5120#define NVM_DIR_NEXT_MFW_MASK 0x00000001
5121#define NVM_DIR_SEQ_MASK 0xfffffffe
5122#define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
5123
5124#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
5125
5126 u32 num_images;
5127 u32 rsrv;
5128 struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */
5129};
5130
5131#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + \
5132 (_num_images - \
5133 1) * sizeof(struct nvm_code_entry) + \
5134 NVM_CRC_SIZE)
5135
5136struct nvm_vpd_image {
5137 u32 format_revision;
5138#define VPD_IMAGE_VERSION 1
5139
5140 /* This array length depends on the number of VPD fields */
5141 u8 vpd_data[1];
5142};
5143
5144/****************************************************************************
5145* NVRAM FULL MAP *
5146****************************************************************************/
5147#define DIR_ID_1 (0)
5148#define DIR_ID_2 (1)
5149#define MAX_DIR_IDS (2)
5150
5151#define MFW_BUNDLE_1 (0)
5152#define MFW_BUNDLE_2 (1)
5153#define MAX_MFW_BUNDLES (2)
5154
5155#define FLASH_PAGE_SIZE 0x1000
5156#define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */
5157#define ASIC_MIM_MAX_SIZE (300 * FLASH_PAGE_SIZE) /* 1.2Mb */
5158#define FPGA_MIM_MAX_SIZE (25 * FLASH_PAGE_SIZE) /* 60Kb */
5159
5160#define LIM_MAX_SIZE ((2 * \
5161 FLASH_PAGE_SIZE) - \
5162 sizeof(struct legacy_bootstrap_region) - \
5163 NVM_RSV_SIZE)
5164#define LIM_OFFSET (NVM_OFFSET(lim_image))
5165#define NVM_RSV_SIZE (44)
5166#define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : \
5167 FPGA_MIM_MAX_SIZE)
5168#define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + \
5169 ((idx == \
5170 NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
5171#define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + \
5172 MIM_MAX_SIZE(is_asic) * 2)
5173
5174union nvm_dir_union {
5175 struct nvm_dir dir;
5176 u8 page[FLASH_PAGE_SIZE];
5177};
5178
5179/* Address
5180 * +-------------------+ 0x000000
5181 * | Bootstrap: |
5182 * | magic_number |
5183 * | sram_start_addr |
5184 * | code_len |
5185 * | code_start_addr |
5186 * | crc |
5187 * +-------------------+ 0x000014
5188 * | rsrv |
5189 * +-------------------+ 0x000040
5190 * | LIM |
5191 * +-------------------+ 0x002000
5192 * | Dir1 |
5193 * +-------------------+ 0x003000
5194 * | Dir2 |
5195 * +-------------------+ 0x004000
5196 * | MIM1 |
5197 * +-------------------+ 0x130000
5198 * | MIM2 |
5199 * +-------------------+ 0x25C000
5200 * | Rest Images: |
5201 * | TIM1/2 |
5202 * | MFW_TRACE1/2 |
5203 * | Eagle/Falcon FW |
5204 * | PCIE/AVS FW |
5205 * | MBA/CCM/L2B |
5206 * | VPD |
5207 * | optic_modules |
5208 * | ... |
5209 * +-------------------+ 0x400000
5210 */
5211struct nvm_image {
5212/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
5213 /* NVM Offset (size) */
5214 struct legacy_bootstrap_region bootstrap;
5215 u8 rsrv[NVM_RSV_SIZE];
5216 u8 lim_image[LIM_MAX_SIZE];
5217 union nvm_dir_union dir[MAX_MFW_BUNDLES];
5218
5219 /* MIM1_IMAGE 0x004000 (0x12c000) */
5220 /* MIM2_IMAGE 0x130000 (0x12c000) */
5221/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
5222}; /* 0x134 */
5223
5224#define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->f))))
5225
5226struct hw_set_info {
5227 u32 reg_type;
5228#define GRC_REG_TYPE 1
5229#define PHY_REG_TYPE 2
5230#define PCI_REG_TYPE 4
5231
5232 u32 bank_num;
5233 u32 pf_num;
5234 u32 operation;
5235#define READ_OP 1
5236#define WRITE_OP 2
5237#define RMW_SET_OP 3
5238#define RMW_CLR_OP 4
5239
5240 u32 reg_addr;
5241 u32 reg_data;
5242
5243 u32 reset_type;
5244#define POR_RESET_TYPE BIT(0)
5245#define HARD_RESET_TYPE BIT(1)
5246#define CORE_RESET_TYPE BIT(2)
5247#define MCP_RESET_TYPE BIT(3)
5248#define PERSET_ASSERT BIT(4)
5249#define PERSET_DEASSERT BIT(5)
5250};
5251
5252struct hw_set_image {
5253 u32 format_version;
5254#define HW_SET_IMAGE_VERSION 1
5255 u32 no_hw_sets;
5256
5257 /* This array length depends on the no_hw_sets */
5258 struct hw_set_info hw_sets[1];
5259};
5260
5261#endif