blob: 587c0bd7043471659cc48645e7840055a061f023 [file] [log] [blame]
Arnd Bergmanncf82e0e2013-03-19 17:45:37 +01001config ARCH_SIRF
2 bool "CSR SiRF" if ARCH_MULTI_V7
3 select ARCH_REQUIRE_GPIOLIB
4 select GENERIC_CLOCKEVENTS
5 select GENERIC_IRQ_CHIP
6 select MIGHT_HAVE_CACHE_L2X0
7 select NO_IOPORT
8 select PINCTRL
9 select PINCTRL_SIRF
10 help
11 Support for CSR SiRFprimaII/Marco/Polo platforms
12
Barry Song156a0992012-08-23 13:41:58 +080013if ARCH_SIRF
14
Barry Songd4fe49e2013-03-18 15:04:38 +080015menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
16
17config ARCH_ATLAS6
18 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
19 default y
20 select CPU_V7
21 select SIRF_IRQ
22 help
23 Support for CSR SiRFSoC ARM Cortex A9 Platform
Barry Song156a0992012-08-23 13:41:58 +080024
25config ARCH_PRIMA2
26 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
27 default y
28 select CPU_V7
Barry Songc1e3c112012-08-23 13:41:59 +080029 select SIRF_IRQ
Russell Kingb1b3f492012-10-06 17:12:25 +010030 select ZONE_DMA
Barry Song156a0992012-08-23 13:41:58 +080031 help
32 Support for CSR SiRFSoC ARM Cortex A9 Platform
33
Barry Song4898de32012-12-20 19:37:32 +080034config ARCH_MARCO
35 bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
36 default y
37 select ARM_GIC
38 select CPU_V7
39 select HAVE_SMP
40 select SMP_ON_UP
41 help
42 Support for CSR SiRFSoC ARM Cortex A9 Platform
43
Barry Song156a0992012-08-23 13:41:58 +080044endmenu
45
Barry Songc1e3c112012-08-23 13:41:59 +080046config SIRF_IRQ
47 bool
48
Barry Song156a0992012-08-23 13:41:58 +080049endif