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gerrit-public.fairphone.software / kernel / msm-5.4 / d2912cb15bdda8ba4a5dd73396ad62641af2f520 / . / arch / arm / boot / dts / am335x-base0033.dts
blob: 89c00ce42c261c5866a6c566e7aec1ab51bfb974 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
Enric Balletbo i Serra5cda1622013-09-10 16:55:49 +0200[diff] [blame]2/*
3 * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
4 *
5 * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
Enric Balletbo i Serra5cda1622013-09-10 16:55:49 +0200[diff] [blame]6 */
7
8#include "am335x-igep0033.dtsi"
9
10/ {
11 model = "IGEP COM AM335x on AQUILA Expansion";
12 compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
Enric Balletbo i Serra0710b672013-11-26 15:03:38 -0800[diff] [blame]13
14 hdmi {
15 compatible = "ti,tilcdc,slave";
16 i2c = <&i2c0>;
17 pinctrl-names = "default", "off";
18 pinctrl-0 = <&nxp_hdmi_pins>;
19 pinctrl-1 = <&nxp_hdmi_off_pins>;
20 status = "okay";
21 };
Enric Balletbo i Serraf3689fd2013-11-26 15:03:38 -0800[diff] [blame]22
23 leds_base {
24 pinctrl-names = "default";
25 pinctrl-0 = <&leds_base_pins>;
26
27 compatible = "gpio-leds";
28
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -0400[diff] [blame]29 led0 {
Enric Balletbo i Serraf3689fd2013-11-26 15:03:38 -0800[diff] [blame]30 label = "base:red:user";
31 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */
32 default-state = "off";
33 };
34
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -0400[diff] [blame]35 led1 {
Enric Balletbo i Serraf3689fd2013-11-26 15:03:38 -0800[diff] [blame]36 label = "base:green:user";
37 gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */
38 default-state = "off";
39 };
40 };
Enric Balletbo i Serra0710b672013-11-26 15:03:38 -0800[diff] [blame]41};
42
43&am33xx_pinmux {
44 nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
45 pinctrl-single,pins = <
Christina Quast0b119fa2019-04-09 18:03:37 +0200[diff] [blame]46 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */
47 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
48 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
49 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
50 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
51 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
52 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
53 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
54 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
55 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
56 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
57 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
58 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
59 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
60 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
61 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
62 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
63 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
64 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
65 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
66 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
Enric Balletbo i Serra0710b672013-11-26 15:03:38 -0800[diff] [blame]67 >;
68 };
69 nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
70 pinctrl-single,pins = <
Christina Quast0b119fa2019-04-09 18:03:37 +0200[diff] [blame]71 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */
Enric Balletbo i Serra0710b672013-11-26 15:03:38 -0800[diff] [blame]72 >;
73 };
Enric Balletbo i Serraf3689fd2013-11-26 15:03:38 -0800[diff] [blame]74
75 leds_base_pins: pinmux_leds_base_pins {
76 pinctrl-single,pins = <
Christina Quast0b119fa2019-04-09 18:03:37 +0200[diff] [blame]77 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
78 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */
Enric Balletbo i Serraf3689fd2013-11-26 15:03:38 -0800[diff] [blame]79 >;
80 };
Enric Balletbo i Serra0710b672013-11-26 15:03:38 -0800[diff] [blame]81};
82
83&lcdc {
84 status = "okay";
Enric Balletbo i Serra5cda1622013-09-10 16:55:49 +0200[diff] [blame]85};
Enric Balletbo i Serrad8e5b2b2013-11-26 15:03:38 -0800[diff] [blame]86
87&i2c0 {
88 eeprom: eeprom@50 {
Javier Martinez Canillas05e7d622017-05-23 15:34:31 +0200[diff] [blame]89 compatible = "atmel,24c256";
Enric Balletbo i Serrad8e5b2b2013-11-26 15:03:38 -0800[diff] [blame]90 reg = <0x50>;
91 };
92};