| Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| Lokesh Vutla | 148127d | 2017-08-12 09:36:04 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ |
| Lokesh Vutla | 148127d | 2017-08-12 09:36:04 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include "dra74x.dtsi" |
| 7 | |
| 8 | / { |
| 9 | compatible = "ti,dra762", "ti,dra7"; |
| 10 | |
| Faiz Abbas | 09a070a | 2018-07-10 04:05:30 -0700 | [diff] [blame] | 11 | ocp { |
| 12 | target-module@42c01900 { |
| 13 | compatible = "ti,sysc-dra7-mcan", "ti,sysc"; |
| 14 | ranges = <0x0 0x42c00000 0x2000>; |
| 15 | #address-cells = <1>; |
| 16 | #size-cells = <1>; |
| 17 | reg = <0x42c01900 0x4>, |
| 18 | <0x42c01904 0x4>, |
| 19 | <0x42c01908 0x4>; |
| 20 | reg-names = "rev", "sysc", "syss"; |
| 21 | ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | |
| 22 | SYSC_DRA7_MCAN_ENAWAKEUP)>; |
| 23 | ti,syss-mask = <1>; |
| Tero Kristo | b5f8ffb | 2018-08-31 18:14:51 +0300 | [diff] [blame] | 24 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; |
| Faiz Abbas | 09a070a | 2018-07-10 04:05:30 -0700 | [diff] [blame] | 25 | clock-names = "fck"; |
| Faiz Abbas | 0adbe83 | 2018-07-10 04:05:30 -0700 | [diff] [blame] | 26 | |
| 27 | m_can0: mcan@1a00 { |
| 28 | compatible = "bosch,m_can"; |
| 29 | reg = <0x1a00 0x4000>, <0x0 0x18FC>; |
| 30 | reg-names = "m_can", "message_ram"; |
| 31 | interrupt-parent = <&gic>; |
| 32 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| 33 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| 34 | interrupt-names = "int0", "int1"; |
| 35 | clocks = <&mcan_clk>, <&l3_iclk_div>; |
| 36 | clock-names = "cclk", "hclk"; |
| 37 | bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; |
| 38 | }; |
| Faiz Abbas | 09a070a | 2018-07-10 04:05:30 -0700 | [diff] [blame] | 39 | }; |
| 40 | }; |
| 41 | |
| Lokesh Vutla | 148127d | 2017-08-12 09:36:04 +0530 | [diff] [blame] | 42 | }; |
| 43 | |
| 44 | /* MCAN interrupts are hard-wired to irqs 67, 68 */ |
| 45 | &crossbar_mpu { |
| 46 | ti,irqs-skip = <10 67 68 133 139 140>; |
| 47 | }; |
| Lokesh Vutla | 6ae8d5c | 2018-07-10 04:05:30 -0700 | [diff] [blame] | 48 | |
| 49 | &scm_conf_clocks { |
| 50 | dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { |
| 51 | #clock-cells = <0>; |
| 52 | compatible = "ti,divider-clock"; |
| 53 | clocks = <&dpll_gmac_x2_ck>; |
| 54 | ti,max-div = <63>; |
| 55 | reg = <0x03fc>; |
| 56 | ti,bit-shift=<20>; |
| 57 | ti,latch-bit=<26>; |
| 58 | assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; |
| 59 | assigned-clock-rates = <80000000>; |
| 60 | }; |
| 61 | |
| 62 | dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { |
| 63 | #clock-cells = <0>; |
| 64 | compatible = "ti,mux-clock"; |
| 65 | clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; |
| 66 | reg = <0x3fc>; |
| 67 | ti,bit-shift = <29>; |
| 68 | ti,latch-bit=<26>; |
| 69 | assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; |
| 70 | assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; |
| 71 | }; |
| 72 | |
| 73 | mcan_clk: mcan_clk@3fc { |
| 74 | #clock-cells = <0>; |
| 75 | compatible = "ti,gate-clock"; |
| 76 | clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; |
| 77 | ti,bit-shift = <27>; |
| 78 | reg = <0x3fc>; |
| 79 | }; |
| 80 | }; |