blob: 0b1f6799a32eac271d08f75fecff59e9ece6099e [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Russell King002547b2006-06-20 20:46:52 +01002/*
Russell King4baa9922008-08-02 10:55:55 +01003 * arch/arm/include/asm/pgtable-nommu.h
Russell King002547b2006-06-20 20:46:52 +01004 *
5 * Copyright (C) 1995-2002 Russell King
6 * Copyright (C) 2004 Hyok S. Choi
Russell King002547b2006-06-20 20:46:52 +01007 */
8#ifndef _ASMARM_PGTABLE_NOMMU_H
9#define _ASMARM_PGTABLE_NOMMU_H
10
11#ifndef __ASSEMBLY__
12
Russell King002547b2006-06-20 20:46:52 +010013#include <linux/slab.h>
14#include <asm/processor.h>
15#include <asm/page.h>
Russell King002547b2006-06-20 20:46:52 +010016
17/*
18 * Trivial page table functions.
19 */
20#define pgd_present(pgd) (1)
21#define pgd_none(pgd) (0)
22#define pgd_bad(pgd) (0)
23#define pgd_clear(pgdp)
24#define kern_addr_valid(addr) (1)
25#define pmd_offset(a, b) ((void *)0)
26/* FIXME */
27/*
28 * PMD_SHIFT determines the size of the area a second-level page table can map
29 * PGDIR_SHIFT determines what a third-level page table entry can map
30 */
31#define PGDIR_SHIFT 21
32
33#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
34#define PGDIR_MASK (~(PGDIR_SIZE-1))
35/* FIXME */
36
37#define PAGE_NONE __pgprot(0)
38#define PAGE_SHARED __pgprot(0)
39#define PAGE_COPY __pgprot(0)
40#define PAGE_READONLY __pgprot(0)
41#define PAGE_KERNEL __pgprot(0)
42
Russell King002547b2006-06-20 20:46:52 +010043#define swapper_pg_dir ((pgd_t *) 0)
44
45#define __swp_type(x) (0)
46#define __swp_offset(x) (0)
47#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
48#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
49#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
50
51
52typedef pte_t *pte_addr_t;
53
Russell King002547b2006-06-20 20:46:52 +010054/*
55 * ZERO_PAGE is a global shared page that is always zero: used
56 * for zero-mapped memory areas etc..
57 */
58#define ZERO_PAGE(vaddr) (virt_to_page(0))
59
60/*
61 * Mark the prot value as uncacheable and unbufferable.
62 */
Arnd Bergmanne2fce0a2017-02-02 13:30:40 +010063#define pgprot_noncached(prot) (prot)
64#define pgprot_writecombine(prot) (prot)
65#define pgprot_dmacoherent(prot) (prot)
Vladimir Murzin7ef47832017-05-24 10:30:18 +010066#define pgprot_device(prot) (prot)
Russell King002547b2006-06-20 20:46:52 +010067
68
69/*
70 * These would be in other places but having them here reduces the diffs.
71 */
72extern unsigned int kobjsize(const void *objp);
Russell King002547b2006-06-20 20:46:52 +010073
74/*
75 * No page table caches to initialise.
76 */
77#define pgtable_cache_init() do { } while (0)
Russell King002547b2006-06-20 20:46:52 +010078
79/*
80 * All 32bit addresses are effectively valid for vmalloc...
81 * Sort of meaningless for non-VM targets.
82 */
Fenkart/Bostandzhyanc931b4f2010-02-07 21:47:17 +010083#define VMALLOC_START 0UL
84#define VMALLOC_END 0xffffffffUL
Russell King002547b2006-06-20 20:46:52 +010085
Kirill A. Shutemovd016bf72015-02-11 15:26:41 -080086#define FIRST_USER_ADDRESS 0UL
Russell King002547b2006-06-20 20:46:52 +010087
Greg Ungerer92df7852008-03-05 06:59:14 +010088#include <asm-generic/pgtable.h>
89
Russell King002547b2006-06-20 20:46:52 +010090#else
91
92/*
93 * dummy tlb and user structures.
94 */
95#define v3_tlb_fns (0)
96#define v4_tlb_fns (0)
97#define v4wb_tlb_fns (0)
98#define v4wbi_tlb_fns (0)
Catalin Marinas7b4c9652007-07-20 11:42:57 +010099#define v6wbi_tlb_fns (0)
Catalin Marinas2eb8c822007-07-20 11:43:02 +0100100#define v7wbi_tlb_fns (0)
Russell King002547b2006-06-20 20:46:52 +0100101
102#define v3_user_fns (0)
103#define v4_user_fns (0)
104#define v4_mc_user_fns (0)
105#define v4wb_user_fns (0)
106#define v4wt_user_fns (0)
107#define v6_user_fns (0)
108#define xscale_mc_user_fns (0)
109
110#endif /*__ASSEMBLY__*/
111
112#endif /* _ASMARM_PGTABLE_H */