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gerrit-public.fairphone.software / kernel / msm-5.4 / d2912cb15bdda8ba4a5dd73396ad62641af2f520 / . / arch / arm / mach-omap2 / prcm_mpu44xx.h
blob: ff3484b04365ffa7fda810843c7eee3eca013aff [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]2/*
3 * OMAP44xx PRCM MPU instance offset macros
4 *
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600[diff] [blame]5 * Copyright (C) 2010, 2012 Texas Instruments, Inc.
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]6 * Copyright (C) 2010 Nokia Corporation
7 *
8 * Paul Walmsley (paul@pwsan.com)
9 * Rajendra Nayak (rnayak@ti.com)
10 * Benoit Cousson (b-cousson@ti.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]18 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
19 * or "OMAP4430".
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
24
Santosh Shilimkar40243ad2013-05-29 12:38:05 -0400[diff] [blame]25#include "prcm_mpu_44xx_54xx.h"
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600[diff] [blame]26
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]27#define OMAP4430_PRCM_MPU_BASE 0x48243000
28
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]29#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]31
32/* PRCM_MPU instances */
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]33#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
34#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
35#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
36#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]37
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]38/* PRCM_MPU clockdomain register offsets (from instance start) */
Benoit Cousson1a9f5e82011-02-08 14:30:31 -0700[diff] [blame]39#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
40#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]41
42
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]43/*
44 * PRCM_MPU
45 *
46 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
47 * point of view the PRCM_MPU is a single entity. It shares the same
48 * programming model as the global PRCM and thus can be assimilate as two new
49 * MOD inside the PRCM
50 */
51
52/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
Benoit Coussona3b90ad2011-07-09 19:15:06 -0600[diff] [blame]53#define OMAP4_REVISION_PRCM_OFFSET 0x0000
54#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]55
56/* PRCM_MPU.DEVICE_PRM register offsets */
Benoit Coussona3b90ad2011-07-09 19:15:06 -0600[diff] [blame]57#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
58#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
59#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
60#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]61
62/* PRCM_MPU.CPU0 register offsets */
Benoit Coussona3b90ad2011-07-09 19:15:06 -0600[diff] [blame]63#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
64#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
65#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
66#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
67#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
68#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
69#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
70#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
71#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
72#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
73#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
74#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
75#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
76#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]77
78/* PRCM_MPU.CPU1 register offsets */
Benoit Coussona3b90ad2011-07-09 19:15:06 -0600[diff] [blame]79#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
80#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
81#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
82#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
83#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
84#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
85#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
86#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
87#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
88#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
89#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
90#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
91#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
92#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]93
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]94#endif