| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 1 | /* | 
 | 2 |  * AM33XX PRM_XXX register bits | 
 | 3 |  * | 
 | 4 |  * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | 
 | 5 |  * | 
 | 6 |  * This program is free software; you can redistribute it and/or | 
 | 7 |  * modify it under the terms of the GNU General Public License as | 
 | 8 |  * published by the Free Software Foundation version 2. | 
 | 9 |  * | 
 | 10 |  * This program is distributed "as is" WITHOUT ANY WARRANTY of any | 
 | 11 |  * kind, whether express or implied; without even the implied warranty | 
 | 12 |  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | 
 | 13 |  * GNU General Public License for more details. | 
 | 14 |  */ | 
 | 15 |  | 
 | 16 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H | 
 | 17 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H | 
 | 18 |  | 
 | 19 | #include "prm.h" | 
 | 20 |  | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 21 | #define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 22 | #define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 23 | #define AM33XX_GFX_MEM_STATEST_MASK			(0x3 << 4) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 24 | #define AM33XX_GLOBAL_WARM_SW_RST_MASK			(1 << 1) | 
| Tony Lindgren | 7323f21 | 2013-08-28 22:24:13 -0700 | [diff] [blame] | 25 | #define AM33XX_RST_GLOBAL_WARM_SW_MASK			(1 << 0) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 26 | #define AM33XX_PRUSS_MEM_ONSTATE_MASK			(0x3 << 5) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 27 | #define AM33XX_PRUSS_MEM_RETSTATE_MASK			(1 << 7) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 28 | #define AM33XX_PRUSS_MEM_STATEST_MASK			(0x3 << 23) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 29 | #define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24 | 
 | 30 | #define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 31 | #define AM33XX_LOGICRETSTATE_MASK			(1 << 2) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 32 | #define AM33XX_LOGICRETSTATE_3_3_MASK			(1 << 3) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 33 | #define AM33XX_LOGICSTATEST_SHIFT			2 | 
 | 34 | #define AM33XX_LOGICSTATEST_MASK			(1 << 2) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 35 | #define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4 | 
 | 36 | #define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 37 | #define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 38 | #define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 39 | #define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 40 | #define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 41 | #define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 42 | #define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 43 | #define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 44 | #define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 45 | #define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 46 | #define AM33XX_PER_MEM_ONSTATE_MASK			(0x3 << 25) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 47 | #define AM33XX_PER_MEM_RETSTATE_MASK			(1 << 29) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 48 | #define AM33XX_PER_MEM_STATEST_MASK			(0x3 << 17) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 49 | #define AM33XX_RAM_MEM_ONSTATE_MASK			(0x3 << 30) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 50 | #define AM33XX_RAM_MEM_RETSTATE_MASK			(1 << 27) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 51 | #define AM33XX_RAM_MEM_STATEST_MASK			(0x3 << 21) | 
| Vaibhav Hiremath | ddd04b9 | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 52 | #endif |