blob: 32a3b7c5b8dc2defd0f6891e3bb466ee24ad7312 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Max Filippove85e3352012-12-03 15:01:43 +04002/*
3 * linux/arch/xtensa/boot/boot-elf/boot.lds.S
4 *
5 * Copyright (C) 2008 - 2013 by Tensilica Inc.
6 *
7 * Chris Zankel <chris@zankel.net>
8 * Marc Gauthier <marc@tensilica.com
9 * Pete Delaney <piet@tensilica.com>
Max Filippove85e3352012-12-03 15:01:43 +040010 */
11
12#include <asm/vectors.h>
Chris Zankel4bedea92005-06-23 22:01:12 -070013OUTPUT_ARCH(xtensa)
Marc Gauthiered3174d2007-10-23 16:40:24 -070014ENTRY(_ResetVector)
Chris Zankel4bedea92005-06-23 22:01:12 -070015
16SECTIONS
17{
Max Filippove85e3352012-12-03 15:01:43 +040018 .ResetVector.text XCHAL_RESET_VECTOR_VADDR :
Chris Zankel4bedea92005-06-23 22:01:12 -070019 {
Max Filippove85e3352012-12-03 15:01:43 +040020 *(.ResetVector.text)
Chris Zankel4bedea92005-06-23 22:01:12 -070021 }
22
Max Filippova9f2fc62016-04-13 05:20:02 +030023 .image KERNELOFFSET: AT (CONFIG_KERNEL_LOAD_ADDRESS)
Chris Zankel4bedea92005-06-23 22:01:12 -070024 {
25 _image_start = .;
26 *(image)
27 . = (. + 3) & ~ 3;
28 _image_end = . ;
29 }
30
Chris Zankel4bedea92005-06-23 22:01:12 -070031 .bss ((LOADADDR(.image) + SIZEOF(.image) + 3) & ~ 3):
32 {
33 __bss_start = .;
34 *(.sbss)
35 *(.scommon)
36 *(.dynbss)
37 *(.bss)
38 __bss_end = .;
39 }
Chris Zankel4bedea92005-06-23 22:01:12 -070040}