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Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001/*
Ivo van Doorn96481b22010-08-06 20:47:57 +02002 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
Gertjan van Wingerde9c9a0d12009-11-08 16:39:55 +01003 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020010 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020034#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/eeprom_93cx6.h>
42
43#include "rt2x00.h"
44#include "rt2x00pci.h"
45#include "rt2x00soc.h"
Bartlomiej Zolnierkiewicz7ef5cc92009-11-04 18:35:32 +010046#include "rt2800lib.h"
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +010047#include "rt2800.h"
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020048#include "rt2800pci.h"
49
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020050/*
51 * Allow hardware encryption to be disabled.
52 */
Rusty Russelleb939922011-12-19 14:08:01 +000053static bool modparam_nohwcrypt = false;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020054module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
Gertjan van Wingerdead417a52012-09-03 03:25:51 +020057static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
58{
59 return modparam_nohwcrypt;
60}
61
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020062static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
63{
64 unsigned int i;
65 u32 reg;
66
Luis Correiaf18d4462010-04-03 12:49:53 +010067 /*
68 * SOC devices don't support MCU requests.
69 */
70 if (rt2x00_is_soc(rt2x00dev))
71 return;
72
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020073 for (i = 0; i < 200; i++) {
Helmut Schaa9a819992011-04-18 15:34:01 +020074 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020075
76 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
77 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
80 break;
81
82 udelay(REGISTER_BUSY_DELAY);
83 }
84
85 if (i == 200)
86 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
87
Helmut Schaa9a819992011-04-18 15:34:01 +020088 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
89 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020090}
91
John Crispin5818a462013-03-13 13:20:15 +010092#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
Gabor Juhosa02308e2012-12-29 14:51:51 +010093static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020094{
Gertjan van Wingerdeef8397c2010-11-13 19:11:22 +010095 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +020096
Gabor Juhosa02308e2012-12-29 14:51:51 +010097 if (!base_addr)
98 return -ENOMEM;
99
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200100 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
Gertjan van Wingerdeef8397c2010-11-13 19:11:22 +0100101
102 iounmap(base_addr);
Gabor Juhosa02308e2012-12-29 14:51:51 +0100103 return 0;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200104}
105#else
Gabor Juhosa02308e2012-12-29 14:51:51 +0100106static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200107{
Gabor Juhosa02308e2012-12-29 14:51:51 +0100108 return -ENOMEM;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200109}
John Crispin5818a462013-03-13 13:20:15 +0100110#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200111
Gertjan van Wingerde72c72962010-11-13 19:10:54 +0100112#ifdef CONFIG_PCI
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200113static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
114{
115 struct rt2x00_dev *rt2x00dev = eeprom->data;
116 u32 reg;
117
Helmut Schaa9a819992011-04-18 15:34:01 +0200118 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200119
120 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
121 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
122 eeprom->reg_data_clock =
123 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
124 eeprom->reg_chip_select =
125 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
126}
127
128static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
129{
130 struct rt2x00_dev *rt2x00dev = eeprom->data;
131 u32 reg = 0;
132
133 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
134 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
135 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
136 !!eeprom->reg_data_clock);
137 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
138 !!eeprom->reg_chip_select);
139
Helmut Schaa9a819992011-04-18 15:34:01 +0200140 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200141}
142
Gabor Juhosa02308e2012-12-29 14:51:51 +0100143static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200144{
145 struct eeprom_93cx6 eeprom;
146 u32 reg;
147
Helmut Schaa9a819992011-04-18 15:34:01 +0200148 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200149
150 eeprom.data = rt2x00dev;
151 eeprom.register_read = rt2800pci_eepromregister_read;
152 eeprom.register_write = rt2800pci_eepromregister_write;
Gertjan van Wingerde20f8b132010-06-29 21:44:18 +0200153 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
154 {
155 case 0:
156 eeprom.width = PCI_EEPROM_WIDTH_93C46;
157 break;
158 case 1:
159 eeprom.width = PCI_EEPROM_WIDTH_93C66;
160 break;
161 default:
162 eeprom.width = PCI_EEPROM_WIDTH_93C86;
163 break;
164 }
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200165 eeprom.reg_data_in = 0;
166 eeprom.reg_data_out = 0;
167 eeprom.reg_data_clock = 0;
168 eeprom.reg_chip_select = 0;
169
170 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
171 EEPROM_SIZE / sizeof(u16));
Gabor Juhosa02308e2012-12-29 14:51:51 +0100172
173 return 0;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200174}
175
Gertjan van Wingerdea6598682009-11-08 12:30:35 +0100176static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
177{
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +0100178 return rt2800_efuse_detect(rt2x00dev);
Gertjan van Wingerdea6598682009-11-08 12:30:35 +0100179}
180
Gabor Juhosa02308e2012-12-29 14:51:51 +0100181static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200182{
Gabor Juhosa02308e2012-12-29 14:51:51 +0100183 return rt2800_read_eeprom_efuse(rt2x00dev);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200184}
185#else
Gabor Juhosa02308e2012-12-29 14:51:51 +0100186static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200187{
Gabor Juhosa02308e2012-12-29 14:51:51 +0100188 return -EOPNOTSUPP;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200189}
190
Gertjan van Wingerdea6598682009-11-08 12:30:35 +0100191static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
192{
193 return 0;
194}
195
Gabor Juhosa02308e2012-12-29 14:51:51 +0100196static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200197{
Gabor Juhosa02308e2012-12-29 14:51:51 +0100198 return -EOPNOTSUPP;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200199}
Gertjan van Wingerde72c72962010-11-13 19:10:54 +0100200#endif /* CONFIG_PCI */
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200201
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200202/*
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100203 * Queue handlers.
204 */
205static void rt2800pci_start_queue(struct data_queue *queue)
206{
207 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
208 u32 reg;
209
210 switch (queue->qid) {
211 case QID_RX:
Helmut Schaa9a819992011-04-18 15:34:01 +0200212 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100213 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
Helmut Schaa9a819992011-04-18 15:34:01 +0200214 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100215 break;
216 case QID_BEACON:
Helmut Schaa9a819992011-04-18 15:34:01 +0200217 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100218 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
219 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
220 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
Helmut Schaa9a819992011-04-18 15:34:01 +0200221 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
Helmut Schaa69cf36a2011-01-30 13:16:03 +0100222
Helmut Schaa9a819992011-04-18 15:34:01 +0200223 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
Helmut Schaa69cf36a2011-01-30 13:16:03 +0100224 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
Helmut Schaa9a819992011-04-18 15:34:01 +0200225 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100226 break;
227 default:
228 break;
Joe Perches6403eab2011-06-03 11:51:20 +0000229 }
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100230}
231
232static void rt2800pci_kick_queue(struct data_queue *queue)
233{
234 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
235 struct queue_entry *entry;
236
237 switch (queue->qid) {
Ivo van Doornf615e9a2010-12-13 12:36:38 +0100238 case QID_AC_VO:
239 case QID_AC_VI:
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100240 case QID_AC_BE:
241 case QID_AC_BK:
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100242 entry = rt2x00queue_get_entry(queue, Q_INDEX);
Helmut Schaa9a819992011-04-18 15:34:01 +0200243 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
244 entry->entry_idx);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100245 break;
246 case QID_MGMT:
247 entry = rt2x00queue_get_entry(queue, Q_INDEX);
Helmut Schaa9a819992011-04-18 15:34:01 +0200248 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
249 entry->entry_idx);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100250 break;
251 default:
252 break;
253 }
254}
255
256static void rt2800pci_stop_queue(struct data_queue *queue)
257{
258 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
259 u32 reg;
260
261 switch (queue->qid) {
262 case QID_RX:
Helmut Schaa9a819992011-04-18 15:34:01 +0200263 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100264 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
Helmut Schaa9a819992011-04-18 15:34:01 +0200265 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100266 break;
267 case QID_BEACON:
Helmut Schaa9a819992011-04-18 15:34:01 +0200268 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100269 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
270 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
271 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
Helmut Schaa9a819992011-04-18 15:34:01 +0200272 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
Helmut Schaa69cf36a2011-01-30 13:16:03 +0100273
Helmut Schaa9a819992011-04-18 15:34:01 +0200274 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
Helmut Schaa69cf36a2011-01-30 13:16:03 +0100275 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
Helmut Schaa9a819992011-04-18 15:34:01 +0200276 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100277
278 /*
Helmut Schaaabc11992011-08-06 13:13:48 +0200279 * Wait for current invocation to finish. The tasklet
280 * won't be scheduled anymore afterwards since we disabled
281 * the TBTT and PRE TBTT timer.
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100282 */
Helmut Schaaabc11992011-08-06 13:13:48 +0200283 tasklet_kill(&rt2x00dev->tbtt_tasklet);
284 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
285
Ivo van Doorn5450b7e2010-12-13 12:34:22 +0100286 break;
287 default:
288 break;
289 }
290}
291
292/*
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200293 * Firmware functions
294 */
295static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
296{
Woody Hunga89534e2012-06-13 15:01:16 +0800297 /*
298 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
299 */
300 if (rt2x00_rt(rt2x00dev, RT3290))
301 return FIRMWARE_RT3290;
302 else
303 return FIRMWARE_RT2860;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200304}
305
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200306static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200307 const u8 *data, const size_t len)
308{
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200309 u32 reg;
310
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200311 /*
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200312 * enable Host program ram write selection
313 */
314 reg = 0;
315 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
Helmut Schaa9a819992011-04-18 15:34:01 +0200316 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200317
318 /*
319 * Write firmware to device.
320 */
Ivo van Doornd4c838e2011-04-30 17:14:49 +0200321 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
322 data, len);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200323
Helmut Schaa9a819992011-04-18 15:34:01 +0200324 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
325 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200326
Helmut Schaa9a819992011-04-18 15:34:01 +0200327 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
328 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200329
330 return 0;
331}
332
333/*
334 * Initialization functions.
335 */
336static bool rt2800pci_get_entry_state(struct queue_entry *entry)
337{
338 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
339 u32 word;
340
341 if (entry->queue->qid == QID_RX) {
342 rt2x00_desc_read(entry_priv->desc, 1, &word);
343
344 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
345 } else {
346 rt2x00_desc_read(entry_priv->desc, 1, &word);
347
348 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
349 }
350}
351
352static void rt2800pci_clear_entry(struct queue_entry *entry)
353{
354 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
355 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
Helmut Schaa95192332010-10-02 11:29:30 +0200356 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200357 u32 word;
358
359 if (entry->queue->qid == QID_RX) {
360 rt2x00_desc_read(entry_priv->desc, 0, &word);
361 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
362 rt2x00_desc_write(entry_priv->desc, 0, word);
363
364 rt2x00_desc_read(entry_priv->desc, 1, &word);
365 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
366 rt2x00_desc_write(entry_priv->desc, 1, word);
Helmut Schaa95192332010-10-02 11:29:30 +0200367
368 /*
369 * Set RX IDX in register to inform hardware that we have
370 * handled this entry and it is available for reuse again.
371 */
Helmut Schaa9a819992011-04-18 15:34:01 +0200372 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
Helmut Schaa95192332010-10-02 11:29:30 +0200373 entry->entry_idx);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200374 } else {
375 rt2x00_desc_read(entry_priv->desc, 1, &word);
376 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
377 rt2x00_desc_write(entry_priv->desc, 1, word);
378 }
379}
380
381static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
382{
383 struct queue_entry_priv_pci *entry_priv;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200384
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200385 /*
386 * Initialize registers.
387 */
388 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
Helmut Schaa9a819992011-04-18 15:34:01 +0200389 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
390 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
391 rt2x00dev->tx[0].limit);
392 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
393 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200394
395 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
Helmut Schaa9a819992011-04-18 15:34:01 +0200396 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
397 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
398 rt2x00dev->tx[1].limit);
399 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
400 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200401
402 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
Helmut Schaa9a819992011-04-18 15:34:01 +0200403 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
404 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
405 rt2x00dev->tx[2].limit);
406 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
407 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200408
409 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
Helmut Schaa9a819992011-04-18 15:34:01 +0200410 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
411 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
412 rt2x00dev->tx[3].limit);
413 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
414 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200415
Jakub Kicinski3a4b43f2012-04-03 03:40:50 +0200416 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
417 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
418 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
419 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
420
421 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
422 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
423 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
424 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
425
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200426 entry_priv = rt2x00dev->rx->entries[0].priv_data;
Helmut Schaa9a819992011-04-18 15:34:01 +0200427 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
428 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
429 rt2x00dev->rx[0].limit);
430 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
431 rt2x00dev->rx[0].limit - 1);
432 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200433
Jakub Kicinskif7b395e2012-04-03 03:40:47 +0200434 rt2800_disable_wpdma(rt2x00dev);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200435
Helmut Schaa9a819992011-04-18 15:34:01 +0200436 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200437
438 return 0;
439}
440
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200441/*
442 * Device state switch handlers.
443 */
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200444static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
445 enum dev_state state)
446{
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200447 u32 reg;
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100448 unsigned long flags;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200449
450 /*
451 * When interrupts are being enabled, the interrupt registers
452 * should clear the register to assure a clean state.
453 */
454 if (state == STATE_RADIO_IRQ_ON) {
Helmut Schaa9a819992011-04-18 15:34:01 +0200455 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
456 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100457 }
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200458
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100459 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
Stanislaw Gruszkadfd00c42012-01-13 12:59:32 +0100460 reg = 0;
461 if (state == STATE_RADIO_IRQ_ON) {
462 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
463 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
464 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
465 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
466 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
467 }
Helmut Schaa9a819992011-04-18 15:34:01 +0200468 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100469 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
470
471 if (state == STATE_RADIO_IRQ_OFF) {
472 /*
Helmut Schaaabc11992011-08-06 13:13:48 +0200473 * Wait for possibly running tasklets to finish.
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100474 */
Helmut Schaaabc11992011-08-06 13:13:48 +0200475 tasklet_kill(&rt2x00dev->txstatus_tasklet);
476 tasklet_kill(&rt2x00dev->rxdone_tasklet);
477 tasklet_kill(&rt2x00dev->autowake_tasklet);
478 tasklet_kill(&rt2x00dev->tbtt_tasklet);
479 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100480 }
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200481}
482
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +0200483static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
484{
485 u32 reg;
486
487 /*
488 * Reset DMA indexes
489 */
Helmut Schaa9a819992011-04-18 15:34:01 +0200490 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +0200491 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
492 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
493 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
494 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
495 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
496 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
Helmut Schaa9a819992011-04-18 15:34:01 +0200498 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +0200499
Helmut Schaa9a819992011-04-18 15:34:01 +0200500 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +0200502
Gertjan van Wingerde872834d2011-05-18 20:25:31 +0200503 if (rt2x00_is_pcie(rt2x00dev) &&
504 (rt2x00_rt(rt2x00dev, RT3572) ||
John Li2ed71882012-02-17 17:33:06 +0800505 rt2x00_rt(rt2x00dev, RT5390) ||
506 rt2x00_rt(rt2x00dev, RT5392))) {
Helmut Schaa9a819992011-04-18 15:34:01 +0200507 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
Gabor Juhosadde5882011-03-03 11:46:45 +0100508 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
509 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
Helmut Schaa9a819992011-04-18 15:34:01 +0200510 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
Gabor Juhosadde5882011-03-03 11:46:45 +0100511 }
RA-Shiang Tu60687ba2011-02-20 13:57:46 +0100512
Helmut Schaa9a819992011-04-18 15:34:01 +0200513 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +0200514
Stanislaw Gruszka2a48e8a2012-01-24 14:09:08 +0100515 reg = 0;
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +0200516 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
517 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
Helmut Schaa9a819992011-04-18 15:34:01 +0200518 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +0200519
Helmut Schaa9a819992011-04-18 15:34:01 +0200520 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +0200521
522 return 0;
523}
524
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200525static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
526{
Jakub Kicinskie8b461c2012-02-22 21:58:58 +0100527 int retval;
528
Jakub Kicinski52b82432012-04-03 03:40:49 +0200529 /* Wait for DMA, ignore error until we initialize queues. */
530 rt2800_wait_wpdma_ready(rt2x00dev);
531
532 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200533 return -EIO;
534
Jakub Kicinskie8b461c2012-02-22 21:58:58 +0100535 retval = rt2800_enable_radio(rt2x00dev);
536 if (retval)
537 return retval;
538
539 /* After resume MCU_BOOT_SIGNAL will trash these. */
540 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
541 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
542
543 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
544 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
545
546 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
547 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
548
549 return retval;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200550}
551
552static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
553{
RA-Jay Hung7f6e1442011-01-10 11:27:43 +0100554 if (rt2x00_is_soc(rt2x00dev)) {
555 rt2800_disable_radio(rt2x00dev);
Helmut Schaa9a819992011-04-18 15:34:01 +0200556 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
557 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
RA-Jay Hung7f6e1442011-01-10 11:27:43 +0100558 }
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200559}
560
561static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
562 enum dev_state state)
563{
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200564 if (state == STATE_AWAKE) {
Jakub Kicinski09a33112012-02-22 21:58:57 +0100565 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
566 0, 0x02);
567 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
RA-Jay Hung7f6e1442011-01-10 11:27:43 +0100568 } else if (state == STATE_SLEEP) {
Helmut Schaa9a819992011-04-18 15:34:01 +0200569 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
570 0xffffffff);
571 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
572 0xffffffff);
Jakub Kicinski09a33112012-02-22 21:58:57 +0100573 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
574 0xff, 0x01);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200575 }
576
577 return 0;
578}
579
580static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
581 enum dev_state state)
582{
583 int retval = 0;
584
585 switch (state) {
586 case STATE_RADIO_ON:
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200587 retval = rt2800pci_enable_radio(rt2x00dev);
588 break;
589 case STATE_RADIO_OFF:
590 /*
591 * After the radio has been disabled, the device should
592 * be put to sleep for powersaving.
593 */
594 rt2800pci_disable_radio(rt2x00dev);
595 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
596 break;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200597 case STATE_RADIO_IRQ_ON:
598 case STATE_RADIO_IRQ_OFF:
599 rt2800pci_toggle_irq(rt2x00dev, state);
600 break;
601 case STATE_DEEP_SLEEP:
602 case STATE_SLEEP:
603 case STATE_STANDBY:
604 case STATE_AWAKE:
605 retval = rt2800pci_set_state(rt2x00dev, state);
606 break;
607 default:
608 retval = -ENOTSUPP;
609 break;
610 }
611
612 if (unlikely(retval))
613 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
614 state, retval);
615
616 return retval;
617}
618
619/*
620 * TX descriptor initialization
621 */
Ivo van Doorn0c5879b2010-08-06 20:47:20 +0200622static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200623{
Ivo van Doorn0c5879b2010-08-06 20:47:20 +0200624 return (__le32 *) entry->skb->data;
Helmut Schaa745b1ae2010-04-15 09:13:35 +0200625}
626
Ivo van Doorn93331452010-08-23 19:53:39 +0200627static void rt2800pci_write_tx_desc(struct queue_entry *entry,
Helmut Schaa745b1ae2010-04-15 09:13:35 +0200628 struct txentry_desc *txdesc)
629{
Ivo van Doorn93331452010-08-23 19:53:39 +0200630 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
631 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
Gertjan van Wingerde85b7a8b2010-05-11 23:51:40 +0200632 __le32 *txd = entry_priv->desc;
Helmut Schaa745b1ae2010-04-15 09:13:35 +0200633 u32 word;
634
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200635 /*
636 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
637 * must contains a TXWI structure + 802.11 header + padding + 802.11
638 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
639 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
640 * data. It means that LAST_SEC0 is always 0.
641 */
642
643 /*
644 * Initialize TX descriptor
645 */
Helmut Schaa3de3d962011-09-07 20:11:26 +0200646 word = 0;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200647 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
648 rt2x00_desc_write(txd, 0, word);
649
Helmut Schaa3de3d962011-09-07 20:11:26 +0200650 word = 0;
Ivo van Doorn93331452010-08-23 19:53:39 +0200651 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200652 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
653 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
654 rt2x00_set_field32(&word, TXD_W1_BURST,
655 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
Gertjan van Wingerde85b7a8b2010-05-11 23:51:40 +0200656 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200657 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
658 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
659 rt2x00_desc_write(txd, 1, word);
660
Helmut Schaa3de3d962011-09-07 20:11:26 +0200661 word = 0;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200662 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
Gertjan van Wingerde85b7a8b2010-05-11 23:51:40 +0200663 skbdesc->skb_dma + TXWI_DESC_SIZE);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200664 rt2x00_desc_write(txd, 2, word);
665
Helmut Schaa3de3d962011-09-07 20:11:26 +0200666 word = 0;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200667 rt2x00_set_field32(&word, TXD_W3_WIV,
668 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
669 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
670 rt2x00_desc_write(txd, 3, word);
Gertjan van Wingerde85b7a8b2010-05-11 23:51:40 +0200671
672 /*
673 * Register descriptor details in skb frame descriptor.
674 */
675 skbdesc->desc = txd;
676 skbdesc->desc_len = TXD_DESC_SIZE;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200677}
678
679/*
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200680 * RX control handlers
681 */
682static void rt2800pci_fill_rxdone(struct queue_entry *entry,
683 struct rxdone_entry_desc *rxdesc)
684{
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200685 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
686 __le32 *rxd = entry_priv->desc;
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200687 u32 word;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200688
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200689 rt2x00_desc_read(rxd, 3, &word);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200690
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200691 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200692 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
693
Gertjan van Wingerde78b8f3b2010-05-08 23:40:20 +0200694 /*
695 * Unfortunately we don't know the cipher type used during
696 * decryption. This prevents us from correct providing
697 * correct statistics through debugfs.
698 */
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200699 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200700
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200701 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200702 /*
703 * Hardware has stripped IV/EIV data from 802.11 frame during
704 * decryption. Unfortunately the descriptor doesn't contain
705 * any fields with the EIV/IV data either, so they can't
706 * be restored by rt2x00lib.
707 */
708 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
709
Gertjan van Wingerdea45f3692011-01-30 13:22:41 +0100710 /*
711 * The hardware has already checked the Michael Mic and has
712 * stripped it from the frame. Signal this to mac80211.
713 */
714 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
715
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200716 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
717 rxdesc->flags |= RX_FLAG_DECRYPTED;
718 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
719 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
720 }
721
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200722 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200723 rxdesc->dev_flags |= RXDONE_MY_BSS;
724
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200725 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200726 rxdesc->dev_flags |= RXDONE_L2PAD;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200727
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200728 /*
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200729 * Process the RXWI structure that is at the start of the buffer.
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200730 */
Ivo van Doorn74861922010-07-11 12:23:50 +0200731 rt2800_process_rxwi(entry, rxdesc);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200732}
733
734/*
735 * Interrupt functions.
736 */
Gertjan van Wingerde4d66edc2010-03-30 23:50:26 +0200737static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
738{
739 struct ieee80211_conf conf = { .flags = 0 };
740 struct rt2x00lib_conf libconf = { .conf = &conf };
741
742 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
743}
744
Helmut Schaa2e7798b2011-03-28 13:30:09 +0200745static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
Helmut Schaa96c3da72010-10-02 11:27:35 +0200746{
747 struct data_queue *queue;
748 struct queue_entry *entry;
749 u32 status;
750 u8 qid;
Helmut Schaa2e7798b2011-03-28 13:30:09 +0200751 int max_tx_done = 16;
Helmut Schaa96c3da72010-10-02 11:27:35 +0200752
Johannes Stezenbachc4d63242010-12-27 15:04:29 +0100753 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
Helmut Schaa12eec2c2010-10-09 13:35:48 +0200754 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
Helmut Schaa87443e82011-03-03 19:39:27 +0100755 if (unlikely(qid >= QID_RX)) {
Helmut Schaa96c3da72010-10-02 11:27:35 +0200756 /*
757 * Unknown queue, this shouldn't happen. Just drop
758 * this tx status.
759 */
760 WARNING(rt2x00dev, "Got TX status report with "
Johannes Stezenbach094a1d92010-12-13 12:34:00 +0100761 "unexpected pid %u, dropping\n", qid);
Helmut Schaa96c3da72010-10-02 11:27:35 +0200762 break;
763 }
764
Helmut Schaa11f818e2011-03-03 19:38:55 +0100765 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
Helmut Schaa96c3da72010-10-02 11:27:35 +0200766 if (unlikely(queue == NULL)) {
767 /*
768 * The queue is NULL, this shouldn't happen. Stop
769 * processing here and drop the tx status
770 */
771 WARNING(rt2x00dev, "Got TX status for an unavailable "
Johannes Stezenbach094a1d92010-12-13 12:34:00 +0100772 "queue %u, dropping\n", qid);
Helmut Schaa96c3da72010-10-02 11:27:35 +0200773 break;
774 }
775
Helmut Schaa87443e82011-03-03 19:39:27 +0100776 if (unlikely(rt2x00queue_empty(queue))) {
Helmut Schaa96c3da72010-10-02 11:27:35 +0200777 /*
778 * The queue is empty. Stop processing here
779 * and drop the tx status.
780 */
781 WARNING(rt2x00dev, "Got TX status for an empty "
Johannes Stezenbach094a1d92010-12-13 12:34:00 +0100782 "queue %u, dropping\n", qid);
Helmut Schaa96c3da72010-10-02 11:27:35 +0200783 break;
784 }
785
786 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
Helmut Schaa31937c42011-09-07 20:10:02 +0200787 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
Helmut Schaa2e7798b2011-03-28 13:30:09 +0200788
789 if (--max_tx_done == 0)
790 break;
Helmut Schaa96c3da72010-10-02 11:27:35 +0200791 }
Helmut Schaa2e7798b2011-03-28 13:30:09 +0200792
793 return !max_tx_done;
Helmut Schaa96c3da72010-10-02 11:27:35 +0200794}
795
Helmut Schaa7a5a6812011-04-18 15:31:31 +0200796static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
797 struct rt2x00_field32 irq_field)
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100798{
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100799 u32 reg;
800
801 /*
802 * Enable a single interrupt. The interrupt mask register
803 * access needs locking.
804 */
Helmut Schaa0aa13b22011-03-03 19:45:16 +0100805 spin_lock_irq(&rt2x00dev->irqmask_lock);
Helmut Schaa9a819992011-04-18 15:34:01 +0200806 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100807 rt2x00_set_field32(&reg, irq_field, 1);
Helmut Schaa9a819992011-04-18 15:34:01 +0200808 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
Helmut Schaa0aa13b22011-03-03 19:45:16 +0100809 spin_unlock_irq(&rt2x00dev->irqmask_lock);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100810}
811
Helmut Schaa96c3da72010-10-02 11:27:35 +0200812static void rt2800pci_txstatus_tasklet(unsigned long data)
813{
Helmut Schaa2e7798b2011-03-28 13:30:09 +0200814 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
815 if (rt2800pci_txdone(rt2x00dev))
816 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100817
818 /*
819 * No need to enable the tx status interrupt here as we always
820 * leave it enabled to minimize the possibility of a tx status
821 * register overflow. See comment in interrupt handler.
822 */
Helmut Schaa96c3da72010-10-02 11:27:35 +0200823}
824
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100825static void rt2800pci_pretbtt_tasklet(unsigned long data)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200826{
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100827 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
828 rt2x00lib_pretbtt(rt2x00dev);
Helmut Schaaabc11992011-08-06 13:13:48 +0200829 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
830 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100831}
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200832
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100833static void rt2800pci_tbtt_tasklet(unsigned long data)
834{
835 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
Helmut Schaa290d6082012-03-09 15:31:50 +0100836 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
837 u32 reg;
838
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100839 rt2x00lib_beacondone(rt2x00dev);
Helmut Schaa290d6082012-03-09 15:31:50 +0100840
841 if (rt2x00dev->intf_ap_count) {
842 /*
843 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
844 * causing beacon skew and as a result causing problems with
845 * some powersaving clients over time. Shorten the beacon
846 * interval every 64 beacons by 64us to mitigate this effect.
847 */
848 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
849 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
850 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
851 (rt2x00dev->beacon_int * 16) - 1);
852 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
853 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
854 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
855 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
856 (rt2x00dev->beacon_int * 16));
857 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
858 }
859 drv_data->tbtt_tick++;
860 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
861 }
862
Helmut Schaaabc11992011-08-06 13:13:48 +0200863 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
864 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100865}
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200866
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100867static void rt2800pci_rxdone_tasklet(unsigned long data)
868{
869 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
Helmut Schaa16638932011-03-28 13:29:44 +0200870 if (rt2x00pci_rxdone(rt2x00dev))
871 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
Helmut Schaaabc11992011-08-06 13:13:48 +0200872 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
Helmut Schaa16638932011-03-28 13:29:44 +0200873 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100874}
Helmut Schaaad903192010-06-29 21:46:43 +0200875
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100876static void rt2800pci_autowake_tasklet(unsigned long data)
877{
878 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
879 rt2800pci_wakeup(rt2x00dev);
Helmut Schaaabc11992011-08-06 13:13:48 +0200880 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
881 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200882}
883
Helmut Schaa96c3da72010-10-02 11:27:35 +0200884static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
885{
886 u32 status;
887 int i;
888
889 /*
890 * The TX_FIFO_STATUS interrupt needs special care. We should
891 * read TX_STA_FIFO but we should do it immediately as otherwise
892 * the register can overflow and we would lose status reports.
893 *
894 * Hence, read the TX_STA_FIFO register and copy all tx status
895 * reports into a kernel FIFO which is handled in the txstatus
896 * tasklet. We use a tasklet to process the tx status reports
897 * because we can schedule the tasklet multiple times (when the
898 * interrupt fires again during tx status processing).
899 *
900 * Furthermore we don't disable the TX_FIFO_STATUS
901 * interrupt here but leave it enabled so that the TX_STA_FIFO
Helmut Schaa3736fe52011-03-03 19:45:39 +0100902 * can also be read while the tx status tasklet gets executed.
Helmut Schaa96c3da72010-10-02 11:27:35 +0200903 *
904 * Since we have only one producer and one consumer we don't
905 * need to lock the kfifo.
906 */
Helmut Schaaefd2f272010-11-04 20:37:22 +0100907 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
Helmut Schaa9a819992011-04-18 15:34:01 +0200908 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
Helmut Schaa96c3da72010-10-02 11:27:35 +0200909
910 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
911 break;
912
Johannes Stezenbachc4d63242010-12-27 15:04:29 +0100913 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
Helmut Schaa96c3da72010-10-02 11:27:35 +0200914 WARNING(rt2x00dev, "TX status FIFO overrun,"
915 "drop tx status report.\n");
916 break;
917 }
918 }
919
920 /* Schedule the tasklet for processing the tx status. */
921 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
922}
923
Helmut Schaa78e256c2010-07-11 12:26:48 +0200924static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
925{
926 struct rt2x00_dev *rt2x00dev = dev_instance;
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100927 u32 reg, mask;
Helmut Schaa78e256c2010-07-11 12:26:48 +0200928
929 /* Read status and ACK all interrupts */
Helmut Schaa9a819992011-04-18 15:34:01 +0200930 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
931 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
Helmut Schaa78e256c2010-07-11 12:26:48 +0200932
933 if (!reg)
934 return IRQ_NONE;
935
936 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
937 return IRQ_HANDLED;
938
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100939 /*
940 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
941 * for interrupts and interrupt masks we can just use the value of
942 * INT_SOURCE_CSR to create the interrupt mask.
943 */
944 mask = ~reg;
945
946 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
Helmut Schaa96c3da72010-10-02 11:27:35 +0200947 rt2800pci_txstatus_interrupt(rt2x00dev);
Helmut Schaa96c3da72010-10-02 11:27:35 +0200948 /*
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100949 * Never disable the TX_FIFO_STATUS interrupt.
Helmut Schaa96c3da72010-10-02 11:27:35 +0200950 */
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100951 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
Helmut Schaa96c3da72010-10-02 11:27:35 +0200952 }
953
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100954 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
955 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
956
957 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
958 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
959
960 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
961 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
962
963 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
964 tasklet_schedule(&rt2x00dev->autowake_tasklet);
965
966 /*
967 * Disable all interrupts for which a tasklet was scheduled right now,
968 * the tasklet will reenable the appropriate interrupts.
969 */
Helmut Schaa0aa13b22011-03-03 19:45:16 +0100970 spin_lock(&rt2x00dev->irqmask_lock);
Helmut Schaa9a819992011-04-18 15:34:01 +0200971 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100972 reg &= mask;
Helmut Schaa9a819992011-04-18 15:34:01 +0200973 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
Helmut Schaa0aa13b22011-03-03 19:45:16 +0100974 spin_unlock(&rt2x00dev->irqmask_lock);
Helmut Schaaa9d61e92011-01-30 13:18:38 +0100975
976 return IRQ_HANDLED;
Helmut Schaa78e256c2010-07-11 12:26:48 +0200977}
978
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200979/*
980 * Device probe functions.
981 */
Gabor Juhosa02308e2012-12-29 14:51:51 +0100982static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
Bartlomiej Zolnierkiewicz7ab71322009-11-08 14:38:54 +0100983{
Gabor Juhosa02308e2012-12-29 14:51:51 +0100984 int retval;
985
Gertjan van Wingerdecea90e52010-02-13 20:55:47 +0100986 if (rt2x00_is_soc(rt2x00dev))
Gabor Juhosa02308e2012-12-29 14:51:51 +0100987 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
Gertjan van Wingerdecea90e52010-02-13 20:55:47 +0100988 else if (rt2800pci_efuse_detect(rt2x00dev))
Gabor Juhosa02308e2012-12-29 14:51:51 +0100989 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
Gertjan van Wingerdecea90e52010-02-13 20:55:47 +0100990 else
Gabor Juhosa02308e2012-12-29 14:51:51 +0100991 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
992
993 return retval;
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +0200994}
995
Helmut Schaae7836192010-07-11 12:28:54 +0200996static const struct ieee80211_ops rt2800pci_mac80211_ops = {
997 .tx = rt2x00mac_tx,
998 .start = rt2x00mac_start,
999 .stop = rt2x00mac_stop,
1000 .add_interface = rt2x00mac_add_interface,
1001 .remove_interface = rt2x00mac_remove_interface,
1002 .config = rt2x00mac_config,
1003 .configure_filter = rt2x00mac_configure_filter,
Helmut Schaae7836192010-07-11 12:28:54 +02001004 .set_key = rt2x00mac_set_key,
1005 .sw_scan_start = rt2x00mac_sw_scan_start,
1006 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1007 .get_stats = rt2x00mac_get_stats,
1008 .get_tkip_seq = rt2800_get_tkip_seq,
1009 .set_rts_threshold = rt2800_set_rts_threshold,
Helmut Schaaa2b13282011-09-08 14:38:01 +02001010 .sta_add = rt2x00mac_sta_add,
1011 .sta_remove = rt2x00mac_sta_remove,
Helmut Schaae7836192010-07-11 12:28:54 +02001012 .bss_info_changed = rt2x00mac_bss_info_changed,
1013 .conf_tx = rt2800_conf_tx,
1014 .get_tsf = rt2800_get_tsf,
1015 .rfkill_poll = rt2x00mac_rfkill_poll,
1016 .ampdu_action = rt2800_ampdu_action,
Ivo van Doornf44df182010-11-04 20:40:11 +01001017 .flush = rt2x00mac_flush,
Helmut Schaa977206d2010-12-13 12:31:58 +01001018 .get_survey = rt2800_get_survey,
Ivo van Doorne7dee442011-04-18 15:34:41 +02001019 .get_ringparam = rt2x00mac_get_ringparam,
Gertjan van Wingerde5f0dd292011-07-06 23:00:21 +02001020 .tx_frames_pending = rt2x00mac_tx_frames_pending,
Helmut Schaae7836192010-07-11 12:28:54 +02001021};
1022
Ivo van Doorne7966432010-07-11 12:31:23 +02001023static const struct rt2800_ops rt2800pci_rt2800_ops = {
1024 .register_read = rt2x00pci_register_read,
1025 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1026 .register_write = rt2x00pci_register_write,
1027 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1028 .register_multiread = rt2x00pci_register_multiread,
1029 .register_multiwrite = rt2x00pci_register_multiwrite,
1030 .regbusy_read = rt2x00pci_regbusy_read,
Gertjan van Wingerdead417a52012-09-03 03:25:51 +02001031 .read_eeprom = rt2800pci_read_eeprom,
1032 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
Ivo van Doorne7966432010-07-11 12:31:23 +02001033 .drv_write_firmware = rt2800pci_write_firmware,
1034 .drv_init_registers = rt2800pci_init_registers,
Ivo van Doorn0c5879b2010-08-06 20:47:20 +02001035 .drv_get_txwi = rt2800pci_get_txwi,
Ivo van Doorne7966432010-07-11 12:31:23 +02001036};
1037
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001038static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1039 .irq_handler = rt2800pci_interrupt,
Helmut Schaaa9d61e92011-01-30 13:18:38 +01001040 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1041 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1042 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1043 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1044 .autowake_tasklet = rt2800pci_autowake_tasklet,
Gertjan van Wingerdead417a52012-09-03 03:25:51 +02001045 .probe_hw = rt2800_probe_hw,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001046 .get_firmware_name = rt2800pci_get_firmware_name,
Ivo van Doornf31c9a82010-07-11 12:30:37 +02001047 .check_firmware = rt2800_check_firmware,
1048 .load_firmware = rt2800_load_firmware,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001049 .initialize = rt2x00pci_initialize,
1050 .uninitialize = rt2x00pci_uninitialize,
1051 .get_entry_state = rt2800pci_get_entry_state,
1052 .clear_entry = rt2800pci_clear_entry,
1053 .set_device_state = rt2800pci_set_device_state,
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001054 .rfkill_poll = rt2800_rfkill_poll,
1055 .link_stats = rt2800_link_stats,
1056 .reset_tuner = rt2800_reset_tuner,
1057 .link_tuner = rt2800_link_tuner,
Helmut Schaa9e33a352011-03-28 13:33:40 +02001058 .gain_calibration = rt2800_gain_calibration,
John Li2e9c43d2012-02-16 21:40:57 +08001059 .vco_calibration = rt2800_vco_calibration,
Ivo van Doorndbba3062010-12-13 12:34:54 +01001060 .start_queue = rt2800pci_start_queue,
1061 .kick_queue = rt2800pci_kick_queue,
1062 .stop_queue = rt2800pci_stop_queue,
Ivo van Doorn152a5992011-04-18 15:31:02 +02001063 .flush_queue = rt2x00pci_flush_queue,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001064 .write_tx_desc = rt2800pci_write_tx_desc,
Ivo van Doorn0c5879b2010-08-06 20:47:20 +02001065 .write_tx_data = rt2800_write_tx_data,
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +02001066 .write_beacon = rt2800_write_beacon,
Helmut Schaa69cf36a2011-01-30 13:16:03 +01001067 .clear_beacon = rt2800_clear_beacon,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001068 .fill_rxdone = rt2800pci_fill_rxdone,
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001069 .config_shared_key = rt2800_config_shared_key,
1070 .config_pairwise_key = rt2800_config_pairwise_key,
1071 .config_filter = rt2800_config_filter,
1072 .config_intf = rt2800_config_intf,
1073 .config_erp = rt2800_config_erp,
1074 .config_ant = rt2800_config_ant,
1075 .config = rt2800_config,
Helmut Schaaa2b13282011-09-08 14:38:01 +02001076 .sta_add = rt2800_sta_add,
1077 .sta_remove = rt2800_sta_remove,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001078};
1079
1080static const struct data_queue_desc rt2800pci_queue_rx = {
Helmut Schaaefd2f272010-11-04 20:37:22 +01001081 .entry_num = 128,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001082 .data_size = AGGREGATION_SIZE,
1083 .desc_size = RXD_DESC_SIZE,
1084 .priv_size = sizeof(struct queue_entry_priv_pci),
1085};
1086
1087static const struct data_queue_desc rt2800pci_queue_tx = {
Helmut Schaaefd2f272010-11-04 20:37:22 +01001088 .entry_num = 64,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001089 .data_size = AGGREGATION_SIZE,
1090 .desc_size = TXD_DESC_SIZE,
1091 .priv_size = sizeof(struct queue_entry_priv_pci),
1092};
1093
1094static const struct data_queue_desc rt2800pci_queue_bcn = {
Helmut Schaaefd2f272010-11-04 20:37:22 +01001095 .entry_num = 8,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001096 .data_size = 0, /* No DMA required for beacons */
1097 .desc_size = TXWI_DESC_SIZE,
1098 .priv_size = sizeof(struct queue_entry_priv_pci),
1099};
1100
1101static const struct rt2x00_ops rt2800pci_ops = {
Gertjan van Wingerde04d03622009-11-23 22:44:51 +01001102 .name = KBUILD_MODNAME,
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01001103 .drv_data_size = sizeof(struct rt2800_drv_data),
Gertjan van Wingerde04d03622009-11-23 22:44:51 +01001104 .max_ap_intf = 8,
1105 .eeprom_size = EEPROM_SIZE,
1106 .rf_size = RF_SIZE,
1107 .tx_queues = NUM_TX_QUEUES,
Gertjan van Wingerdee6218cc2009-11-23 22:44:52 +01001108 .extra_tx_headroom = TXWI_DESC_SIZE,
Gertjan van Wingerde04d03622009-11-23 22:44:51 +01001109 .rx = &rt2800pci_queue_rx,
1110 .tx = &rt2800pci_queue_tx,
1111 .bcn = &rt2800pci_queue_bcn,
1112 .lib = &rt2800pci_rt2x00_ops,
Ivo van Doorne7966432010-07-11 12:31:23 +02001113 .drv = &rt2800pci_rt2800_ops,
Helmut Schaae7836192010-07-11 12:28:54 +02001114 .hw = &rt2800pci_mac80211_ops,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001115#ifdef CONFIG_RT2X00_LIB_DEBUGFS
Gertjan van Wingerde04d03622009-11-23 22:44:51 +01001116 .debugfs = &rt2800_rt2x00debug,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001117#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1118};
1119
1120/*
1121 * RT2800pci module information.
1122 */
Gertjan van Wingerde72c72962010-11-13 19:10:54 +01001123#ifdef CONFIG_PCI
Alexey Dobriyana3aa1882010-01-07 11:58:11 +00001124static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
Gertjan van Wingerdee01ae272011-04-18 15:32:13 +02001125 { PCI_DEVICE(0x1814, 0x0601) },
1126 { PCI_DEVICE(0x1814, 0x0681) },
1127 { PCI_DEVICE(0x1814, 0x0701) },
1128 { PCI_DEVICE(0x1814, 0x0781) },
1129 { PCI_DEVICE(0x1814, 0x3090) },
1130 { PCI_DEVICE(0x1814, 0x3091) },
1131 { PCI_DEVICE(0x1814, 0x3092) },
1132 { PCI_DEVICE(0x1432, 0x7708) },
1133 { PCI_DEVICE(0x1432, 0x7727) },
1134 { PCI_DEVICE(0x1432, 0x7728) },
1135 { PCI_DEVICE(0x1432, 0x7738) },
1136 { PCI_DEVICE(0x1432, 0x7748) },
1137 { PCI_DEVICE(0x1432, 0x7758) },
1138 { PCI_DEVICE(0x1432, 0x7768) },
1139 { PCI_DEVICE(0x1462, 0x891a) },
1140 { PCI_DEVICE(0x1a3b, 0x1059) },
Woody Hunga89534e2012-06-13 15:01:16 +08001141#ifdef CONFIG_RT2800PCI_RT3290
1142 { PCI_DEVICE(0x1814, 0x3290) },
1143#endif
Gertjan van Wingerdef93bc9b2010-11-13 19:09:50 +01001144#ifdef CONFIG_RT2800PCI_RT33XX
Gertjan van Wingerdee01ae272011-04-18 15:32:13 +02001145 { PCI_DEVICE(0x1814, 0x3390) },
Gertjan van Wingerdef93bc9b2010-11-13 19:09:50 +01001146#endif
Gertjan van Wingerdede1ebdc2010-02-14 12:52:05 +01001147#ifdef CONFIG_RT2800PCI_RT35XX
Gertjan van Wingerdee01ae272011-04-18 15:32:13 +02001148 { PCI_DEVICE(0x1432, 0x7711) },
1149 { PCI_DEVICE(0x1432, 0x7722) },
1150 { PCI_DEVICE(0x1814, 0x3060) },
1151 { PCI_DEVICE(0x1814, 0x3062) },
1152 { PCI_DEVICE(0x1814, 0x3562) },
1153 { PCI_DEVICE(0x1814, 0x3592) },
1154 { PCI_DEVICE(0x1814, 0x3593) },
Xose Vazquez Perezc4806012013-02-01 14:28:49 +01001155 { PCI_DEVICE(0x1814, 0x359f) },
Gertjan van Wingerdede1ebdc2010-02-14 12:52:05 +01001156#endif
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01001157#ifdef CONFIG_RT2800PCI_RT53XX
villacis@palosanto.comccf91bd2012-05-16 21:07:12 +02001158 { PCI_DEVICE(0x1814, 0x5360) },
Xose Vazquez Perezf57d7b62012-04-14 23:33:21 +02001159 { PCI_DEVICE(0x1814, 0x5362) },
Gertjan van Wingerdee01ae272011-04-18 15:32:13 +02001160 { PCI_DEVICE(0x1814, 0x5390) },
Xose Vazquez Perezf57d7b62012-04-14 23:33:21 +02001161 { PCI_DEVICE(0x1814, 0x5392) },
zero.lin5126d972011-08-31 20:43:52 +02001162 { PCI_DEVICE(0x1814, 0x539a) },
Zero.Lin2aed6912012-05-10 10:06:31 +08001163 { PCI_DEVICE(0x1814, 0x539b) },
Gertjan van Wingerde71e0b382011-07-06 22:58:55 +02001164 { PCI_DEVICE(0x1814, 0x539f) },
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01001165#endif
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001166 { 0, }
1167};
Gertjan van Wingerde72c72962010-11-13 19:10:54 +01001168#endif /* CONFIG_PCI */
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001169
1170MODULE_AUTHOR(DRV_PROJECT);
1171MODULE_VERSION(DRV_VERSION);
1172MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1173MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
Gertjan van Wingerde72c72962010-11-13 19:10:54 +01001174#ifdef CONFIG_PCI
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001175MODULE_FIRMWARE(FIRMWARE_RT2860);
1176MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
Gertjan van Wingerde72c72962010-11-13 19:10:54 +01001177#endif /* CONFIG_PCI */
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001178MODULE_LICENSE("GPL");
1179
John Crispin5818a462013-03-13 13:20:15 +01001180#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
Gertjan van Wingerde714fa662010-02-13 20:55:48 +01001181static int rt2800soc_probe(struct platform_device *pdev)
1182{
Helmut Schaa6e93d712010-03-02 16:34:49 +01001183 return rt2x00soc_probe(pdev, &rt2800pci_ops);
Gertjan van Wingerde714fa662010-02-13 20:55:48 +01001184}
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001185
1186static struct platform_driver rt2800soc_driver = {
1187 .driver = {
1188 .name = "rt2800_wmac",
1189 .owner = THIS_MODULE,
1190 .mod_name = KBUILD_MODNAME,
1191 },
Gertjan van Wingerde714fa662010-02-13 20:55:48 +01001192 .probe = rt2800soc_probe,
Bill Pemberton69202352012-12-03 09:56:39 -05001193 .remove = rt2x00soc_remove,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001194 .suspend = rt2x00soc_suspend,
1195 .resume = rt2x00soc_resume,
1196};
John Crispin5818a462013-03-13 13:20:15 +01001197#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001198
Gertjan van Wingerde72c72962010-11-13 19:10:54 +01001199#ifdef CONFIG_PCI
Gertjan van Wingerdee01ae272011-04-18 15:32:13 +02001200static int rt2800pci_probe(struct pci_dev *pci_dev,
1201 const struct pci_device_id *id)
1202{
1203 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1204}
1205
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001206static struct pci_driver rt2800pci_driver = {
1207 .name = KBUILD_MODNAME,
1208 .id_table = rt2800pci_device_table,
Gertjan van Wingerdee01ae272011-04-18 15:32:13 +02001209 .probe = rt2800pci_probe,
Bill Pemberton69202352012-12-03 09:56:39 -05001210 .remove = rt2x00pci_remove,
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001211 .suspend = rt2x00pci_suspend,
1212 .resume = rt2x00pci_resume,
1213};
Gertjan van Wingerde72c72962010-11-13 19:10:54 +01001214#endif /* CONFIG_PCI */
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001215
1216static int __init rt2800pci_init(void)
1217{
1218 int ret = 0;
1219
John Crispin5818a462013-03-13 13:20:15 +01001220#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001221 ret = platform_driver_register(&rt2800soc_driver);
1222 if (ret)
1223 return ret;
1224#endif
Gertjan van Wingerde72c72962010-11-13 19:10:54 +01001225#ifdef CONFIG_PCI
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001226 ret = pci_register_driver(&rt2800pci_driver);
1227 if (ret) {
John Crispin5818a462013-03-13 13:20:15 +01001228#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001229 platform_driver_unregister(&rt2800soc_driver);
1230#endif
1231 return ret;
1232 }
1233#endif
1234
1235 return ret;
1236}
1237
1238static void __exit rt2800pci_exit(void)
1239{
Gertjan van Wingerde72c72962010-11-13 19:10:54 +01001240#ifdef CONFIG_PCI
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001241 pci_unregister_driver(&rt2800pci_driver);
1242#endif
John Crispin5818a462013-03-13 13:20:15 +01001243#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
Ivo van Doorna9b3a9f2009-10-15 22:04:14 +02001244 platform_driver_unregister(&rt2800soc_driver);
1245#endif
1246}
1247
1248module_init(rt2800pci_init);
1249module_exit(rt2800pci_exit);