arch/arm/boot/dts/sama5d3_uart.dtsi

/*
 * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
 * UART support
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 *
 * Licensed under GPLv2.
 */

#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/at91.h>

/ {
	ahb {
		apb {
			pinctrl@fffff200 {
				uart0 {
					pinctrl_uart0: uart0-0 {
						atmel,pins =
							<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
							 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PC30 periph A with pullup, conflicts with ISI_PCK */
					};
				};

				uart1 {
					pinctrl_uart1: uart1-0 {
						atmel,pins =
							<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
							 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
					};
				};
			};

			pmc: pmc@fffffc00 {
				periphck {
					uart0_clk: uart0_clk {
						#clock-cells = <0>;
						reg = <16>;
						atmel,clk-output-range = <0 66000000>;
					};

					uart1_clk: uart1_clk {
						#clock-cells = <0>;
						reg = <17>;
						atmel,clk-output-range = <0 66000000>;
					};
				};
			};

			uart0: serial@f0024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf0024000 0x200>;
				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart0>;
				clocks = <&uart0_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			uart1: serial@f8028000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8028000 0x200>;
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart1>;
				clocks = <&uart1_clk>;
				clock-names = "usart";
				status = "disabled";
			};
		};
	};
};