Songjun Wu | e0a25b6 | 2015-10-08 18:13:31 +0800 | [diff] [blame] | 1 | #ifndef __ATMEL_CLASSD_H_ |
| 2 | #define __ATMEL_CLASSD_H_ |
| 3 | |
| 4 | #define CLASSD_CR 0x00000000 |
| 5 | #define CLASSD_CR_RESET 0x1 |
| 6 | |
| 7 | #define CLASSD_MR 0x00000004 |
| 8 | |
| 9 | #define CLASSD_MR_LEN_DIS 0x0 |
| 10 | #define CLASSD_MR_LEN_EN 0x1 |
| 11 | #define CLASSD_MR_LEN_MASK (0x1 << 0) |
| 12 | #define CLASSD_MR_LEN_SHIFT (0) |
| 13 | |
| 14 | #define CLASSD_MR_LMUTE_DIS 0x0 |
| 15 | #define CLASSD_MR_LMUTE_EN 0x1 |
| 16 | #define CLASSD_MR_LMUTE_SHIFT (0x1) |
| 17 | #define CLASSD_MR_LMUTE_MASK (0x1 << 1) |
| 18 | |
| 19 | #define CLASSD_MR_REN_DIS 0x0 |
| 20 | #define CLASSD_MR_REN_EN 0x1 |
| 21 | #define CLASSD_MR_REN_MASK (0x1 << 4) |
| 22 | #define CLASSD_MR_REN_SHIFT (4) |
| 23 | |
| 24 | #define CLASSD_MR_RMUTE_DIS 0x0 |
| 25 | #define CLASSD_MR_RMUTE_EN 0x1 |
| 26 | #define CLASSD_MR_RMUTE_SHIFT (0x5) |
| 27 | #define CLASSD_MR_RMUTE_MASK (0x1 << 5) |
| 28 | |
| 29 | #define CLASSD_MR_PWMTYP_SINGLE 0x0 |
| 30 | #define CLASSD_MR_PWMTYP_DIFF 0x1 |
| 31 | #define CLASSD_MR_PWMTYP_MASK (0x1 << 8) |
| 32 | #define CLASSD_MR_PWMTYP_SHIFT (8) |
| 33 | |
| 34 | #define CLASSD_MR_NON_OVERLAP_DIS 0x0 |
| 35 | #define CLASSD_MR_NON_OVERLAP_EN 0x1 |
| 36 | #define CLASSD_MR_NON_OVERLAP_MASK (0x1 << 16) |
| 37 | #define CLASSD_MR_NON_OVERLAP_SHIFT (16) |
| 38 | |
| 39 | #define CLASSD_MR_NOVR_VAL_5NS 0x0 |
| 40 | #define CLASSD_MR_NOVR_VAL_10NS 0x1 |
| 41 | #define CLASSD_MR_NOVR_VAL_15NS 0x2 |
| 42 | #define CLASSD_MR_NOVR_VAL_20NS 0x3 |
| 43 | #define CLASSD_MR_NOVR_VAL_MASK (0x3 << 20) |
| 44 | #define CLASSD_MR_NOVR_VAL_SHIFT (20) |
| 45 | |
| 46 | #define CLASSD_INTPMR 0x00000008 |
| 47 | |
| 48 | #define CLASSD_INTPMR_ATTL_MASK (0x3f << 0) |
| 49 | #define CLASSD_INTPMR_ATTL_SHIFT (0) |
| 50 | #define CLASSD_INTPMR_ATTR_MASK (0x3f << 8) |
| 51 | #define CLASSD_INTPMR_ATTR_SHIFT (8) |
| 52 | |
| 53 | #define CLASSD_INTPMR_DSP_CLK_FREQ_12M288 0x0 |
| 54 | #define CLASSD_INTPMR_DSP_CLK_FREQ_11M2896 0x1 |
| 55 | #define CLASSD_INTPMR_DSP_CLK_FREQ_MASK (0x1 << 16) |
| 56 | #define CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT (16) |
| 57 | |
| 58 | #define CLASSD_INTPMR_DEEMP_DIS 0x0 |
| 59 | #define CLASSD_INTPMR_DEEMP_EN 0x1 |
| 60 | #define CLASSD_INTPMR_DEEMP_MASK (0x1 << 18) |
| 61 | #define CLASSD_INTPMR_DEEMP_SHIFT (18) |
| 62 | |
| 63 | #define CLASSD_INTPMR_SWAP_LEFT_ON_LSB 0x0 |
| 64 | #define CLASSD_INTPMR_SWAP_RIGHT_ON_LSB 0x1 |
| 65 | #define CLASSD_INTPMR_SWAP_MASK (0x1 << 19) |
| 66 | #define CLASSD_INTPMR_SWAP_SHIFT (19) |
| 67 | |
| 68 | #define CLASSD_INTPMR_FRAME_8K 0x0 |
| 69 | #define CLASSD_INTPMR_FRAME_16K 0x1 |
| 70 | #define CLASSD_INTPMR_FRAME_32K 0x2 |
| 71 | #define CLASSD_INTPMR_FRAME_48K 0x3 |
| 72 | #define CLASSD_INTPMR_FRAME_96K 0x4 |
| 73 | #define CLASSD_INTPMR_FRAME_22K 0x5 |
| 74 | #define CLASSD_INTPMR_FRAME_44K 0x6 |
| 75 | #define CLASSD_INTPMR_FRAME_88K 0x7 |
| 76 | #define CLASSD_INTPMR_FRAME_MASK (0x7 << 20) |
| 77 | #define CLASSD_INTPMR_FRAME_SHIFT (20) |
| 78 | |
| 79 | #define CLASSD_INTPMR_EQCFG_FLAT 0x0 |
| 80 | #define CLASSD_INTPMR_EQCFG_B_BOOST_12 0x1 |
| 81 | #define CLASSD_INTPMR_EQCFG_B_BOOST_6 0x2 |
| 82 | #define CLASSD_INTPMR_EQCFG_B_CUT_12 0x3 |
| 83 | #define CLASSD_INTPMR_EQCFG_B_CUT_6 0x4 |
| 84 | #define CLASSD_INTPMR_EQCFG_M_BOOST_3 0x5 |
| 85 | #define CLASSD_INTPMR_EQCFG_M_BOOST_8 0x6 |
| 86 | #define CLASSD_INTPMR_EQCFG_M_CUT_3 0x7 |
| 87 | #define CLASSD_INTPMR_EQCFG_M_CUT_8 0x8 |
| 88 | #define CLASSD_INTPMR_EQCFG_T_BOOST_12 0x9 |
| 89 | #define CLASSD_INTPMR_EQCFG_T_BOOST_6 0xa |
| 90 | #define CLASSD_INTPMR_EQCFG_T_CUT_12 0xb |
| 91 | #define CLASSD_INTPMR_EQCFG_T_CUT_6 0xc |
| 92 | #define CLASSD_INTPMR_EQCFG_SHIFT (24) |
| 93 | |
| 94 | #define CLASSD_INTPMR_MONO_DIS 0x0 |
| 95 | #define CLASSD_INTPMR_MONO_EN 0x1 |
| 96 | #define CLASSD_INTPMR_MONO_MASK (0x1 << 28) |
| 97 | #define CLASSD_INTPMR_MONO_SHIFT (28) |
| 98 | |
| 99 | #define CLASSD_INTPMR_MONO_MODE_MIX 0x0 |
| 100 | #define CLASSD_INTPMR_MONO_MODE_SAT 0x1 |
| 101 | #define CLASSD_INTPMR_MONO_MODE_LEFT 0x2 |
| 102 | #define CLASSD_INTPMR_MONO_MODE_RIGHT 0x3 |
| 103 | #define CLASSD_INTPMR_MONO_MODE_MASK (0x3 << 29) |
| 104 | #define CLASSD_INTPMR_MONO_MODE_SHIFT (29) |
| 105 | |
| 106 | #define CLASSD_INTSR 0x0000000c |
| 107 | |
| 108 | #define CLASSD_THR 0x00000010 |
| 109 | |
| 110 | #define CLASSD_IER 0x00000014 |
| 111 | |
| 112 | #define CLASSD_IDR 0x00000018 |
| 113 | |
| 114 | #define CLASSD_IMR 0x0000001c |
| 115 | |
| 116 | #define CLASSD_ISR 0x00000020 |
| 117 | |
| 118 | #define CLASSD_WPMR 0x000000e4 |
| 119 | |
| 120 | #endif |