blob: be5b645815e58c26075af2a43d5080ebb820130d [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Maxime Ripardf72f4b42016-07-20 16:11:36 +02002/*
Quentin Schulz23f75d72017-12-05 15:46:41 +01003 * AXP20x pinctrl and GPIO driver
Maxime Ripardf72f4b42016-07-20 16:11:36 +02004 *
5 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
Quentin Schulz23f75d72017-12-05 15:46:41 +01006 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
Maxime Ripardf72f4b42016-07-20 16:11:36 +02007 */
8
9#include <linux/bitops.h>
10#include <linux/device.h>
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/mfd/axp20x.h>
16#include <linux/module.h>
17#include <linux/of.h>
Quentin Schulze1190082017-12-05 15:46:46 +010018#include <linux/of_device.h>
Quentin Schulz23f75d72017-12-05 15:46:41 +010019#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
Maxime Ripardf72f4b42016-07-20 16:11:36 +020022#include <linux/platform_device.h>
23#include <linux/regmap.h>
24#include <linux/slab.h>
25
26#define AXP20X_GPIO_FUNCTIONS 0x7
27#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
28#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
29#define AXP20X_GPIO_FUNCTION_INPUT 2
30
Quentin Schulz23f75d72017-12-05 15:46:41 +010031#define AXP20X_FUNC_GPIO_OUT 0
32#define AXP20X_FUNC_GPIO_IN 1
33#define AXP20X_FUNC_LDO 2
34#define AXP20X_FUNC_ADC 3
35#define AXP20X_FUNCS_NB 4
36
37#define AXP20X_MUX_GPIO_OUT 0
38#define AXP20X_MUX_GPIO_IN BIT(1)
39#define AXP20X_MUX_ADC BIT(2)
40
Quentin Schulze1190082017-12-05 15:46:46 +010041#define AXP813_MUX_ADC (BIT(2) | BIT(0))
42
Quentin Schulz23f75d72017-12-05 15:46:41 +010043struct axp20x_pctrl_desc {
44 const struct pinctrl_pin_desc *pins;
45 unsigned int npins;
46 /* Stores the pins supporting LDO function. Bit offset is pin number. */
47 u8 ldo_mask;
48 /* Stores the pins supporting ADC function. Bit offset is pin number. */
49 u8 adc_mask;
Quentin Schulz48e706f2017-12-05 15:46:44 +010050 u8 gpio_status_offset;
Quentin Schulza0a4b4c2017-12-05 15:46:45 +010051 u8 adc_mux;
Quentin Schulz23f75d72017-12-05 15:46:41 +010052};
53
54struct axp20x_pinctrl_function {
55 const char *name;
56 unsigned int muxval;
57 const char **groups;
58 unsigned int ngroups;
59};
60
Quentin Schulzd242e602017-12-05 15:46:43 +010061struct axp20x_pctl {
Maxime Ripardf72f4b42016-07-20 16:11:36 +020062 struct gpio_chip chip;
63 struct regmap *regmap;
Quentin Schulz23f75d72017-12-05 15:46:41 +010064 struct pinctrl_dev *pctl_dev;
65 struct device *dev;
66 const struct axp20x_pctrl_desc *desc;
67 struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
68};
69
70static const struct pinctrl_pin_desc axp209_pins[] = {
71 PINCTRL_PIN(0, "GPIO0"),
72 PINCTRL_PIN(1, "GPIO1"),
73 PINCTRL_PIN(2, "GPIO2"),
74};
75
Quentin Schulze1190082017-12-05 15:46:46 +010076static const struct pinctrl_pin_desc axp813_pins[] = {
77 PINCTRL_PIN(0, "GPIO0"),
78 PINCTRL_PIN(1, "GPIO1"),
79};
80
Quentin Schulz23f75d72017-12-05 15:46:41 +010081static const struct axp20x_pctrl_desc axp20x_data = {
82 .pins = axp209_pins,
83 .npins = ARRAY_SIZE(axp209_pins),
84 .ldo_mask = BIT(0) | BIT(1),
85 .adc_mask = BIT(0) | BIT(1),
Quentin Schulz48e706f2017-12-05 15:46:44 +010086 .gpio_status_offset = 4,
Quentin Schulza0a4b4c2017-12-05 15:46:45 +010087 .adc_mux = AXP20X_MUX_ADC,
Maxime Ripardf72f4b42016-07-20 16:11:36 +020088};
89
Quentin Schulze1190082017-12-05 15:46:46 +010090static const struct axp20x_pctrl_desc axp813_data = {
91 .pins = axp813_pins,
92 .npins = ARRAY_SIZE(axp813_pins),
93 .ldo_mask = BIT(0) | BIT(1),
94 .adc_mask = BIT(0),
95 .gpio_status_offset = 0,
96 .adc_mux = AXP813_MUX_ADC,
97};
98
Quentin Schulz3cac9912017-12-05 15:46:39 +010099static int axp20x_gpio_get_reg(unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200100{
101 switch (offset) {
102 case 0:
103 return AXP20X_GPIO0_CTRL;
104 case 1:
105 return AXP20X_GPIO1_CTRL;
106 case 2:
107 return AXP20X_GPIO2_CTRL;
108 }
109
110 return -EINVAL;
111}
112
Quentin Schulz3cac9912017-12-05 15:46:39 +0100113static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200114{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100115 return pinctrl_gpio_direction_input(chip->base + offset);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200116}
117
Quentin Schulz3cac9912017-12-05 15:46:39 +0100118static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200119{
Quentin Schulzd242e602017-12-05 15:46:43 +0100120 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200121 unsigned int val;
Quentin Schulz1d2b2ac2016-11-23 15:11:50 +0100122 int ret;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200123
Quentin Schulzd242e602017-12-05 15:46:43 +0100124 ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200125 if (ret)
126 return ret;
127
Quentin Schulz48e706f2017-12-05 15:46:44 +0100128 return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200129}
130
Quentin Schulz3cac9912017-12-05 15:46:39 +0100131static int axp20x_gpio_get_direction(struct gpio_chip *chip,
132 unsigned int offset)
Maxime Ripard81d37532016-09-21 23:51:22 +0300133{
Quentin Schulzd242e602017-12-05 15:46:43 +0100134 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripard81d37532016-09-21 23:51:22 +0300135 unsigned int val;
136 int reg, ret;
137
138 reg = axp20x_gpio_get_reg(offset);
139 if (reg < 0)
140 return reg;
141
Quentin Schulzd242e602017-12-05 15:46:43 +0100142 ret = regmap_read(pctl->regmap, reg, &val);
Maxime Ripard81d37532016-09-21 23:51:22 +0300143 if (ret)
144 return ret;
145
146 /*
147 * This shouldn't really happen if the pin is in use already,
148 * or if it's not in use yet, it doesn't matter since we're
149 * going to change the value soon anyway. Default to output.
150 */
151 if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
152 return 0;
153
154 /*
155 * The GPIO directions are the three lowest values.
156 * 2 is input, 0 and 1 are output
157 */
158 return val & 2;
159}
160
Quentin Schulz3cac9912017-12-05 15:46:39 +0100161static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200162 int value)
163{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100164 chip->set(chip, offset, value);
165
166 return 0;
167}
168
169static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
170 int value)
171{
Quentin Schulzd242e602017-12-05 15:46:43 +0100172 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200173 int reg;
174
175 reg = axp20x_gpio_get_reg(offset);
176 if (reg < 0)
Quentin Schulz23f75d72017-12-05 15:46:41 +0100177 return;
178
Quentin Schulzd242e602017-12-05 15:46:43 +0100179 regmap_update_bits(pctl->regmap, reg,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100180 AXP20X_GPIO_FUNCTIONS,
181 value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
182 AXP20X_GPIO_FUNCTION_OUT_LOW);
183}
184
185static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
186 u8 config)
187{
Quentin Schulzd242e602017-12-05 15:46:43 +0100188 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100189 int reg;
190
191 reg = axp20x_gpio_get_reg(offset);
192 if (reg < 0)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200193 return reg;
194
Quentin Schulzd242e602017-12-05 15:46:43 +0100195 return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100196 config);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200197}
198
Quentin Schulz23f75d72017-12-05 15:46:41 +0100199static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200200{
Quentin Schulzd242e602017-12-05 15:46:43 +0100201 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100202
Quentin Schulzd242e602017-12-05 15:46:43 +0100203 return ARRAY_SIZE(pctl->funcs);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100204}
205
206static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
207 unsigned int selector)
208{
Quentin Schulzd242e602017-12-05 15:46:43 +0100209 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100210
Quentin Schulzd242e602017-12-05 15:46:43 +0100211 return pctl->funcs[selector].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100212}
213
214static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
215 unsigned int selector,
216 const char * const **groups,
217 unsigned int *num_groups)
218{
Quentin Schulzd242e602017-12-05 15:46:43 +0100219 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100220
Quentin Schulzd242e602017-12-05 15:46:43 +0100221 *groups = pctl->funcs[selector].groups;
222 *num_groups = pctl->funcs[selector].ngroups;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100223
224 return 0;
225}
226
227static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
228 unsigned int function, unsigned int group)
229{
Quentin Schulzd242e602017-12-05 15:46:43 +0100230 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100231 unsigned int mask;
232
233 /* Every pin supports GPIO_OUT and GPIO_IN functions */
234 if (function <= AXP20X_FUNC_GPIO_IN)
235 return axp20x_pmx_set(pctldev, group,
Quentin Schulzd242e602017-12-05 15:46:43 +0100236 pctl->funcs[function].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100237
238 if (function == AXP20X_FUNC_LDO)
Quentin Schulzd242e602017-12-05 15:46:43 +0100239 mask = pctl->desc->ldo_mask;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100240 else
Quentin Schulzd242e602017-12-05 15:46:43 +0100241 mask = pctl->desc->adc_mask;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100242
243 if (!(BIT(group) & mask))
244 return -EINVAL;
245
246 /*
247 * We let the regulator framework handle the LDO muxing as muxing bits
248 * are basically also regulators on/off bits. It's better not to enforce
249 * any state of the regulator when selecting LDO mux so that we don't
250 * interfere with the regulator driver.
251 */
252 if (function == AXP20X_FUNC_LDO)
253 return 0;
254
Quentin Schulzd242e602017-12-05 15:46:43 +0100255 return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100256}
257
258static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
259 struct pinctrl_gpio_range *range,
260 unsigned int offset, bool input)
261{
Quentin Schulzd242e602017-12-05 15:46:43 +0100262 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100263
264 if (input)
265 return axp20x_pmx_set(pctldev, offset,
Quentin Schulzd242e602017-12-05 15:46:43 +0100266 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100267
268 return axp20x_pmx_set(pctldev, offset,
Quentin Schulzd242e602017-12-05 15:46:43 +0100269 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100270}
271
272static const struct pinmux_ops axp20x_pmx_ops = {
273 .get_functions_count = axp20x_pmx_func_cnt,
274 .get_function_name = axp20x_pmx_func_name,
275 .get_function_groups = axp20x_pmx_func_groups,
276 .set_mux = axp20x_pmx_set_mux,
277 .gpio_set_direction = axp20x_pmx_gpio_set_direction,
278 .strict = true,
279};
280
281static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
282{
Quentin Schulzd242e602017-12-05 15:46:43 +0100283 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100284
Quentin Schulzd242e602017-12-05 15:46:43 +0100285 return pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100286}
287
288static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
289 const unsigned int **pins, unsigned int *num_pins)
290{
Quentin Schulzd242e602017-12-05 15:46:43 +0100291 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100292
Quentin Schulzd242e602017-12-05 15:46:43 +0100293 *pins = (unsigned int *)&pctl->desc->pins[selector];
Quentin Schulz23f75d72017-12-05 15:46:41 +0100294 *num_pins = 1;
295
296 return 0;
297}
298
299static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
300 unsigned int selector)
301{
Quentin Schulzd242e602017-12-05 15:46:43 +0100302 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100303
Quentin Schulzd242e602017-12-05 15:46:43 +0100304 return pctl->desc->pins[selector].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100305}
306
307static const struct pinctrl_ops axp20x_pctrl_ops = {
308 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
309 .dt_free_map = pinconf_generic_dt_free_map,
310 .get_groups_count = axp20x_groups_cnt,
311 .get_group_name = axp20x_group_name,
312 .get_group_pins = axp20x_group_pins,
313};
314
Anton Vasilyev504c7692018-08-06 19:06:35 +0300315static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100316 unsigned int mask_len,
317 struct axp20x_pinctrl_function *func,
318 const struct pinctrl_pin_desc *pins)
319{
320 unsigned long int mask_cpy = mask;
321 const char **group;
322 unsigned int ngroups = hweight8(mask);
323 int bit;
324
325 func->ngroups = ngroups;
326 if (func->ngroups > 0) {
Kees Cooka86854d2018-06-12 14:07:58 -0700327 func->groups = devm_kcalloc(dev,
328 ngroups, sizeof(const char *),
Quentin Schulz23f75d72017-12-05 15:46:41 +0100329 GFP_KERNEL);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300330 if (!func->groups)
331 return -ENOMEM;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100332 group = func->groups;
333 for_each_set_bit(bit, &mask_cpy, mask_len) {
334 *group = pins[bit].name;
335 group++;
336 }
337 }
Anton Vasilyev504c7692018-08-06 19:06:35 +0300338
339 return 0;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100340}
341
Anton Vasilyev504c7692018-08-06 19:06:35 +0300342static int axp20x_build_funcs_groups(struct platform_device *pdev)
Quentin Schulz23f75d72017-12-05 15:46:41 +0100343{
Quentin Schulzd242e602017-12-05 15:46:43 +0100344 struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300345 int i, ret, pin, npins = pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100346
Quentin Schulzd242e602017-12-05 15:46:43 +0100347 pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
348 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
349 pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
350 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
351 pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
Quentin Schulz23f75d72017-12-05 15:46:41 +0100352 /*
353 * Muxval for LDO is useless as we won't use it.
354 * See comment in axp20x_pmx_set_mux.
355 */
Quentin Schulzd242e602017-12-05 15:46:43 +0100356 pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
Quentin Schulza0a4b4c2017-12-05 15:46:45 +0100357 pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100358
359 /* Every pin supports GPIO_OUT and GPIO_IN functions */
360 for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
Quentin Schulzd242e602017-12-05 15:46:43 +0100361 pctl->funcs[i].ngroups = npins;
Kees Cooka86854d2018-06-12 14:07:58 -0700362 pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
363 npins, sizeof(char *),
Quentin Schulz23f75d72017-12-05 15:46:41 +0100364 GFP_KERNEL);
Aditya Pakki1adc90c2019-03-12 10:19:10 -0500365 if (!pctl->funcs[i].groups)
366 return -ENOMEM;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100367 for (pin = 0; pin < npins; pin++)
Quentin Schulzd242e602017-12-05 15:46:43 +0100368 pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100369 }
370
Anton Vasilyev504c7692018-08-06 19:06:35 +0300371 ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
Quentin Schulzd242e602017-12-05 15:46:43 +0100372 npins, &pctl->funcs[AXP20X_FUNC_LDO],
373 pctl->desc->pins);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300374 if (ret)
375 return ret;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100376
Anton Vasilyev504c7692018-08-06 19:06:35 +0300377 ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
Quentin Schulzd242e602017-12-05 15:46:43 +0100378 npins, &pctl->funcs[AXP20X_FUNC_ADC],
379 pctl->desc->pins);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300380 if (ret)
381 return ret;
382
383 return 0;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200384}
385
Quentin Schulze1190082017-12-05 15:46:46 +0100386static const struct of_device_id axp20x_pctl_match[] = {
387 { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
388 { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
389 { }
390};
391MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
392
Quentin Schulzd242e602017-12-05 15:46:43 +0100393static int axp20x_pctl_probe(struct platform_device *pdev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200394{
395 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
Quentin Schulzd242e602017-12-05 15:46:43 +0100396 struct axp20x_pctl *pctl;
Quentin Schulze1190082017-12-05 15:46:46 +0100397 struct device *dev = &pdev->dev;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100398 struct pinctrl_desc *pctrl_desc;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200399 int ret;
400
401 if (!of_device_is_available(pdev->dev.of_node))
402 return -ENODEV;
403
404 if (!axp20x) {
405 dev_err(&pdev->dev, "Parent drvdata not set\n");
406 return -EINVAL;
407 }
408
Quentin Schulzd242e602017-12-05 15:46:43 +0100409 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
410 if (!pctl)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200411 return -ENOMEM;
412
Quentin Schulzd242e602017-12-05 15:46:43 +0100413 pctl->chip.base = -1;
414 pctl->chip.can_sleep = true;
415 pctl->chip.request = gpiochip_generic_request;
416 pctl->chip.free = gpiochip_generic_free;
417 pctl->chip.parent = &pdev->dev;
418 pctl->chip.label = dev_name(&pdev->dev);
419 pctl->chip.owner = THIS_MODULE;
420 pctl->chip.get = axp20x_gpio_get;
421 pctl->chip.get_direction = axp20x_gpio_get_direction;
422 pctl->chip.set = axp20x_gpio_set;
423 pctl->chip.direction_input = axp20x_gpio_input;
424 pctl->chip.direction_output = axp20x_gpio_output;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200425
Julia Lawall9b8ee3c2018-01-02 14:28:04 +0100426 pctl->desc = of_device_get_match_data(dev);
Quentin Schulza0498152017-12-13 09:55:03 +0100427
428 pctl->chip.ngpio = pctl->desc->npins;
429
Quentin Schulzd242e602017-12-05 15:46:43 +0100430 pctl->regmap = axp20x->regmap;
431 pctl->dev = &pdev->dev;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100432
Quentin Schulzd242e602017-12-05 15:46:43 +0100433 platform_set_drvdata(pdev, pctl);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100434
Anton Vasilyev504c7692018-08-06 19:06:35 +0300435 ret = axp20x_build_funcs_groups(pdev);
436 if (ret) {
437 dev_err(&pdev->dev, "failed to build groups\n");
438 return ret;
439 }
Quentin Schulz23f75d72017-12-05 15:46:41 +0100440
441 pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
442 if (!pctrl_desc)
443 return -ENOMEM;
444
445 pctrl_desc->name = dev_name(&pdev->dev);
446 pctrl_desc->owner = THIS_MODULE;
Quentin Schulzd242e602017-12-05 15:46:43 +0100447 pctrl_desc->pins = pctl->desc->pins;
448 pctrl_desc->npins = pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100449 pctrl_desc->pctlops = &axp20x_pctrl_ops;
450 pctrl_desc->pmxops = &axp20x_pmx_ops;
451
Quentin Schulzd242e602017-12-05 15:46:43 +0100452 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
453 if (IS_ERR(pctl->pctl_dev)) {
Quentin Schulz23f75d72017-12-05 15:46:41 +0100454 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
Quentin Schulzd242e602017-12-05 15:46:43 +0100455 return PTR_ERR(pctl->pctl_dev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100456 }
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200457
Quentin Schulzd242e602017-12-05 15:46:43 +0100458 ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200459 if (ret) {
460 dev_err(&pdev->dev, "Failed to register GPIO chip\n");
461 return ret;
462 }
463
Quentin Schulzd242e602017-12-05 15:46:43 +0100464 ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
465 pctl->desc->pins->number,
466 pctl->desc->pins->number,
467 pctl->desc->npins);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100468 if (ret) {
469 dev_err(&pdev->dev, "failed to add pin range\n");
470 return ret;
471 }
472
473 dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200474
475 return 0;
476}
477
Quentin Schulzd242e602017-12-05 15:46:43 +0100478static struct platform_driver axp20x_pctl_driver = {
479 .probe = axp20x_pctl_probe,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200480 .driver = {
481 .name = "axp20x-gpio",
Quentin Schulzd242e602017-12-05 15:46:43 +0100482 .of_match_table = axp20x_pctl_match,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200483 },
484};
485
Quentin Schulzd242e602017-12-05 15:46:43 +0100486module_platform_driver(axp20x_pctl_driver);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200487
488MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
Quentin Schulz23f75d72017-12-05 15:46:41 +0100489MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
490MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200491MODULE_LICENSE("GPL");