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gerrit-public.fairphone.software / kernel / msm-5.4 / d5ff835f88c7c346ba748f389bd4ef5eae619ebc / . / arch / powerpc / include / asm / timex.h
blob: 2cf846edb3fcc4e941e44a8fc032eecd789b22d7 [file] [log] [blame]
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]1#ifndef _ASM_POWERPC_TIMEX_H
2#define _ASM_POWERPC_TIMEX_H
3
4#ifdef __KERNEL__
5
6/*
7 * PowerPC architecture timex specifications
8 */
9
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]10#include <asm/cputable.h>
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]11#include <asm/reg.h>
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]12
Benjamin Herrenschmidtcbd27b82005-10-12 11:39:33 +1000[diff] [blame]13#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]14
15typedef unsigned long cycles_t;
16
17static inline cycles_t get_cycles(void)
18{
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]19#ifdef __powerpc64__
20 return mftb();
21#else
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]22 cycles_t ret;
23
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]24 /*
25 * For the "cycle" counter we use the timebase lower half.
26 * Currently only used on SMP.
27 */
28
29 ret = 0;
30
31 __asm__ __volatile__(
LEROY Christopheae2163b2013-11-22 17:57:31 +0100[diff] [blame]32#ifdef CONFIG_8xx
33 "97: mftb %0\n"
34#else
Scott Woodbeb2dc02013-08-20 19:33:12 -0500[diff] [blame]35 "97: mfspr %0, %2\n"
LEROY Christopheae2163b2013-11-22 17:57:31 +0100[diff] [blame]36#endif
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]37 "99:\n"
38 ".section __ftr_fixup,\"a\"\n"
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]39 ".align 2\n"
40 "98:\n"
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]41 " .long %1\n"
42 " .long 0\n"
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]43 " .long 97b-98b\n"
44 " .long 99b-98b\n"
Michael Ellermanfac23fe2008-06-24 11:32:54 +1000[diff] [blame]45 " .long 0\n"
46 " .long 0\n"
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]47 ".previous"
LEROY Christopheae2163b2013-11-22 17:57:31 +0100[diff] [blame]48#ifdef CONFIG_8xx
49 : "=r" (ret) : "i" (CPU_FTR_601));
50#else
Scott Woodbeb2dc02013-08-20 19:33:12 -0500[diff] [blame]51 : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
LEROY Christopheae2163b2013-11-22 17:57:31 +0100[diff] [blame]52#endif
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]53 return ret;
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]54#endif
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]55}
56
57#endif /* __KERNEL__ */
58#endif /* _ASM_POWERPC_TIMEX_H */