blob: 27911c07558d928b82c82d2a295927da6e4da8e8 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Driver for the Macintosh 68K onboard MACE controller with PSC
3 * driven DMA. The MACE driver code is derived from mace.c. The
4 * Mac68k theory of operation is courtesy of the MacBSD wizards.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Copyright (C) 1996 Paul Mackerras.
12 * Copyright (C) 1998 Alan Cox <alan@redhat.com>
13 *
14 * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver
15 */
16
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/crc32.h>
Akinobu Mitabc63eb92006-12-19 13:09:08 -080025#include <linux/bitrev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/io.h>
27#include <asm/pgtable.h>
28#include <asm/irq.h>
29#include <asm/macintosh.h>
30#include <asm/macints.h>
31#include <asm/mac_psc.h>
32#include <asm/page.h>
33#include "mace.h"
34
35#define N_TX_RING 1
36#define N_RX_RING 8
37#define N_RX_PAGES ((N_RX_RING * 0x0800 + PAGE_SIZE - 1) / PAGE_SIZE)
38#define TX_TIMEOUT HZ
39
40/* Bits in transmit DMA status */
41#define TX_DMA_ERR 0x80
42
43/* The MACE is simply wired down on a Mac68K box */
44
45#define MACE_BASE (void *)(0x50F1C000)
46#define MACE_PROM (void *)(0x50F08001)
47
48struct mace_data {
49 volatile struct mace *mace;
50 volatile unsigned char *tx_ring;
51 volatile unsigned char *tx_ring_phys;
52 volatile unsigned char *rx_ring;
53 volatile unsigned char *rx_ring_phys;
54 int dma_intr;
55 struct net_device_stats stats;
56 int rx_slot, rx_tail;
57 int tx_slot, tx_sloti, tx_count;
58};
59
60struct mace_frame {
61 u16 len;
62 u16 status;
63 u16 rntpc;
64 u16 rcvcc;
65 u32 pad1;
66 u32 pad2;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040067 u8 data[1];
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 /* And frame continues.. */
69};
70
71#define PRIV_BYTES sizeof(struct mace_data)
72
73extern void psc_debug_dump(void);
74
75static int mace_open(struct net_device *dev);
76static int mace_close(struct net_device *dev);
77static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
78static struct net_device_stats *mace_stats(struct net_device *dev);
79static void mace_set_multicast(struct net_device *dev);
80static int mace_set_address(struct net_device *dev, void *addr);
David Howells7d12e782006-10-05 14:55:46 +010081static irqreturn_t mace_interrupt(int irq, void *dev_id);
82static irqreturn_t mace_dma_intr(int irq, void *dev_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -070083static void mace_tx_timeout(struct net_device *dev);
84
Linus Torvalds1da177e2005-04-16 15:20:36 -070085/*
86 * Load a receive DMA channel with a base address and ring length
87 */
88
89static void mace_load_rxdma_base(struct net_device *dev, int set)
90{
91 struct mace_data *mp = (struct mace_data *) dev->priv;
92
93 psc_write_word(PSC_ENETRD_CMD + set, 0x0100);
94 psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys);
95 psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING);
96 psc_write_word(PSC_ENETRD_CMD + set, 0x9800);
97 mp->rx_tail = 0;
98}
99
100/*
101 * Reset the receive DMA subsystem
102 */
103
104static void mace_rxdma_reset(struct net_device *dev)
105{
106 struct mace_data *mp = (struct mace_data *) dev->priv;
107 volatile struct mace *mace = mp->mace;
108 u8 maccc = mace->maccc;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400109
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110 mace->maccc = maccc & ~ENRCV;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400111
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 psc_write_word(PSC_ENETRD_CTL, 0x8800);
113 mace_load_rxdma_base(dev, 0x00);
114 psc_write_word(PSC_ENETRD_CTL, 0x0400);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400115
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116 psc_write_word(PSC_ENETRD_CTL, 0x8800);
117 mace_load_rxdma_base(dev, 0x10);
118 psc_write_word(PSC_ENETRD_CTL, 0x0400);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400119
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 mace->maccc = maccc;
121 mp->rx_slot = 0;
122
123 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);
124 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);
125}
126
127/*
128 * Reset the transmit DMA subsystem
129 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400130
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131static void mace_txdma_reset(struct net_device *dev)
132{
133 struct mace_data *mp = (struct mace_data *) dev->priv;
134 volatile struct mace *mace = mp->mace;
135 u8 maccc;
136
137 psc_write_word(PSC_ENETWR_CTL, 0x8800);
138
139 maccc = mace->maccc;
140 mace->maccc = maccc & ~ENXMT;
141
142 mp->tx_slot = mp->tx_sloti = 0;
143 mp->tx_count = N_TX_RING;
144
145 psc_write_word(PSC_ENETWR_CTL, 0x0400);
146 mace->maccc = maccc;
147}
148
149/*
150 * Disable DMA
151 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400152
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153static void mace_dma_off(struct net_device *dev)
154{
155 psc_write_word(PSC_ENETRD_CTL, 0x8800);
156 psc_write_word(PSC_ENETRD_CTL, 0x1000);
157 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);
158 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);
159
160 psc_write_word(PSC_ENETWR_CTL, 0x8800);
161 psc_write_word(PSC_ENETWR_CTL, 0x1000);
162 psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);
163 psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);
164}
165
166/*
167 * Not really much of a probe. The hardware table tells us if this
168 * model of Macintrash has a MACE (AV macintoshes)
169 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400170
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171struct net_device *mace_probe(int unit)
172{
173 int j;
174 struct mace_data *mp;
175 unsigned char *addr;
176 struct net_device *dev;
177 unsigned char checksum = 0;
178 static int found = 0;
179 int err;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400180
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 if (found || macintosh_config->ether_type != MAC_ETHER_MACE)
182 return ERR_PTR(-ENODEV);
183
184 found = 1; /* prevent 'finding' one on every device probe */
185
186 dev = alloc_etherdev(PRIV_BYTES);
187 if (!dev)
188 return ERR_PTR(-ENOMEM);
189
190 if (unit >= 0)
191 sprintf(dev->name, "eth%d", unit);
192
193 mp = (struct mace_data *) dev->priv;
194 dev->base_addr = (u32)MACE_BASE;
195 mp->mace = (volatile struct mace *) MACE_BASE;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400196
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197 dev->irq = IRQ_MAC_MACE;
198 mp->dma_intr = IRQ_MAC_MACE_DMA;
199
200 /*
201 * The PROM contains 8 bytes which total 0xFF when XOR'd
202 * together. Due to the usual peculiar apple brain damage
203 * the bytes are spaced out in a strange boundary and the
204 * bits are reversed.
205 */
206
207 addr = (void *)MACE_PROM;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400208
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 for (j = 0; j < 6; ++j) {
Akinobu Mitabc63eb92006-12-19 13:09:08 -0800210 u8 v = bitrev8(addr[j<<4]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 checksum ^= v;
212 dev->dev_addr[j] = v;
213 }
214 for (; j < 8; ++j) {
Akinobu Mitabc63eb92006-12-19 13:09:08 -0800215 checksum ^= bitrev8(addr[j<<4]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400217
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218 if (checksum != 0xFF) {
219 free_netdev(dev);
220 return ERR_PTR(-ENODEV);
221 }
222
223 memset(&mp->stats, 0, sizeof(mp->stats));
224
225 dev->open = mace_open;
226 dev->stop = mace_close;
227 dev->hard_start_xmit = mace_xmit_start;
228 dev->tx_timeout = mace_tx_timeout;
229 dev->watchdog_timeo = TX_TIMEOUT;
230 dev->get_stats = mace_stats;
231 dev->set_multicast_list = mace_set_multicast;
232 dev->set_mac_address = mace_set_address;
233
234 printk(KERN_INFO "%s: 68K MACE, hardware address %.2X", dev->name, dev->dev_addr[0]);
235 for (j = 1 ; j < 6 ; j++) printk(":%.2X", dev->dev_addr[j]);
236 printk("\n");
237
238 err = register_netdev(dev);
239 if (!err)
240 return dev;
241
242 free_netdev(dev);
243 return ERR_PTR(err);
244}
245
246/*
247 * Load the address on a mace controller.
248 */
249
250static int mace_set_address(struct net_device *dev, void *addr)
251{
252 unsigned char *p = addr;
253 struct mace_data *mp = (struct mace_data *) dev->priv;
254 volatile struct mace *mb = mp->mace;
255 int i;
256 unsigned long flags;
257 u8 maccc;
258
259 local_irq_save(flags);
260
261 maccc = mb->maccc;
262
263 /* load up the hardware address */
264 mb->iac = ADDRCHG | PHYADDR;
265 while ((mb->iac & ADDRCHG) != 0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400266
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 for (i = 0; i < 6; ++i) {
268 mb->padr = dev->dev_addr[i] = p[i];
269 }
270
271 mb->maccc = maccc;
272 local_irq_restore(flags);
273
274 return 0;
275}
276
277/*
278 * Open the Macintosh MACE. Most of this is playing with the DMA
279 * engine. The ethernet chip is quite friendly.
280 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400281
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282static int mace_open(struct net_device *dev)
283{
284 struct mace_data *mp = (struct mace_data *) dev->priv;
285 volatile struct mace *mb = mp->mace;
286#if 0
287 int i;
288
289 i = 200;
290 while (--i) {
291 mb->biucc = SWRST;
292 if (mb->biucc & SWRST) {
293 udelay(10);
294 continue;
295 }
296 break;
297 }
298 if (!i) {
299 printk(KERN_ERR "%s: software reset failed!!\n", dev->name);
300 return -EAGAIN;
301 }
302#endif
303
304 mb->biucc = XMTSP_64;
305 mb->fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | XMTBRST | RCVBRST;
306 mb->xmtfc = AUTO_PAD_XMIT;
307 mb->plscc = PORTSEL_AUI;
308 /* mb->utr = RTRD; */
309
310 if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {
311 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq);
312 return -EAGAIN;
313 }
314 if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {
315 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr);
316 free_irq(dev->irq, dev);
317 return -EAGAIN;
318 }
319
320 /* Allocate the DMA ring buffers */
321
322 mp->rx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, N_RX_PAGES);
323 mp->tx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, 0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400324
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 if (mp->tx_ring==NULL || mp->rx_ring==NULL) {
326 if (mp->rx_ring) free_pages((u32) mp->rx_ring, N_RX_PAGES);
327 if (mp->tx_ring) free_pages((u32) mp->tx_ring, 0);
328 free_irq(dev->irq, dev);
329 free_irq(mp->dma_intr, dev);
330 printk(KERN_ERR "%s: unable to allocate DMA buffers\n", dev->name);
331 return -ENOMEM;
332 }
333
334 mp->rx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->rx_ring);
335 mp->tx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->tx_ring);
336
337 /* We want the Rx buffer to be uncached and the Tx buffer to be writethrough */
338
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400339 kernel_set_cachemode((void *)mp->rx_ring, N_RX_PAGES * PAGE_SIZE, IOMAP_NOCACHE_NONSER);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 kernel_set_cachemode((void *)mp->tx_ring, PAGE_SIZE, IOMAP_WRITETHROUGH);
341
342 mace_dma_off(dev);
343
344 /* Not sure what these do */
345
346 psc_write_word(PSC_ENETWR_CTL, 0x9000);
347 psc_write_word(PSC_ENETRD_CTL, 0x9000);
348 psc_write_word(PSC_ENETWR_CTL, 0x0400);
349 psc_write_word(PSC_ENETRD_CTL, 0x0400);
350
351#if 0
352 /* load up the hardware address */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400353
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354 mb->iac = ADDRCHG | PHYADDR;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400355
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 while ((mb->iac & ADDRCHG) != 0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400357
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 for (i = 0; i < 6; ++i)
359 mb->padr = dev->dev_addr[i];
360
361 /* clear the multicast filter */
362 mb->iac = ADDRCHG | LOGADDR;
363
364 while ((mb->iac & ADDRCHG) != 0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400365
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 for (i = 0; i < 8; ++i)
367 mb->ladrf = 0;
368
369 mb->plscc = PORTSEL_GPSI + ENPLSIO;
370
371 mb->maccc = ENXMT | ENRCV;
372 mb->imr = RCVINT;
373#endif
374
375 mace_rxdma_reset(dev);
376 mace_txdma_reset(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400377
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 return 0;
379}
380
381/*
382 * Shut down the mace and its interrupt channel
383 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385static int mace_close(struct net_device *dev)
386{
387 struct mace_data *mp = (struct mace_data *) dev->priv;
388 volatile struct mace *mb = mp->mace;
389
390 mb->maccc = 0; /* disable rx and tx */
391 mb->imr = 0xFF; /* disable all irqs */
392 mace_dma_off(dev); /* disable rx and tx dma */
393
394 free_irq(dev->irq, dev);
395 free_irq(IRQ_MAC_MACE_DMA, dev);
396
397 free_pages((u32) mp->rx_ring, N_RX_PAGES);
398 free_pages((u32) mp->tx_ring, 0);
399
400 return 0;
401}
402
403/*
404 * Transmit a frame
405 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400406
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
408{
409 struct mace_data *mp = (struct mace_data *) dev->priv;
410
411 /* Stop the queue if the buffer is full */
412
413 if (!mp->tx_count) {
414 netif_stop_queue(dev);
415 return 1;
416 }
417 mp->tx_count--;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400418
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419 mp->stats.tx_packets++;
420 mp->stats.tx_bytes += skb->len;
421
422 /* We need to copy into our xmit buffer to take care of alignment and caching issues */
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -0300423 skb_copy_from_linear_data(skb, mp->tx_ring, skb->len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424
425 /* load the Tx DMA and fire it off */
426
427 psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys);
428 psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
429 psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);
430
431 mp->tx_slot ^= 0x10;
432
433 dev_kfree_skb(skb);
434
435 return 0;
436}
437
438static struct net_device_stats *mace_stats(struct net_device *dev)
439{
440 struct mace_data *p = (struct mace_data *) dev->priv;
441 return &p->stats;
442}
443
444static void mace_set_multicast(struct net_device *dev)
445{
446 struct mace_data *mp = (struct mace_data *) dev->priv;
447 volatile struct mace *mb = mp->mace;
448 int i, j;
449 u32 crc;
450 u8 maccc;
451
452 maccc = mb->maccc;
453 mb->maccc &= ~PROM;
454
455 if (dev->flags & IFF_PROMISC) {
456 mb->maccc |= PROM;
457 } else {
458 unsigned char multicast_filter[8];
459 struct dev_mc_list *dmi = dev->mc_list;
460
461 if (dev->flags & IFF_ALLMULTI) {
462 for (i = 0; i < 8; i++) {
463 multicast_filter[i] = 0xFF;
464 }
465 } else {
466 for (i = 0; i < 8; i++)
467 multicast_filter[i] = 0;
468 for (i = 0; i < dev->mc_count; i++) {
469 crc = ether_crc_le(6, dmi->dmi_addr);
470 j = crc >> 26; /* bit number in multicast_filter */
471 multicast_filter[j >> 3] |= 1 << (j & 7);
472 dmi = dmi->next;
473 }
474 }
475
476 mb->iac = ADDRCHG | LOGADDR;
477 while (mb->iac & ADDRCHG);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400478
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 for (i = 0; i < 8; ++i) {
480 mb->ladrf = multicast_filter[i];
481 }
482 }
483
484 mb->maccc = maccc;
485}
486
487/*
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400488 * Miscellaneous interrupts are handled here. We may end up
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 * having to bash the chip on the head for bad errors
490 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400491
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
493{
494 volatile struct mace *mb = mp->mace;
495 static int mace_babbles, mace_jabbers;
496
497 if (intr & MPCO) {
498 mp->stats.rx_missed_errors += 256;
499 }
500 mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */
501
502 if (intr & RNTPCO) {
503 mp->stats.rx_length_errors += 256;
504 }
505 mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */
506
507 if (intr & CERR) {
508 ++mp->stats.tx_heartbeat_errors;
509 }
510 if (intr & BABBLE) {
511 if (mace_babbles++ < 4) {
512 printk(KERN_DEBUG "mace: babbling transmitter\n");
513 }
514 }
515 if (intr & JABBER) {
516 if (mace_jabbers++ < 4) {
517 printk(KERN_DEBUG "mace: jabbering transceiver\n");
518 }
519 }
520}
521
522/*
523 * A transmit error has occurred. (We kick the transmit side from
524 * the DMA completion)
525 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400526
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527static void mace_xmit_error(struct net_device *dev)
528{
529 struct mace_data *mp = (struct mace_data *) dev->priv;
530 volatile struct mace *mb = mp->mace;
531 u8 xmtfs, xmtrc;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400532
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 xmtfs = mb->xmtfs;
534 xmtrc = mb->xmtrc;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400535
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 if (xmtfs & XMTSV) {
537 if (xmtfs & UFLO) {
538 printk("%s: DMA underrun.\n", dev->name);
539 mp->stats.tx_errors++;
540 mp->stats.tx_fifo_errors++;
541 mace_txdma_reset(dev);
542 }
543 if (xmtfs & RTRY) {
544 mp->stats.collisions++;
545 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400546 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547}
548
549/*
550 * A receive interrupt occurred.
551 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400552
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553static void mace_recv_interrupt(struct net_device *dev)
554{
555/* struct mace_data *mp = (struct mace_data *) dev->priv; */
556// volatile struct mace *mb = mp->mace;
557}
558
559/*
560 * Process the chip interrupt
561 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400562
David Howells7d12e782006-10-05 14:55:46 +0100563static irqreturn_t mace_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564{
565 struct net_device *dev = (struct net_device *) dev_id;
566 struct mace_data *mp = (struct mace_data *) dev->priv;
567 volatile struct mace *mb = mp->mace;
568 u8 ir;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400569
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570 ir = mb->ir;
571 mace_handle_misc_intrs(mp, ir);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400572
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 if (ir & XMTINT) {
574 mace_xmit_error(dev);
575 }
576 if (ir & RCVINT) {
577 mace_recv_interrupt(dev);
578 }
579 return IRQ_HANDLED;
580}
581
582static void mace_tx_timeout(struct net_device *dev)
583{
584/* struct mace_data *mp = (struct mace_data *) dev->priv; */
585// volatile struct mace *mb = mp->mace;
586}
587
588/*
589 * Handle a newly arrived frame
590 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400591
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
593{
594 struct mace_data *mp = (struct mace_data *) dev->priv;
595 struct sk_buff *skb;
596
597 if (mf->status & RS_OFLO) {
598 printk("%s: fifo overflow.\n", dev->name);
599 mp->stats.rx_errors++;
600 mp->stats.rx_fifo_errors++;
601 }
602 if (mf->status&(RS_CLSN|RS_FRAMERR|RS_FCSERR))
603 mp->stats.rx_errors++;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605 if (mf->status&RS_CLSN) {
606 mp->stats.collisions++;
607 }
608 if (mf->status&RS_FRAMERR) {
609 mp->stats.rx_frame_errors++;
610 }
611 if (mf->status&RS_FCSERR) {
612 mp->stats.rx_crc_errors++;
613 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400614
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 skb = dev_alloc_skb(mf->len+2);
616 if (!skb) {
617 mp->stats.rx_dropped++;
618 return;
619 }
620 skb_reserve(skb,2);
621 memcpy(skb_put(skb, mf->len), mf->data, mf->len);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400622
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623 skb->protocol = eth_type_trans(skb, dev);
624 netif_rx(skb);
625 dev->last_rx = jiffies;
626 mp->stats.rx_packets++;
627 mp->stats.rx_bytes += mf->len;
628}
629
630/*
631 * The PSC has passed us a DMA interrupt event.
632 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400633
David Howells7d12e782006-10-05 14:55:46 +0100634static irqreturn_t mace_dma_intr(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635{
636 struct net_device *dev = (struct net_device *) dev_id;
637 struct mace_data *mp = (struct mace_data *) dev->priv;
638 int left, head;
639 u16 status;
640 u32 baka;
641
642 /* Not sure what this does */
643
644 while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY));
645 if (!(baka & 0x60000000)) return IRQ_NONE;
646
647 /*
648 * Process the read queue
649 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400650
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 status = psc_read_word(PSC_ENETRD_CTL);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400652
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 if (status & 0x2000) {
654 mace_rxdma_reset(dev);
655 } else if (status & 0x0100) {
656 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);
657
658 left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
659 head = N_RX_RING - left;
660
661 /* Loop through the ring buffer and process new packages */
662
663 while (mp->rx_tail < head) {
664 mace_dma_rx_frame(dev, (struct mace_frame *) (mp->rx_ring + (mp->rx_tail * 0x0800)));
665 mp->rx_tail++;
666 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400667
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 /* If we're out of buffers in this ring then switch to */
669 /* the other set, otherwise just reactivate this one. */
670
671 if (!left) {
672 mace_load_rxdma_base(dev, mp->rx_slot);
673 mp->rx_slot ^= 0x10;
674 } else {
675 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);
676 }
677 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400678
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679 /*
680 * Process the write queue
681 */
682
683 status = psc_read_word(PSC_ENETWR_CTL);
684
685 if (status & 0x2000) {
686 mace_txdma_reset(dev);
687 } else if (status & 0x0100) {
688 psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);
689 mp->tx_sloti ^= 0x10;
690 mp->tx_count++;
691 netif_wake_queue(dev);
692 }
693 return IRQ_HANDLED;
694}
695
696MODULE_LICENSE("GPL");