| Dan Liang | 8c83a60 | 2011-03-10 19:08:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Chip-specific header file for the AT91SAM9x5 family |
| 3 | * |
| 4 | * Copyright (C) 2009-2012 Atmel Corporation. |
| 5 | * |
| 6 | * Common definitions. |
| 7 | * Based on AT91SAM9x5 datasheet. |
| 8 | * |
| 9 | * Licensed under GPLv2 or later. |
| 10 | */ |
| 11 | |
| 12 | #ifndef AT91SAM9X5_H |
| 13 | #define AT91SAM9X5_H |
| 14 | |
| 15 | /* |
| 16 | * Peripheral identifiers/interrupts. |
| 17 | */ |
| 18 | #define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */ |
| 19 | #define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */ |
| 20 | #define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */ |
| 21 | #define AT91SAM9X5_ID_USART0 5 /* USART 0 */ |
| 22 | #define AT91SAM9X5_ID_USART1 6 /* USART 1 */ |
| 23 | #define AT91SAM9X5_ID_USART2 7 /* USART 2 */ |
| 24 | #define AT91SAM9X5_ID_USART3 8 /* USART 3 */ |
| 25 | #define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */ |
| 26 | #define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */ |
| 27 | #define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */ |
| 28 | #define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */ |
| 29 | #define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */ |
| 30 | #define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */ |
| 31 | #define AT91SAM9X5_ID_UART0 15 /* UART 0 */ |
| 32 | #define AT91SAM9X5_ID_UART1 16 /* UART 1 */ |
| 33 | #define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ |
| 34 | #define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */ |
| 35 | #define AT91SAM9X5_ID_ADC 19 /* ADC Controller */ |
| 36 | #define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */ |
| 37 | #define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */ |
| 38 | #define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */ |
| 39 | #define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */ |
| 40 | #define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */ |
| 41 | #define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */ |
| 42 | #define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */ |
| 43 | #define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */ |
| 44 | #define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */ |
| 45 | #define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */ |
| 46 | #define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */ |
| 47 | #define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */ |
| 48 | #define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */ |
| 49 | |
| 50 | /* |
| 51 | * User Peripheral physical base addresses. |
| 52 | */ |
| 53 | #define AT91SAM9X5_BASE_USART0 0xf801c000 |
| 54 | #define AT91SAM9X5_BASE_USART1 0xf8020000 |
| 55 | #define AT91SAM9X5_BASE_USART2 0xf8024000 |
| 56 | |
| 57 | /* |
| Dan Liang | 8c83a60 | 2011-03-10 19:08:52 +0100 | [diff] [blame] | 58 | * Base addresses for early serial code (uncompress.h) |
| 59 | */ |
| 60 | #define AT91_DBGU AT91_BASE_DBGU0 |
| 61 | #define AT91_USART0 AT91SAM9X5_BASE_USART0 |
| 62 | #define AT91_USART1 AT91SAM9X5_BASE_USART1 |
| 63 | #define AT91_USART2 AT91SAM9X5_BASE_USART2 |
| 64 | |
| 65 | /* |
| 66 | * Internal Memory. |
| 67 | */ |
| 68 | #define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
| 69 | #define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ |
| 70 | |
| 71 | #define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */ |
| 72 | #define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ |
| 73 | |
| 74 | #endif |