blob: 871acdbeed1a3cfe7129276b0f30e5b28be68bb7 [file] [log] [blame]
Alex Chiang2ceb3fb2009-10-21 21:45:20 -06001What: /sys/devices/system/cpu/
2Date: pre-git history
3Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
4Description:
5 A collection of both global and individual CPU attributes
6
7 Individual CPU attributes are contained in subdirectories
8 named by the kernel's logical CPU number, e.g.:
9
10 /sys/devices/system/cpu/cpu#/
11
12
Alex Chiangd93fc862009-10-21 21:45:25 -060013What: /sys/devices/system/cpu/kernel_max
14 /sys/devices/system/cpu/offline
15 /sys/devices/system/cpu/online
16 /sys/devices/system/cpu/possible
17 /sys/devices/system/cpu/present
18Date: December 2008
19Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
20Description: CPU topology files that describe kernel limits related to
21 hotplug. Briefly:
22
23 kernel_max: the maximum cpu index allowed by the kernel
24 configuration.
25
26 offline: cpus that are not online because they have been
27 HOTPLUGGED off or exceed the limit of cpus allowed by the
28 kernel configuration (kernel_max above).
29
30 online: cpus that are online and being scheduled.
31
32 possible: cpus that have been allocated resources and can be
33 brought online if they are present.
34
35 present: cpus that have been identified as being present in
36 the system.
37
38 See Documentation/cputopology.txt for more information.
39
40
Mark Langsdorf2fad2d92009-04-09 15:31:53 +020041What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
42Date: August 2008
43KernelVersion: 2.6.27
44Contact: mark.langsdorf@amd.com
45Description: These files exist in every cpu's cache index directories.
46 There are currently 2 cache_disable_# files in each
47 directory. Reading from these files on a supported
48 processor will return that cache disable index value
49 for that processor and node. Writing to one of these
50 files will cause the specificed cache index to be disabled.
51
52 Currently, only AMD Family 10h Processors support cache index
53 disable, and only for their L3 caches. See the BIOS and
54 Kernel Developer's Guide at
55 http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
56 for formatting information and other details on the
57 cache index disable.
58Users: joachim.deguara@amd.com