| Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 1 | #ifndef _ASM_X86_INTEL_PUNIT_IPC_H_ |
| 2 | #define _ASM_X86_INTEL_PUNIT_IPC_H_ |
| 3 | |
| 4 | /* |
| 5 | * Three types of 8bit P-Unit IPC commands are supported, |
| 6 | * bit[7:6]: [00]: BIOS; [01]: GTD; [10]: ISPD. |
| 7 | */ |
| 8 | typedef enum { |
| 9 | BIOS_IPC = 0, |
| 10 | GTDRIVER_IPC, |
| 11 | ISPDRIVER_IPC, |
| 12 | RESERVED_IPC, |
| 13 | } IPC_TYPE; |
| 14 | |
| 15 | #define IPC_TYPE_OFFSET 6 |
| 16 | #define IPC_PUNIT_BIOS_CMD_BASE (BIOS_IPC << IPC_TYPE_OFFSET) |
| 17 | #define IPC_PUNIT_GTD_CMD_BASE (GTDDRIVER_IPC << IPC_TYPE_OFFSET) |
| 18 | #define IPC_PUNIT_ISPD_CMD_BASE (ISPDRIVER_IPC << IPC_TYPE_OFFSET) |
| 19 | #define IPC_PUNIT_CMD_TYPE_MASK (RESERVED_IPC << IPC_TYPE_OFFSET) |
| 20 | |
| 21 | /* BIOS => Pcode commands */ |
| 22 | #define IPC_PUNIT_BIOS_ZERO (IPC_PUNIT_BIOS_CMD_BASE | 0x00) |
| 23 | #define IPC_PUNIT_BIOS_VR_INTERFACE (IPC_PUNIT_BIOS_CMD_BASE | 0x01) |
| 24 | #define IPC_PUNIT_BIOS_READ_PCS (IPC_PUNIT_BIOS_CMD_BASE | 0x02) |
| 25 | #define IPC_PUNIT_BIOS_WRITE_PCS (IPC_PUNIT_BIOS_CMD_BASE | 0x03) |
| 26 | #define IPC_PUNIT_BIOS_READ_PCU_CONFIG (IPC_PUNIT_BIOS_CMD_BASE | 0x04) |
| 27 | #define IPC_PUNIT_BIOS_WRITE_PCU_CONFIG (IPC_PUNIT_BIOS_CMD_BASE | 0x05) |
| 28 | #define IPC_PUNIT_BIOS_READ_PL1_SETTING (IPC_PUNIT_BIOS_CMD_BASE | 0x06) |
| 29 | #define IPC_PUNIT_BIOS_WRITE_PL1_SETTING (IPC_PUNIT_BIOS_CMD_BASE | 0x07) |
| 30 | #define IPC_PUNIT_BIOS_TRIGGER_VDD_RAM (IPC_PUNIT_BIOS_CMD_BASE | 0x08) |
| 31 | #define IPC_PUNIT_BIOS_READ_TELE_INFO (IPC_PUNIT_BIOS_CMD_BASE | 0x09) |
| 32 | #define IPC_PUNIT_BIOS_READ_TELE_TRACE_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0a) |
| 33 | #define IPC_PUNIT_BIOS_WRITE_TELE_TRACE_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0b) |
| 34 | #define IPC_PUNIT_BIOS_READ_TELE_EVENT_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0c) |
| 35 | #define IPC_PUNIT_BIOS_WRITE_TELE_EVENT_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0d) |
| 36 | #define IPC_PUNIT_BIOS_READ_TELE_TRACE (IPC_PUNIT_BIOS_CMD_BASE | 0x0e) |
| 37 | #define IPC_PUNIT_BIOS_WRITE_TELE_TRACE (IPC_PUNIT_BIOS_CMD_BASE | 0x0f) |
| 38 | #define IPC_PUNIT_BIOS_READ_TELE_EVENT (IPC_PUNIT_BIOS_CMD_BASE | 0x10) |
| 39 | #define IPC_PUNIT_BIOS_WRITE_TELE_EVENT (IPC_PUNIT_BIOS_CMD_BASE | 0x11) |
| 40 | #define IPC_PUNIT_BIOS_READ_MODULE_TEMP (IPC_PUNIT_BIOS_CMD_BASE | 0x12) |
| 41 | #define IPC_PUNIT_BIOS_RESERVED (IPC_PUNIT_BIOS_CMD_BASE | 0x13) |
| 42 | #define IPC_PUNIT_BIOS_READ_VOLTAGE_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x14) |
| 43 | #define IPC_PUNIT_BIOS_WRITE_VOLTAGE_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x15) |
| 44 | #define IPC_PUNIT_BIOS_READ_RATIO_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x16) |
| 45 | #define IPC_PUNIT_BIOS_WRITE_RATIO_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x17) |
| 46 | #define IPC_PUNIT_BIOS_READ_VF_GL_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x18) |
| 47 | #define IPC_PUNIT_BIOS_WRITE_VF_GL_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x19) |
| 48 | #define IPC_PUNIT_BIOS_READ_FM_SOC_TEMP_THRESH (IPC_PUNIT_BIOS_CMD_BASE | 0x1a) |
| 49 | #define IPC_PUNIT_BIOS_WRITE_FM_SOC_TEMP_THRESH (IPC_PUNIT_BIOS_CMD_BASE | 0x1b) |
| 50 | |
| 51 | /* GT Driver => Pcode commands */ |
| 52 | #define IPC_PUNIT_GTD_ZERO (IPC_PUNIT_GTD_CMD_BASE | 0x00) |
| 53 | #define IPC_PUNIT_GTD_CONFIG (IPC_PUNIT_GTD_CMD_BASE | 0x01) |
| 54 | #define IPC_PUNIT_GTD_READ_ICCP_LIC_CDYN_SCAL (IPC_PUNIT_GTD_CMD_BASE | 0x02) |
| 55 | #define IPC_PUNIT_GTD_WRITE_ICCP_LIC_CDYN_SCAL (IPC_PUNIT_GTD_CMD_BASE | 0x03) |
| 56 | #define IPC_PUNIT_GTD_GET_WM_VAL (IPC_PUNIT_GTD_CMD_BASE | 0x06) |
| 57 | #define IPC_PUNIT_GTD_WRITE_CONFIG_WISHREQ (IPC_PUNIT_GTD_CMD_BASE | 0x07) |
| 58 | #define IPC_PUNIT_GTD_READ_REQ_DUTY_CYCLE (IPC_PUNIT_GTD_CMD_BASE | 0x16) |
| 59 | #define IPC_PUNIT_GTD_DIS_VOL_FREQ_CHG_REQUEST (IPC_PUNIT_GTD_CMD_BASE | 0x17) |
| 60 | #define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_CTRL (IPC_PUNIT_GTD_CMD_BASE | 0x1a) |
| 61 | #define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_TUNING (IPC_PUNIT_GTD_CMD_BASE | 0x1c) |
| 62 | |
| 63 | /* ISP Driver => Pcode commands */ |
| 64 | #define IPC_PUNIT_ISPD_ZERO (IPC_PUNIT_ISPD_CMD_BASE | 0x00) |
| 65 | #define IPC_PUNIT_ISPD_CONFIG (IPC_PUNIT_ISPD_CMD_BASE | 0x01) |
| 66 | #define IPC_PUNIT_ISPD_GET_ISP_LTR_VAL (IPC_PUNIT_ISPD_CMD_BASE | 0x02) |
| 67 | #define IPC_PUNIT_ISPD_ACCESS_IU_FREQ_BOUNDS (IPC_PUNIT_ISPD_CMD_BASE | 0x03) |
| 68 | #define IPC_PUNIT_ISPD_READ_CDYN_LEVEL (IPC_PUNIT_ISPD_CMD_BASE | 0x04) |
| 69 | #define IPC_PUNIT_ISPD_WRITE_CDYN_LEVEL (IPC_PUNIT_ISPD_CMD_BASE | 0x05) |
| 70 | |
| 71 | /* Error codes */ |
| 72 | #define IPC_PUNIT_ERR_SUCCESS 0 |
| 73 | #define IPC_PUNIT_ERR_INVALID_CMD 1 |
| 74 | #define IPC_PUNIT_ERR_INVALID_PARAMETER 2 |
| 75 | #define IPC_PUNIT_ERR_CMD_TIMEOUT 3 |
| 76 | #define IPC_PUNIT_ERR_CMD_LOCKED 4 |
| 77 | #define IPC_PUNIT_ERR_INVALID_VR_ID 5 |
| 78 | #define IPC_PUNIT_ERR_VR_ERR 6 |
| 79 | |
| 80 | #if IS_ENABLED(CONFIG_INTEL_PUNIT_IPC) |
| 81 | |
| 82 | int intel_punit_ipc_simple_command(int cmd, int para1, int para2); |
| 83 | int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out); |
| 84 | |
| 85 | #else |
| 86 | |
| 87 | static inline int intel_punit_ipc_simple_command(int cmd, |
| 88 | int para1, int para2) |
| 89 | { |
| 90 | return -ENODEV; |
| 91 | } |
| 92 | |
| 93 | static inline int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, |
| 94 | u32 *in, u32 *out) |
| 95 | { |
| 96 | return -ENODEV; |
| 97 | } |
| 98 | |
| 99 | #endif /* CONFIG_INTEL_PUNIT_IPC */ |
| 100 | |
| 101 | #endif |