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gerrit-public.fairphone.software / kernel / msm-5.4 / dd040f76cef0cc977b83e905a16b68d41322b735 / . / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob: 76508f82f8594e3459fcb64963a8a8f036e206ae [file] [log] [blame]
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_phy.h"
19#include "ar9003_eeprom.h"
20
21#define COMP_HDR_LEN 4
22#define COMP_CKSUM_LEN 2
23
24#define AR_CH0_TOP (0x00016288)
Vasanthakumar Thiagarajan52a0e242010-11-10 05:03:11 -0800[diff] [blame]25#define AR_CH0_TOP_XPABIASLVL (0x300)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]26#define AR_CH0_TOP_XPABIASLVL_S (8)
27
28#define AR_CH0_THERM (0x00016290)
Vasanthakumar Thiagarajan52a0e242010-11-10 05:03:11 -0800[diff] [blame]29#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
30#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
31#define AR_CH0_THERM_XPASHORT2GND 0x4
32#define AR_CH0_THERM_XPASHORT2GND_S 2
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]33
34#define AR_SWITCH_TABLE_COM_ALL (0xffff)
35#define AR_SWITCH_TABLE_COM_ALL_S (0)
36
37#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
38#define AR_SWITCH_TABLE_COM2_ALL_S (0)
39
40#define AR_SWITCH_TABLE_ALL (0xfff)
41#define AR_SWITCH_TABLE_ALL_S (0)
42
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]43#define LE16(x) __constant_cpu_to_le16(x)
44#define LE32(x) __constant_cpu_to_le32(x)
45
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]46/* Local defines to distinguish between extension and control CTL's */
47#define EXT_ADDITIVE (0x8000)
48#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
49#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
50#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
51#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
52#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
53#define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
54#define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
55#define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
56
57#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
58#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
59
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]60#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
61
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]62static int ar9003_hw_power_interpolate(int32_t x,
63 int32_t *px, int32_t *py, u_int16_t np);
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]64
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]65static const struct ar9300_eeprom ar9300_default = {
66 .eepromVersion = 2,
67 .templateVersion = 2,
68 .macAddr = {1, 2, 3, 4, 5, 6},
69 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
70 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
71 .baseEepHeader = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]72 .regDmn = { LE16(0), LE16(0x1f) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]73 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
74 .opCapFlags = {
75 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
76 .eepMisc = 0,
77 },
78 .rfSilent = 0,
79 .blueToothOptions = 0,
80 .deviceCap = 0,
81 .deviceType = 5, /* takes lower byte in eeprom location */
82 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
83 .params_for_tuning_caps = {0, 0},
84 .featureEnable = 0x0c,
85 /*
86 * bit0 - enable tx temp comp - disabled
87 * bit1 - enable tx volt comp - disabled
88 * bit2 - enable fastClock - enabled
89 * bit3 - enable doubling - enabled
90 * bit4 - enable internal regulator - disabled
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]91 * bit5 - enable pa predistortion - disabled
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]92 */
93 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
94 .eepromWriteEnableGpio = 3,
95 .wlanDisableGpio = 0,
96 .wlanLedGpio = 8,
97 .rxBandSelectGpio = 0xff,
98 .txrxgain = 0,
99 .swreg = 0,
100 },
101 .modalHeader2G = {
102 /* ar9300_modal_eep_header 2g */
103 /* 4 idle,t1,t2,b(4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]104 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]105 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]106 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]107
108 /*
109 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
110 * rx1, rx12, b (2 bits each)
111 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]112 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]113
114 /*
115 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
116 * for ar9280 (0xa20c/b20c 5:0)
117 */
118 .xatten1DB = {0, 0, 0},
119
120 /*
121 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
122 * for ar9280 (0xa20c/b20c 16:12
123 */
124 .xatten1Margin = {0, 0, 0},
125 .tempSlope = 36,
126 .voltSlope = 0,
127
128 /*
129 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
130 * channels in usual fbin coding format
131 */
132 .spurChans = {0, 0, 0, 0, 0},
133
134 /*
135 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
136 * if the register is per chain
137 */
138 .noiseFloorThreshCh = {-1, 0, 0},
139 .ob = {1, 1, 1},/* 3 chain */
140 .db_stage2 = {1, 1, 1}, /* 3 chain */
141 .db_stage3 = {0, 0, 0},
142 .db_stage4 = {0, 0, 0},
143 .xpaBiasLvl = 0,
144 .txFrameToDataStart = 0x0e,
145 .txFrameToPaOn = 0x0e,
146 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
147 .antennaGain = 0,
148 .switchSettling = 0x2c,
149 .adcDesiredSize = -30,
150 .txEndToXpaOff = 0,
151 .txEndToRxOn = 0x2,
152 .txFrameToXpaOn = 0xe,
153 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]154 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
155 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]156 .futureModal = {
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]157 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]158 },
159 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]160 .base_ext1 = {
161 .ant_div_control = 0,
162 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
163 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]164 .calFreqPier2G = {
165 FREQ2FBIN(2412, 1),
166 FREQ2FBIN(2437, 1),
167 FREQ2FBIN(2472, 1),
168 },
169 /* ar9300_cal_data_per_freq_op_loop 2g */
170 .calPierData2G = {
171 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
172 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
173 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
174 },
175 .calTarget_freqbin_Cck = {
176 FREQ2FBIN(2412, 1),
177 FREQ2FBIN(2484, 1),
178 },
179 .calTarget_freqbin_2G = {
180 FREQ2FBIN(2412, 1),
181 FREQ2FBIN(2437, 1),
182 FREQ2FBIN(2472, 1)
183 },
184 .calTarget_freqbin_2GHT20 = {
185 FREQ2FBIN(2412, 1),
186 FREQ2FBIN(2437, 1),
187 FREQ2FBIN(2472, 1)
188 },
189 .calTarget_freqbin_2GHT40 = {
190 FREQ2FBIN(2412, 1),
191 FREQ2FBIN(2437, 1),
192 FREQ2FBIN(2472, 1)
193 },
194 .calTargetPowerCck = {
195 /* 1L-5L,5S,11L,11S */
196 { {36, 36, 36, 36} },
197 { {36, 36, 36, 36} },
198 },
199 .calTargetPower2G = {
200 /* 6-24,36,48,54 */
201 { {32, 32, 28, 24} },
202 { {32, 32, 28, 24} },
203 { {32, 32, 28, 24} },
204 },
205 .calTargetPower2GHT20 = {
206 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
207 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
208 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
209 },
210 .calTargetPower2GHT40 = {
211 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
212 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
213 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
214 },
215 .ctlIndex_2G = {
216 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
217 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
218 },
219 .ctl_freqbin_2G = {
220 {
221 FREQ2FBIN(2412, 1),
222 FREQ2FBIN(2417, 1),
223 FREQ2FBIN(2457, 1),
224 FREQ2FBIN(2462, 1)
225 },
226 {
227 FREQ2FBIN(2412, 1),
228 FREQ2FBIN(2417, 1),
229 FREQ2FBIN(2462, 1),
230 0xFF,
231 },
232
233 {
234 FREQ2FBIN(2412, 1),
235 FREQ2FBIN(2417, 1),
236 FREQ2FBIN(2462, 1),
237 0xFF,
238 },
239 {
240 FREQ2FBIN(2422, 1),
241 FREQ2FBIN(2427, 1),
242 FREQ2FBIN(2447, 1),
243 FREQ2FBIN(2452, 1)
244 },
245
246 {
247 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
248 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
249 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
250 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
251 },
252
253 {
254 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
255 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
256 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
257 0,
258 },
259
260 {
261 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
262 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
263 FREQ2FBIN(2472, 1),
264 0,
265 },
266
267 {
268 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
269 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
270 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
271 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
272 },
273
274 {
275 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
276 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
277 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
278 },
279
280 {
281 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
282 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
283 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
284 0
285 },
286
287 {
288 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
289 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
290 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
291 0
292 },
293
294 {
295 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
296 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
297 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]298 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]299 }
300 },
301 .ctlPowerData_2G = {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]302 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
303 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
304 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]305
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]306 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
307 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
308 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]309
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]310 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
311 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
312 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]313
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]314 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
315 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
316 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]317 },
318 .modalHeader5G = {
319 /* 4 idle,t1,t2,b (4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]320 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]321 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]322 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]323 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
324 .antCtrlChain = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]325 LE16(0x000), LE16(0x000), LE16(0x000),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]326 },
327 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
328 .xatten1DB = {0, 0, 0},
329
330 /*
331 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
332 * for merlin (0xa20c/b20c 16:12
333 */
334 .xatten1Margin = {0, 0, 0},
335 .tempSlope = 68,
336 .voltSlope = 0,
337 /* spurChans spur channels in usual fbin coding format */
338 .spurChans = {0, 0, 0, 0, 0},
339 /* noiseFloorThreshCh Check if the register is per chain */
340 .noiseFloorThreshCh = {-1, 0, 0},
341 .ob = {3, 3, 3}, /* 3 chain */
342 .db_stage2 = {3, 3, 3}, /* 3 chain */
343 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
344 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
345 .xpaBiasLvl = 0,
346 .txFrameToDataStart = 0x0e,
347 .txFrameToPaOn = 0x0e,
348 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
349 .antennaGain = 0,
350 .switchSettling = 0x2d,
351 .adcDesiredSize = -30,
352 .txEndToXpaOff = 0,
353 .txEndToRxOn = 0x2,
354 .txFrameToXpaOn = 0xe,
355 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]356 .papdRateMaskHt20 = LE32(0x0c80c080),
357 .papdRateMaskHt40 = LE32(0x0080c080),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]358 .futureModal = {
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]359 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]360 },
361 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]362 .base_ext2 = {
363 .tempSlopeLow = 0,
364 .tempSlopeHigh = 0,
365 .xatten1DBLow = {0, 0, 0},
366 .xatten1MarginLow = {0, 0, 0},
367 .xatten1DBHigh = {0, 0, 0},
368 .xatten1MarginHigh = {0, 0, 0}
369 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]370 .calFreqPier5G = {
371 FREQ2FBIN(5180, 0),
372 FREQ2FBIN(5220, 0),
373 FREQ2FBIN(5320, 0),
374 FREQ2FBIN(5400, 0),
375 FREQ2FBIN(5500, 0),
376 FREQ2FBIN(5600, 0),
377 FREQ2FBIN(5725, 0),
378 FREQ2FBIN(5825, 0)
379 },
380 .calPierData5G = {
381 {
382 {0, 0, 0, 0, 0},
383 {0, 0, 0, 0, 0},
384 {0, 0, 0, 0, 0},
385 {0, 0, 0, 0, 0},
386 {0, 0, 0, 0, 0},
387 {0, 0, 0, 0, 0},
388 {0, 0, 0, 0, 0},
389 {0, 0, 0, 0, 0},
390 },
391 {
392 {0, 0, 0, 0, 0},
393 {0, 0, 0, 0, 0},
394 {0, 0, 0, 0, 0},
395 {0, 0, 0, 0, 0},
396 {0, 0, 0, 0, 0},
397 {0, 0, 0, 0, 0},
398 {0, 0, 0, 0, 0},
399 {0, 0, 0, 0, 0},
400 },
401 {
402 {0, 0, 0, 0, 0},
403 {0, 0, 0, 0, 0},
404 {0, 0, 0, 0, 0},
405 {0, 0, 0, 0, 0},
406 {0, 0, 0, 0, 0},
407 {0, 0, 0, 0, 0},
408 {0, 0, 0, 0, 0},
409 {0, 0, 0, 0, 0},
410 },
411
412 },
413 .calTarget_freqbin_5G = {
414 FREQ2FBIN(5180, 0),
415 FREQ2FBIN(5220, 0),
416 FREQ2FBIN(5320, 0),
417 FREQ2FBIN(5400, 0),
418 FREQ2FBIN(5500, 0),
419 FREQ2FBIN(5600, 0),
420 FREQ2FBIN(5725, 0),
421 FREQ2FBIN(5825, 0)
422 },
423 .calTarget_freqbin_5GHT20 = {
424 FREQ2FBIN(5180, 0),
425 FREQ2FBIN(5240, 0),
426 FREQ2FBIN(5320, 0),
427 FREQ2FBIN(5500, 0),
428 FREQ2FBIN(5700, 0),
429 FREQ2FBIN(5745, 0),
430 FREQ2FBIN(5725, 0),
431 FREQ2FBIN(5825, 0)
432 },
433 .calTarget_freqbin_5GHT40 = {
434 FREQ2FBIN(5180, 0),
435 FREQ2FBIN(5240, 0),
436 FREQ2FBIN(5320, 0),
437 FREQ2FBIN(5500, 0),
438 FREQ2FBIN(5700, 0),
439 FREQ2FBIN(5745, 0),
440 FREQ2FBIN(5725, 0),
441 FREQ2FBIN(5825, 0)
442 },
443 .calTargetPower5G = {
444 /* 6-24,36,48,54 */
445 { {20, 20, 20, 10} },
446 { {20, 20, 20, 10} },
447 { {20, 20, 20, 10} },
448 { {20, 20, 20, 10} },
449 { {20, 20, 20, 10} },
450 { {20, 20, 20, 10} },
451 { {20, 20, 20, 10} },
452 { {20, 20, 20, 10} },
453 },
454 .calTargetPower5GHT20 = {
455 /*
456 * 0_8_16,1-3_9-11_17-19,
457 * 4,5,6,7,12,13,14,15,20,21,22,23
458 */
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
464 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
465 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
466 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
467 },
468 .calTargetPower5GHT40 = {
469 /*
470 * 0_8_16,1-3_9-11_17-19,
471 * 4,5,6,7,12,13,14,15,20,21,22,23
472 */
473 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
474 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
475 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
476 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
477 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
478 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
479 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
480 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
481 },
482 .ctlIndex_5G = {
483 0x10, 0x16, 0x18, 0x40, 0x46,
484 0x48, 0x30, 0x36, 0x38
485 },
486 .ctl_freqbin_5G = {
487 {
488 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
489 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
490 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
491 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
492 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
493 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
494 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
495 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
496 },
497 {
498 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
499 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
500 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
501 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
502 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
503 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
504 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
505 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
506 },
507
508 {
509 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
510 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
511 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
512 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
513 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
514 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
515 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
516 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
517 },
518
519 {
520 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
521 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
522 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
523 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
524 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
525 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
526 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
527 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
528 },
529
530 {
531 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
532 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
533 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
534 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
535 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
536 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
537 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
538 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
539 },
540
541 {
542 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
543 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
544 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
545 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
546 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
547 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
548 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
549 /* Data[5].ctlEdges[7].bChannel */ 0xFF
550 },
551
552 {
553 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
554 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
555 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
556 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
557 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
558 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
559 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
560 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
561 },
562
563 {
564 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
565 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
566 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
567 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
568 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
569 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
570 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
571 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
572 },
573
574 {
575 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
576 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
577 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
578 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
579 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
580 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
581 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
582 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
583 }
584 },
585 .ctlPowerData_5G = {
586 {
587 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]588 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
589 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]590 }
591 },
592 {
593 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]594 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
595 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]596 }
597 },
598 {
599 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]600 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
601 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]602 }
603 },
604 {
605 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]606 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
607 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]608 }
609 },
610 {
611 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]612 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
613 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]614 }
615 },
616 {
617 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]618 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
619 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]620 }
621 },
622 {
623 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]624 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
625 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]626 }
627 },
628 {
629 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]630 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
631 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]632 }
633 },
634 {
635 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]636 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
637 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]638 }
639 },
640 }
641};
642
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]643static const struct ar9300_eeprom ar9300_x113 = {
644 .eepromVersion = 2,
645 .templateVersion = 6,
646 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
647 .custData = {"x113-023-f0000"},
648 .baseEepHeader = {
649 .regDmn = { LE16(0), LE16(0x1f) },
650 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
651 .opCapFlags = {
652 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
653 .eepMisc = 0,
654 },
655 .rfSilent = 0,
656 .blueToothOptions = 0,
657 .deviceCap = 0,
658 .deviceType = 5, /* takes lower byte in eeprom location */
659 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
660 .params_for_tuning_caps = {0, 0},
661 .featureEnable = 0x0d,
662 /*
663 * bit0 - enable tx temp comp - disabled
664 * bit1 - enable tx volt comp - disabled
665 * bit2 - enable fastClock - enabled
666 * bit3 - enable doubling - enabled
667 * bit4 - enable internal regulator - disabled
668 * bit5 - enable pa predistortion - disabled
669 */
670 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
671 .eepromWriteEnableGpio = 6,
672 .wlanDisableGpio = 0,
673 .wlanLedGpio = 8,
674 .rxBandSelectGpio = 0xff,
675 .txrxgain = 0x21,
676 .swreg = 0,
677 },
678 .modalHeader2G = {
679 /* ar9300_modal_eep_header 2g */
680 /* 4 idle,t1,t2,b(4 bits per setting) */
681 .antCtrlCommon = LE32(0x110),
682 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
683 .antCtrlCommon2 = LE32(0x44444),
684
685 /*
686 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
687 * rx1, rx12, b (2 bits each)
688 */
689 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
690
691 /*
692 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
693 * for ar9280 (0xa20c/b20c 5:0)
694 */
695 .xatten1DB = {0, 0, 0},
696
697 /*
698 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
699 * for ar9280 (0xa20c/b20c 16:12
700 */
701 .xatten1Margin = {0, 0, 0},
702 .tempSlope = 25,
703 .voltSlope = 0,
704
705 /*
706 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
707 * channels in usual fbin coding format
708 */
709 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
710
711 /*
712 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
713 * if the register is per chain
714 */
715 .noiseFloorThreshCh = {-1, 0, 0},
716 .ob = {1, 1, 1},/* 3 chain */
717 .db_stage2 = {1, 1, 1}, /* 3 chain */
718 .db_stage3 = {0, 0, 0},
719 .db_stage4 = {0, 0, 0},
720 .xpaBiasLvl = 0,
721 .txFrameToDataStart = 0x0e,
722 .txFrameToPaOn = 0x0e,
723 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
724 .antennaGain = 0,
725 .switchSettling = 0x2c,
726 .adcDesiredSize = -30,
727 .txEndToXpaOff = 0,
728 .txEndToRxOn = 0x2,
729 .txFrameToXpaOn = 0xe,
730 .thresh62 = 28,
731 .papdRateMaskHt20 = LE32(0x0c80c080),
732 .papdRateMaskHt40 = LE32(0x0080c080),
733 .futureModal = {
734 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
735 },
736 },
737 .base_ext1 = {
738 .ant_div_control = 0,
739 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
740 },
741 .calFreqPier2G = {
742 FREQ2FBIN(2412, 1),
743 FREQ2FBIN(2437, 1),
744 FREQ2FBIN(2472, 1),
745 },
746 /* ar9300_cal_data_per_freq_op_loop 2g */
747 .calPierData2G = {
748 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
749 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
750 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
751 },
752 .calTarget_freqbin_Cck = {
753 FREQ2FBIN(2412, 1),
754 FREQ2FBIN(2472, 1),
755 },
756 .calTarget_freqbin_2G = {
757 FREQ2FBIN(2412, 1),
758 FREQ2FBIN(2437, 1),
759 FREQ2FBIN(2472, 1)
760 },
761 .calTarget_freqbin_2GHT20 = {
762 FREQ2FBIN(2412, 1),
763 FREQ2FBIN(2437, 1),
764 FREQ2FBIN(2472, 1)
765 },
766 .calTarget_freqbin_2GHT40 = {
767 FREQ2FBIN(2412, 1),
768 FREQ2FBIN(2437, 1),
769 FREQ2FBIN(2472, 1)
770 },
771 .calTargetPowerCck = {
772 /* 1L-5L,5S,11L,11S */
773 { {34, 34, 34, 34} },
774 { {34, 34, 34, 34} },
775 },
776 .calTargetPower2G = {
777 /* 6-24,36,48,54 */
778 { {34, 34, 32, 32} },
779 { {34, 34, 32, 32} },
780 { {34, 34, 32, 32} },
781 },
782 .calTargetPower2GHT20 = {
783 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
784 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
785 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
786 },
787 .calTargetPower2GHT40 = {
788 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
789 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
790 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
791 },
792 .ctlIndex_2G = {
793 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
794 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
795 },
796 .ctl_freqbin_2G = {
797 {
798 FREQ2FBIN(2412, 1),
799 FREQ2FBIN(2417, 1),
800 FREQ2FBIN(2457, 1),
801 FREQ2FBIN(2462, 1)
802 },
803 {
804 FREQ2FBIN(2412, 1),
805 FREQ2FBIN(2417, 1),
806 FREQ2FBIN(2462, 1),
807 0xFF,
808 },
809
810 {
811 FREQ2FBIN(2412, 1),
812 FREQ2FBIN(2417, 1),
813 FREQ2FBIN(2462, 1),
814 0xFF,
815 },
816 {
817 FREQ2FBIN(2422, 1),
818 FREQ2FBIN(2427, 1),
819 FREQ2FBIN(2447, 1),
820 FREQ2FBIN(2452, 1)
821 },
822
823 {
824 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
825 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
826 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
827 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
828 },
829
830 {
831 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
832 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
833 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
834 0,
835 },
836
837 {
838 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
839 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
840 FREQ2FBIN(2472, 1),
841 0,
842 },
843
844 {
845 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
846 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
847 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
848 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
849 },
850
851 {
852 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
853 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
854 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
855 },
856
857 {
858 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
859 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
860 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
861 0
862 },
863
864 {
865 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
866 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
867 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
868 0
869 },
870
871 {
872 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
873 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
874 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
875 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
876 }
877 },
878 .ctlPowerData_2G = {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]879 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
880 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
881 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]882
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]883 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
884 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
885 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]886
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]887 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
888 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
889 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]890
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]891 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
892 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
893 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]894 },
895 .modalHeader5G = {
896 /* 4 idle,t1,t2,b (4 bits per setting) */
897 .antCtrlCommon = LE32(0x220),
898 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
899 .antCtrlCommon2 = LE32(0x11111),
900 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
901 .antCtrlChain = {
902 LE16(0x150), LE16(0x150), LE16(0x150),
903 },
904 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
905 .xatten1DB = {0, 0, 0},
906
907 /*
908 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
909 * for merlin (0xa20c/b20c 16:12
910 */
911 .xatten1Margin = {0, 0, 0},
912 .tempSlope = 68,
913 .voltSlope = 0,
914 /* spurChans spur channels in usual fbin coding format */
915 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
916 /* noiseFloorThreshCh Check if the register is per chain */
917 .noiseFloorThreshCh = {-1, 0, 0},
918 .ob = {3, 3, 3}, /* 3 chain */
919 .db_stage2 = {3, 3, 3}, /* 3 chain */
920 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
921 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
922 .xpaBiasLvl = 0,
923 .txFrameToDataStart = 0x0e,
924 .txFrameToPaOn = 0x0e,
925 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
926 .antennaGain = 0,
927 .switchSettling = 0x2d,
928 .adcDesiredSize = -30,
929 .txEndToXpaOff = 0,
930 .txEndToRxOn = 0x2,
931 .txFrameToXpaOn = 0xe,
932 .thresh62 = 28,
933 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
934 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
935 .futureModal = {
936 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
937 },
938 },
939 .base_ext2 = {
940 .tempSlopeLow = 72,
941 .tempSlopeHigh = 105,
942 .xatten1DBLow = {0, 0, 0},
943 .xatten1MarginLow = {0, 0, 0},
944 .xatten1DBHigh = {0, 0, 0},
945 .xatten1MarginHigh = {0, 0, 0}
946 },
947 .calFreqPier5G = {
948 FREQ2FBIN(5180, 0),
949 FREQ2FBIN(5240, 0),
950 FREQ2FBIN(5320, 0),
951 FREQ2FBIN(5400, 0),
952 FREQ2FBIN(5500, 0),
953 FREQ2FBIN(5600, 0),
954 FREQ2FBIN(5745, 0),
955 FREQ2FBIN(5785, 0)
956 },
957 .calPierData5G = {
958 {
959 {0, 0, 0, 0, 0},
960 {0, 0, 0, 0, 0},
961 {0, 0, 0, 0, 0},
962 {0, 0, 0, 0, 0},
963 {0, 0, 0, 0, 0},
964 {0, 0, 0, 0, 0},
965 {0, 0, 0, 0, 0},
966 {0, 0, 0, 0, 0},
967 },
968 {
969 {0, 0, 0, 0, 0},
970 {0, 0, 0, 0, 0},
971 {0, 0, 0, 0, 0},
972 {0, 0, 0, 0, 0},
973 {0, 0, 0, 0, 0},
974 {0, 0, 0, 0, 0},
975 {0, 0, 0, 0, 0},
976 {0, 0, 0, 0, 0},
977 },
978 {
979 {0, 0, 0, 0, 0},
980 {0, 0, 0, 0, 0},
981 {0, 0, 0, 0, 0},
982 {0, 0, 0, 0, 0},
983 {0, 0, 0, 0, 0},
984 {0, 0, 0, 0, 0},
985 {0, 0, 0, 0, 0},
986 {0, 0, 0, 0, 0},
987 },
988
989 },
990 .calTarget_freqbin_5G = {
991 FREQ2FBIN(5180, 0),
992 FREQ2FBIN(5220, 0),
993 FREQ2FBIN(5320, 0),
994 FREQ2FBIN(5400, 0),
995 FREQ2FBIN(5500, 0),
996 FREQ2FBIN(5600, 0),
997 FREQ2FBIN(5745, 0),
998 FREQ2FBIN(5785, 0)
999 },
1000 .calTarget_freqbin_5GHT20 = {
1001 FREQ2FBIN(5180, 0),
1002 FREQ2FBIN(5240, 0),
1003 FREQ2FBIN(5320, 0),
1004 FREQ2FBIN(5400, 0),
1005 FREQ2FBIN(5500, 0),
1006 FREQ2FBIN(5700, 0),
1007 FREQ2FBIN(5745, 0),
1008 FREQ2FBIN(5825, 0)
1009 },
1010 .calTarget_freqbin_5GHT40 = {
1011 FREQ2FBIN(5190, 0),
1012 FREQ2FBIN(5230, 0),
1013 FREQ2FBIN(5320, 0),
1014 FREQ2FBIN(5410, 0),
1015 FREQ2FBIN(5510, 0),
1016 FREQ2FBIN(5670, 0),
1017 FREQ2FBIN(5755, 0),
1018 FREQ2FBIN(5825, 0)
1019 },
1020 .calTargetPower5G = {
1021 /* 6-24,36,48,54 */
1022 { {42, 40, 40, 34} },
1023 { {42, 40, 40, 34} },
1024 { {42, 40, 40, 34} },
1025 { {42, 40, 40, 34} },
1026 { {42, 40, 40, 34} },
1027 { {42, 40, 40, 34} },
1028 { {42, 40, 40, 34} },
1029 { {42, 40, 40, 34} },
1030 },
1031 .calTargetPower5GHT20 = {
1032 /*
1033 * 0_8_16,1-3_9-11_17-19,
1034 * 4,5,6,7,12,13,14,15,20,21,22,23
1035 */
1036 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1037 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1038 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1039 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1040 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1041 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1042 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1043 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1044 },
1045 .calTargetPower5GHT40 = {
1046 /*
1047 * 0_8_16,1-3_9-11_17-19,
1048 * 4,5,6,7,12,13,14,15,20,21,22,23
1049 */
1050 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1051 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1052 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1053 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1054 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1055 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1056 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1057 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1058 },
1059 .ctlIndex_5G = {
1060 0x10, 0x16, 0x18, 0x40, 0x46,
1061 0x48, 0x30, 0x36, 0x38
1062 },
1063 .ctl_freqbin_5G = {
1064 {
1065 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1066 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1067 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1068 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1069 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1070 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1071 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1072 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1073 },
1074 {
1075 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1076 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1077 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1078 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1079 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1080 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1081 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1082 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1083 },
1084
1085 {
1086 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1087 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1088 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1089 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1090 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1091 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1092 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1093 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1094 },
1095
1096 {
1097 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1098 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1099 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1100 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1101 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1102 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1103 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1104 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1105 },
1106
1107 {
1108 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1109 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1110 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1111 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1112 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1113 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1114 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1115 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1116 },
1117
1118 {
1119 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1120 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1121 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1122 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1123 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1124 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1125 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1126 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1127 },
1128
1129 {
1130 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1131 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1132 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1133 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1134 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1135 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1136 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1137 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1138 },
1139
1140 {
1141 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1142 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1143 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1144 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1145 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1146 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1147 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1148 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1149 },
1150
1151 {
1152 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1153 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1154 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1155 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1156 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1157 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1158 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1159 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1160 }
1161 },
1162 .ctlPowerData_5G = {
1163 {
1164 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1165 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1166 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1167 }
1168 },
1169 {
1170 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1171 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1172 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1173 }
1174 },
1175 {
1176 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1177 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1178 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1179 }
1180 },
1181 {
1182 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1183 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1184 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1185 }
1186 },
1187 {
1188 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1189 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1190 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1191 }
1192 },
1193 {
1194 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1195 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1196 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1197 }
1198 },
1199 {
1200 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1201 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1202 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1203 }
1204 },
1205 {
1206 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1207 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1208 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1209 }
1210 },
1211 {
1212 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1213 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1214 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1215 }
1216 },
1217 }
1218};
1219
1220
1221static const struct ar9300_eeprom ar9300_h112 = {
1222 .eepromVersion = 2,
1223 .templateVersion = 3,
1224 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1225 .custData = {"h112-241-f0000"},
1226 .baseEepHeader = {
1227 .regDmn = { LE16(0), LE16(0x1f) },
1228 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1229 .opCapFlags = {
1230 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1231 .eepMisc = 0,
1232 },
1233 .rfSilent = 0,
1234 .blueToothOptions = 0,
1235 .deviceCap = 0,
1236 .deviceType = 5, /* takes lower byte in eeprom location */
1237 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1238 .params_for_tuning_caps = {0, 0},
1239 .featureEnable = 0x0d,
1240 /*
1241 * bit0 - enable tx temp comp - disabled
1242 * bit1 - enable tx volt comp - disabled
1243 * bit2 - enable fastClock - enabled
1244 * bit3 - enable doubling - enabled
1245 * bit4 - enable internal regulator - disabled
1246 * bit5 - enable pa predistortion - disabled
1247 */
1248 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1249 .eepromWriteEnableGpio = 6,
1250 .wlanDisableGpio = 0,
1251 .wlanLedGpio = 8,
1252 .rxBandSelectGpio = 0xff,
1253 .txrxgain = 0x10,
1254 .swreg = 0,
1255 },
1256 .modalHeader2G = {
1257 /* ar9300_modal_eep_header 2g */
1258 /* 4 idle,t1,t2,b(4 bits per setting) */
1259 .antCtrlCommon = LE32(0x110),
1260 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1261 .antCtrlCommon2 = LE32(0x44444),
1262
1263 /*
1264 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1265 * rx1, rx12, b (2 bits each)
1266 */
1267 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1268
1269 /*
1270 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1271 * for ar9280 (0xa20c/b20c 5:0)
1272 */
1273 .xatten1DB = {0, 0, 0},
1274
1275 /*
1276 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1277 * for ar9280 (0xa20c/b20c 16:12
1278 */
1279 .xatten1Margin = {0, 0, 0},
1280 .tempSlope = 25,
1281 .voltSlope = 0,
1282
1283 /*
1284 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1285 * channels in usual fbin coding format
1286 */
1287 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1288
1289 /*
1290 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1291 * if the register is per chain
1292 */
1293 .noiseFloorThreshCh = {-1, 0, 0},
1294 .ob = {1, 1, 1},/* 3 chain */
1295 .db_stage2 = {1, 1, 1}, /* 3 chain */
1296 .db_stage3 = {0, 0, 0},
1297 .db_stage4 = {0, 0, 0},
1298 .xpaBiasLvl = 0,
1299 .txFrameToDataStart = 0x0e,
1300 .txFrameToPaOn = 0x0e,
1301 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1302 .antennaGain = 0,
1303 .switchSettling = 0x2c,
1304 .adcDesiredSize = -30,
1305 .txEndToXpaOff = 0,
1306 .txEndToRxOn = 0x2,
1307 .txFrameToXpaOn = 0xe,
1308 .thresh62 = 28,
1309 .papdRateMaskHt20 = LE32(0x80c080),
1310 .papdRateMaskHt40 = LE32(0x80c080),
1311 .futureModal = {
1312 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1313 },
1314 },
1315 .base_ext1 = {
1316 .ant_div_control = 0,
1317 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1318 },
1319 .calFreqPier2G = {
1320 FREQ2FBIN(2412, 1),
1321 FREQ2FBIN(2437, 1),
1322 FREQ2FBIN(2472, 1),
1323 },
1324 /* ar9300_cal_data_per_freq_op_loop 2g */
1325 .calPierData2G = {
1326 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1327 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1328 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1329 },
1330 .calTarget_freqbin_Cck = {
1331 FREQ2FBIN(2412, 1),
1332 FREQ2FBIN(2484, 1),
1333 },
1334 .calTarget_freqbin_2G = {
1335 FREQ2FBIN(2412, 1),
1336 FREQ2FBIN(2437, 1),
1337 FREQ2FBIN(2472, 1)
1338 },
1339 .calTarget_freqbin_2GHT20 = {
1340 FREQ2FBIN(2412, 1),
1341 FREQ2FBIN(2437, 1),
1342 FREQ2FBIN(2472, 1)
1343 },
1344 .calTarget_freqbin_2GHT40 = {
1345 FREQ2FBIN(2412, 1),
1346 FREQ2FBIN(2437, 1),
1347 FREQ2FBIN(2472, 1)
1348 },
1349 .calTargetPowerCck = {
1350 /* 1L-5L,5S,11L,11S */
1351 { {34, 34, 34, 34} },
1352 { {34, 34, 34, 34} },
1353 },
1354 .calTargetPower2G = {
1355 /* 6-24,36,48,54 */
1356 { {34, 34, 32, 32} },
1357 { {34, 34, 32, 32} },
1358 { {34, 34, 32, 32} },
1359 },
1360 .calTargetPower2GHT20 = {
1361 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1362 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1363 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1364 },
1365 .calTargetPower2GHT40 = {
1366 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1367 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1368 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1369 },
1370 .ctlIndex_2G = {
1371 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1372 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1373 },
1374 .ctl_freqbin_2G = {
1375 {
1376 FREQ2FBIN(2412, 1),
1377 FREQ2FBIN(2417, 1),
1378 FREQ2FBIN(2457, 1),
1379 FREQ2FBIN(2462, 1)
1380 },
1381 {
1382 FREQ2FBIN(2412, 1),
1383 FREQ2FBIN(2417, 1),
1384 FREQ2FBIN(2462, 1),
1385 0xFF,
1386 },
1387
1388 {
1389 FREQ2FBIN(2412, 1),
1390 FREQ2FBIN(2417, 1),
1391 FREQ2FBIN(2462, 1),
1392 0xFF,
1393 },
1394 {
1395 FREQ2FBIN(2422, 1),
1396 FREQ2FBIN(2427, 1),
1397 FREQ2FBIN(2447, 1),
1398 FREQ2FBIN(2452, 1)
1399 },
1400
1401 {
1402 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1403 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1404 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1405 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1406 },
1407
1408 {
1409 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1410 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1411 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1412 0,
1413 },
1414
1415 {
1416 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1417 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1418 FREQ2FBIN(2472, 1),
1419 0,
1420 },
1421
1422 {
1423 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1424 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1425 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1426 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1427 },
1428
1429 {
1430 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1431 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1432 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1433 },
1434
1435 {
1436 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1437 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1438 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1439 0
1440 },
1441
1442 {
1443 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1444 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1445 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1446 0
1447 },
1448
1449 {
1450 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1451 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1452 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1453 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1454 }
1455 },
1456 .ctlPowerData_2G = {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1457 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1458 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1459 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1460
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1461 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
1462 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1463 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1464
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1465 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1466 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1467 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1468
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1469 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1470 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1471 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1472 },
1473 .modalHeader5G = {
1474 /* 4 idle,t1,t2,b (4 bits per setting) */
1475 .antCtrlCommon = LE32(0x220),
1476 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1477 .antCtrlCommon2 = LE32(0x44444),
1478 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1479 .antCtrlChain = {
1480 LE16(0x150), LE16(0x150), LE16(0x150),
1481 },
1482 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1483 .xatten1DB = {0, 0, 0},
1484
1485 /*
1486 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1487 * for merlin (0xa20c/b20c 16:12
1488 */
1489 .xatten1Margin = {0, 0, 0},
1490 .tempSlope = 45,
1491 .voltSlope = 0,
1492 /* spurChans spur channels in usual fbin coding format */
1493 .spurChans = {0, 0, 0, 0, 0},
1494 /* noiseFloorThreshCh Check if the register is per chain */
1495 .noiseFloorThreshCh = {-1, 0, 0},
1496 .ob = {3, 3, 3}, /* 3 chain */
1497 .db_stage2 = {3, 3, 3}, /* 3 chain */
1498 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1499 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1500 .xpaBiasLvl = 0,
1501 .txFrameToDataStart = 0x0e,
1502 .txFrameToPaOn = 0x0e,
1503 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1504 .antennaGain = 0,
1505 .switchSettling = 0x2d,
1506 .adcDesiredSize = -30,
1507 .txEndToXpaOff = 0,
1508 .txEndToRxOn = 0x2,
1509 .txFrameToXpaOn = 0xe,
1510 .thresh62 = 28,
1511 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1512 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1513 .futureModal = {
1514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1515 },
1516 },
1517 .base_ext2 = {
1518 .tempSlopeLow = 40,
1519 .tempSlopeHigh = 50,
1520 .xatten1DBLow = {0, 0, 0},
1521 .xatten1MarginLow = {0, 0, 0},
1522 .xatten1DBHigh = {0, 0, 0},
1523 .xatten1MarginHigh = {0, 0, 0}
1524 },
1525 .calFreqPier5G = {
1526 FREQ2FBIN(5180, 0),
1527 FREQ2FBIN(5220, 0),
1528 FREQ2FBIN(5320, 0),
1529 FREQ2FBIN(5400, 0),
1530 FREQ2FBIN(5500, 0),
1531 FREQ2FBIN(5600, 0),
1532 FREQ2FBIN(5700, 0),
1533 FREQ2FBIN(5825, 0)
1534 },
1535 .calPierData5G = {
1536 {
1537 {0, 0, 0, 0, 0},
1538 {0, 0, 0, 0, 0},
1539 {0, 0, 0, 0, 0},
1540 {0, 0, 0, 0, 0},
1541 {0, 0, 0, 0, 0},
1542 {0, 0, 0, 0, 0},
1543 {0, 0, 0, 0, 0},
1544 {0, 0, 0, 0, 0},
1545 },
1546 {
1547 {0, 0, 0, 0, 0},
1548 {0, 0, 0, 0, 0},
1549 {0, 0, 0, 0, 0},
1550 {0, 0, 0, 0, 0},
1551 {0, 0, 0, 0, 0},
1552 {0, 0, 0, 0, 0},
1553 {0, 0, 0, 0, 0},
1554 {0, 0, 0, 0, 0},
1555 },
1556 {
1557 {0, 0, 0, 0, 0},
1558 {0, 0, 0, 0, 0},
1559 {0, 0, 0, 0, 0},
1560 {0, 0, 0, 0, 0},
1561 {0, 0, 0, 0, 0},
1562 {0, 0, 0, 0, 0},
1563 {0, 0, 0, 0, 0},
1564 {0, 0, 0, 0, 0},
1565 },
1566
1567 },
1568 .calTarget_freqbin_5G = {
1569 FREQ2FBIN(5180, 0),
1570 FREQ2FBIN(5240, 0),
1571 FREQ2FBIN(5320, 0),
1572 FREQ2FBIN(5400, 0),
1573 FREQ2FBIN(5500, 0),
1574 FREQ2FBIN(5600, 0),
1575 FREQ2FBIN(5700, 0),
1576 FREQ2FBIN(5825, 0)
1577 },
1578 .calTarget_freqbin_5GHT20 = {
1579 FREQ2FBIN(5180, 0),
1580 FREQ2FBIN(5240, 0),
1581 FREQ2FBIN(5320, 0),
1582 FREQ2FBIN(5400, 0),
1583 FREQ2FBIN(5500, 0),
1584 FREQ2FBIN(5700, 0),
1585 FREQ2FBIN(5745, 0),
1586 FREQ2FBIN(5825, 0)
1587 },
1588 .calTarget_freqbin_5GHT40 = {
1589 FREQ2FBIN(5180, 0),
1590 FREQ2FBIN(5240, 0),
1591 FREQ2FBIN(5320, 0),
1592 FREQ2FBIN(5400, 0),
1593 FREQ2FBIN(5500, 0),
1594 FREQ2FBIN(5700, 0),
1595 FREQ2FBIN(5745, 0),
1596 FREQ2FBIN(5825, 0)
1597 },
1598 .calTargetPower5G = {
1599 /* 6-24,36,48,54 */
1600 { {30, 30, 28, 24} },
1601 { {30, 30, 28, 24} },
1602 { {30, 30, 28, 24} },
1603 { {30, 30, 28, 24} },
1604 { {30, 30, 28, 24} },
1605 { {30, 30, 28, 24} },
1606 { {30, 30, 28, 24} },
1607 { {30, 30, 28, 24} },
1608 },
1609 .calTargetPower5GHT20 = {
1610 /*
1611 * 0_8_16,1-3_9-11_17-19,
1612 * 4,5,6,7,12,13,14,15,20,21,22,23
1613 */
1614 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1615 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1616 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1617 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1618 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1619 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1620 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1621 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1622 },
1623 .calTargetPower5GHT40 = {
1624 /*
1625 * 0_8_16,1-3_9-11_17-19,
1626 * 4,5,6,7,12,13,14,15,20,21,22,23
1627 */
1628 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1629 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1630 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1631 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1632 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1633 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1634 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1635 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1636 },
1637 .ctlIndex_5G = {
1638 0x10, 0x16, 0x18, 0x40, 0x46,
1639 0x48, 0x30, 0x36, 0x38
1640 },
1641 .ctl_freqbin_5G = {
1642 {
1643 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1644 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1645 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1646 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1647 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1648 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1649 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1650 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1651 },
1652 {
1653 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1654 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1655 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1656 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1657 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1658 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1659 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1660 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1661 },
1662
1663 {
1664 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1665 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1666 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1667 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1668 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1669 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1670 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1671 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1672 },
1673
1674 {
1675 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1676 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1677 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1678 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1679 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1680 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1681 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1682 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1683 },
1684
1685 {
1686 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1687 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1688 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1689 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1690 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1691 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1692 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1693 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1694 },
1695
1696 {
1697 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1698 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1699 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1700 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1701 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1702 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1703 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1704 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1705 },
1706
1707 {
1708 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1709 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1710 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1711 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1712 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1713 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1714 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1715 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1716 },
1717
1718 {
1719 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1720 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1721 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1722 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1723 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1724 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1725 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1726 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1727 },
1728
1729 {
1730 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1731 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1732 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1733 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1734 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1735 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1736 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1737 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1738 }
1739 },
1740 .ctlPowerData_5G = {
1741 {
1742 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1743 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1744 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1745 }
1746 },
1747 {
1748 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1749 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1750 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1751 }
1752 },
1753 {
1754 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1755 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1756 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1757 }
1758 },
1759 {
1760 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1761 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1762 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1763 }
1764 },
1765 {
1766 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1767 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1768 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1769 }
1770 },
1771 {
1772 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1773 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1774 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1775 }
1776 },
1777 {
1778 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1779 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1780 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1781 }
1782 },
1783 {
1784 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1785 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1786 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1787 }
1788 },
1789 {
1790 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1791 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1792 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1793 }
1794 },
1795 }
1796};
1797
1798
1799static const struct ar9300_eeprom ar9300_x112 = {
1800 .eepromVersion = 2,
1801 .templateVersion = 5,
1802 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1803 .custData = {"x112-041-f0000"},
1804 .baseEepHeader = {
1805 .regDmn = { LE16(0), LE16(0x1f) },
1806 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1807 .opCapFlags = {
1808 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1809 .eepMisc = 0,
1810 },
1811 .rfSilent = 0,
1812 .blueToothOptions = 0,
1813 .deviceCap = 0,
1814 .deviceType = 5, /* takes lower byte in eeprom location */
1815 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1816 .params_for_tuning_caps = {0, 0},
1817 .featureEnable = 0x0d,
1818 /*
1819 * bit0 - enable tx temp comp - disabled
1820 * bit1 - enable tx volt comp - disabled
1821 * bit2 - enable fastclock - enabled
1822 * bit3 - enable doubling - enabled
1823 * bit4 - enable internal regulator - disabled
1824 * bit5 - enable pa predistortion - disabled
1825 */
1826 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1827 .eepromWriteEnableGpio = 6,
1828 .wlanDisableGpio = 0,
1829 .wlanLedGpio = 8,
1830 .rxBandSelectGpio = 0xff,
1831 .txrxgain = 0x0,
1832 .swreg = 0,
1833 },
1834 .modalHeader2G = {
1835 /* ar9300_modal_eep_header 2g */
1836 /* 4 idle,t1,t2,b(4 bits per setting) */
1837 .antCtrlCommon = LE32(0x110),
1838 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1839 .antCtrlCommon2 = LE32(0x22222),
1840
1841 /*
1842 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1843 * rx1, rx12, b (2 bits each)
1844 */
1845 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1846
1847 /*
1848 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1849 * for ar9280 (0xa20c/b20c 5:0)
1850 */
1851 .xatten1DB = {0x1b, 0x1b, 0x1b},
1852
1853 /*
1854 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1855 * for ar9280 (0xa20c/b20c 16:12
1856 */
1857 .xatten1Margin = {0x15, 0x15, 0x15},
1858 .tempSlope = 50,
1859 .voltSlope = 0,
1860
1861 /*
1862 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1863 * channels in usual fbin coding format
1864 */
1865 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1866
1867 /*
1868 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1869 * if the register is per chain
1870 */
1871 .noiseFloorThreshCh = {-1, 0, 0},
1872 .ob = {1, 1, 1},/* 3 chain */
1873 .db_stage2 = {1, 1, 1}, /* 3 chain */
1874 .db_stage3 = {0, 0, 0},
1875 .db_stage4 = {0, 0, 0},
1876 .xpaBiasLvl = 0,
1877 .txFrameToDataStart = 0x0e,
1878 .txFrameToPaOn = 0x0e,
1879 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1880 .antennaGain = 0,
1881 .switchSettling = 0x2c,
1882 .adcDesiredSize = -30,
1883 .txEndToXpaOff = 0,
1884 .txEndToRxOn = 0x2,
1885 .txFrameToXpaOn = 0xe,
1886 .thresh62 = 28,
1887 .papdRateMaskHt20 = LE32(0x0c80c080),
1888 .papdRateMaskHt40 = LE32(0x0080c080),
1889 .futureModal = {
1890 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1891 },
1892 },
1893 .base_ext1 = {
1894 .ant_div_control = 0,
1895 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1896 },
1897 .calFreqPier2G = {
1898 FREQ2FBIN(2412, 1),
1899 FREQ2FBIN(2437, 1),
1900 FREQ2FBIN(2472, 1),
1901 },
1902 /* ar9300_cal_data_per_freq_op_loop 2g */
1903 .calPierData2G = {
1904 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1905 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1906 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1907 },
1908 .calTarget_freqbin_Cck = {
1909 FREQ2FBIN(2412, 1),
1910 FREQ2FBIN(2472, 1),
1911 },
1912 .calTarget_freqbin_2G = {
1913 FREQ2FBIN(2412, 1),
1914 FREQ2FBIN(2437, 1),
1915 FREQ2FBIN(2472, 1)
1916 },
1917 .calTarget_freqbin_2GHT20 = {
1918 FREQ2FBIN(2412, 1),
1919 FREQ2FBIN(2437, 1),
1920 FREQ2FBIN(2472, 1)
1921 },
1922 .calTarget_freqbin_2GHT40 = {
1923 FREQ2FBIN(2412, 1),
1924 FREQ2FBIN(2437, 1),
1925 FREQ2FBIN(2472, 1)
1926 },
1927 .calTargetPowerCck = {
1928 /* 1L-5L,5S,11L,11s */
1929 { {38, 38, 38, 38} },
1930 { {38, 38, 38, 38} },
1931 },
1932 .calTargetPower2G = {
1933 /* 6-24,36,48,54 */
1934 { {38, 38, 36, 34} },
1935 { {38, 38, 36, 34} },
1936 { {38, 38, 34, 32} },
1937 },
1938 .calTargetPower2GHT20 = {
1939 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1940 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1941 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1942 },
1943 .calTargetPower2GHT40 = {
1944 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1945 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1946 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1947 },
1948 .ctlIndex_2G = {
1949 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1950 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1951 },
1952 .ctl_freqbin_2G = {
1953 {
1954 FREQ2FBIN(2412, 1),
1955 FREQ2FBIN(2417, 1),
1956 FREQ2FBIN(2457, 1),
1957 FREQ2FBIN(2462, 1)
1958 },
1959 {
1960 FREQ2FBIN(2412, 1),
1961 FREQ2FBIN(2417, 1),
1962 FREQ2FBIN(2462, 1),
1963 0xFF,
1964 },
1965
1966 {
1967 FREQ2FBIN(2412, 1),
1968 FREQ2FBIN(2417, 1),
1969 FREQ2FBIN(2462, 1),
1970 0xFF,
1971 },
1972 {
1973 FREQ2FBIN(2422, 1),
1974 FREQ2FBIN(2427, 1),
1975 FREQ2FBIN(2447, 1),
1976 FREQ2FBIN(2452, 1)
1977 },
1978
1979 {
1980 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1981 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1982 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1983 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1984 },
1985
1986 {
1987 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1988 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1989 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1990 0,
1991 },
1992
1993 {
1994 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1995 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1996 FREQ2FBIN(2472, 1),
1997 0,
1998 },
1999
2000 {
2001 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2002 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2003 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2004 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2005 },
2006
2007 {
2008 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2009 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2010 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2011 },
2012
2013 {
2014 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2015 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2016 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2017 0
2018 },
2019
2020 {
2021 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2022 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2023 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2024 0
2025 },
2026
2027 {
2028 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2029 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2030 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2031 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2032 }
2033 },
2034 .ctlPowerData_2G = {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2035 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2036 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2037 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2038
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2039 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2040 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2041 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2042
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2043 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2044 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2045 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2046
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2047 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2048 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2049 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2050 },
2051 .modalHeader5G = {
2052 /* 4 idle,t1,t2,b (4 bits per setting) */
2053 .antCtrlCommon = LE32(0x110),
2054 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2055 .antCtrlCommon2 = LE32(0x22222),
2056 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2057 .antCtrlChain = {
2058 LE16(0x0), LE16(0x0), LE16(0x0),
2059 },
2060 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2061 .xatten1DB = {0x13, 0x19, 0x17},
2062
2063 /*
2064 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2065 * for merlin (0xa20c/b20c 16:12
2066 */
2067 .xatten1Margin = {0x19, 0x19, 0x19},
2068 .tempSlope = 70,
2069 .voltSlope = 15,
2070 /* spurChans spur channels in usual fbin coding format */
2071 .spurChans = {0, 0, 0, 0, 0},
2072 /* noiseFloorThreshch check if the register is per chain */
2073 .noiseFloorThreshCh = {-1, 0, 0},
2074 .ob = {3, 3, 3}, /* 3 chain */
2075 .db_stage2 = {3, 3, 3}, /* 3 chain */
2076 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2077 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2078 .xpaBiasLvl = 0,
2079 .txFrameToDataStart = 0x0e,
2080 .txFrameToPaOn = 0x0e,
2081 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2082 .antennaGain = 0,
2083 .switchSettling = 0x2d,
2084 .adcDesiredSize = -30,
2085 .txEndToXpaOff = 0,
2086 .txEndToRxOn = 0x2,
2087 .txFrameToXpaOn = 0xe,
2088 .thresh62 = 28,
2089 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2090 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2091 .futureModal = {
2092 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2093 },
2094 },
2095 .base_ext2 = {
2096 .tempSlopeLow = 72,
2097 .tempSlopeHigh = 105,
2098 .xatten1DBLow = {0x10, 0x14, 0x10},
2099 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2100 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2101 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2102 },
2103 .calFreqPier5G = {
2104 FREQ2FBIN(5180, 0),
2105 FREQ2FBIN(5220, 0),
2106 FREQ2FBIN(5320, 0),
2107 FREQ2FBIN(5400, 0),
2108 FREQ2FBIN(5500, 0),
2109 FREQ2FBIN(5600, 0),
2110 FREQ2FBIN(5700, 0),
2111 FREQ2FBIN(5785, 0)
2112 },
2113 .calPierData5G = {
2114 {
2115 {0, 0, 0, 0, 0},
2116 {0, 0, 0, 0, 0},
2117 {0, 0, 0, 0, 0},
2118 {0, 0, 0, 0, 0},
2119 {0, 0, 0, 0, 0},
2120 {0, 0, 0, 0, 0},
2121 {0, 0, 0, 0, 0},
2122 {0, 0, 0, 0, 0},
2123 },
2124 {
2125 {0, 0, 0, 0, 0},
2126 {0, 0, 0, 0, 0},
2127 {0, 0, 0, 0, 0},
2128 {0, 0, 0, 0, 0},
2129 {0, 0, 0, 0, 0},
2130 {0, 0, 0, 0, 0},
2131 {0, 0, 0, 0, 0},
2132 {0, 0, 0, 0, 0},
2133 },
2134 {
2135 {0, 0, 0, 0, 0},
2136 {0, 0, 0, 0, 0},
2137 {0, 0, 0, 0, 0},
2138 {0, 0, 0, 0, 0},
2139 {0, 0, 0, 0, 0},
2140 {0, 0, 0, 0, 0},
2141 {0, 0, 0, 0, 0},
2142 {0, 0, 0, 0, 0},
2143 },
2144
2145 },
2146 .calTarget_freqbin_5G = {
2147 FREQ2FBIN(5180, 0),
2148 FREQ2FBIN(5220, 0),
2149 FREQ2FBIN(5320, 0),
2150 FREQ2FBIN(5400, 0),
2151 FREQ2FBIN(5500, 0),
2152 FREQ2FBIN(5600, 0),
2153 FREQ2FBIN(5725, 0),
2154 FREQ2FBIN(5825, 0)
2155 },
2156 .calTarget_freqbin_5GHT20 = {
2157 FREQ2FBIN(5180, 0),
2158 FREQ2FBIN(5220, 0),
2159 FREQ2FBIN(5320, 0),
2160 FREQ2FBIN(5400, 0),
2161 FREQ2FBIN(5500, 0),
2162 FREQ2FBIN(5600, 0),
2163 FREQ2FBIN(5725, 0),
2164 FREQ2FBIN(5825, 0)
2165 },
2166 .calTarget_freqbin_5GHT40 = {
2167 FREQ2FBIN(5180, 0),
2168 FREQ2FBIN(5220, 0),
2169 FREQ2FBIN(5320, 0),
2170 FREQ2FBIN(5400, 0),
2171 FREQ2FBIN(5500, 0),
2172 FREQ2FBIN(5600, 0),
2173 FREQ2FBIN(5725, 0),
2174 FREQ2FBIN(5825, 0)
2175 },
2176 .calTargetPower5G = {
2177 /* 6-24,36,48,54 */
2178 { {32, 32, 28, 26} },
2179 { {32, 32, 28, 26} },
2180 { {32, 32, 28, 26} },
2181 { {32, 32, 26, 24} },
2182 { {32, 32, 26, 24} },
2183 { {32, 32, 24, 22} },
2184 { {30, 30, 24, 22} },
2185 { {30, 30, 24, 22} },
2186 },
2187 .calTargetPower5GHT20 = {
2188 /*
2189 * 0_8_16,1-3_9-11_17-19,
2190 * 4,5,6,7,12,13,14,15,20,21,22,23
2191 */
2192 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2193 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2194 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2195 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2196 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2197 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2198 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2199 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2200 },
2201 .calTargetPower5GHT40 = {
2202 /*
2203 * 0_8_16,1-3_9-11_17-19,
2204 * 4,5,6,7,12,13,14,15,20,21,22,23
2205 */
2206 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2207 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2208 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2209 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2210 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2211 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2212 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2213 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2214 },
2215 .ctlIndex_5G = {
2216 0x10, 0x16, 0x18, 0x40, 0x46,
2217 0x48, 0x30, 0x36, 0x38
2218 },
2219 .ctl_freqbin_5G = {
2220 {
2221 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2222 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2223 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2224 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2225 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2226 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2227 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2228 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2229 },
2230 {
2231 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2232 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2233 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2234 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2235 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2236 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2237 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2238 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2239 },
2240
2241 {
2242 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2243 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2244 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2245 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2246 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2247 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2248 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2249 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2250 },
2251
2252 {
2253 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2254 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2255 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2256 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2257 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2258 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2259 /* Data[3].ctledges[6].bchannel */ 0xFF,
2260 /* Data[3].ctledges[7].bchannel */ 0xFF,
2261 },
2262
2263 {
2264 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2265 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2266 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2267 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2268 /* Data[4].ctledges[4].bchannel */ 0xFF,
2269 /* Data[4].ctledges[5].bchannel */ 0xFF,
2270 /* Data[4].ctledges[6].bchannel */ 0xFF,
2271 /* Data[4].ctledges[7].bchannel */ 0xFF,
2272 },
2273
2274 {
2275 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2276 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2277 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2278 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2279 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2280 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2281 /* Data[5].ctledges[6].bchannel */ 0xFF,
2282 /* Data[5].ctledges[7].bchannel */ 0xFF
2283 },
2284
2285 {
2286 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2287 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2288 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2289 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2290 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2291 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2292 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2293 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2294 },
2295
2296 {
2297 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2298 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2299 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2300 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2301 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2302 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2303 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2304 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2305 },
2306
2307 {
2308 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2309 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2310 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2311 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2312 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2313 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2314 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2315 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2316 }
2317 },
2318 .ctlPowerData_5G = {
2319 {
2320 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2321 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2322 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2323 }
2324 },
2325 {
2326 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2327 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2328 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2329 }
2330 },
2331 {
2332 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2333 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2334 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2335 }
2336 },
2337 {
2338 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2339 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2340 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2341 }
2342 },
2343 {
2344 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2345 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2346 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2347 }
2348 },
2349 {
2350 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2351 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2352 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2353 }
2354 },
2355 {
2356 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2357 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2358 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2359 }
2360 },
2361 {
2362 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2363 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2364 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2365 }
2366 },
2367 {
2368 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2369 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2370 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2371 }
2372 },
2373 }
2374};
2375
2376static const struct ar9300_eeprom ar9300_h116 = {
2377 .eepromVersion = 2,
2378 .templateVersion = 4,
2379 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2380 .custData = {"h116-041-f0000"},
2381 .baseEepHeader = {
2382 .regDmn = { LE16(0), LE16(0x1f) },
2383 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2384 .opCapFlags = {
2385 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
2386 .eepMisc = 0,
2387 },
2388 .rfSilent = 0,
2389 .blueToothOptions = 0,
2390 .deviceCap = 0,
2391 .deviceType = 5, /* takes lower byte in eeprom location */
2392 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2393 .params_for_tuning_caps = {0, 0},
2394 .featureEnable = 0x0d,
2395 /*
2396 * bit0 - enable tx temp comp - disabled
2397 * bit1 - enable tx volt comp - disabled
2398 * bit2 - enable fastClock - enabled
2399 * bit3 - enable doubling - enabled
2400 * bit4 - enable internal regulator - disabled
2401 * bit5 - enable pa predistortion - disabled
2402 */
2403 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2404 .eepromWriteEnableGpio = 6,
2405 .wlanDisableGpio = 0,
2406 .wlanLedGpio = 8,
2407 .rxBandSelectGpio = 0xff,
2408 .txrxgain = 0x10,
2409 .swreg = 0,
2410 },
2411 .modalHeader2G = {
2412 /* ar9300_modal_eep_header 2g */
2413 /* 4 idle,t1,t2,b(4 bits per setting) */
2414 .antCtrlCommon = LE32(0x110),
2415 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2416 .antCtrlCommon2 = LE32(0x44444),
2417
2418 /*
2419 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2420 * rx1, rx12, b (2 bits each)
2421 */
2422 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2423
2424 /*
2425 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2426 * for ar9280 (0xa20c/b20c 5:0)
2427 */
2428 .xatten1DB = {0x1f, 0x1f, 0x1f},
2429
2430 /*
2431 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2432 * for ar9280 (0xa20c/b20c 16:12
2433 */
2434 .xatten1Margin = {0x12, 0x12, 0x12},
2435 .tempSlope = 25,
2436 .voltSlope = 0,
2437
2438 /*
2439 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2440 * channels in usual fbin coding format
2441 */
2442 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2443
2444 /*
2445 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2446 * if the register is per chain
2447 */
2448 .noiseFloorThreshCh = {-1, 0, 0},
2449 .ob = {1, 1, 1},/* 3 chain */
2450 .db_stage2 = {1, 1, 1}, /* 3 chain */
2451 .db_stage3 = {0, 0, 0},
2452 .db_stage4 = {0, 0, 0},
2453 .xpaBiasLvl = 0,
2454 .txFrameToDataStart = 0x0e,
2455 .txFrameToPaOn = 0x0e,
2456 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2457 .antennaGain = 0,
2458 .switchSettling = 0x2c,
2459 .adcDesiredSize = -30,
2460 .txEndToXpaOff = 0,
2461 .txEndToRxOn = 0x2,
2462 .txFrameToXpaOn = 0xe,
2463 .thresh62 = 28,
2464 .papdRateMaskHt20 = LE32(0x0c80C080),
2465 .papdRateMaskHt40 = LE32(0x0080C080),
2466 .futureModal = {
2467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468 },
2469 },
2470 .base_ext1 = {
2471 .ant_div_control = 0,
2472 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2473 },
2474 .calFreqPier2G = {
2475 FREQ2FBIN(2412, 1),
2476 FREQ2FBIN(2437, 1),
2477 FREQ2FBIN(2472, 1),
2478 },
2479 /* ar9300_cal_data_per_freq_op_loop 2g */
2480 .calPierData2G = {
2481 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2482 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2483 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2484 },
2485 .calTarget_freqbin_Cck = {
2486 FREQ2FBIN(2412, 1),
2487 FREQ2FBIN(2472, 1),
2488 },
2489 .calTarget_freqbin_2G = {
2490 FREQ2FBIN(2412, 1),
2491 FREQ2FBIN(2437, 1),
2492 FREQ2FBIN(2472, 1)
2493 },
2494 .calTarget_freqbin_2GHT20 = {
2495 FREQ2FBIN(2412, 1),
2496 FREQ2FBIN(2437, 1),
2497 FREQ2FBIN(2472, 1)
2498 },
2499 .calTarget_freqbin_2GHT40 = {
2500 FREQ2FBIN(2412, 1),
2501 FREQ2FBIN(2437, 1),
2502 FREQ2FBIN(2472, 1)
2503 },
2504 .calTargetPowerCck = {
2505 /* 1L-5L,5S,11L,11S */
2506 { {34, 34, 34, 34} },
2507 { {34, 34, 34, 34} },
2508 },
2509 .calTargetPower2G = {
2510 /* 6-24,36,48,54 */
2511 { {34, 34, 32, 32} },
2512 { {34, 34, 32, 32} },
2513 { {34, 34, 32, 32} },
2514 },
2515 .calTargetPower2GHT20 = {
2516 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2517 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2518 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2519 },
2520 .calTargetPower2GHT40 = {
2521 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2522 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2523 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2524 },
2525 .ctlIndex_2G = {
2526 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2527 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2528 },
2529 .ctl_freqbin_2G = {
2530 {
2531 FREQ2FBIN(2412, 1),
2532 FREQ2FBIN(2417, 1),
2533 FREQ2FBIN(2457, 1),
2534 FREQ2FBIN(2462, 1)
2535 },
2536 {
2537 FREQ2FBIN(2412, 1),
2538 FREQ2FBIN(2417, 1),
2539 FREQ2FBIN(2462, 1),
2540 0xFF,
2541 },
2542
2543 {
2544 FREQ2FBIN(2412, 1),
2545 FREQ2FBIN(2417, 1),
2546 FREQ2FBIN(2462, 1),
2547 0xFF,
2548 },
2549 {
2550 FREQ2FBIN(2422, 1),
2551 FREQ2FBIN(2427, 1),
2552 FREQ2FBIN(2447, 1),
2553 FREQ2FBIN(2452, 1)
2554 },
2555
2556 {
2557 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2558 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2559 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2560 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2561 },
2562
2563 {
2564 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2565 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2566 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2567 0,
2568 },
2569
2570 {
2571 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2572 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2573 FREQ2FBIN(2472, 1),
2574 0,
2575 },
2576
2577 {
2578 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2579 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2580 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2581 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2582 },
2583
2584 {
2585 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2586 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2587 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2588 },
2589
2590 {
2591 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2592 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2593 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2594 0
2595 },
2596
2597 {
2598 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2599 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2600 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2601 0
2602 },
2603
2604 {
2605 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2606 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2607 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2608 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2609 }
2610 },
2611 .ctlPowerData_2G = {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2612 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2613 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2614 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2615
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2616 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2617 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2618 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2619
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2620 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2621 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2622 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2623
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2624 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2625 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2626 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2627 },
2628 .modalHeader5G = {
2629 /* 4 idle,t1,t2,b (4 bits per setting) */
2630 .antCtrlCommon = LE32(0x220),
2631 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2632 .antCtrlCommon2 = LE32(0x44444),
2633 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2634 .antCtrlChain = {
2635 LE16(0x150), LE16(0x150), LE16(0x150),
2636 },
2637 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2638 .xatten1DB = {0x19, 0x19, 0x19},
2639
2640 /*
2641 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2642 * for merlin (0xa20c/b20c 16:12
2643 */
2644 .xatten1Margin = {0x14, 0x14, 0x14},
2645 .tempSlope = 70,
2646 .voltSlope = 0,
2647 /* spurChans spur channels in usual fbin coding format */
2648 .spurChans = {0, 0, 0, 0, 0},
2649 /* noiseFloorThreshCh Check if the register is per chain */
2650 .noiseFloorThreshCh = {-1, 0, 0},
2651 .ob = {3, 3, 3}, /* 3 chain */
2652 .db_stage2 = {3, 3, 3}, /* 3 chain */
2653 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2654 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2655 .xpaBiasLvl = 0,
2656 .txFrameToDataStart = 0x0e,
2657 .txFrameToPaOn = 0x0e,
2658 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2659 .antennaGain = 0,
2660 .switchSettling = 0x2d,
2661 .adcDesiredSize = -30,
2662 .txEndToXpaOff = 0,
2663 .txEndToRxOn = 0x2,
2664 .txFrameToXpaOn = 0xe,
2665 .thresh62 = 28,
2666 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2667 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2668 .futureModal = {
2669 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2670 },
2671 },
2672 .base_ext2 = {
2673 .tempSlopeLow = 35,
2674 .tempSlopeHigh = 50,
2675 .xatten1DBLow = {0, 0, 0},
2676 .xatten1MarginLow = {0, 0, 0},
2677 .xatten1DBHigh = {0, 0, 0},
2678 .xatten1MarginHigh = {0, 0, 0}
2679 },
2680 .calFreqPier5G = {
2681 FREQ2FBIN(5180, 0),
2682 FREQ2FBIN(5220, 0),
2683 FREQ2FBIN(5320, 0),
2684 FREQ2FBIN(5400, 0),
2685 FREQ2FBIN(5500, 0),
2686 FREQ2FBIN(5600, 0),
2687 FREQ2FBIN(5700, 0),
2688 FREQ2FBIN(5785, 0)
2689 },
2690 .calPierData5G = {
2691 {
2692 {0, 0, 0, 0, 0},
2693 {0, 0, 0, 0, 0},
2694 {0, 0, 0, 0, 0},
2695 {0, 0, 0, 0, 0},
2696 {0, 0, 0, 0, 0},
2697 {0, 0, 0, 0, 0},
2698 {0, 0, 0, 0, 0},
2699 {0, 0, 0, 0, 0},
2700 },
2701 {
2702 {0, 0, 0, 0, 0},
2703 {0, 0, 0, 0, 0},
2704 {0, 0, 0, 0, 0},
2705 {0, 0, 0, 0, 0},
2706 {0, 0, 0, 0, 0},
2707 {0, 0, 0, 0, 0},
2708 {0, 0, 0, 0, 0},
2709 {0, 0, 0, 0, 0},
2710 },
2711 {
2712 {0, 0, 0, 0, 0},
2713 {0, 0, 0, 0, 0},
2714 {0, 0, 0, 0, 0},
2715 {0, 0, 0, 0, 0},
2716 {0, 0, 0, 0, 0},
2717 {0, 0, 0, 0, 0},
2718 {0, 0, 0, 0, 0},
2719 {0, 0, 0, 0, 0},
2720 },
2721
2722 },
2723 .calTarget_freqbin_5G = {
2724 FREQ2FBIN(5180, 0),
2725 FREQ2FBIN(5240, 0),
2726 FREQ2FBIN(5320, 0),
2727 FREQ2FBIN(5400, 0),
2728 FREQ2FBIN(5500, 0),
2729 FREQ2FBIN(5600, 0),
2730 FREQ2FBIN(5700, 0),
2731 FREQ2FBIN(5825, 0)
2732 },
2733 .calTarget_freqbin_5GHT20 = {
2734 FREQ2FBIN(5180, 0),
2735 FREQ2FBIN(5240, 0),
2736 FREQ2FBIN(5320, 0),
2737 FREQ2FBIN(5400, 0),
2738 FREQ2FBIN(5500, 0),
2739 FREQ2FBIN(5700, 0),
2740 FREQ2FBIN(5745, 0),
2741 FREQ2FBIN(5825, 0)
2742 },
2743 .calTarget_freqbin_5GHT40 = {
2744 FREQ2FBIN(5180, 0),
2745 FREQ2FBIN(5240, 0),
2746 FREQ2FBIN(5320, 0),
2747 FREQ2FBIN(5400, 0),
2748 FREQ2FBIN(5500, 0),
2749 FREQ2FBIN(5700, 0),
2750 FREQ2FBIN(5745, 0),
2751 FREQ2FBIN(5825, 0)
2752 },
2753 .calTargetPower5G = {
2754 /* 6-24,36,48,54 */
2755 { {30, 30, 28, 24} },
2756 { {30, 30, 28, 24} },
2757 { {30, 30, 28, 24} },
2758 { {30, 30, 28, 24} },
2759 { {30, 30, 28, 24} },
2760 { {30, 30, 28, 24} },
2761 { {30, 30, 28, 24} },
2762 { {30, 30, 28, 24} },
2763 },
2764 .calTargetPower5GHT20 = {
2765 /*
2766 * 0_8_16,1-3_9-11_17-19,
2767 * 4,5,6,7,12,13,14,15,20,21,22,23
2768 */
2769 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2770 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2771 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2772 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2773 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2774 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2775 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2776 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2777 },
2778 .calTargetPower5GHT40 = {
2779 /*
2780 * 0_8_16,1-3_9-11_17-19,
2781 * 4,5,6,7,12,13,14,15,20,21,22,23
2782 */
2783 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2784 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2785 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2786 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2787 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2788 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2789 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2790 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2791 },
2792 .ctlIndex_5G = {
2793 0x10, 0x16, 0x18, 0x40, 0x46,
2794 0x48, 0x30, 0x36, 0x38
2795 },
2796 .ctl_freqbin_5G = {
2797 {
2798 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2799 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2800 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2801 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2802 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2803 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2804 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2805 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2806 },
2807 {
2808 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2809 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2810 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2811 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2812 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2813 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2814 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2815 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2816 },
2817
2818 {
2819 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2820 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2821 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2822 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2823 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2824 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2825 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2826 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2827 },
2828
2829 {
2830 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2831 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2832 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2833 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2834 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2835 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2836 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2837 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2838 },
2839
2840 {
2841 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2842 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2843 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2844 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2845 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2846 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2847 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2848 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2849 },
2850
2851 {
2852 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2853 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2854 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2855 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2856 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2857 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2858 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2859 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2860 },
2861
2862 {
2863 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2864 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2865 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2866 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2867 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2868 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2869 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2870 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2871 },
2872
2873 {
2874 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2875 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2876 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2877 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2878 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2879 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2880 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2881 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2882 },
2883
2884 {
2885 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2886 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2887 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2888 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2889 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2890 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2891 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2892 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2893 }
2894 },
2895 .ctlPowerData_5G = {
2896 {
2897 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2898 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2899 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2900 }
2901 },
2902 {
2903 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2904 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2905 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2906 }
2907 },
2908 {
2909 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2910 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2911 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2912 }
2913 },
2914 {
2915 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2916 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2917 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2918 }
2919 },
2920 {
2921 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2922 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2923 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2924 }
2925 },
2926 {
2927 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2928 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2929 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2930 }
2931 },
2932 {
2933 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2934 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2935 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2936 }
2937 },
2938 {
2939 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2940 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2941 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2942 }
2943 },
2944 {
2945 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2946 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2947 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2948 }
2949 },
2950 }
2951};
2952
2953
2954static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2955 &ar9300_default,
2956 &ar9300_x112,
2957 &ar9300_h116,
2958 &ar9300_h112,
2959 &ar9300_x113,
2960};
2961
2962static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2963{
2964#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2965 int it;
2966
2967 for (it = 0; it < N_LOOP; it++)
2968 if (ar9300_eep_templates[it]->templateVersion == id)
2969 return ar9300_eep_templates[it];
2970 return NULL;
2971#undef N_LOOP
2972}
2973
2974
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]2975static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2976{
2977 if (fbin == AR9300_BCHAN_UNUSED)
2978 return fbin;
2979
2980 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2981}
2982
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2983static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2984{
2985 return 0;
2986}
2987
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]2988static int interpolate(int x, int xa, int xb, int ya, int yb)
2989{
2990 int bf, factor, plus;
2991
2992 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2993 factor = bf / 2;
2994 plus = bf % 2;
2995 return ya + factor + plus;
2996}
2997
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2998static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2999 enum eeprom_param param)
3000{
3001 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3002 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3003
3004 switch (param) {
3005 case EEP_MAC_LSW:
3006 return eep->macAddr[0] << 8 | eep->macAddr[1];
3007 case EEP_MAC_MID:
3008 return eep->macAddr[2] << 8 | eep->macAddr[3];
3009 case EEP_MAC_MSW:
3010 return eep->macAddr[4] << 8 | eep->macAddr[5];
3011 case EEP_REG_0:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3012 return le16_to_cpu(pBase->regDmn[0]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3013 case EEP_REG_1:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3014 return le16_to_cpu(pBase->regDmn[1]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3015 case EEP_OP_CAP:
3016 return pBase->deviceCap;
3017 case EEP_OP_MODE:
3018 return pBase->opCapFlags.opFlags;
3019 case EEP_RF_SILENT:
3020 return pBase->rfSilent;
3021 case EEP_TX_MASK:
3022 return (pBase->txrxMask >> 4) & 0xf;
3023 case EEP_RX_MASK:
3024 return pBase->txrxMask & 0xf;
3025 case EEP_DRIVE_STRENGTH:
3026#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3027 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3028 case EEP_INTERNAL_REGULATOR:
3029 /* Bit 4 is internal regulator flag */
3030 return (pBase->featureEnable & 0x10) >> 4;
3031 case EEP_SWREG:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3032 return le32_to_cpu(pBase->swreg);
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]3033 case EEP_PAPRD:
3034 return !!(pBase->featureEnable & BIT(5));
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +0530[diff] [blame]3035 case EEP_CHAIN_MASK_REDUCE:
3036 return (pBase->miscConfiguration >> 0x3) & 0x1;
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3037 case EEP_ANT_DIV_CTL1:
3038 return le32_to_cpu(eep->base_ext1.ant_div_control);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3039 default:
3040 return 0;
3041 }
3042}
3043
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3044static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3045 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3046{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3047 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3048
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3049 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3050 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3051
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3052 *buffer = (val >> (8 * (address % 2))) & 0xff;
3053 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3054}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3055
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3056static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3057 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3058{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3059 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3060
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3061 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3062 return false;
3063
3064 buffer[0] = val >> 8;
3065 buffer[1] = val & 0xff;
3066
3067 return true;
3068}
3069
3070static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3071 int count)
3072{
3073 struct ath_common *common = ath9k_hw_common(ah);
3074 int i;
3075
3076 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3077 ath_dbg(common, ATH_DBG_EEPROM,
3078 "eeprom address not in range\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3079 return false;
3080 }
3081
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3082 /*
3083 * Since we're reading the bytes in reverse order from a little-endian
3084 * word stream, an even address means we only use the lower half of
3085 * the 16-bit word at that address
3086 */
3087 if (address % 2 == 0) {
3088 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3089 goto error;
3090
3091 count--;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3092 }
3093
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3094 for (i = 0; i < count / 2; i++) {
3095 if (!ar9300_eeprom_read_word(common, address, buffer))
3096 goto error;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3097
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3098 address -= 2;
3099 buffer += 2;
3100 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3101
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3102 if (count % 2)
3103 if (!ar9300_eeprom_read_byte(common, address, buffer))
3104 goto error;
3105
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3106 return true;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3107
3108error:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3109 ath_dbg(common, ATH_DBG_EEPROM,
3110 "unable to read eeprom region at offset %d\n", address);
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3111 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3112}
3113
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3114static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3115{
3116 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3117
3118 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3119 AR9300_OTP_STATUS_VALID, 1000))
3120 return false;
3121
3122 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3123 return true;
3124}
3125
3126static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3127 int count)
3128{
3129 u32 data;
3130 int i;
3131
3132 for (i = 0; i < count; i++) {
3133 int offset = 8 * ((address - i) % 4);
3134 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3135 return false;
3136
3137 buffer[i] = (data >> offset) & 0xff;
3138 }
3139
3140 return true;
3141}
3142
3143
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3144static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3145 int *length, int *major, int *minor)
3146{
3147 unsigned long value[4];
3148
3149 value[0] = best[0];
3150 value[1] = best[1];
3151 value[2] = best[2];
3152 value[3] = best[3];
3153 *code = ((value[0] >> 5) & 0x0007);
3154 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3155 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3156 *major = (value[2] & 0x000f);
3157 *minor = (value[3] & 0x00ff);
3158}
3159
3160static u16 ar9300_comp_cksum(u8 *data, int dsize)
3161{
3162 int it, checksum = 0;
3163
3164 for (it = 0; it < dsize; it++) {
3165 checksum += data[it];
3166 checksum &= 0xffff;
3167 }
3168
3169 return checksum;
3170}
3171
3172static bool ar9300_uncompress_block(struct ath_hw *ah,
3173 u8 *mptr,
3174 int mdataSize,
3175 u8 *block,
3176 int size)
3177{
3178 int it;
3179 int spot;
3180 int offset;
3181 int length;
3182 struct ath_common *common = ath9k_hw_common(ah);
3183
3184 spot = 0;
3185
3186 for (it = 0; it < size; it += (length+2)) {
3187 offset = block[it];
3188 offset &= 0xff;
3189 spot += offset;
3190 length = block[it+1];
3191 length &= 0xff;
3192
Luis R. Rodriguez803288e2010-08-30 19:26:32 -0400[diff] [blame]3193 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3194 ath_dbg(common, ATH_DBG_EEPROM,
3195 "Restore at %d: spot=%d offset=%d length=%d\n",
3196 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3197 memcpy(&mptr[spot], &block[it+2], length);
3198 spot += length;
3199 } else if (length > 0) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3200 ath_dbg(common, ATH_DBG_EEPROM,
3201 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3202 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3203 return false;
3204 }
3205 }
3206 return true;
3207}
3208
3209static int ar9300_compress_decision(struct ath_hw *ah,
3210 int it,
3211 int code,
3212 int reference,
3213 u8 *mptr,
3214 u8 *word, int length, int mdata_size)
3215{
3216 struct ath_common *common = ath9k_hw_common(ah);
3217 u8 *dptr;
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3218 const struct ar9300_eeprom *eep = NULL;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3219
3220 switch (code) {
3221 case _CompressNone:
3222 if (length != mdata_size) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3223 ath_dbg(common, ATH_DBG_EEPROM,
3224 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3225 mdata_size, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3226 return -1;
3227 }
3228 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3229 ath_dbg(common, ATH_DBG_EEPROM,
3230 "restored eeprom %d: uncompressed, length %d\n",
3231 it, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3232 break;
3233 case _CompressBlock:
3234 if (reference == 0) {
3235 dptr = mptr;
3236 } else {
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3237 eep = ar9003_eeprom_struct_find_by_id(reference);
3238 if (eep == NULL) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3239 ath_dbg(common, ATH_DBG_EEPROM,
3240 "cant find reference eeprom struct %d\n",
3241 reference);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3242 return -1;
3243 }
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3244 memcpy(mptr, eep, mdata_size);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3245 }
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3246 ath_dbg(common, ATH_DBG_EEPROM,
3247 "restore eeprom %d: block, reference %d, length %d\n",
3248 it, reference, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3249 ar9300_uncompress_block(ah, mptr, mdata_size,
3250 (u8 *) (word + COMP_HDR_LEN), length);
3251 break;
3252 default:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3253 ath_dbg(common, ATH_DBG_EEPROM,
3254 "unknown compression code %d\n", code);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3255 return -1;
3256 }
3257 return 0;
3258}
3259
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3260typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3261 int count);
3262
3263static bool ar9300_check_header(void *data)
3264{
3265 u32 *word = data;
3266 return !(*word == 0 || *word == ~0);
3267}
3268
3269static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3270 int base_addr)
3271{
3272 u8 header[4];
3273
3274 if (!read(ah, base_addr, header, 4))
3275 return false;
3276
3277 return ar9300_check_header(header);
3278}
3279
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3280static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3281 int mdata_size)
3282{
3283 struct ath_common *common = ath9k_hw_common(ah);
3284 u16 *data = (u16 *) mptr;
3285 int i;
3286
3287 for (i = 0; i < mdata_size / 2; i++, data++)
3288 ath9k_hw_nvram_read(common, i, data);
3289
3290 return 0;
3291}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3292/*
3293 * Read the configuration data from the eeprom.
3294 * The data can be put in any specified memory buffer.
3295 *
3296 * Returns -1 on error.
3297 * Returns address of next memory location on success.
3298 */
3299static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3300 u8 *mptr, int mdata_size)
3301{
3302#define MDEFAULT 15
3303#define MSTATE 100
3304 int cptr;
3305 u8 *word;
3306 int code;
3307 int reference, length, major, minor;
3308 int osize;
3309 int it;
3310 u16 checksum, mchecksum;
3311 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3312 eeprom_read_op read;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3313
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3314 if (ath9k_hw_use_flash(ah))
3315 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3316
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3317 word = kzalloc(2048, GFP_KERNEL);
3318 if (!word)
3319 return -1;
3320
3321 memcpy(mptr, &ar9300_default, mdata_size);
3322
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3323 read = ar9300_read_eeprom;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3324 if (AR_SREV_9485(ah))
3325 cptr = AR9300_BASE_ADDR_4K;
3326 else
3327 cptr = AR9300_BASE_ADDR;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3328 ath_dbg(common, ATH_DBG_EEPROM,
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3329 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3330 if (ar9300_check_eeprom_header(ah, read, cptr))
3331 goto found;
3332
3333 cptr = AR9300_BASE_ADDR_512;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3334 ath_dbg(common, ATH_DBG_EEPROM,
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3335 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3336 if (ar9300_check_eeprom_header(ah, read, cptr))
3337 goto found;
3338
3339 read = ar9300_read_otp;
3340 cptr = AR9300_BASE_ADDR;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3341 ath_dbg(common, ATH_DBG_EEPROM,
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3342 "Trying OTP accesss at Address 0x%04x\n", cptr);
3343 if (ar9300_check_eeprom_header(ah, read, cptr))
3344 goto found;
3345
3346 cptr = AR9300_BASE_ADDR_512;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3347 ath_dbg(common, ATH_DBG_EEPROM,
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3348 "Trying OTP accesss at Address 0x%04x\n", cptr);
3349 if (ar9300_check_eeprom_header(ah, read, cptr))
3350 goto found;
3351
3352 goto fail;
3353
3354found:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3355 ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3356
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3357 for (it = 0; it < MSTATE; it++) {
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3358 if (!read(ah, cptr, word, COMP_HDR_LEN))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3359 goto fail;
3360
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3361 if (!ar9300_check_header(word))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3362 break;
3363
3364 ar9300_comp_hdr_unpack(word, &code, &reference,
3365 &length, &major, &minor);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3366 ath_dbg(common, ATH_DBG_EEPROM,
3367 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3368 cptr, code, reference, length, major, minor);
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3369 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3370 (AR_SREV_9485(ah) && length >= (4 * 1024))) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3371 ath_dbg(common, ATH_DBG_EEPROM,
3372 "Skipping bad header\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3373 cptr -= COMP_HDR_LEN;
3374 continue;
3375 }
3376
3377 osize = length;
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3378 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3379 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3380 mchecksum = word[COMP_HDR_LEN + osize] |
3381 (word[COMP_HDR_LEN + osize + 1] << 8);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3382 ath_dbg(common, ATH_DBG_EEPROM,
3383 "checksum %x %x\n", checksum, mchecksum);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3384 if (checksum == mchecksum) {
3385 ar9300_compress_decision(ah, it, code, reference, mptr,
3386 word, length, mdata_size);
3387 } else {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3388 ath_dbg(common, ATH_DBG_EEPROM,
3389 "skipping block with bad checksum\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3390 }
3391 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3392 }
3393
3394 kfree(word);
3395 return cptr;
3396
3397fail:
3398 kfree(word);
3399 return -1;
3400}
3401
3402/*
3403 * Restore the configuration structure by reading the eeprom.
3404 * This function destroys any existing in-memory structure
3405 * content.
3406 */
3407static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3408{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3409 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3410
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3411 if (ar9300_eeprom_restore_internal(ah, mptr,
3412 sizeof(struct ar9300_eeprom)) < 0)
3413 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3414
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3415 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3416}
3417
3418/* XXX: review hardware docs */
3419static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3420{
3421 return ah->eeprom.ar9300_eep.eepromVersion;
3422}
3423
3424/* XXX: could be read from the eepromVersion, not sure yet */
3425static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3426{
3427 return 0;
3428}
3429
3430static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
Rajkumar Manoharanf799a302010-09-16 11:40:06 +0530[diff] [blame]3431 enum ath9k_hal_freq_band freq_band)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3432{
3433 return 1;
3434}
3435
Felix Fietkau601e0cb2010-07-11 12:48:39 +0200[diff] [blame]3436static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3437 struct ath9k_channel *chan)
3438{
3439 return -EINVAL;
3440}
3441
3442static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3443{
3444 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3445
3446 if (is2ghz)
3447 return eep->modalHeader2G.xpaBiasLvl;
3448 else
3449 return eep->modalHeader5G.xpaBiasLvl;
3450}
3451
3452static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3453{
3454 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3455
3456 if (AR_SREV_9485(ah))
3457 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3458 else {
3459 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3460 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB,
3461 bias >> 2);
3462 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
3463 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3464}
3465
3466static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3467{
3468 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3469 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3470
3471 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3472 val = eep->modalHeader2G.antCtrlCommon;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3473 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3474 val = eep->modalHeader5G.antCtrlCommon;
3475 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3476}
3477
3478static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3479{
3480 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3481 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3482
3483 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3484 val = eep->modalHeader2G.antCtrlCommon2;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3485 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3486 val = eep->modalHeader5G.antCtrlCommon2;
3487 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3488}
3489
3490static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3491 int chain,
3492 bool is2ghz)
3493{
3494 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3495 __le16 val = 0;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3496
3497 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3498 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3499 val = eep->modalHeader2G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3500 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3501 val = eep->modalHeader5G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3502 }
3503
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3504 return le16_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3505}
3506
3507static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3508{
3509 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3510 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3511
3512 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3513 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3514
3515 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3516 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3517
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3518 if (!AR_SREV_9485(ah)) {
3519 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3520 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL,
3521 value);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3522
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3523 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3524 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL,
3525 value);
3526 }
3527
3528 if (AR_SREV_9485(ah)) {
3529 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3530 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
3531 value);
3532 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
3533 value >> 6);
3534 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
3535 value >> 7);
3536 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3537}
3538
3539static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3540{
3541 int drive_strength;
3542 unsigned long reg;
3543
3544 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3545
3546 if (!drive_strength)
3547 return;
3548
3549 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3550 reg &= ~0x00ffffc0;
3551 reg |= 0x5 << 21;
3552 reg |= 0x5 << 18;
3553 reg |= 0x5 << 15;
3554 reg |= 0x5 << 12;
3555 reg |= 0x5 << 9;
3556 reg |= 0x5 << 6;
3557 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3558
3559 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3560 reg &= ~0xffffffe0;
3561 reg |= 0x5 << 29;
3562 reg |= 0x5 << 26;
3563 reg |= 0x5 << 23;
3564 reg |= 0x5 << 20;
3565 reg |= 0x5 << 17;
3566 reg |= 0x5 << 14;
3567 reg |= 0x5 << 11;
3568 reg |= 0x5 << 8;
3569 reg |= 0x5 << 5;
3570 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3571
3572 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3573 reg &= ~0xff800000;
3574 reg |= 0x5 << 29;
3575 reg |= 0x5 << 26;
3576 reg |= 0x5 << 23;
3577 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3578}
3579
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3580static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3581 struct ath9k_channel *chan)
3582{
3583 int f[3], t[3];
3584 u16 value;
3585 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3586
3587 if (chain >= 0 && chain < 3) {
3588 if (IS_CHAN_2GHZ(chan))
3589 return eep->modalHeader2G.xatten1DB[chain];
3590 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3591 t[0] = eep->base_ext2.xatten1DBLow[chain];
3592 f[0] = 5180;
3593 t[1] = eep->modalHeader5G.xatten1DB[chain];
3594 f[1] = 5500;
3595 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3596 f[2] = 5785;
3597 value = ar9003_hw_power_interpolate((s32) chan->channel,
3598 f, t, 3);
3599 return value;
3600 } else
3601 return eep->modalHeader5G.xatten1DB[chain];
3602 }
3603
3604 return 0;
3605}
3606
3607
3608static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3609 struct ath9k_channel *chan)
3610{
3611 int f[3], t[3];
3612 u16 value;
3613 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3614
3615 if (chain >= 0 && chain < 3) {
3616 if (IS_CHAN_2GHZ(chan))
3617 return eep->modalHeader2G.xatten1Margin[chain];
3618 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3619 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3620 f[0] = 5180;
3621 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3622 f[1] = 5500;
3623 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3624 f[2] = 5785;
3625 value = ar9003_hw_power_interpolate((s32) chan->channel,
3626 f, t, 3);
3627 return value;
3628 } else
3629 return eep->modalHeader5G.xatten1Margin[chain];
3630 }
3631
3632 return 0;
3633}
3634
3635static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3636{
3637 int i;
3638 u16 value;
3639 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3640 AR_PHY_EXT_ATTEN_CTL_1,
3641 AR_PHY_EXT_ATTEN_CTL_2,
3642 };
3643
3644 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3645 for (i = 0; i < 3; i++) {
3646 value = ar9003_hw_atten_chain_get(ah, i, chan);
3647 REG_RMW_FIELD(ah, ext_atten_reg[i],
3648 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3649
3650 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3651 REG_RMW_FIELD(ah, ext_atten_reg[i],
3652 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
3653 }
3654}
3655
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3656static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3657{
3658 int timeout = 100;
3659
3660 while (pmu_set != REG_READ(ah, pmu_reg)) {
3661 if (timeout-- == 0)
3662 return false;
3663 REG_WRITE(ah, pmu_reg, pmu_set);
3664 udelay(10);
3665 }
3666
3667 return true;
3668}
3669
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3670static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3671{
3672 int internal_regulator =
3673 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3674
3675 if (internal_regulator) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3676 if (AR_SREV_9485(ah)) {
3677 int reg_pmu_set;
3678
3679 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3680 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3681 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3682 return;
3683
3684 reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
3685 (7 << 14) | (6 << 17) | (1 << 20) |
3686 (3 << 24) | (1 << 28);
3687
3688 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3689 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3690 return;
3691
3692 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3693 | (4 << 26);
3694 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3695 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3696 return;
3697
3698 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3699 | (1 << 21);
3700 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3701 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3702 return;
3703 } else {
3704 /* Internal regulator is ON. Write swreg register. */
3705 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3706 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3707 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3708 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3709 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3710 /* Set REG_CONTROL1.SWREG_PROGRAM */
3711 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3712 REG_READ(ah,
3713 AR_RTC_REG_CONTROL1) |
3714 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3715 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3716 } else {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3717 if (AR_SREV_9485(ah)) {
3718 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3719 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3720 AR_PHY_PMU2_PGM))
3721 udelay(10);
3722
3723 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3724 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3725 AR_PHY_PMU1_PWD))
3726 udelay(10);
3727 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3728 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3729 AR_PHY_PMU2_PGM))
3730 udelay(10);
3731 } else
3732 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3733 (REG_READ(ah,
3734 AR_RTC_SLEEP_CLK) |
3735 AR_RTC_FORCE_SWREG_PRD));
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3736 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3737
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3738}
3739
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame^]3740static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3741{
3742 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3743 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3744
3745 if (eep->baseEepHeader.featureEnable & 0x40) {
3746 tuning_caps_param &= 0x7f;
3747 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3748 tuning_caps_param);
3749 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3750 tuning_caps_param);
3751 }
3752}
3753
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3754static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3755 struct ath9k_channel *chan)
3756{
3757 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3758 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3759 ar9003_hw_drive_strength_apply(ah);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3760 ar9003_hw_atten_apply(ah, chan);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3761 ar9003_hw_internal_regulator_apply(ah);
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame^]3762 if (AR_SREV_9485(ah))
3763 ar9003_hw_apply_tuning_caps(ah);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3764}
3765
3766static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3767 struct ath9k_channel *chan)
3768{
3769}
3770
3771/*
3772 * Returns the interpolated y value corresponding to the specified x value
3773 * from the np ordered pairs of data (px,py).
3774 * The pairs do not have to be in any order.
3775 * If the specified x value is less than any of the px,
3776 * the returned y value is equal to the py for the lowest px.
3777 * If the specified x value is greater than any of the px,
3778 * the returned y value is equal to the py for the highest px.
3779 */
3780static int ar9003_hw_power_interpolate(int32_t x,
3781 int32_t *px, int32_t *py, u_int16_t np)
3782{
3783 int ip = 0;
3784 int lx = 0, ly = 0, lhave = 0;
3785 int hx = 0, hy = 0, hhave = 0;
3786 int dx = 0;
3787 int y = 0;
3788
3789 lhave = 0;
3790 hhave = 0;
3791
3792 /* identify best lower and higher x calibration measurement */
3793 for (ip = 0; ip < np; ip++) {
3794 dx = x - px[ip];
3795
3796 /* this measurement is higher than our desired x */
3797 if (dx <= 0) {
3798 if (!hhave || dx > (x - hx)) {
3799 /* new best higher x measurement */
3800 hx = px[ip];
3801 hy = py[ip];
3802 hhave = 1;
3803 }
3804 }
3805 /* this measurement is lower than our desired x */
3806 if (dx >= 0) {
3807 if (!lhave || dx < (x - lx)) {
3808 /* new best lower x measurement */
3809 lx = px[ip];
3810 ly = py[ip];
3811 lhave = 1;
3812 }
3813 }
3814 }
3815
3816 /* the low x is good */
3817 if (lhave) {
3818 /* so is the high x */
3819 if (hhave) {
3820 /* they're the same, so just pick one */
3821 if (hx == lx)
3822 y = ly;
3823 else /* interpolate */
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]3824 y = interpolate(x, lx, hx, ly, hy);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3825 } else /* only low is good, use it */
3826 y = ly;
3827 } else if (hhave) /* only high is good, use it */
3828 y = hy;
3829 else /* nothing is good,this should never happen unless np=0, ???? */
3830 y = -(1 << 30);
3831 return y;
3832}
3833
3834static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3835 u16 rateIndex, u16 freq, bool is2GHz)
3836{
3837 u16 numPiers, i;
3838 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3839 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3840 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3841 struct cal_tgt_pow_legacy *pEepromTargetPwr;
3842 u8 *pFreqBin;
3843
3844 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]3845 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3846 pEepromTargetPwr = eep->calTargetPower2G;
3847 pFreqBin = eep->calTarget_freqbin_2G;
3848 } else {
3849 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3850 pEepromTargetPwr = eep->calTargetPower5G;
3851 pFreqBin = eep->calTarget_freqbin_5G;
3852 }
3853
3854 /*
3855 * create array of channels and targetpower from
3856 * targetpower piers stored on eeprom
3857 */
3858 for (i = 0; i < numPiers; i++) {
3859 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3860 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3861 }
3862
3863 /* interpolate to get target power for given frequency */
3864 return (u8) ar9003_hw_power_interpolate((s32) freq,
3865 freqArray,
3866 targetPowerArray, numPiers);
3867}
3868
3869static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3870 u16 rateIndex,
3871 u16 freq, bool is2GHz)
3872{
3873 u16 numPiers, i;
3874 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3875 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3876 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3877 struct cal_tgt_pow_ht *pEepromTargetPwr;
3878 u8 *pFreqBin;
3879
3880 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]3881 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3882 pEepromTargetPwr = eep->calTargetPower2GHT20;
3883 pFreqBin = eep->calTarget_freqbin_2GHT20;
3884 } else {
3885 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3886 pEepromTargetPwr = eep->calTargetPower5GHT20;
3887 pFreqBin = eep->calTarget_freqbin_5GHT20;
3888 }
3889
3890 /*
3891 * create array of channels and targetpower
3892 * from targetpower piers stored on eeprom
3893 */
3894 for (i = 0; i < numPiers; i++) {
3895 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3896 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3897 }
3898
3899 /* interpolate to get target power for given frequency */
3900 return (u8) ar9003_hw_power_interpolate((s32) freq,
3901 freqArray,
3902 targetPowerArray, numPiers);
3903}
3904
3905static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3906 u16 rateIndex,
3907 u16 freq, bool is2GHz)
3908{
3909 u16 numPiers, i;
3910 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3911 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3912 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3913 struct cal_tgt_pow_ht *pEepromTargetPwr;
3914 u8 *pFreqBin;
3915
3916 if (is2GHz) {
3917 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3918 pEepromTargetPwr = eep->calTargetPower2GHT40;
3919 pFreqBin = eep->calTarget_freqbin_2GHT40;
3920 } else {
3921 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3922 pEepromTargetPwr = eep->calTargetPower5GHT40;
3923 pFreqBin = eep->calTarget_freqbin_5GHT40;
3924 }
3925
3926 /*
3927 * create array of channels and targetpower from
3928 * targetpower piers stored on eeprom
3929 */
3930 for (i = 0; i < numPiers; i++) {
3931 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3932 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3933 }
3934
3935 /* interpolate to get target power for given frequency */
3936 return (u8) ar9003_hw_power_interpolate((s32) freq,
3937 freqArray,
3938 targetPowerArray, numPiers);
3939}
3940
3941static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3942 u16 rateIndex, u16 freq)
3943{
3944 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3945 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3946 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3947 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3948 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3949 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3950
3951 /*
3952 * create array of channels and targetpower from
3953 * targetpower piers stored on eeprom
3954 */
3955 for (i = 0; i < numPiers; i++) {
3956 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3957 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3958 }
3959
3960 /* interpolate to get target power for given frequency */
3961 return (u8) ar9003_hw_power_interpolate((s32) freq,
3962 freqArray,
3963 targetPowerArray, numPiers);
3964}
3965
3966/* Set tx power registers to array of values passed in */
3967static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
3968{
3969#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
3970 /* make sure forced gain is not set */
3971 REG_WRITE(ah, 0xa458, 0);
3972
3973 /* Write the OFDM power per rate set */
3974
3975 /* 6 (LSB), 9, 12, 18 (MSB) */
3976 REG_WRITE(ah, 0xa3c0,
3977 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
3978 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
3979 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
3980 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3981
3982 /* 24 (LSB), 36, 48, 54 (MSB) */
3983 REG_WRITE(ah, 0xa3c4,
3984 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
3985 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
3986 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
3987 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3988
3989 /* Write the CCK power per rate set */
3990
3991 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3992 REG_WRITE(ah, 0xa3c8,
3993 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
3994 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
3995 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
3996 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
3997
3998 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3999 REG_WRITE(ah, 0xa3cc,
4000 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4001 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4002 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4003 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4004 );
4005
4006 /* Write the HT20 power per rate set */
4007
4008 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4009 REG_WRITE(ah, 0xa3d0,
4010 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4011 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4012 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4013 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4014 );
4015
4016 /* 6 (LSB), 7, 12, 13 (MSB) */
4017 REG_WRITE(ah, 0xa3d4,
4018 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4019 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4020 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4021 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4022 );
4023
4024 /* 14 (LSB), 15, 20, 21 */
4025 REG_WRITE(ah, 0xa3e4,
4026 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4027 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4028 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4029 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4030 );
4031
4032 /* Mixed HT20 and HT40 rates */
4033
4034 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4035 REG_WRITE(ah, 0xa3e8,
4036 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4037 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4038 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4039 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4040 );
4041
4042 /*
4043 * Write the HT40 power per rate set
4044 * correct PAR difference between HT40 and HT20/LEGACY
4045 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4046 */
4047 REG_WRITE(ah, 0xa3d8,
4048 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4049 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4050 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4051 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4052 );
4053
4054 /* 6 (LSB), 7, 12, 13 (MSB) */
4055 REG_WRITE(ah, 0xa3dc,
4056 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4057 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4058 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4059 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4060 );
4061
4062 /* 14 (LSB), 15, 20, 21 */
4063 REG_WRITE(ah, 0xa3ec,
4064 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4065 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4066 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4067 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4068 );
4069
4070 return 0;
4071#undef POW_SM
4072}
4073
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4074static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4075 u8 *targetPowerValT2)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4076{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4077 /* XXX: hard code for now, need to get from eeprom struct */
4078 u8 ht40PowerIncForPdadc = 0;
4079 bool is2GHz = false;
4080 unsigned int i = 0;
4081 struct ath_common *common = ath9k_hw_common(ah);
4082
4083 if (freq < 4000)
4084 is2GHz = true;
4085
4086 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4087 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4088 is2GHz);
4089 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4090 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4091 is2GHz);
4092 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4093 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4094 is2GHz);
4095 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4096 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4097 is2GHz);
4098 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4099 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4100 freq);
4101 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4102 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4103 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4104 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4105 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4106 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4107 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4108 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4109 is2GHz);
4110 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4111 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4112 freq, is2GHz);
4113 targetPowerValT2[ALL_TARGET_HT20_4] =
4114 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4115 is2GHz);
4116 targetPowerValT2[ALL_TARGET_HT20_5] =
4117 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4118 is2GHz);
4119 targetPowerValT2[ALL_TARGET_HT20_6] =
4120 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4121 is2GHz);
4122 targetPowerValT2[ALL_TARGET_HT20_7] =
4123 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4124 is2GHz);
4125 targetPowerValT2[ALL_TARGET_HT20_12] =
4126 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4127 is2GHz);
4128 targetPowerValT2[ALL_TARGET_HT20_13] =
4129 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4130 is2GHz);
4131 targetPowerValT2[ALL_TARGET_HT20_14] =
4132 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4133 is2GHz);
4134 targetPowerValT2[ALL_TARGET_HT20_15] =
4135 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4136 is2GHz);
4137 targetPowerValT2[ALL_TARGET_HT20_20] =
4138 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4139 is2GHz);
4140 targetPowerValT2[ALL_TARGET_HT20_21] =
4141 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4142 is2GHz);
4143 targetPowerValT2[ALL_TARGET_HT20_22] =
4144 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4145 is2GHz);
4146 targetPowerValT2[ALL_TARGET_HT20_23] =
4147 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4148 is2GHz);
4149 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4150 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4151 is2GHz) + ht40PowerIncForPdadc;
4152 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4153 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4154 freq,
4155 is2GHz) + ht40PowerIncForPdadc;
4156 targetPowerValT2[ALL_TARGET_HT40_4] =
4157 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4158 is2GHz) + ht40PowerIncForPdadc;
4159 targetPowerValT2[ALL_TARGET_HT40_5] =
4160 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4161 is2GHz) + ht40PowerIncForPdadc;
4162 targetPowerValT2[ALL_TARGET_HT40_6] =
4163 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4164 is2GHz) + ht40PowerIncForPdadc;
4165 targetPowerValT2[ALL_TARGET_HT40_7] =
4166 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4167 is2GHz) + ht40PowerIncForPdadc;
4168 targetPowerValT2[ALL_TARGET_HT40_12] =
4169 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4170 is2GHz) + ht40PowerIncForPdadc;
4171 targetPowerValT2[ALL_TARGET_HT40_13] =
4172 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4173 is2GHz) + ht40PowerIncForPdadc;
4174 targetPowerValT2[ALL_TARGET_HT40_14] =
4175 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4176 is2GHz) + ht40PowerIncForPdadc;
4177 targetPowerValT2[ALL_TARGET_HT40_15] =
4178 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4179 is2GHz) + ht40PowerIncForPdadc;
4180 targetPowerValT2[ALL_TARGET_HT40_20] =
4181 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4182 is2GHz) + ht40PowerIncForPdadc;
4183 targetPowerValT2[ALL_TARGET_HT40_21] =
4184 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4185 is2GHz) + ht40PowerIncForPdadc;
4186 targetPowerValT2[ALL_TARGET_HT40_22] =
4187 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4188 is2GHz) + ht40PowerIncForPdadc;
4189 targetPowerValT2[ALL_TARGET_HT40_23] =
4190 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4191 is2GHz) + ht40PowerIncForPdadc;
4192
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]4193 for (i = 0; i < ar9300RateSize; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4194 ath_dbg(common, ATH_DBG_EEPROM,
4195 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4196 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4197}
4198
4199static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4200 int mode,
4201 int ipier,
4202 int ichain,
4203 int *pfrequency,
4204 int *pcorrection,
4205 int *ptemperature, int *pvoltage)
4206{
4207 u8 *pCalPier;
4208 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4209 int is2GHz;
4210 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4211 struct ath_common *common = ath9k_hw_common(ah);
4212
4213 if (ichain >= AR9300_MAX_CHAINS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4214 ath_dbg(common, ATH_DBG_EEPROM,
4215 "Invalid chain index, must be less than %d\n",
4216 AR9300_MAX_CHAINS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4217 return -1;
4218 }
4219
4220 if (mode) { /* 5GHz */
4221 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4222 ath_dbg(common, ATH_DBG_EEPROM,
4223 "Invalid 5GHz cal pier index, must be less than %d\n",
4224 AR9300_NUM_5G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4225 return -1;
4226 }
4227 pCalPier = &(eep->calFreqPier5G[ipier]);
4228 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4229 is2GHz = 0;
4230 } else {
4231 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4232 ath_dbg(common, ATH_DBG_EEPROM,
4233 "Invalid 2GHz cal pier index, must be less than %d\n",
4234 AR9300_NUM_2G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4235 return -1;
4236 }
4237
4238 pCalPier = &(eep->calFreqPier2G[ipier]);
4239 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4240 is2GHz = 1;
4241 }
4242
4243 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4244 *pcorrection = pCalPierStruct->refPower;
4245 *ptemperature = pCalPierStruct->tempMeas;
4246 *pvoltage = pCalPierStruct->voltMeas;
4247
4248 return 0;
4249}
4250
4251static int ar9003_hw_power_control_override(struct ath_hw *ah,
4252 int frequency,
4253 int *correction,
4254 int *voltage, int *temperature)
4255{
4256 int tempSlope = 0;
4257 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4258 int f[3], t[3];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4259
4260 REG_RMW(ah, AR_PHY_TPC_11_B0,
4261 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4262 AR_PHY_TPC_OLPC_GAIN_DELTA);
4263 REG_RMW(ah, AR_PHY_TPC_11_B1,
4264 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4265 AR_PHY_TPC_OLPC_GAIN_DELTA);
4266 REG_RMW(ah, AR_PHY_TPC_11_B2,
4267 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4268 AR_PHY_TPC_OLPC_GAIN_DELTA);
4269
4270 /* enable open loop power control on chip */
4271 REG_RMW(ah, AR_PHY_TPC_6_B0,
4272 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4273 AR_PHY_TPC_6_ERROR_EST_MODE);
4274 REG_RMW(ah, AR_PHY_TPC_6_B1,
4275 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4276 AR_PHY_TPC_6_ERROR_EST_MODE);
4277 REG_RMW(ah, AR_PHY_TPC_6_B2,
4278 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4279 AR_PHY_TPC_6_ERROR_EST_MODE);
4280
4281 /*
4282 * enable temperature compensation
4283 * Need to use register names
4284 */
4285 if (frequency < 4000)
4286 tempSlope = eep->modalHeader2G.tempSlope;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4287 else if (eep->base_ext2.tempSlopeLow != 0) {
4288 t[0] = eep->base_ext2.tempSlopeLow;
4289 f[0] = 5180;
4290 t[1] = eep->modalHeader5G.tempSlope;
4291 f[1] = 5500;
4292 t[2] = eep->base_ext2.tempSlopeHigh;
4293 f[2] = 5785;
4294 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4295 f, t, 3);
4296 } else
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4297 tempSlope = eep->modalHeader5G.tempSlope;
4298
4299 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4300 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4301 temperature[0]);
4302
4303 return 0;
4304}
4305
4306/* Apply the recorded correction values. */
4307static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4308{
4309 int ichain, ipier, npier;
4310 int mode;
4311 int lfrequency[AR9300_MAX_CHAINS],
4312 lcorrection[AR9300_MAX_CHAINS],
4313 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4314 int hfrequency[AR9300_MAX_CHAINS],
4315 hcorrection[AR9300_MAX_CHAINS],
4316 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4317 int fdiff;
4318 int correction[AR9300_MAX_CHAINS],
4319 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4320 int pfrequency, pcorrection, ptemperature, pvoltage;
4321 struct ath_common *common = ath9k_hw_common(ah);
4322
4323 mode = (frequency >= 4000);
4324 if (mode)
4325 npier = AR9300_NUM_5G_CAL_PIERS;
4326 else
4327 npier = AR9300_NUM_2G_CAL_PIERS;
4328
4329 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4330 lfrequency[ichain] = 0;
4331 hfrequency[ichain] = 100000;
4332 }
4333 /* identify best lower and higher frequency calibration measurement */
4334 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4335 for (ipier = 0; ipier < npier; ipier++) {
4336 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4337 &pfrequency, &pcorrection,
4338 &ptemperature, &pvoltage)) {
4339 fdiff = frequency - pfrequency;
4340
4341 /*
4342 * this measurement is higher than
4343 * our desired frequency
4344 */
4345 if (fdiff <= 0) {
4346 if (hfrequency[ichain] <= 0 ||
4347 hfrequency[ichain] >= 100000 ||
4348 fdiff >
4349 (frequency - hfrequency[ichain])) {
4350 /*
4351 * new best higher
4352 * frequency measurement
4353 */
4354 hfrequency[ichain] = pfrequency;
4355 hcorrection[ichain] =
4356 pcorrection;
4357 htemperature[ichain] =
4358 ptemperature;
4359 hvoltage[ichain] = pvoltage;
4360 }
4361 }
4362 if (fdiff >= 0) {
4363 if (lfrequency[ichain] <= 0
4364 || fdiff <
4365 (frequency - lfrequency[ichain])) {
4366 /*
4367 * new best lower
4368 * frequency measurement
4369 */
4370 lfrequency[ichain] = pfrequency;
4371 lcorrection[ichain] =
4372 pcorrection;
4373 ltemperature[ichain] =
4374 ptemperature;
4375 lvoltage[ichain] = pvoltage;
4376 }
4377 }
4378 }
4379 }
4380 }
4381
4382 /* interpolate */
4383 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4384 ath_dbg(common, ATH_DBG_EEPROM,
4385 "ch=%d f=%d low=%d %d h=%d %d\n",
4386 ichain, frequency, lfrequency[ichain],
4387 lcorrection[ichain], hfrequency[ichain],
4388 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4389 /* they're the same, so just pick one */
4390 if (hfrequency[ichain] == lfrequency[ichain]) {
4391 correction[ichain] = lcorrection[ichain];
4392 voltage[ichain] = lvoltage[ichain];
4393 temperature[ichain] = ltemperature[ichain];
4394 }
4395 /* the low frequency is good */
4396 else if (frequency - lfrequency[ichain] < 1000) {
4397 /* so is the high frequency, interpolate */
4398 if (hfrequency[ichain] - frequency < 1000) {
4399
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4400 correction[ichain] = interpolate(frequency,
4401 lfrequency[ichain],
4402 hfrequency[ichain],
4403 lcorrection[ichain],
4404 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4405
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4406 temperature[ichain] = interpolate(frequency,
4407 lfrequency[ichain],
4408 hfrequency[ichain],
4409 ltemperature[ichain],
4410 htemperature[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4411
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4412 voltage[ichain] = interpolate(frequency,
4413 lfrequency[ichain],
4414 hfrequency[ichain],
4415 lvoltage[ichain],
4416 hvoltage[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4417 }
4418 /* only low is good, use it */
4419 else {
4420 correction[ichain] = lcorrection[ichain];
4421 temperature[ichain] = ltemperature[ichain];
4422 voltage[ichain] = lvoltage[ichain];
4423 }
4424 }
4425 /* only high is good, use it */
4426 else if (hfrequency[ichain] - frequency < 1000) {
4427 correction[ichain] = hcorrection[ichain];
4428 temperature[ichain] = htemperature[ichain];
4429 voltage[ichain] = hvoltage[ichain];
4430 } else { /* nothing is good, presume 0???? */
4431 correction[ichain] = 0;
4432 temperature[ichain] = 0;
4433 voltage[ichain] = 0;
4434 }
4435 }
4436
4437 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4438 temperature);
4439
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4440 ath_dbg(common, ATH_DBG_EEPROM,
4441 "for frequency=%d, calibration correction = %d %d %d\n",
4442 frequency, correction[0], correction[1], correction[2]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4443
4444 return 0;
4445}
4446
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4447static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4448 int idx,
4449 int edge,
4450 bool is2GHz)
4451{
4452 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4453 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4454
4455 if (is2GHz)
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4456 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4457 else
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4458 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4459}
4460
4461static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4462 int idx,
4463 unsigned int edge,
4464 u16 freq,
4465 bool is2GHz)
4466{
4467 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4468 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4469
4470 u8 *ctl_freqbin = is2GHz ?
4471 &eep->ctl_freqbin_2G[idx][0] :
4472 &eep->ctl_freqbin_5G[idx][0];
4473
4474 if (is2GHz) {
4475 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4476 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4477 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4478 } else {
4479 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4480 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4481 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4482 }
4483
4484 return AR9300_MAX_RATE_POWER;
4485}
4486
4487/*
4488 * Find the maximum conformance test limit for the given channel and CTL info
4489 */
4490static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4491 u16 freq, int idx, bool is2GHz)
4492{
4493 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4494 u8 *ctl_freqbin = is2GHz ?
4495 &eep->ctl_freqbin_2G[idx][0] :
4496 &eep->ctl_freqbin_5G[idx][0];
4497 u16 num_edges = is2GHz ?
4498 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4499 unsigned int edge;
4500
4501 /* Get the edge power */
4502 for (edge = 0;
4503 (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
4504 edge++) {
4505 /*
4506 * If there's an exact channel match or an inband flag set
4507 * on the lower channel use the given rdEdgePower
4508 */
4509 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4510 twiceMaxEdgePower =
4511 ar9003_hw_get_direct_edge_power(eep, idx,
4512 edge, is2GHz);
4513 break;
4514 } else if ((edge > 0) &&
4515 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4516 is2GHz))) {
4517 twiceMaxEdgePower =
4518 ar9003_hw_get_indirect_edge_power(eep, idx,
4519 edge, freq,
4520 is2GHz);
4521 /*
4522 * Leave loop - no more affecting edges possible in
4523 * this monotonic increasing list
4524 */
4525 break;
4526 }
4527 }
4528 return twiceMaxEdgePower;
4529}
4530
4531static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4532 struct ath9k_channel *chan,
4533 u8 *pPwrArray, u16 cfgCtl,
4534 u8 twiceAntennaReduction,
4535 u8 twiceMaxRegulatoryPower,
4536 u16 powerLimit)
4537{
4538 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4539 struct ath_common *common = ath9k_hw_common(ah);
4540 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4541 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4542 static const u16 tpScaleReductionTable[5] = {
4543 0, 3, 6, 9, AR9300_MAX_RATE_POWER
4544 };
4545 int i;
4546 int16_t twiceLargestAntenna;
4547 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4548 static const u16 ctlModesFor11a[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4549 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4550 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4551 static const u16 ctlModesFor11g[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4552 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4553 CTL_11G_EXT, CTL_2GHT40
4554 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4555 u16 numCtlModes;
4556 const u16 *pCtlMode;
4557 u16 ctlMode, freq;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4558 struct chan_centers centers;
4559 u8 *ctlIndex;
4560 u8 ctlNum;
4561 u16 twiceMinEdgePower;
4562 bool is2ghz = IS_CHAN_2GHZ(chan);
4563
4564 ath9k_hw_get_channel_centers(ah, chan, &centers);
4565
4566 /* Compute TxPower reduction due to Antenna Gain */
4567 if (is2ghz)
4568 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4569 else
4570 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4571
4572 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4573 twiceLargestAntenna, 0);
4574
4575 /*
4576 * scaledPower is the minimum of the user input power level
4577 * and the regulatory allowed power level
4578 */
4579 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4580
4581 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4582 maxRegAllowedPower -=
4583 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4584 }
4585
4586 scaledPower = min(powerLimit, maxRegAllowedPower);
4587
4588 /*
4589 * Reduce scaled Power by number of chains active to get
4590 * to per chain tx power level
4591 */
4592 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4593 case 1:
4594 break;
4595 case 2:
4596 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4597 break;
4598 case 3:
4599 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4600 break;
4601 }
4602
4603 scaledPower = max((u16)0, scaledPower);
4604
4605 /*
4606 * Get target powers from EEPROM - our baseline for TX Power
4607 */
4608 if (is2ghz) {
4609 /* Setup for CTL modes */
4610 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4611 numCtlModes =
4612 ARRAY_SIZE(ctlModesFor11g) -
4613 SUB_NUM_CTL_MODES_AT_2G_40;
4614 pCtlMode = ctlModesFor11g;
4615 if (IS_CHAN_HT40(chan))
4616 /* All 2G CTL's */
4617 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4618 } else {
4619 /* Setup for CTL modes */
4620 /* CTL_11A, CTL_5GHT20 */
4621 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4622 SUB_NUM_CTL_MODES_AT_5G_40;
4623 pCtlMode = ctlModesFor11a;
4624 if (IS_CHAN_HT40(chan))
4625 /* All 5G CTL's */
4626 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4627 }
4628
4629 /*
4630 * For MIMO, need to apply regulatory caps individually across
4631 * dynamically running modes: CCK, OFDM, HT20, HT40
4632 *
4633 * The outer loop walks through each possible applicable runtime mode.
4634 * The inner loop walks through each ctlIndex entry in EEPROM.
4635 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4636 */
4637 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4638 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4639 (pCtlMode[ctlMode] == CTL_2GHT40);
4640 if (isHt40CtlMode)
4641 freq = centers.synth_center;
4642 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4643 freq = centers.ext_center;
4644 else
4645 freq = centers.ctl_center;
4646
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4647 ath_dbg(common, ATH_DBG_REGULATORY,
4648 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4649 ctlMode, numCtlModes, isHt40CtlMode,
4650 (pCtlMode[ctlMode] & EXT_ADDITIVE));
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4651
4652 /* walk through each CTL index stored in EEPROM */
4653 if (is2ghz) {
4654 ctlIndex = pEepData->ctlIndex_2G;
4655 ctlNum = AR9300_NUM_CTLS_2G;
4656 } else {
4657 ctlIndex = pEepData->ctlIndex_5G;
4658 ctlNum = AR9300_NUM_CTLS_5G;
4659 }
4660
4661 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4662 ath_dbg(common, ATH_DBG_REGULATORY,
4663 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4664 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4665 chan->channel);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4666
4667 /*
4668 * compare test group from regulatory
4669 * channel list with test mode from pCtlMode
4670 * list
4671 */
4672 if ((((cfgCtl & ~CTL_MODE_M) |
4673 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4674 ctlIndex[i]) ||
4675 (((cfgCtl & ~CTL_MODE_M) |
4676 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4677 ((ctlIndex[i] & CTL_MODE_M) |
4678 SD_NO_CTL))) {
4679 twiceMinEdgePower =
4680 ar9003_hw_get_max_edge_power(pEepData,
4681 freq, i,
4682 is2ghz);
4683
4684 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4685 /*
4686 * Find the minimum of all CTL
4687 * edge powers that apply to
4688 * this channel
4689 */
4690 twiceMaxEdgePower =
4691 min(twiceMaxEdgePower,
4692 twiceMinEdgePower);
4693 else {
4694 /* specific */
4695 twiceMaxEdgePower =
4696 twiceMinEdgePower;
4697 break;
4698 }
4699 }
4700 }
4701
4702 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4703
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4704 ath_dbg(common, ATH_DBG_REGULATORY,
4705 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4706 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4707 scaledPower, minCtlPower);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4708
4709 /* Apply ctl mode to correct target power set */
4710 switch (pCtlMode[ctlMode]) {
4711 case CTL_11B:
4712 for (i = ALL_TARGET_LEGACY_1L_5L;
4713 i <= ALL_TARGET_LEGACY_11S; i++)
4714 pPwrArray[i] =
4715 (u8)min((u16)pPwrArray[i],
4716 minCtlPower);
4717 break;
4718 case CTL_11A:
4719 case CTL_11G:
4720 for (i = ALL_TARGET_LEGACY_6_24;
4721 i <= ALL_TARGET_LEGACY_54; i++)
4722 pPwrArray[i] =
4723 (u8)min((u16)pPwrArray[i],
4724 minCtlPower);
4725 break;
4726 case CTL_5GHT20:
4727 case CTL_2GHT20:
4728 for (i = ALL_TARGET_HT20_0_8_16;
4729 i <= ALL_TARGET_HT20_21; i++)
4730 pPwrArray[i] =
4731 (u8)min((u16)pPwrArray[i],
4732 minCtlPower);
4733 pPwrArray[ALL_TARGET_HT20_22] =
4734 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4735 minCtlPower);
4736 pPwrArray[ALL_TARGET_HT20_23] =
4737 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4738 minCtlPower);
4739 break;
4740 case CTL_5GHT40:
4741 case CTL_2GHT40:
4742 for (i = ALL_TARGET_HT40_0_8_16;
4743 i <= ALL_TARGET_HT40_23; i++)
4744 pPwrArray[i] =
4745 (u8)min((u16)pPwrArray[i],
4746 minCtlPower);
4747 break;
4748 default:
4749 break;
4750 }
4751 } /* end ctl mode checking */
4752}
4753
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4754static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4755 struct ath9k_channel *chan, u16 cfgCtl,
4756 u8 twiceAntennaReduction,
4757 u8 twiceMaxRegulatoryPower,
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4758 u8 powerLimit, bool test)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4759{
Felix Fietkau6b7b6cf2010-10-20 02:09:44 +0200[diff] [blame]4760 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4761 struct ath_common *common = ath9k_hw_common(ah);
4762 u8 targetPowerValT2[ar9300RateSize];
4763 unsigned int i = 0;
4764
4765 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4766 ar9003_hw_set_power_per_rate_table(ah, chan,
4767 targetPowerValT2, cfgCtl,
4768 twiceAntennaReduction,
4769 twiceMaxRegulatoryPower,
4770 powerLimit);
4771
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4772 regulatory->max_power_level = 0;
4773 for (i = 0; i < ar9300RateSize; i++) {
4774 if (targetPowerValT2[i] > regulatory->max_power_level)
4775 regulatory->max_power_level = targetPowerValT2[i];
4776 }
4777
4778 if (test)
4779 return;
4780
4781 for (i = 0; i < ar9300RateSize; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4782 ath_dbg(common, ATH_DBG_EEPROM,
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]4783 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4784 }
4785
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4786 /*
4787 * This is the TX power we send back to driver core,
4788 * and it can use to pass to userspace to display our
4789 * currently configured TX power setting.
4790 *
4791 * Since power is rate dependent, use one of the indices
4792 * from the AR9300_Rates enum to select an entry from
4793 * targetPowerValT2[] to report. Currently returns the
4794 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4795 * as CCK power is less interesting (?).
4796 */
4797 i = ALL_TARGET_LEGACY_6_24; /* legacy */
4798 if (IS_CHAN_HT40(chan))
4799 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4800 else if (IS_CHAN_HT20(chan))
4801 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4802
4803 ah->txpower_limit = targetPowerValT2[i];
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4804 regulatory->max_power_level = targetPowerValT2[i];
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4805
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4806 /* Write target power array to registers */
4807 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4808 ar9003_hw_calibration_apply(ah, chan->channel);
4809}
4810
4811static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4812 u16 i, bool is2GHz)
4813{
4814 return AR_NO_SPUR;
4815}
4816
Luis R. Rodriguezc14a85d2010-04-15 17:39:21 -0400[diff] [blame]4817s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4818{
4819 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4820
4821 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4822}
4823
4824s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4825{
4826 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4827
4828 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4829}
4830
Vasanthakumar Thiagarajan272ceba2010-12-06 04:27:46 -0800[diff] [blame]4831u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
4832{
4833 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4834
4835 if (is_2ghz)
4836 return eep->modalHeader2G.spurChans;
4837 else
4838 return eep->modalHeader5G.spurChans;
4839}
4840
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4841const struct eeprom_ops eep_ar9300_ops = {
4842 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4843 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4844 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4845 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4846 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
4847 .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
4848 .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
4849 .set_board_values = ath9k_hw_ar9300_set_board_values,
4850 .set_addac = ath9k_hw_ar9300_set_addac,
4851 .set_txpower = ath9k_hw_ar9300_set_txpower,
4852 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
4853};