blob: bcceee8114a45bc3d8758ba3b9c874e31b61207b [file] [log] [blame]
Andy Yanb21f4b62014-12-05 14:26:31 +08001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DW_HDMI__
11#define __DW_HDMI__
12
13#include <drm/drmP.h>
14
Russell Kingb5814ff2015-03-27 12:50:58 +000015struct dw_hdmi;
16
Andy Yanb21f4b62014-12-05 14:26:31 +080017enum {
18 DW_HDMI_RES_8,
19 DW_HDMI_RES_10,
20 DW_HDMI_RES_12,
21 DW_HDMI_RES_MAX,
22};
23
Laurent Pinchartfaba6c32017-01-17 10:29:06 +020024enum dw_hdmi_phy_type {
25 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
26 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
27 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
28 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
29 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
30 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
31 DW_HDMI_PHY_VENDOR_PHY = 0xfe,
32};
33
Andy Yanb21f4b62014-12-05 14:26:31 +080034struct dw_hdmi_mpll_config {
35 unsigned long mpixelclock;
36 struct {
37 u16 cpce;
38 u16 gmp;
39 } res[DW_HDMI_RES_MAX];
40};
41
42struct dw_hdmi_curr_ctrl {
43 unsigned long mpixelclock;
44 u16 curr[DW_HDMI_RES_MAX];
45};
46
Yakir Yang034705a2015-03-31 23:56:10 -040047struct dw_hdmi_phy_config {
Andy Yanb21f4b62014-12-05 14:26:31 +080048 unsigned long mpixelclock;
49 u16 sym_ctr; /*clock symbol and transmitter control*/
50 u16 term; /*transmission termination value*/
Yakir Yang034705a2015-03-31 23:56:10 -040051 u16 vlev_ctr; /* voltage level control */
Andy Yanb21f4b62014-12-05 14:26:31 +080052};
53
Laurent Pinchartf1585f62017-03-06 01:36:15 +020054struct dw_hdmi_phy_ops {
55 int (*init)(struct dw_hdmi *hdmi, void *data,
56 struct drm_display_mode *mode);
57 void (*disable)(struct dw_hdmi *hdmi, void *data);
58 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
59};
60
Andy Yanb21f4b62014-12-05 14:26:31 +080061struct dw_hdmi_plat_data {
Neil Armstrong80e2f972017-03-03 19:20:06 +020062 struct regmap *regm;
Laurent Pinchartf1585f62017-03-06 01:36:15 +020063 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
64 struct drm_display_mode *mode);
65
66 /* Vendor PHY support */
67 const struct dw_hdmi_phy_ops *phy_ops;
68 const char *phy_name;
69 void *phy_data;
70
71 /* Synopsys PHY support */
Andy Yanb21f4b62014-12-05 14:26:31 +080072 const struct dw_hdmi_mpll_config *mpll_cfg;
73 const struct dw_hdmi_curr_ctrl *cur_ctr;
Yakir Yang034705a2015-03-31 23:56:10 -040074 const struct dw_hdmi_phy_config *phy_config;
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +020075 int (*configure_phy)(struct dw_hdmi *hdmi,
76 const struct dw_hdmi_plat_data *pdata,
77 unsigned long mpixelclock);
Andy Yanb21f4b62014-12-05 14:26:31 +080078};
79
Laurent Pinchart69497eb2017-01-17 10:29:00 +020080int dw_hdmi_probe(struct platform_device *pdev,
81 const struct dw_hdmi_plat_data *plat_data);
82void dw_hdmi_remove(struct platform_device *pdev);
Laurent Pinchartecaa98f2017-01-17 10:28:52 +020083void dw_hdmi_unbind(struct device *dev);
Laurent Pinchartc6081192017-01-17 10:28:57 +020084int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
Andy Yanb21f4b62014-12-05 14:26:31 +080085 const struct dw_hdmi_plat_data *plat_data);
Russell Kingb5814ff2015-03-27 12:50:58 +000086
87void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
Russell Kingb90120a2015-03-27 12:59:58 +000088void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
89void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
Russell Kingb5814ff2015-03-27 12:50:58 +000090
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +020091/* PHY configuration */
92void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
93 unsigned char addr);
94
Andy Yanb21f4b62014-12-05 14:26:31 +080095#endif /* __IMX_HDMI_H__ */