blob: 0f583ca7e66efb09a9c40ee46b8188b3676c6703 [file] [log] [blame]
Andy Yanb21f4b62014-12-05 14:26:31 +08001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DW_HDMI__
11#define __DW_HDMI__
12
13#include <drm/drmP.h>
14
Russell Kingb5814ff2015-03-27 12:50:58 +000015struct dw_hdmi;
16
Andy Yanb21f4b62014-12-05 14:26:31 +080017enum {
18 DW_HDMI_RES_8,
19 DW_HDMI_RES_10,
20 DW_HDMI_RES_12,
21 DW_HDMI_RES_MAX,
22};
23
24enum dw_hdmi_devtype {
25 IMX6Q_HDMI,
26 IMX6DL_HDMI,
Andy Yan12b9f202015-01-07 15:48:27 +080027 RK3288_HDMI,
Andy Yanb21f4b62014-12-05 14:26:31 +080028};
29
Laurent Pinchartfaba6c32017-01-17 10:29:06 +020030enum dw_hdmi_phy_type {
31 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
32 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
33 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
34 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
35 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
36 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
37 DW_HDMI_PHY_VENDOR_PHY = 0xfe,
38};
39
Andy Yanb21f4b62014-12-05 14:26:31 +080040struct dw_hdmi_mpll_config {
41 unsigned long mpixelclock;
42 struct {
43 u16 cpce;
44 u16 gmp;
45 } res[DW_HDMI_RES_MAX];
46};
47
48struct dw_hdmi_curr_ctrl {
49 unsigned long mpixelclock;
50 u16 curr[DW_HDMI_RES_MAX];
51};
52
Yakir Yang034705a2015-03-31 23:56:10 -040053struct dw_hdmi_phy_config {
Andy Yanb21f4b62014-12-05 14:26:31 +080054 unsigned long mpixelclock;
55 u16 sym_ctr; /*clock symbol and transmitter control*/
56 u16 term; /*transmission termination value*/
Yakir Yang034705a2015-03-31 23:56:10 -040057 u16 vlev_ctr; /* voltage level control */
Andy Yanb21f4b62014-12-05 14:26:31 +080058};
59
Laurent Pinchartf1585f62017-03-06 01:36:15 +020060struct dw_hdmi_phy_ops {
61 int (*init)(struct dw_hdmi *hdmi, void *data,
62 struct drm_display_mode *mode);
63 void (*disable)(struct dw_hdmi *hdmi, void *data);
64 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
65};
66
Andy Yanb21f4b62014-12-05 14:26:31 +080067struct dw_hdmi_plat_data {
68 enum dw_hdmi_devtype dev_type;
Laurent Pinchartf1585f62017-03-06 01:36:15 +020069 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
70 struct drm_display_mode *mode);
71
72 /* Vendor PHY support */
73 const struct dw_hdmi_phy_ops *phy_ops;
74 const char *phy_name;
75 void *phy_data;
76
77 /* Synopsys PHY support */
Andy Yanb21f4b62014-12-05 14:26:31 +080078 const struct dw_hdmi_mpll_config *mpll_cfg;
79 const struct dw_hdmi_curr_ctrl *cur_ctr;
Yakir Yang034705a2015-03-31 23:56:10 -040080 const struct dw_hdmi_phy_config *phy_config;
Andy Yanb21f4b62014-12-05 14:26:31 +080081};
82
Laurent Pinchart69497eb2017-01-17 10:29:00 +020083int dw_hdmi_probe(struct platform_device *pdev,
84 const struct dw_hdmi_plat_data *plat_data);
85void dw_hdmi_remove(struct platform_device *pdev);
Laurent Pinchartecaa98f2017-01-17 10:28:52 +020086void dw_hdmi_unbind(struct device *dev);
Laurent Pinchartc6081192017-01-17 10:28:57 +020087int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
Andy Yanb21f4b62014-12-05 14:26:31 +080088 const struct dw_hdmi_plat_data *plat_data);
Russell Kingb5814ff2015-03-27 12:50:58 +000089
90void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
Russell Kingb90120a2015-03-27 12:59:58 +000091void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
92void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
Russell Kingb5814ff2015-03-27 12:50:58 +000093
Andy Yanb21f4b62014-12-05 14:26:31 +080094#endif /* __IMX_HDMI_H__ */