blob: b6596633036cd3a66c29e0c4c28663980fa7c200 [file] [log] [blame]
Joel Stanley02440622016-04-17 15:50:56 +09301#include "skeleton.dtsi"
2
3/ {
4 model = "Aspeed BMC";
5 compatible = "aspeed,ast2500";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&vic>;
9
10 cpus {
11 #address-cells = <1>;
12 #size-cells = <0>;
13
14 cpu@0 {
15 compatible = "arm,arm1176jzf-s";
16 device_type = "cpu";
17 reg = <0>;
18 };
19 };
20
21 ahb {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 vic: interrupt-controller@1e6c0080 {
28 compatible = "aspeed,ast2400-vic";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 valid-sources = <0xfefff7ff 0x0807ffff>;
32 reg = <0x1e6c0080 0x80>;
33 };
34
Joel Stanley34ea5c92017-01-04 16:30:34 +110035 mac0: ethernet@1e660000 {
Benjamin Herrenschmidt78d28542017-04-12 13:27:02 +100036 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
Joel Stanley34ea5c92017-01-04 16:30:34 +110037 reg = <0x1e660000 0x180>;
38 interrupts = <2>;
Joel Stanley34ea5c92017-01-04 16:30:34 +110039 status = "disabled";
40 };
41
42 mac1: ethernet@1e680000 {
Benjamin Herrenschmidt78d28542017-04-12 13:27:02 +100043 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
Joel Stanley34ea5c92017-01-04 16:30:34 +110044 reg = <0x1e680000 0x180>;
45 interrupts = <3>;
Joel Stanley34ea5c92017-01-04 16:30:34 +110046 status = "disabled";
47 };
48
Joel Stanley02440622016-04-17 15:50:56 +093049 apb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 clk_clkin: clk_clkin@1e6e2070 {
56 #clock-cells = <0>;
57 compatible = "aspeed,g5-clkin-clock";
58 reg = <0x1e6e2070 0x04>;
59 };
60
Andrew Jefferyb590c8d2016-12-06 14:53:47 +110061 syscon: syscon@1e6e2000 {
62 compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
63 reg = <0x1e6e2000 0x1a8>;
64
65 pinctrl: pinctrl {
66 compatible = "aspeed,g5-pinctrl";
67 aspeed,external-nodes = <&gfx &lhc>;
68
69 pinctrl_acpi_default: acpi_default {
70 function = "ACPI";
71 groups = "ACPI";
72 };
73
74 pinctrl_adc0_default: adc0_default {
75 function = "ADC0";
76 groups = "ADC0";
77 };
78
79 pinctrl_adc1_default: adc1_default {
80 function = "ADC1";
81 groups = "ADC1";
82 };
83
84 pinctrl_adc10_default: adc10_default {
85 function = "ADC10";
86 groups = "ADC10";
87 };
88
89 pinctrl_adc11_default: adc11_default {
90 function = "ADC11";
91 groups = "ADC11";
92 };
93
94 pinctrl_adc12_default: adc12_default {
95 function = "ADC12";
96 groups = "ADC12";
97 };
98
99 pinctrl_adc13_default: adc13_default {
100 function = "ADC13";
101 groups = "ADC13";
102 };
103
104 pinctrl_adc14_default: adc14_default {
105 function = "ADC14";
106 groups = "ADC14";
107 };
108
109 pinctrl_adc15_default: adc15_default {
110 function = "ADC15";
111 groups = "ADC15";
112 };
113
114 pinctrl_adc2_default: adc2_default {
115 function = "ADC2";
116 groups = "ADC2";
117 };
118
119 pinctrl_adc3_default: adc3_default {
120 function = "ADC3";
121 groups = "ADC3";
122 };
123
124 pinctrl_adc4_default: adc4_default {
125 function = "ADC4";
126 groups = "ADC4";
127 };
128
129 pinctrl_adc5_default: adc5_default {
130 function = "ADC5";
131 groups = "ADC5";
132 };
133
134 pinctrl_adc6_default: adc6_default {
135 function = "ADC6";
136 groups = "ADC6";
137 };
138
139 pinctrl_adc7_default: adc7_default {
140 function = "ADC7";
141 groups = "ADC7";
142 };
143
144 pinctrl_adc8_default: adc8_default {
145 function = "ADC8";
146 groups = "ADC8";
147 };
148
149 pinctrl_adc9_default: adc9_default {
150 function = "ADC9";
151 groups = "ADC9";
152 };
153
154 pinctrl_bmcint_default: bmcint_default {
155 function = "BMCINT";
156 groups = "BMCINT";
157 };
158
159 pinctrl_ddcclk_default: ddcclk_default {
160 function = "DDCCLK";
161 groups = "DDCCLK";
162 };
163
164 pinctrl_ddcdat_default: ddcdat_default {
165 function = "DDCDAT";
166 groups = "DDCDAT";
167 };
168
169 pinctrl_espi_default: espi_default {
170 function = "ESPI";
171 groups = "ESPI";
172 };
173
174 pinctrl_fwspics1_default: fwspics1_default {
175 function = "FWSPICS1";
176 groups = "FWSPICS1";
177 };
178
179 pinctrl_fwspics2_default: fwspics2_default {
180 function = "FWSPICS2";
181 groups = "FWSPICS2";
182 };
183
184 pinctrl_gpid0_default: gpid0_default {
185 function = "GPID0";
186 groups = "GPID0";
187 };
188
189 pinctrl_gpid2_default: gpid2_default {
190 function = "GPID2";
191 groups = "GPID2";
192 };
193
194 pinctrl_gpid4_default: gpid4_default {
195 function = "GPID4";
196 groups = "GPID4";
197 };
198
199 pinctrl_gpid6_default: gpid6_default {
200 function = "GPID6";
201 groups = "GPID6";
202 };
203
204 pinctrl_gpie0_default: gpie0_default {
205 function = "GPIE0";
206 groups = "GPIE0";
207 };
208
209 pinctrl_gpie2_default: gpie2_default {
210 function = "GPIE2";
211 groups = "GPIE2";
212 };
213
214 pinctrl_gpie4_default: gpie4_default {
215 function = "GPIE4";
216 groups = "GPIE4";
217 };
218
219 pinctrl_gpie6_default: gpie6_default {
220 function = "GPIE6";
221 groups = "GPIE6";
222 };
223
224 pinctrl_i2c10_default: i2c10_default {
225 function = "I2C10";
226 groups = "I2C10";
227 };
228
229 pinctrl_i2c11_default: i2c11_default {
230 function = "I2C11";
231 groups = "I2C11";
232 };
233
234 pinctrl_i2c12_default: i2c12_default {
235 function = "I2C12";
236 groups = "I2C12";
237 };
238
239 pinctrl_i2c13_default: i2c13_default {
240 function = "I2C13";
241 groups = "I2C13";
242 };
243
244 pinctrl_i2c14_default: i2c14_default {
245 function = "I2C14";
246 groups = "I2C14";
247 };
248
249 pinctrl_i2c3_default: i2c3_default {
250 function = "I2C3";
251 groups = "I2C3";
252 };
253
254 pinctrl_i2c4_default: i2c4_default {
255 function = "I2C4";
256 groups = "I2C4";
257 };
258
259 pinctrl_i2c5_default: i2c5_default {
260 function = "I2C5";
261 groups = "I2C5";
262 };
263
264 pinctrl_i2c6_default: i2c6_default {
265 function = "I2C6";
266 groups = "I2C6";
267 };
268
269 pinctrl_i2c7_default: i2c7_default {
270 function = "I2C7";
271 groups = "I2C7";
272 };
273
274 pinctrl_i2c8_default: i2c8_default {
275 function = "I2C8";
276 groups = "I2C8";
277 };
278
279 pinctrl_i2c9_default: i2c9_default {
280 function = "I2C9";
281 groups = "I2C9";
282 };
283
284 pinctrl_lad0_default: lad0_default {
285 function = "LAD0";
286 groups = "LAD0";
287 };
288
289 pinctrl_lad1_default: lad1_default {
290 function = "LAD1";
291 groups = "LAD1";
292 };
293
294 pinctrl_lad2_default: lad2_default {
295 function = "LAD2";
296 groups = "LAD2";
297 };
298
299 pinctrl_lad3_default: lad3_default {
300 function = "LAD3";
301 groups = "LAD3";
302 };
303
304 pinctrl_lclk_default: lclk_default {
305 function = "LCLK";
306 groups = "LCLK";
307 };
308
309 pinctrl_lframe_default: lframe_default {
310 function = "LFRAME";
311 groups = "LFRAME";
312 };
313
314 pinctrl_lpchc_default: lpchc_default {
315 function = "LPCHC";
316 groups = "LPCHC";
317 };
318
319 pinctrl_lpcpd_default: lpcpd_default {
320 function = "LPCPD";
321 groups = "LPCPD";
322 };
323
324 pinctrl_lpcplus_default: lpcplus_default {
325 function = "LPCPLUS";
326 groups = "LPCPLUS";
327 };
328
329 pinctrl_lpcpme_default: lpcpme_default {
330 function = "LPCPME";
331 groups = "LPCPME";
332 };
333
334 pinctrl_lpcrst_default: lpcrst_default {
335 function = "LPCRST";
336 groups = "LPCRST";
337 };
338
339 pinctrl_lpcsmi_default: lpcsmi_default {
340 function = "LPCSMI";
341 groups = "LPCSMI";
342 };
343
344 pinctrl_lsirq_default: lsirq_default {
345 function = "LSIRQ";
346 groups = "LSIRQ";
347 };
348
349 pinctrl_mac1link_default: mac1link_default {
350 function = "MAC1LINK";
351 groups = "MAC1LINK";
352 };
353
354 pinctrl_mac2link_default: mac2link_default {
355 function = "MAC2LINK";
356 groups = "MAC2LINK";
357 };
358
359 pinctrl_mdio1_default: mdio1_default {
360 function = "MDIO1";
361 groups = "MDIO1";
362 };
363
364 pinctrl_mdio2_default: mdio2_default {
365 function = "MDIO2";
366 groups = "MDIO2";
367 };
368
369 pinctrl_ncts1_default: ncts1_default {
370 function = "NCTS1";
371 groups = "NCTS1";
372 };
373
374 pinctrl_ncts2_default: ncts2_default {
375 function = "NCTS2";
376 groups = "NCTS2";
377 };
378
379 pinctrl_ncts3_default: ncts3_default {
380 function = "NCTS3";
381 groups = "NCTS3";
382 };
383
384 pinctrl_ncts4_default: ncts4_default {
385 function = "NCTS4";
386 groups = "NCTS4";
387 };
388
389 pinctrl_ndcd1_default: ndcd1_default {
390 function = "NDCD1";
391 groups = "NDCD1";
392 };
393
394 pinctrl_ndcd2_default: ndcd2_default {
395 function = "NDCD2";
396 groups = "NDCD2";
397 };
398
399 pinctrl_ndcd3_default: ndcd3_default {
400 function = "NDCD3";
401 groups = "NDCD3";
402 };
403
404 pinctrl_ndcd4_default: ndcd4_default {
405 function = "NDCD4";
406 groups = "NDCD4";
407 };
408
409 pinctrl_ndsr1_default: ndsr1_default {
410 function = "NDSR1";
411 groups = "NDSR1";
412 };
413
414 pinctrl_ndsr2_default: ndsr2_default {
415 function = "NDSR2";
416 groups = "NDSR2";
417 };
418
419 pinctrl_ndsr3_default: ndsr3_default {
420 function = "NDSR3";
421 groups = "NDSR3";
422 };
423
424 pinctrl_ndsr4_default: ndsr4_default {
425 function = "NDSR4";
426 groups = "NDSR4";
427 };
428
429 pinctrl_ndtr1_default: ndtr1_default {
430 function = "NDTR1";
431 groups = "NDTR1";
432 };
433
434 pinctrl_ndtr2_default: ndtr2_default {
435 function = "NDTR2";
436 groups = "NDTR2";
437 };
438
439 pinctrl_ndtr3_default: ndtr3_default {
440 function = "NDTR3";
441 groups = "NDTR3";
442 };
443
444 pinctrl_ndtr4_default: ndtr4_default {
445 function = "NDTR4";
446 groups = "NDTR4";
447 };
448
449 pinctrl_nri1_default: nri1_default {
450 function = "NRI1";
451 groups = "NRI1";
452 };
453
454 pinctrl_nri2_default: nri2_default {
455 function = "NRI2";
456 groups = "NRI2";
457 };
458
459 pinctrl_nri3_default: nri3_default {
460 function = "NRI3";
461 groups = "NRI3";
462 };
463
464 pinctrl_nri4_default: nri4_default {
465 function = "NRI4";
466 groups = "NRI4";
467 };
468
469 pinctrl_nrts1_default: nrts1_default {
470 function = "NRTS1";
471 groups = "NRTS1";
472 };
473
474 pinctrl_nrts2_default: nrts2_default {
475 function = "NRTS2";
476 groups = "NRTS2";
477 };
478
479 pinctrl_nrts3_default: nrts3_default {
480 function = "NRTS3";
481 groups = "NRTS3";
482 };
483
484 pinctrl_nrts4_default: nrts4_default {
485 function = "NRTS4";
486 groups = "NRTS4";
487 };
488
489 pinctrl_oscclk_default: oscclk_default {
490 function = "OSCCLK";
491 groups = "OSCCLK";
492 };
493
494 pinctrl_pewake_default: pewake_default {
495 function = "PEWAKE";
496 groups = "PEWAKE";
497 };
498
499 pinctrl_pnor_default: pnor_default {
500 function = "PNOR";
501 groups = "PNOR";
502 };
503
504 pinctrl_pwm0_default: pwm0_default {
505 function = "PWM0";
506 groups = "PWM0";
507 };
508
509 pinctrl_pwm1_default: pwm1_default {
510 function = "PWM1";
511 groups = "PWM1";
512 };
513
514 pinctrl_pwm2_default: pwm2_default {
515 function = "PWM2";
516 groups = "PWM2";
517 };
518
519 pinctrl_pwm3_default: pwm3_default {
520 function = "PWM3";
521 groups = "PWM3";
522 };
523
524 pinctrl_pwm4_default: pwm4_default {
525 function = "PWM4";
526 groups = "PWM4";
527 };
528
529 pinctrl_pwm5_default: pwm5_default {
530 function = "PWM5";
531 groups = "PWM5";
532 };
533
534 pinctrl_pwm6_default: pwm6_default {
535 function = "PWM6";
536 groups = "PWM6";
537 };
538
539 pinctrl_pwm7_default: pwm7_default {
540 function = "PWM7";
541 groups = "PWM7";
542 };
543
544 pinctrl_rgmii1_default: rgmii1_default {
545 function = "RGMII1";
546 groups = "RGMII1";
547 };
548
549 pinctrl_rgmii2_default: rgmii2_default {
550 function = "RGMII2";
551 groups = "RGMII2";
552 };
553
554 pinctrl_rmii1_default: rmii1_default {
555 function = "RMII1";
556 groups = "RMII1";
557 };
558
559 pinctrl_rmii2_default: rmii2_default {
560 function = "RMII2";
561 groups = "RMII2";
562 };
563
564 pinctrl_rxd1_default: rxd1_default {
565 function = "RXD1";
566 groups = "RXD1";
567 };
568
569 pinctrl_rxd2_default: rxd2_default {
570 function = "RXD2";
571 groups = "RXD2";
572 };
573
574 pinctrl_rxd3_default: rxd3_default {
575 function = "RXD3";
576 groups = "RXD3";
577 };
578
579 pinctrl_rxd4_default: rxd4_default {
580 function = "RXD4";
581 groups = "RXD4";
582 };
583
584 pinctrl_salt1_default: salt1_default {
585 function = "SALT1";
586 groups = "SALT1";
587 };
588
589 pinctrl_salt10_default: salt10_default {
590 function = "SALT10";
591 groups = "SALT10";
592 };
593
594 pinctrl_salt11_default: salt11_default {
595 function = "SALT11";
596 groups = "SALT11";
597 };
598
599 pinctrl_salt12_default: salt12_default {
600 function = "SALT12";
601 groups = "SALT12";
602 };
603
604 pinctrl_salt13_default: salt13_default {
605 function = "SALT13";
606 groups = "SALT13";
607 };
608
609 pinctrl_salt14_default: salt14_default {
610 function = "SALT14";
611 groups = "SALT14";
612 };
613
614 pinctrl_salt2_default: salt2_default {
615 function = "SALT2";
616 groups = "SALT2";
617 };
618
619 pinctrl_salt3_default: salt3_default {
620 function = "SALT3";
621 groups = "SALT3";
622 };
623
624 pinctrl_salt4_default: salt4_default {
625 function = "SALT4";
626 groups = "SALT4";
627 };
628
629 pinctrl_salt5_default: salt5_default {
630 function = "SALT5";
631 groups = "SALT5";
632 };
633
634 pinctrl_salt6_default: salt6_default {
635 function = "SALT6";
636 groups = "SALT6";
637 };
638
639 pinctrl_salt7_default: salt7_default {
640 function = "SALT7";
641 groups = "SALT7";
642 };
643
644 pinctrl_salt8_default: salt8_default {
645 function = "SALT8";
646 groups = "SALT8";
647 };
648
649 pinctrl_salt9_default: salt9_default {
650 function = "SALT9";
651 groups = "SALT9";
652 };
653
654 pinctrl_scl1_default: scl1_default {
655 function = "SCL1";
656 groups = "SCL1";
657 };
658
659 pinctrl_scl2_default: scl2_default {
660 function = "SCL2";
661 groups = "SCL2";
662 };
663
664 pinctrl_sd1_default: sd1_default {
665 function = "SD1";
666 groups = "SD1";
667 };
668
669 pinctrl_sd2_default: sd2_default {
670 function = "SD2";
671 groups = "SD2";
672 };
673
674 pinctrl_sda1_default: sda1_default {
675 function = "SDA1";
676 groups = "SDA1";
677 };
678
679 pinctrl_sda2_default: sda2_default {
680 function = "SDA2";
681 groups = "SDA2";
682 };
683
684 pinctrl_sgps1_default: sgps1_default {
685 function = "SGPS1";
686 groups = "SGPS1";
687 };
688
689 pinctrl_sgps2_default: sgps2_default {
690 function = "SGPS2";
691 groups = "SGPS2";
692 };
693
694 pinctrl_sioonctrl_default: sioonctrl_default {
695 function = "SIOONCTRL";
696 groups = "SIOONCTRL";
697 };
698
699 pinctrl_siopbi_default: siopbi_default {
700 function = "SIOPBI";
701 groups = "SIOPBI";
702 };
703
704 pinctrl_siopbo_default: siopbo_default {
705 function = "SIOPBO";
706 groups = "SIOPBO";
707 };
708
709 pinctrl_siopwreq_default: siopwreq_default {
710 function = "SIOPWREQ";
711 groups = "SIOPWREQ";
712 };
713
714 pinctrl_siopwrgd_default: siopwrgd_default {
715 function = "SIOPWRGD";
716 groups = "SIOPWRGD";
717 };
718
719 pinctrl_sios3_default: sios3_default {
720 function = "SIOS3";
721 groups = "SIOS3";
722 };
723
724 pinctrl_sios5_default: sios5_default {
725 function = "SIOS5";
726 groups = "SIOS5";
727 };
728
729 pinctrl_siosci_default: siosci_default {
730 function = "SIOSCI";
731 groups = "SIOSCI";
732 };
733
734 pinctrl_spi1_default: spi1_default {
735 function = "SPI1";
736 groups = "SPI1";
737 };
738
739 pinctrl_spi1cs1_default: spi1cs1_default {
740 function = "SPI1CS1";
741 groups = "SPI1CS1";
742 };
743
744 pinctrl_spi1debug_default: spi1debug_default {
745 function = "SPI1DEBUG";
746 groups = "SPI1DEBUG";
747 };
748
749 pinctrl_spi1passthru_default: spi1passthru_default {
750 function = "SPI1PASSTHRU";
751 groups = "SPI1PASSTHRU";
752 };
753
754 pinctrl_spi2ck_default: spi2ck_default {
755 function = "SPI2CK";
756 groups = "SPI2CK";
757 };
758
759 pinctrl_spi2cs0_default: spi2cs0_default {
760 function = "SPI2CS0";
761 groups = "SPI2CS0";
762 };
763
764 pinctrl_spi2cs1_default: spi2cs1_default {
765 function = "SPI2CS1";
766 groups = "SPI2CS1";
767 };
768
769 pinctrl_spi2miso_default: spi2miso_default {
770 function = "SPI2MISO";
771 groups = "SPI2MISO";
772 };
773
774 pinctrl_spi2mosi_default: spi2mosi_default {
775 function = "SPI2MOSI";
776 groups = "SPI2MOSI";
777 };
778
779 pinctrl_timer3_default: timer3_default {
780 function = "TIMER3";
781 groups = "TIMER3";
782 };
783
784 pinctrl_timer4_default: timer4_default {
785 function = "TIMER4";
786 groups = "TIMER4";
787 };
788
789 pinctrl_timer5_default: timer5_default {
790 function = "TIMER5";
791 groups = "TIMER5";
792 };
793
794 pinctrl_timer6_default: timer6_default {
795 function = "TIMER6";
796 groups = "TIMER6";
797 };
798
799 pinctrl_timer7_default: timer7_default {
800 function = "TIMER7";
801 groups = "TIMER7";
802 };
803
804 pinctrl_timer8_default: timer8_default {
805 function = "TIMER8";
806 groups = "TIMER8";
807 };
808
809 pinctrl_txd1_default: txd1_default {
810 function = "TXD1";
811 groups = "TXD1";
812 };
813
814 pinctrl_txd2_default: txd2_default {
815 function = "TXD2";
816 groups = "TXD2";
817 };
818
819 pinctrl_txd3_default: txd3_default {
820 function = "TXD3";
821 groups = "TXD3";
822 };
823
824 pinctrl_txd4_default: txd4_default {
825 function = "TXD4";
826 groups = "TXD4";
827 };
828
829 pinctrl_uart6_default: uart6_default {
830 function = "UART6";
831 groups = "UART6";
832 };
833
834 pinctrl_usbcki_default: usbcki_default {
835 function = "USBCKI";
836 groups = "USBCKI";
837 };
838
839 pinctrl_vgabiosrom_default: vgabiosrom_default {
840 function = "VGABIOSROM";
841 groups = "VGABIOSROM";
842 };
843
844 pinctrl_vgahs_default: vgahs_default {
845 function = "VGAHS";
846 groups = "VGAHS";
847 };
848
849 pinctrl_vgavs_default: vgavs_default {
850 function = "VGAVS";
851 groups = "VGAVS";
852 };
853
854 pinctrl_vpi24_default: vpi24_default {
855 function = "VPI24";
856 groups = "VPI24";
857 };
858
859 pinctrl_vpo_default: vpo_default {
860 function = "VPO";
861 groups = "VPO";
862 };
863
864 pinctrl_wdtrst1_default: wdtrst1_default {
865 function = "WDTRST1";
866 groups = "WDTRST1";
867 };
868
869 pinctrl_wdtrst2_default: wdtrst2_default {
870 function = "WDTRST2";
871 groups = "WDTRST2";
872 };
873
874 };
875 };
876
Joel Stanley02440622016-04-17 15:50:56 +0930877 clk_hpll: clk_hpll@1e6e2024 {
878 #clock-cells = <0>;
879 compatible = "aspeed,g5-hpll-clock";
880 reg = <0x1e6e2024 0x4>;
881 clocks = <&clk_clkin>;
882 };
883
884 clk_ahb: clk_ahb@1e6e2070 {
885 #clock-cells = <0>;
886 compatible = "aspeed,g5-ahb-clock";
887 reg = <0x1e6e2070 0x4>;
888 clocks = <&clk_hpll>;
889 };
890
891 clk_apb: clk_apb@1e6e2008 {
892 #clock-cells = <0>;
893 compatible = "aspeed,g5-apb-clock";
894 reg = <0x1e6e2008 0x4>;
895 clocks = <&clk_hpll>;
896 };
897
898 clk_uart: clk_uart@1e6e2008 {
899 #clock-cells = <0>;
900 compatible = "aspeed,uart-clock";
901 reg = <0x1e6e202c 0x4>;
902 };
903
Andrew Jefferydaf04252016-12-06 14:53:45 +1100904 gfx: display@1e6e6000 {
905 compatible = "aspeed,ast2500-gfx", "syscon";
906 reg = <0x1e6e6000 0x1000>;
907 reg-io-width = <4>;
908 };
909
Joel Stanley02440622016-04-17 15:50:56 +0930910 sram@1e720000 {
911 compatible = "mmio-sram";
912 reg = <0x1e720000 0x9000>; // 36K
913 };
914
Andrew Jeffery2039f902016-12-06 14:53:48 +1100915 gpio: gpio@1e780000 {
916 #gpio-cells = <2>;
917 gpio-controller;
918 compatible = "aspeed,ast2500-gpio";
919 reg = <0x1e780000 0x1000>;
920 interrupts = <20>;
921 gpio-ranges = <&pinctrl 0 0 220>;
922 interrupt-controller;
923 };
924
Joel Stanley02440622016-04-17 15:50:56 +0930925 timer: timer@1e782000 {
926 compatible = "aspeed,ast2400-timer";
927 reg = <0x1e782000 0x90>;
928 // The moxart_timer driver registers only one
929 // interrupt and assumes it's for timer 1
930 //interrupts = <16 17 18 35 36 37 38 39>;
931 interrupts = <16>;
932 clocks = <&clk_apb>;
933 };
934
Andrew Jefferycec822f2016-12-06 14:53:46 +1100935
Joel Stanley02440622016-04-17 15:50:56 +0930936 wdt1: wdt@1e785000 {
937 compatible = "aspeed,wdt";
938 reg = <0x1e785000 0x1c>;
939 interrupts = <27>;
940 };
941
942 wdt2: wdt@1e785020 {
943 compatible = "aspeed,wdt";
944 reg = <0x1e785020 0x1c>;
945 interrupts = <27>;
946 status = "disabled";
947 };
948
949 wdt3: wdt@1e785040 {
950 compatible = "aspeed,wdt";
951 reg = <0x1e785074 0x1c>;
952 status = "disabled";
953 };
954
955 uart1: serial@1e783000 {
956 compatible = "ns16550a";
957 reg = <0x1e783000 0x1000>;
958 reg-shift = <2>;
959 interrupts = <9>;
960 clocks = <&clk_uart>;
961 no-loopback-test;
962 status = "disabled";
963 };
964
Andrew Jefferycec822f2016-12-06 14:53:46 +1100965 lpc: lpc@1e789000 {
966 compatible = "aspeed,ast2500-lpc", "simple-mfd";
967 reg = <0x1e789000 0x1000>;
968
969 #address-cells = <1>;
970 #size-cells = <1>;
971 ranges = <0 0x1e789000 0x1000>;
972
973 lpc_bmc: lpc-bmc@0 {
974 compatible = "aspeed,ast2500-lpc-bmc";
975 reg = <0x0 0x80>;
976 };
977
978 lpc_host: lpc-host@80 {
979 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
980 reg = <0x80 0x1e0>;
981
982 #address-cells = <1>;
983 #size-cells = <1>;
984 ranges = <0 0x80 0x1e0>;
985
986 reg-io-width = <4>;
987
988 lhc: lhc@20 {
989 compatible = "aspeed,ast2500-lhc";
990 reg = <0x20 0x24 0x48 0x8>;
991 };
992 };
993 };
994
Joel Stanley02440622016-04-17 15:50:56 +0930995 uart2: serial@1e78d000 {
996 compatible = "ns16550a";
997 reg = <0x1e78d000 0x1000>;
998 reg-shift = <2>;
999 interrupts = <32>;
1000 clocks = <&clk_uart>;
1001 no-loopback-test;
1002 status = "disabled";
1003 };
1004
1005 uart3: serial@1e78e000 {
1006 compatible = "ns16550a";
1007 reg = <0x1e78e000 0x1000>;
1008 reg-shift = <2>;
1009 interrupts = <33>;
1010 clocks = <&clk_uart>;
1011 no-loopback-test;
1012 status = "disabled";
1013 };
1014
1015 uart4: serial@1e78f000 {
1016 compatible = "ns16550a";
1017 reg = <0x1e78f000 0x1000>;
1018 reg-shift = <2>;
1019 interrupts = <34>;
1020 clocks = <&clk_uart>;
1021 no-loopback-test;
1022 status = "disabled";
1023 };
1024
1025 uart5: serial@1e784000 {
1026 compatible = "ns16550a";
1027 reg = <0x1e784000 0x1000>;
1028 reg-shift = <2>;
1029 interrupts = <10>;
1030 clocks = <&clk_uart>;
1031 current-speed = <38400>;
1032 no-loopback-test;
1033 status = "disabled";
1034 };
1035
1036 uart6: serial@1e787000 {
1037 compatible = "ns16550a";
1038 reg = <0x1e787000 0x1000>;
1039 reg-shift = <2>;
1040 interrupts = <10>;
1041 clocks = <&clk_uart>;
1042 no-loopback-test;
1043 status = "disabled";
1044 };
1045 };
1046 };
1047};