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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Francois Romieu07d3f512007-02-21 22:40:46 +01002 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
Alexey Dobriyana6b7a402011-06-06 10:43:46 +000025#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/dma-mapping.h>
Rafael J. Wysockie1759442010-03-14 14:33:51 +000027#include <linux/pm_runtime.h>
françois romieubca03d52011-01-03 15:07:31 +000028#include <linux/firmware.h>
Stanislaw Gruszkaba04c7c2011-02-22 02:00:11 +000029#include <linux/pci-aspm.h>
Paul Gortmaker70c71602011-05-22 16:47:17 -040030#include <linux/prefetch.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
Francois Romieu99f252b2007-04-02 22:59:59 +020032#include <asm/system.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <asm/io.h>
34#include <asm/irq.h>
35
Francois Romieu865c6522008-05-11 14:51:00 +020036#define RTL8169_VERSION "2.3LK-NAPI"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
françois romieubca03d52011-01-03 15:07:31 +000040#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
hayeswang01dc7fe2011-03-21 01:50:28 +000042#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
Hayes Wang70090422011-07-06 15:58:06 +080044#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
Hayes Wangc2218922011-09-06 16:55:18 +080045#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
Hayes Wang5a5e4442011-02-22 17:26:21 +080047#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
françois romieubca03d52011-01-03 15:07:31 +000048
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#ifdef RTL8169_DEBUG
50#define assert(expr) \
Francois Romieu5b0384f2006-08-16 16:00:01 +020051 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
Harvey Harrisonb39d66a2008-08-20 16:52:04 -070053 #expr,__FILE__,__func__,__LINE__); \
Francois Romieu5b0384f2006-08-16 16:00:01 +020054 }
Joe Perches06fa7352007-10-18 21:15:00 +020055#define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#else
58#define assert(expr) do {} while (0)
59#define dprintk(fmt, args...) do {} while (0)
60#endif /* RTL8169_DEBUG */
61
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +020062#define R8169_MSG_DEFAULT \
Francois Romieuf0e837d2005-09-30 16:54:02 -070063 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +020064
Linus Torvalds1da177e2005-04-16 15:20:36 -070065#define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
Linus Torvalds1da177e2005-04-16 15:20:36 -070068/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
Arjan van de Venf71e1302006-03-03 21:33:57 -050070static const int multicast_filter_limit = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Francois Romieu9c14cea2008-07-05 00:21:15 +020072#define MAX_READ_REQUEST_SHIFT 12
Linus Torvalds1da177e2005-04-16 15:20:36 -070073#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070074#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
françois romieuea8dbdd2009-03-15 01:10:50 +000088#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
Francois Romieue1564ec2008-10-16 22:46:13 +020090#define RTL_EEPROM_SIG_ADDR 0x0000
91
Linus Torvalds1da177e2005-04-16 15:20:36 -070092/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
Junchang Wang06f555f2010-05-30 02:26:07 +000098#define RTL_R32(reg) readl (ioaddr + (reg))
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100enum mac_version {
Francois Romieu85bffe62011-04-27 08:22:39 +0200101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
Hayes Wang70090422011-07-06 15:58:06 +0800134 RTL_GIGA_MAC_VER_34,
Hayes Wangc2218922011-09-06 16:55:18 +0800135 RTL_GIGA_MAC_VER_35,
136 RTL_GIGA_MAC_VER_36,
Francois Romieu85bffe62011-04-27 08:22:39 +0200137 RTL_GIGA_MAC_NONE = 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138};
139
Francois Romieu2b7b4312011-04-18 22:53:24 -0700140enum rtl_tx_desc_version {
141 RTL_TD_0 = 0,
142 RTL_TD_1 = 1,
143};
144
Francois Romieud58d46b2011-05-03 16:38:29 +0200145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151#define _R(NAME,TD,FW,SZ,B) { \
152 .name = NAME, \
153 .txd_version = TD, \
154 .fw_name = FW, \
155 .jumbo_max = SZ, \
156 .jumbo_tx_csum = B \
157}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158
Jesper Juhl3c6bee12006-01-09 20:54:01 -0800159static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 const char *name;
Francois Romieu2b7b4312011-04-18 22:53:24 -0700161 enum rtl_tx_desc_version txd_version;
Francois Romieu85bffe62011-04-27 08:22:39 +0200162 const char *fw_name;
Francois Romieud58d46b2011-05-03 16:38:29 +0200163 u16 jumbo_max;
164 bool jumbo_tx_csum;
Francois Romieu85bffe62011-04-27 08:22:39 +0200165} rtl_chip_infos[] = {
166 /* PCI devices. */
167 [RTL_GIGA_MAC_VER_01] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200168 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200169 [RTL_GIGA_MAC_VER_02] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200170 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200171 [RTL_GIGA_MAC_VER_03] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200172 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200173 [RTL_GIGA_MAC_VER_04] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200174 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200175 [RTL_GIGA_MAC_VER_05] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200177 [RTL_GIGA_MAC_VER_06] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200179 /* PCI-E devices. */
180 [RTL_GIGA_MAC_VER_07] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200182 [RTL_GIGA_MAC_VER_08] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200184 [RTL_GIGA_MAC_VER_09] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200186 [RTL_GIGA_MAC_VER_10] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200187 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200188 [RTL_GIGA_MAC_VER_11] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200190 [RTL_GIGA_MAC_VER_12] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200192 [RTL_GIGA_MAC_VER_13] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200194 [RTL_GIGA_MAC_VER_14] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200196 [RTL_GIGA_MAC_VER_15] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200198 [RTL_GIGA_MAC_VER_16] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200200 [RTL_GIGA_MAC_VER_17] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200201 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200202 [RTL_GIGA_MAC_VER_18] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200203 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200204 [RTL_GIGA_MAC_VER_19] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200206 [RTL_GIGA_MAC_VER_20] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200208 [RTL_GIGA_MAC_VER_21] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200210 [RTL_GIGA_MAC_VER_22] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200212 [RTL_GIGA_MAC_VER_23] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200214 [RTL_GIGA_MAC_VER_24] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200216 [RTL_GIGA_MAC_VER_25] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200217 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
218 JUMBO_9K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200219 [RTL_GIGA_MAC_VER_26] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
221 JUMBO_9K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200222 [RTL_GIGA_MAC_VER_27] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200224 [RTL_GIGA_MAC_VER_28] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200226 [RTL_GIGA_MAC_VER_29] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
228 JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200229 [RTL_GIGA_MAC_VER_30] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
Francois Romieu85bffe62011-04-27 08:22:39 +0200232 [RTL_GIGA_MAC_VER_31] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200234 [RTL_GIGA_MAC_VER_32] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
236 JUMBO_9K, false),
Francois Romieu85bffe62011-04-27 08:22:39 +0200237 [RTL_GIGA_MAC_VER_33] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
239 JUMBO_9K, false),
Hayes Wang70090422011-07-06 15:58:06 +0800240 [RTL_GIGA_MAC_VER_34] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
242 JUMBO_9K, false),
Hayes Wangc2218922011-09-06 16:55:18 +0800243 [RTL_GIGA_MAC_VER_35] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
245 JUMBO_9K, false),
Hayes Wangc2218922011-09-06 16:55:18 +0800246 [RTL_GIGA_MAC_VER_36] =
Francois Romieud58d46b2011-05-03 16:38:29 +0200247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
248 JUMBO_9K, false),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249};
250#undef _R
251
Francois Romieubcf0bf92006-07-26 23:14:13 +0200252enum cfg_version {
253 RTL_CFG_0 = 0x00,
254 RTL_CFG_1,
255 RTL_CFG_2
256};
257
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000258static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
Francois Romieubcf0bf92006-07-26 23:14:13 +0200259 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
Francois Romieud2eed8c2006-08-31 22:01:07 +0200260 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
Francois Romieud81bf552006-09-20 21:31:20 +0200261 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
Francois Romieu07ce4062007-02-23 23:36:39 +0100262 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
Francois Romieubcf0bf92006-07-26 23:14:13 +0200263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
264 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
Lennart Sorensen93a3aa22011-07-28 13:18:11 +0000265 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
Francois Romieubc1660b2007-10-12 23:58:09 +0200266 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
Francois Romieubcf0bf92006-07-26 23:14:13 +0200267 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
268 { PCI_VENDOR_ID_LINKSYS, 0x1032,
269 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
Ciaran McCreesh11d2e282007-11-01 22:48:15 +0100270 { 0x0001, 0x8168,
271 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 {0,},
273};
274
275MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
276
Eric Dumazet6f0333b2010-10-11 11:17:47 +0000277static int rx_buf_sz = 16383;
David S. Miller4300e8c2010-03-26 10:23:30 -0700278static int use_dac;
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200279static struct {
280 u32 msg_enable;
281} debug = { -1 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282
Francois Romieu07d3f512007-02-21 22:40:46 +0100283enum rtl_registers {
284 MAC0 = 0, /* Ethernet hardware address. */
Francois Romieu773d2022007-01-31 23:47:43 +0100285 MAC4 = 4,
Francois Romieu07d3f512007-02-21 22:40:46 +0100286 MAR0 = 8, /* Multicast filter. */
287 CounterAddrLow = 0x10,
288 CounterAddrHigh = 0x14,
289 TxDescStartAddrLow = 0x20,
290 TxDescStartAddrHigh = 0x24,
291 TxHDescStartAddrLow = 0x28,
292 TxHDescStartAddrHigh = 0x2c,
293 FLASH = 0x30,
294 ERSR = 0x36,
295 ChipCmd = 0x37,
296 TxPoll = 0x38,
297 IntrMask = 0x3c,
298 IntrStatus = 0x3e,
Francois Romieu2b7b4312011-04-18 22:53:24 -0700299
Hayes Wang4f6b00e52011-07-06 15:58:02 +0800300 TxConfig = 0x40,
301#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
302#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
303
304 RxConfig = 0x44,
305#define RX128_INT_EN (1 << 15) /* 8111c and later */
306#define RX_MULTI_EN (1 << 14) /* 8111c only */
307#define RXCFG_FIFO_SHIFT 13
308 /* No threshold before first PCI xfer */
309#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
310#define RXCFG_DMA_SHIFT 8
311 /* Unlimited maximum PCI burst. */
312#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
Francois Romieu2b7b4312011-04-18 22:53:24 -0700313
Francois Romieu07d3f512007-02-21 22:40:46 +0100314 RxMissed = 0x4c,
315 Cfg9346 = 0x50,
316 Config0 = 0x51,
317 Config1 = 0x52,
318 Config2 = 0x53,
319 Config3 = 0x54,
320 Config4 = 0x55,
321 Config5 = 0x56,
322 MultiIntr = 0x5c,
323 PHYAR = 0x60,
Francois Romieu07d3f512007-02-21 22:40:46 +0100324 PHYstatus = 0x6c,
325 RxMaxSize = 0xda,
326 CPlusCmd = 0xe0,
327 IntrMitigate = 0xe2,
328 RxDescAddrLow = 0xe4,
329 RxDescAddrHigh = 0xe8,
françois romieuf0298f82011-01-03 15:07:42 +0000330 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
331
332#define NoEarlyTx 0x3f /* Max value : no early transmit. */
333
334 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
335
336#define TxPacketMax (8064 >> 7)
Hayes Wang3090bd92011-09-06 16:55:15 +0800337#define EarlySize 0x27
françois romieuf0298f82011-01-03 15:07:42 +0000338
Francois Romieu07d3f512007-02-21 22:40:46 +0100339 FuncEvent = 0xf0,
340 FuncEventMask = 0xf4,
341 FuncPresetState = 0xf8,
342 FuncForceEvent = 0xfc,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343};
344
Francois Romieuf162a5d2008-06-01 22:37:49 +0200345enum rtl8110_registers {
346 TBICSR = 0x64,
347 TBI_ANAR = 0x68,
348 TBI_LPAR = 0x6a,
349};
350
351enum rtl8168_8101_registers {
352 CSIDR = 0x64,
353 CSIAR = 0x68,
354#define CSIAR_FLAG 0x80000000
355#define CSIAR_WRITE_CMD 0x80000000
356#define CSIAR_BYTE_ENABLE 0x0f
357#define CSIAR_BYTE_ENABLE_SHIFT 12
358#define CSIAR_ADDR_MASK 0x0fff
françois romieu065c27c2011-01-03 15:08:12 +0000359 PMCH = 0x6f,
Francois Romieuf162a5d2008-06-01 22:37:49 +0200360 EPHYAR = 0x80,
361#define EPHYAR_FLAG 0x80000000
362#define EPHYAR_WRITE_CMD 0x80000000
363#define EPHYAR_REG_MASK 0x1f
364#define EPHYAR_REG_SHIFT 16
365#define EPHYAR_DATA_MASK 0xffff
Hayes Wang5a5e4442011-02-22 17:26:21 +0800366 DLLPR = 0xd0,
Hayes Wang4f6b00e52011-07-06 15:58:02 +0800367#define PFM_EN (1 << 6)
Francois Romieuf162a5d2008-06-01 22:37:49 +0200368 DBG_REG = 0xd1,
369#define FIX_NAK_1 (1 << 4)
370#define FIX_NAK_2 (1 << 3)
Hayes Wang5a5e4442011-02-22 17:26:21 +0800371 TWSI = 0xd2,
372 MCU = 0xd3,
Hayes Wang4f6b00e52011-07-06 15:58:02 +0800373#define NOW_IS_OOB (1 << 7)
Hayes Wang5a5e4442011-02-22 17:26:21 +0800374#define EN_NDP (1 << 3)
375#define EN_OOB_RESET (1 << 2)
françois romieudaf9df62009-10-07 12:44:20 +0000376 EFUSEAR = 0xdc,
377#define EFUSEAR_FLAG 0x80000000
378#define EFUSEAR_WRITE_CMD 0x80000000
379#define EFUSEAR_READ_CMD 0x00000000
380#define EFUSEAR_REG_MASK 0x03ff
381#define EFUSEAR_REG_SHIFT 8
382#define EFUSEAR_DATA_MASK 0xff
Francois Romieuf162a5d2008-06-01 22:37:49 +0200383};
384
françois romieuc0e45c12011-01-03 15:08:04 +0000385enum rtl8168_registers {
Hayes Wang4f6b00e52011-07-06 15:58:02 +0800386 LED_FREQ = 0x1a,
387 EEE_LED = 0x1b,
françois romieub646d902011-01-03 15:08:21 +0000388 ERIDR = 0x70,
389 ERIAR = 0x74,
390#define ERIAR_FLAG 0x80000000
391#define ERIAR_WRITE_CMD 0x80000000
392#define ERIAR_READ_CMD 0x00000000
393#define ERIAR_ADDR_BYTE_ALIGN 4
françois romieub646d902011-01-03 15:08:21 +0000394#define ERIAR_TYPE_SHIFT 16
Hayes Wang4f6b00e52011-07-06 15:58:02 +0800395#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
396#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
397#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
398#define ERIAR_MASK_SHIFT 12
399#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
400#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
401#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
françois romieuc0e45c12011-01-03 15:08:04 +0000402 EPHY_RXER_NUM = 0x7c,
403 OCPDR = 0xb0, /* OCP GPHY access */
404#define OCPDR_WRITE_CMD 0x80000000
405#define OCPDR_READ_CMD 0x00000000
406#define OCPDR_REG_MASK 0x7f
407#define OCPDR_GPHY_REG_SHIFT 16
408#define OCPDR_DATA_MASK 0xffff
409 OCPAR = 0xb4,
410#define OCPAR_FLAG 0x80000000
411#define OCPAR_GPHY_WRITE_CMD 0x8000f060
412#define OCPAR_GPHY_READ_CMD 0x0000f060
hayeswang01dc7fe2011-03-21 01:50:28 +0000413 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
414 MISC = 0xf0, /* 8168e only. */
Francois Romieucecb5fd2011-04-01 10:21:07 +0200415#define TXPLA_RST (1 << 29)
Hayes Wang4f6b00e52011-07-06 15:58:02 +0800416#define PWM_EN (1 << 22)
françois romieuc0e45c12011-01-03 15:08:04 +0000417};
418
Francois Romieu07d3f512007-02-21 22:40:46 +0100419enum rtl_register_content {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 /* InterruptStatusBits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100421 SYSErr = 0x8000,
422 PCSTimeout = 0x4000,
423 SWInt = 0x0100,
424 TxDescUnavail = 0x0080,
425 RxFIFOOver = 0x0040,
426 LinkChg = 0x0020,
427 RxOverflow = 0x0010,
428 TxErr = 0x0008,
429 TxOK = 0x0004,
430 RxErr = 0x0002,
431 RxOK = 0x0001,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432
433 /* RxStatusDesc */
David S. Miller8decf862011-09-22 03:23:13 -0400434 RxBOVF = (1 << 24),
Francois Romieu9dccf612006-05-14 12:31:17 +0200435 RxFOVF = (1 << 23),
436 RxRWT = (1 << 22),
437 RxRES = (1 << 21),
438 RxRUNT = (1 << 20),
439 RxCRC = (1 << 19),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440
441 /* ChipCmdBits */
Hayes Wang4f6b00e52011-07-06 15:58:02 +0800442 StopReq = 0x80,
Francois Romieu07d3f512007-02-21 22:40:46 +0100443 CmdReset = 0x10,
444 CmdRxEnb = 0x08,
445 CmdTxEnb = 0x04,
446 RxBufEmpty = 0x01,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
Francois Romieu275391a2007-02-23 23:50:28 +0100448 /* TXPoll register p.5 */
449 HPQ = 0x80, /* Poll cmd on the high prio queue */
450 NPQ = 0x40, /* Poll cmd on the low prio queue */
451 FSWInt = 0x01, /* Forced software interrupt */
452
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453 /* Cfg9346Bits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100454 Cfg9346_Lock = 0x00,
455 Cfg9346_Unlock = 0xc0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
457 /* rx_mode_bits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100458 AcceptErr = 0x20,
459 AcceptRunt = 0x10,
460 AcceptBroadcast = 0x08,
461 AcceptMulticast = 0x04,
462 AcceptMyPhys = 0x02,
463 AcceptAllPhys = 0x01,
Francois Romieu1687b562011-07-19 17:21:29 +0200464#define RX_CONFIG_ACCEPT_MASK 0x3f
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 /* TxConfigBits */
467 TxInterFrameGapShift = 24,
468 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
469
Francois Romieu5d06a992006-02-23 00:47:58 +0100470 /* Config1 register p.24 */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200471 LEDS1 = (1 << 7),
472 LEDS0 = (1 << 6),
Francois Romieuf162a5d2008-06-01 22:37:49 +0200473 Speed_down = (1 << 4),
474 MEMMAP = (1 << 3),
475 IOMAP = (1 << 2),
476 VPD = (1 << 1),
Francois Romieu5d06a992006-02-23 00:47:58 +0100477 PMEnable = (1 << 0), /* Power Management Enable */
478
Francois Romieu6dccd162007-02-13 23:38:05 +0100479 /* Config2 register p. 25 */
françois romieu2ca6cf02011-12-15 08:37:43 +0000480 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
Francois Romieu6dccd162007-02-13 23:38:05 +0100481 PCI_Clock_66MHz = 0x01,
482 PCI_Clock_33MHz = 0x00,
483
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100484 /* Config3 register p.25 */
485 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
486 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
Francois Romieud58d46b2011-05-03 16:38:29 +0200487 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200488 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100489
Francois Romieud58d46b2011-05-03 16:38:29 +0200490 /* Config4 register */
491 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
492
Francois Romieu5d06a992006-02-23 00:47:58 +0100493 /* Config5 register p.27 */
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100494 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
495 MWF = (1 << 5), /* Accept Multicast wakeup frame */
496 UWF = (1 << 4), /* Accept Unicast wakeup frame */
Francois Romieucecb5fd2011-04-01 10:21:07 +0200497 Spi_en = (1 << 3),
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100498 LanWake = (1 << 1), /* LanWake enable/disable */
Francois Romieu5d06a992006-02-23 00:47:58 +0100499 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
500
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501 /* TBICSR p.28 */
502 TBIReset = 0x80000000,
503 TBILoopback = 0x40000000,
504 TBINwEnable = 0x20000000,
505 TBINwRestart = 0x10000000,
506 TBILinkOk = 0x02000000,
507 TBINwComplete = 0x01000000,
508
509 /* CPlusCmd p.31 */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200510 EnableBist = (1 << 15), // 8168 8101
511 Mac_dbgo_oe = (1 << 14), // 8168 8101
512 Normal_mode = (1 << 13), // unused
513 Force_half_dup = (1 << 12), // 8168 8101
514 Force_rxflow_en = (1 << 11), // 8168 8101
515 Force_txflow_en = (1 << 10), // 8168 8101
516 Cxpl_dbg_sel = (1 << 9), // 8168 8101
517 ASF = (1 << 8), // 8168 8101
518 PktCntrDisable = (1 << 7), // 8168 8101
519 Mac_dbgo_sel = 0x001c, // 8168
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520 RxVlan = (1 << 6),
521 RxChkSum = (1 << 5),
522 PCIDAC = (1 << 4),
523 PCIMulRW = (1 << 3),
Francois Romieu0e485152007-02-20 00:00:26 +0100524 INTT_0 = 0x0000, // 8168
525 INTT_1 = 0x0001, // 8168
526 INTT_2 = 0x0002, // 8168
527 INTT_3 = 0x0003, // 8168
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528
529 /* rtl8169_PHYstatus */
Francois Romieu07d3f512007-02-21 22:40:46 +0100530 TBI_Enable = 0x80,
531 TxFlowCtrl = 0x40,
532 RxFlowCtrl = 0x20,
533 _1000bpsF = 0x10,
534 _100bps = 0x08,
535 _10bps = 0x04,
536 LinkStatus = 0x02,
537 FullDup = 0x01,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539 /* _TBICSRBit */
Francois Romieu07d3f512007-02-21 22:40:46 +0100540 TBILinkOK = 0x02000000,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +0200541
542 /* DumpCounterCommand */
Francois Romieu07d3f512007-02-21 22:40:46 +0100543 CounterDump = 0x8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544};
545
Francois Romieu2b7b4312011-04-18 22:53:24 -0700546enum rtl_desc_bit {
547 /* First doubleword. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
549 RingEnd = (1 << 30), /* End of descriptor ring */
550 FirstFrag = (1 << 29), /* First segment of a packet */
551 LastFrag = (1 << 28), /* Final segment of a packet */
Francois Romieu2b7b4312011-04-18 22:53:24 -0700552};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553
Francois Romieu2b7b4312011-04-18 22:53:24 -0700554/* Generic case. */
555enum rtl_tx_desc_bit {
556 /* First doubleword. */
557 TD_LSO = (1 << 27), /* Large Send Offload */
558#define TD_MSS_MAX 0x07ffu /* MSS value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559
Francois Romieu2b7b4312011-04-18 22:53:24 -0700560 /* Second doubleword. */
561 TxVlanTag = (1 << 17), /* Add VLAN tag */
562};
563
564/* 8169, 8168b and 810x except 8102e. */
565enum rtl_tx_desc_bit_0 {
566 /* First doubleword. */
567#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
568 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
569 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
570 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
571};
572
573/* 8102e, 8168c and beyond. */
574enum rtl_tx_desc_bit_1 {
575 /* Second doubleword. */
576#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
577 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
578 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
579 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
580};
581
582static const struct rtl_tx_desc_info {
583 struct {
584 u32 udp;
585 u32 tcp;
586 } checksum;
587 u16 mss_shift;
588 u16 opts_offset;
589} tx_desc_info [] = {
590 [RTL_TD_0] = {
591 .checksum = {
592 .udp = TD0_IP_CS | TD0_UDP_CS,
593 .tcp = TD0_IP_CS | TD0_TCP_CS
594 },
595 .mss_shift = TD0_MSS_SHIFT,
596 .opts_offset = 0
597 },
598 [RTL_TD_1] = {
599 .checksum = {
600 .udp = TD1_IP_CS | TD1_UDP_CS,
601 .tcp = TD1_IP_CS | TD1_TCP_CS
602 },
603 .mss_shift = TD1_MSS_SHIFT,
604 .opts_offset = 1
605 }
606};
607
608enum rtl_rx_desc_bit {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609 /* Rx private */
610 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
611 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
612
613#define RxProtoUDP (PID1)
614#define RxProtoTCP (PID0)
615#define RxProtoIP (PID1 | PID0)
616#define RxProtoMask RxProtoIP
617
618 IPFail = (1 << 16), /* IP checksum failed */
619 UDPFail = (1 << 15), /* UDP/IP checksum failed */
620 TCPFail = (1 << 14), /* TCP/IP checksum failed */
621 RxVlanTag = (1 << 16), /* VLAN tag available */
622};
623
624#define RsvdMask 0x3fffc000
625
626struct TxDesc {
Rolf Eike Beer6cccd6e2007-05-21 22:11:04 +0200627 __le32 opts1;
628 __le32 opts2;
629 __le64 addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630};
631
632struct RxDesc {
Rolf Eike Beer6cccd6e2007-05-21 22:11:04 +0200633 __le32 opts1;
634 __le32 opts2;
635 __le64 addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636};
637
638struct ring_info {
639 struct sk_buff *skb;
640 u32 len;
641 u8 __pad[sizeof(void *) - sizeof(u32)];
642};
643
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200644enum features {
Francois Romieuccdffb92008-07-26 14:26:06 +0200645 RTL_FEATURE_WOL = (1 << 0),
646 RTL_FEATURE_MSI = (1 << 1),
647 RTL_FEATURE_GMII = (1 << 2),
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200648};
649
Ivan Vecera355423d2009-02-06 21:49:57 -0800650struct rtl8169_counters {
651 __le64 tx_packets;
652 __le64 rx_packets;
653 __le64 tx_errors;
654 __le32 rx_errors;
655 __le16 rx_missed;
656 __le16 align_errors;
657 __le32 tx_one_collision;
658 __le32 tx_multi_collision;
659 __le64 rx_unicast;
660 __le64 rx_broadcast;
661 __le32 rx_multicast;
662 __le16 tx_aborted;
663 __le16 tx_underun;
664};
665
Francois Romieuda78dbf2012-01-26 14:18:23 +0100666enum rtl_flag {
Francois Romieu6c4a70c2012-01-31 10:56:44 +0100667 RTL_FLAG_TASK_ENABLED,
Francois Romieuda78dbf2012-01-26 14:18:23 +0100668 RTL_FLAG_TASK_SLOW_PENDING,
669 RTL_FLAG_TASK_RESET_PENDING,
670 RTL_FLAG_TASK_PHY_PENDING,
671 RTL_FLAG_MAX
672};
673
Junchang Wang8027aa22012-03-04 23:30:32 +0100674struct rtl8169_stats {
675 u64 packets;
676 u64 bytes;
677 struct u64_stats_sync syncp;
678};
679
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680struct rtl8169_private {
681 void __iomem *mmio_addr; /* memory map physical address */
Francois Romieucecb5fd2011-04-01 10:21:07 +0200682 struct pci_dev *pci_dev;
David Howellsc4028952006-11-22 14:57:56 +0000683 struct net_device *dev;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700684 struct napi_struct napi;
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200685 u32 msg_enable;
Francois Romieu2b7b4312011-04-18 22:53:24 -0700686 u16 txd_version;
687 u16 mac_version;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
689 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
690 u32 dirty_rx;
691 u32 dirty_tx;
Junchang Wang8027aa22012-03-04 23:30:32 +0100692 struct rtl8169_stats rx_stats;
693 struct rtl8169_stats tx_stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
695 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
696 dma_addr_t TxPhyAddr;
697 dma_addr_t RxPhyAddr;
Eric Dumazet6f0333b2010-10-11 11:17:47 +0000698 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700 struct timer_list timer;
701 u16 cp_cmd;
Francois Romieuda78dbf2012-01-26 14:18:23 +0100702
703 u16 event_slow;
françois romieuc0e45c12011-01-03 15:08:04 +0000704
705 struct mdio_ops {
706 void (*write)(void __iomem *, int, int);
707 int (*read)(void __iomem *, int);
708 } mdio_ops;
709
françois romieu065c27c2011-01-03 15:08:12 +0000710 struct pll_power_ops {
711 void (*down)(struct rtl8169_private *);
712 void (*up)(struct rtl8169_private *);
713 } pll_power_ops;
714
Francois Romieud58d46b2011-05-03 16:38:29 +0200715 struct jumbo_ops {
716 void (*enable)(struct rtl8169_private *);
717 void (*disable)(struct rtl8169_private *);
718 } jumbo_ops;
719
Oliver Neukum54405cd2011-01-06 21:55:13 +0100720 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
Francois Romieuccdffb92008-07-26 14:26:06 +0200721 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
françois romieu4da19632011-01-03 15:07:55 +0000722 void (*phy_reset_enable)(struct rtl8169_private *tp);
Francois Romieu07ce4062007-02-23 23:36:39 +0100723 void (*hw_start)(struct net_device *);
françois romieu4da19632011-01-03 15:07:55 +0000724 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725 unsigned int (*link_ok)(void __iomem *);
Francois Romieu8b4ab282008-11-19 22:05:25 -0800726 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
Francois Romieu4422bcd2012-01-26 11:23:32 +0100727
728 struct {
Francois Romieuda78dbf2012-01-26 14:18:23 +0100729 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
730 struct mutex mutex;
Francois Romieu4422bcd2012-01-26 11:23:32 +0100731 struct work_struct work;
732 } wk;
733
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200734 unsigned features;
Francois Romieuccdffb92008-07-26 14:26:06 +0200735
736 struct mii_if_info mii;
Ivan Vecera355423d2009-02-06 21:49:57 -0800737 struct rtl8169_counters counters;
Rafael J. Wysockie1759442010-03-14 14:33:51 +0000738 u32 saved_wolopts;
David S. Miller8decf862011-09-22 03:23:13 -0400739 u32 opts1_mask;
françois romieuf1e02ed2011-01-13 13:07:53 +0000740
Francois Romieub6ffd972011-06-17 17:00:05 +0200741 struct rtl_fw {
742 const struct firmware *fw;
Francois Romieu1c361ef2011-06-17 17:16:24 +0200743
744#define RTL_VER_SIZE 32
745
746 char version[RTL_VER_SIZE];
747
748 struct rtl_fw_phy_action {
749 __le32 *code;
750 size_t size;
751 } phy_action;
Francois Romieub6ffd972011-06-17 17:00:05 +0200752 } *rtl_fw;
Phil Carmody497888c2011-07-14 15:07:13 +0300753#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754};
755
Ralf Baechle979b6c12005-06-13 14:30:40 -0700756MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758module_param(use_dac, int, 0);
David S. Miller4300e8c2010-03-26 10:23:30 -0700759MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200760module_param_named(debug, debug.msg_enable, int, 0);
761MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762MODULE_LICENSE("GPL");
763MODULE_VERSION(RTL8169_VERSION);
françois romieubca03d52011-01-03 15:07:31 +0000764MODULE_FIRMWARE(FIRMWARE_8168D_1);
765MODULE_FIRMWARE(FIRMWARE_8168D_2);
hayeswang01dc7fe2011-03-21 01:50:28 +0000766MODULE_FIRMWARE(FIRMWARE_8168E_1);
767MODULE_FIRMWARE(FIRMWARE_8168E_2);
David S. Miller8decf862011-09-22 03:23:13 -0400768MODULE_FIRMWARE(FIRMWARE_8168E_3);
Hayes Wang5a5e4442011-02-22 17:26:21 +0800769MODULE_FIRMWARE(FIRMWARE_8105E_1);
Hayes Wangc2218922011-09-06 16:55:18 +0800770MODULE_FIRMWARE(FIRMWARE_8168F_1);
771MODULE_FIRMWARE(FIRMWARE_8168F_2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772
Francois Romieuda78dbf2012-01-26 14:18:23 +0100773static void rtl_lock_work(struct rtl8169_private *tp)
774{
775 mutex_lock(&tp->wk.mutex);
776}
777
778static void rtl_unlock_work(struct rtl8169_private *tp)
779{
780 mutex_unlock(&tp->wk.mutex);
781}
782
Francois Romieud58d46b2011-05-03 16:38:29 +0200783static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
784{
785 int cap = pci_pcie_cap(pdev);
786
787 if (cap) {
788 u16 ctl;
789
790 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
791 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
792 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
793 }
794}
795
françois romieub646d902011-01-03 15:08:21 +0000796static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
797{
798 void __iomem *ioaddr = tp->mmio_addr;
799 int i;
800
801 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
802 for (i = 0; i < 20; i++) {
803 udelay(100);
804 if (RTL_R32(OCPAR) & OCPAR_FLAG)
805 break;
806 }
807 return RTL_R32(OCPDR);
808}
809
810static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
811{
812 void __iomem *ioaddr = tp->mmio_addr;
813 int i;
814
815 RTL_W32(OCPDR, data);
816 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
817 for (i = 0; i < 20; i++) {
818 udelay(100);
819 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
820 break;
821 }
822}
823
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800824static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
françois romieub646d902011-01-03 15:08:21 +0000825{
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800826 void __iomem *ioaddr = tp->mmio_addr;
françois romieub646d902011-01-03 15:08:21 +0000827 int i;
828
829 RTL_W8(ERIDR, cmd);
830 RTL_W32(ERIAR, 0x800010e8);
831 msleep(2);
832 for (i = 0; i < 5; i++) {
833 udelay(100);
Francois Romieu1e4e82b2011-06-24 19:52:13 +0200834 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
françois romieub646d902011-01-03 15:08:21 +0000835 break;
836 }
837
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800838 ocp_write(tp, 0x1, 0x30, 0x00000001);
françois romieub646d902011-01-03 15:08:21 +0000839}
840
841#define OOB_CMD_RESET 0x00
842#define OOB_CMD_DRIVER_START 0x05
843#define OOB_CMD_DRIVER_STOP 0x06
844
Francois Romieucecb5fd2011-04-01 10:21:07 +0200845static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
846{
847 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
848}
849
françois romieub646d902011-01-03 15:08:21 +0000850static void rtl8168_driver_start(struct rtl8169_private *tp)
851{
Francois Romieucecb5fd2011-04-01 10:21:07 +0200852 u16 reg;
françois romieub646d902011-01-03 15:08:21 +0000853 int i;
854
855 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
856
Francois Romieucecb5fd2011-04-01 10:21:07 +0200857 reg = rtl8168_get_ocp_reg(tp);
hayeswang4804b3b2011-03-21 01:50:29 +0000858
françois romieub646d902011-01-03 15:08:21 +0000859 for (i = 0; i < 10; i++) {
860 msleep(10);
hayeswang4804b3b2011-03-21 01:50:29 +0000861 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
françois romieub646d902011-01-03 15:08:21 +0000862 break;
863 }
864}
865
866static void rtl8168_driver_stop(struct rtl8169_private *tp)
867{
Francois Romieucecb5fd2011-04-01 10:21:07 +0200868 u16 reg;
françois romieub646d902011-01-03 15:08:21 +0000869 int i;
870
871 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
872
Francois Romieucecb5fd2011-04-01 10:21:07 +0200873 reg = rtl8168_get_ocp_reg(tp);
hayeswang4804b3b2011-03-21 01:50:29 +0000874
françois romieub646d902011-01-03 15:08:21 +0000875 for (i = 0; i < 10; i++) {
876 msleep(10);
hayeswang4804b3b2011-03-21 01:50:29 +0000877 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
françois romieub646d902011-01-03 15:08:21 +0000878 break;
879 }
880}
881
hayeswang4804b3b2011-03-21 01:50:29 +0000882static int r8168dp_check_dash(struct rtl8169_private *tp)
883{
Francois Romieucecb5fd2011-04-01 10:21:07 +0200884 u16 reg = rtl8168_get_ocp_reg(tp);
hayeswang4804b3b2011-03-21 01:50:29 +0000885
Francois Romieucecb5fd2011-04-01 10:21:07 +0200886 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
hayeswang4804b3b2011-03-21 01:50:29 +0000887}
françois romieub646d902011-01-03 15:08:21 +0000888
françois romieu4da19632011-01-03 15:07:55 +0000889static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890{
891 int i;
892
Francois Romieua6baf3a2007-11-08 23:23:21 +0100893 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894
Francois Romieu23714082006-01-29 00:49:09 +0100895 for (i = 20; i > 0; i--) {
Francois Romieu07d3f512007-02-21 22:40:46 +0100896 /*
897 * Check if the RTL8169 has completed writing to the specified
898 * MII register.
899 */
Francois Romieu5b0384f2006-08-16 16:00:01 +0200900 if (!(RTL_R32(PHYAR) & 0x80000000))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 break;
Francois Romieu23714082006-01-29 00:49:09 +0100902 udelay(25);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903 }
Timo Teräs024a07b2010-06-06 15:38:47 -0700904 /*
Timo Teräs81a95f02010-06-09 17:31:48 -0700905 * According to hardware specs a 20us delay is required after write
906 * complete indication, but before sending next command.
Timo Teräs024a07b2010-06-06 15:38:47 -0700907 */
Timo Teräs81a95f02010-06-09 17:31:48 -0700908 udelay(20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909}
910
françois romieu4da19632011-01-03 15:07:55 +0000911static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912{
913 int i, value = -1;
914
Francois Romieua6baf3a2007-11-08 23:23:21 +0100915 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916
Francois Romieu23714082006-01-29 00:49:09 +0100917 for (i = 20; i > 0; i--) {
Francois Romieu07d3f512007-02-21 22:40:46 +0100918 /*
919 * Check if the RTL8169 has completed retrieving data from
920 * the specified MII register.
921 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922 if (RTL_R32(PHYAR) & 0x80000000) {
Francois Romieua6baf3a2007-11-08 23:23:21 +0100923 value = RTL_R32(PHYAR) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924 break;
925 }
Francois Romieu23714082006-01-29 00:49:09 +0100926 udelay(25);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 }
Timo Teräs81a95f02010-06-09 17:31:48 -0700928 /*
929 * According to hardware specs a 20us delay is required after read
930 * complete indication, but before sending next command.
931 */
932 udelay(20);
933
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 return value;
935}
936
françois romieuc0e45c12011-01-03 15:08:04 +0000937static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
938{
939 int i;
940
941 RTL_W32(OCPDR, data |
942 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
943 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
944 RTL_W32(EPHY_RXER_NUM, 0);
945
946 for (i = 0; i < 100; i++) {
947 mdelay(1);
948 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
949 break;
950 }
951}
952
953static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
954{
955 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
956 (value & OCPDR_DATA_MASK));
957}
958
959static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
960{
961 int i;
962
963 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
964
965 mdelay(1);
966 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
967 RTL_W32(EPHY_RXER_NUM, 0);
968
969 for (i = 0; i < 100; i++) {
970 mdelay(1);
971 if (RTL_R32(OCPAR) & OCPAR_FLAG)
972 break;
973 }
974
975 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
976}
977
françois romieue6de30d2011-01-03 15:08:37 +0000978#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
979
980static void r8168dp_2_mdio_start(void __iomem *ioaddr)
981{
982 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
983}
984
985static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
986{
987 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
988}
989
990static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
991{
992 r8168dp_2_mdio_start(ioaddr);
993
994 r8169_mdio_write(ioaddr, reg_addr, value);
995
996 r8168dp_2_mdio_stop(ioaddr);
997}
998
999static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1000{
1001 int value;
1002
1003 r8168dp_2_mdio_start(ioaddr);
1004
1005 value = r8169_mdio_read(ioaddr, reg_addr);
1006
1007 r8168dp_2_mdio_stop(ioaddr);
1008
1009 return value;
1010}
1011
françois romieu4da19632011-01-03 15:07:55 +00001012static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
Francois Romieudacf8152008-08-02 20:44:13 +02001013{
françois romieuc0e45c12011-01-03 15:08:04 +00001014 tp->mdio_ops.write(tp->mmio_addr, location, val);
Francois Romieudacf8152008-08-02 20:44:13 +02001015}
1016
françois romieu4da19632011-01-03 15:07:55 +00001017static int rtl_readphy(struct rtl8169_private *tp, int location)
1018{
françois romieuc0e45c12011-01-03 15:08:04 +00001019 return tp->mdio_ops.read(tp->mmio_addr, location);
françois romieu4da19632011-01-03 15:07:55 +00001020}
1021
1022static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1023{
1024 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1025}
1026
1027static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
françois romieudaf9df62009-10-07 12:44:20 +00001028{
1029 int val;
1030
françois romieu4da19632011-01-03 15:07:55 +00001031 val = rtl_readphy(tp, reg_addr);
1032 rtl_writephy(tp, reg_addr, (val | p) & ~m);
françois romieudaf9df62009-10-07 12:44:20 +00001033}
1034
Francois Romieuccdffb92008-07-26 14:26:06 +02001035static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1036 int val)
1037{
1038 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieuccdffb92008-07-26 14:26:06 +02001039
françois romieu4da19632011-01-03 15:07:55 +00001040 rtl_writephy(tp, location, val);
Francois Romieuccdffb92008-07-26 14:26:06 +02001041}
1042
1043static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1044{
1045 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieuccdffb92008-07-26 14:26:06 +02001046
françois romieu4da19632011-01-03 15:07:55 +00001047 return rtl_readphy(tp, location);
Francois Romieuccdffb92008-07-26 14:26:06 +02001048}
1049
Francois Romieudacf8152008-08-02 20:44:13 +02001050static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1051{
1052 unsigned int i;
1053
1054 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1055 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1056
1057 for (i = 0; i < 100; i++) {
1058 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1059 break;
1060 udelay(10);
1061 }
1062}
1063
1064static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1065{
1066 u16 value = 0xffff;
1067 unsigned int i;
1068
1069 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1070
1071 for (i = 0; i < 100; i++) {
1072 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1073 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1074 break;
1075 }
1076 udelay(10);
1077 }
1078
1079 return value;
1080}
1081
1082static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1083{
1084 unsigned int i;
1085
1086 RTL_W32(CSIDR, value);
1087 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1088 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1089
1090 for (i = 0; i < 100; i++) {
1091 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1092 break;
1093 udelay(10);
1094 }
1095}
1096
1097static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1098{
1099 u32 value = ~0x00;
1100 unsigned int i;
1101
1102 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1103 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1104
1105 for (i = 0; i < 100; i++) {
1106 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1107 value = RTL_R32(CSIDR);
1108 break;
1109 }
1110 udelay(10);
1111 }
1112
1113 return value;
1114}
1115
Hayes Wang133ac402011-07-06 15:58:05 +08001116static
1117void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1118{
1119 unsigned int i;
1120
1121 BUG_ON((addr & 3) || (mask == 0));
1122 RTL_W32(ERIDR, val);
1123 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1124
1125 for (i = 0; i < 100; i++) {
1126 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1127 break;
1128 udelay(100);
1129 }
1130}
1131
1132static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1133{
1134 u32 value = ~0x00;
1135 unsigned int i;
1136
1137 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1138
1139 for (i = 0; i < 100; i++) {
1140 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1141 value = RTL_R32(ERIDR);
1142 break;
1143 }
1144 udelay(100);
1145 }
1146
1147 return value;
1148}
1149
1150static void
1151rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1152{
1153 u32 val;
1154
1155 val = rtl_eri_read(ioaddr, addr, type);
1156 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1157}
1158
françois romieuc28aa382011-08-02 03:53:43 +00001159struct exgmac_reg {
1160 u16 addr;
1161 u16 mask;
1162 u32 val;
1163};
1164
1165static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1166 const struct exgmac_reg *r, int len)
1167{
1168 while (len-- > 0) {
1169 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1170 r++;
1171 }
1172}
1173
françois romieudaf9df62009-10-07 12:44:20 +00001174static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1175{
1176 u8 value = 0xff;
1177 unsigned int i;
1178
1179 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1180
1181 for (i = 0; i < 300; i++) {
1182 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1183 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1184 break;
1185 }
1186 udelay(100);
1187 }
1188
1189 return value;
1190}
1191
Francois Romieu9085cdfa2012-01-26 12:59:08 +01001192static u16 rtl_get_events(struct rtl8169_private *tp)
1193{
1194 void __iomem *ioaddr = tp->mmio_addr;
1195
1196 return RTL_R16(IntrStatus);
1197}
1198
1199static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1200{
1201 void __iomem *ioaddr = tp->mmio_addr;
1202
1203 RTL_W16(IntrStatus, bits);
1204 mmiowb();
1205}
1206
1207static void rtl_irq_disable(struct rtl8169_private *tp)
1208{
1209 void __iomem *ioaddr = tp->mmio_addr;
1210
1211 RTL_W16(IntrMask, 0);
1212 mmiowb();
1213}
1214
Francois Romieu3e990ff2012-01-26 12:50:01 +01001215static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1216{
1217 void __iomem *ioaddr = tp->mmio_addr;
1218
1219 RTL_W16(IntrMask, bits);
1220}
1221
Francois Romieuda78dbf2012-01-26 14:18:23 +01001222#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1223#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1224#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1225
1226static void rtl_irq_enable_all(struct rtl8169_private *tp)
1227{
1228 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1229}
1230
françois romieu811fd302011-12-04 20:30:45 +00001231static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232{
françois romieu811fd302011-12-04 20:30:45 +00001233 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234
Francois Romieu9085cdfa2012-01-26 12:59:08 +01001235 rtl_irq_disable(tp);
Francois Romieuda78dbf2012-01-26 14:18:23 +01001236 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
françois romieu811fd302011-12-04 20:30:45 +00001237 RTL_R8(ChipCmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238}
1239
françois romieu4da19632011-01-03 15:07:55 +00001240static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241{
françois romieu4da19632011-01-03 15:07:55 +00001242 void __iomem *ioaddr = tp->mmio_addr;
1243
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244 return RTL_R32(TBICSR) & TBIReset;
1245}
1246
françois romieu4da19632011-01-03 15:07:55 +00001247static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248{
françois romieu4da19632011-01-03 15:07:55 +00001249 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250}
1251
1252static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1253{
1254 return RTL_R32(TBICSR) & TBILinkOk;
1255}
1256
1257static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1258{
1259 return RTL_R8(PHYstatus) & LinkStatus;
1260}
1261
françois romieu4da19632011-01-03 15:07:55 +00001262static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001263{
françois romieu4da19632011-01-03 15:07:55 +00001264 void __iomem *ioaddr = tp->mmio_addr;
1265
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1267}
1268
françois romieu4da19632011-01-03 15:07:55 +00001269static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270{
1271 unsigned int val;
1272
françois romieu4da19632011-01-03 15:07:55 +00001273 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1274 rtl_writephy(tp, MII_BMCR, val & 0xffff);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275}
1276
Hayes Wang70090422011-07-06 15:58:06 +08001277static void rtl_link_chg_patch(struct rtl8169_private *tp)
1278{
1279 void __iomem *ioaddr = tp->mmio_addr;
1280 struct net_device *dev = tp->dev;
1281
1282 if (!netif_running(dev))
1283 return;
1284
1285 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1286 if (RTL_R8(PHYstatus) & _1000bpsF) {
1287 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1288 0x00000011, ERIAR_EXGMAC);
1289 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1290 0x00000005, ERIAR_EXGMAC);
1291 } else if (RTL_R8(PHYstatus) & _100bps) {
1292 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1293 0x0000001f, ERIAR_EXGMAC);
1294 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1295 0x00000005, ERIAR_EXGMAC);
1296 } else {
1297 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298 0x0000001f, ERIAR_EXGMAC);
1299 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300 0x0000003f, ERIAR_EXGMAC);
1301 }
1302 /* Reset packet filter */
1303 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1304 ERIAR_EXGMAC);
1305 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1306 ERIAR_EXGMAC);
Hayes Wangc2218922011-09-06 16:55:18 +08001307 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1308 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1309 if (RTL_R8(PHYstatus) & _1000bpsF) {
1310 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1311 0x00000011, ERIAR_EXGMAC);
1312 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1313 0x00000005, ERIAR_EXGMAC);
1314 } else {
1315 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1316 0x0000001f, ERIAR_EXGMAC);
1317 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1318 0x0000003f, ERIAR_EXGMAC);
1319 }
Hayes Wang70090422011-07-06 15:58:06 +08001320 }
1321}
1322
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001323static void __rtl8169_check_link_status(struct net_device *dev,
Francois Romieucecb5fd2011-04-01 10:21:07 +02001324 struct rtl8169_private *tp,
1325 void __iomem *ioaddr, bool pm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001327 if (tp->link_ok(ioaddr)) {
Hayes Wang70090422011-07-06 15:58:06 +08001328 rtl_link_chg_patch(tp);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001329 /* This is to cancel a scheduled suspend if there's one. */
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001330 if (pm)
1331 pm_request_resume(&tp->pci_dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332 netif_carrier_on(dev);
Francois Romieu1519e572011-02-03 12:02:36 +01001333 if (net_ratelimit())
1334 netif_info(tp, ifup, dev, "link up\n");
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001335 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336 netif_carrier_off(dev);
Joe Perchesbf82c182010-02-09 11:49:50 +00001337 netif_info(tp, ifdown, dev, "link down\n");
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001338 if (pm)
hayeswang10953db2011-11-07 20:44:37 +00001339 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001340 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341}
1342
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001343static void rtl8169_check_link_status(struct net_device *dev,
1344 struct rtl8169_private *tp,
1345 void __iomem *ioaddr)
1346{
1347 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1348}
1349
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001350#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1351
1352static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1353{
1354 void __iomem *ioaddr = tp->mmio_addr;
1355 u8 options;
1356 u32 wolopts = 0;
1357
1358 options = RTL_R8(Config1);
1359 if (!(options & PMEnable))
1360 return 0;
1361
1362 options = RTL_R8(Config3);
1363 if (options & LinkUp)
1364 wolopts |= WAKE_PHY;
1365 if (options & MagicPacket)
1366 wolopts |= WAKE_MAGIC;
1367
1368 options = RTL_R8(Config5);
1369 if (options & UWF)
1370 wolopts |= WAKE_UCAST;
1371 if (options & BWF)
1372 wolopts |= WAKE_BCAST;
1373 if (options & MWF)
1374 wolopts |= WAKE_MCAST;
1375
1376 return wolopts;
1377}
1378
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001379static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1380{
1381 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001382
Francois Romieuda78dbf2012-01-26 14:18:23 +01001383 rtl_lock_work(tp);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001384
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001385 wol->supported = WAKE_ANY;
1386 wol->wolopts = __rtl8169_get_wol(tp);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001387
Francois Romieuda78dbf2012-01-26 14:18:23 +01001388 rtl_unlock_work(tp);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001389}
1390
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001391static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001392{
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001393 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu07d3f512007-02-21 22:40:46 +01001394 unsigned int i;
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001395 static const struct {
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001396 u32 opt;
1397 u16 reg;
1398 u8 mask;
1399 } cfg[] = {
1400 { WAKE_ANY, Config1, PMEnable },
1401 { WAKE_PHY, Config3, LinkUp },
1402 { WAKE_MAGIC, Config3, MagicPacket },
1403 { WAKE_UCAST, Config5, UWF },
1404 { WAKE_BCAST, Config5, BWF },
1405 { WAKE_MCAST, Config5, MWF },
1406 { WAKE_ANY, Config5, LanWake }
1407 };
1408
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001409 RTL_W8(Cfg9346, Cfg9346_Unlock);
1410
1411 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1412 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001413 if (wolopts & cfg[i].opt)
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001414 options |= cfg[i].mask;
1415 RTL_W8(cfg[i].reg, options);
1416 }
1417
1418 RTL_W8(Cfg9346, Cfg9346_Lock);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001419}
1420
1421static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1422{
1423 struct rtl8169_private *tp = netdev_priv(dev);
1424
Francois Romieuda78dbf2012-01-26 14:18:23 +01001425 rtl_lock_work(tp);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001426
Francois Romieuf23e7fd2007-10-04 22:36:14 +02001427 if (wol->wolopts)
1428 tp->features |= RTL_FEATURE_WOL;
1429 else
1430 tp->features &= ~RTL_FEATURE_WOL;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001431 __rtl8169_set_wol(tp, wol->wolopts);
Francois Romieuda78dbf2012-01-26 14:18:23 +01001432
1433 rtl_unlock_work(tp);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001434
françois romieuea809072010-11-08 13:23:58 +00001435 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1436
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001437 return 0;
1438}
1439
Francois Romieu31bd2042011-04-26 18:58:59 +02001440static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1441{
Francois Romieu85bffe62011-04-27 08:22:39 +02001442 return rtl_chip_infos[tp->mac_version].fw_name;
Francois Romieu31bd2042011-04-26 18:58:59 +02001443}
1444
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445static void rtl8169_get_drvinfo(struct net_device *dev,
1446 struct ethtool_drvinfo *info)
1447{
1448 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieub6ffd972011-06-17 17:00:05 +02001449 struct rtl_fw *rtl_fw = tp->rtl_fw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450
Rick Jones68aad782011-11-07 13:29:27 +00001451 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1452 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1453 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
Francois Romieu1c361ef2011-06-17 17:16:24 +02001454 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
Rick Jones8ac72d12011-11-22 14:06:26 +00001455 if (!IS_ERR_OR_NULL(rtl_fw))
1456 strlcpy(info->fw_version, rtl_fw->version,
1457 sizeof(info->fw_version));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458}
1459
1460static int rtl8169_get_regs_len(struct net_device *dev)
1461{
1462 return R8169_REGS_SIZE;
1463}
1464
1465static int rtl8169_set_speed_tbi(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001466 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001467{
1468 struct rtl8169_private *tp = netdev_priv(dev);
1469 void __iomem *ioaddr = tp->mmio_addr;
1470 int ret = 0;
1471 u32 reg;
1472
1473 reg = RTL_R32(TBICSR);
1474 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1475 (duplex == DUPLEX_FULL)) {
1476 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1477 } else if (autoneg == AUTONEG_ENABLE)
1478 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1479 else {
Joe Perchesbf82c182010-02-09 11:49:50 +00001480 netif_warn(tp, link, dev,
1481 "incorrect speed setting refused in TBI mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 ret = -EOPNOTSUPP;
1483 }
1484
1485 return ret;
1486}
1487
1488static int rtl8169_set_speed_xmii(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001489 u8 autoneg, u16 speed, u8 duplex, u32 adv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490{
1491 struct rtl8169_private *tp = netdev_priv(dev);
françois romieu3577aa12009-05-19 10:46:48 +00001492 int giga_ctrl, bmcr;
Oliver Neukum54405cd2011-01-06 21:55:13 +01001493 int rc = -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494
Hayes Wang716b50a2011-02-22 17:26:18 +08001495 rtl_writephy(tp, 0x1f, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496
1497 if (autoneg == AUTONEG_ENABLE) {
françois romieu3577aa12009-05-19 10:46:48 +00001498 int auto_nego;
1499
françois romieu4da19632011-01-03 15:07:55 +00001500 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
Oliver Neukum54405cd2011-01-06 21:55:13 +01001501 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1502 ADVERTISE_100HALF | ADVERTISE_100FULL);
1503
1504 if (adv & ADVERTISED_10baseT_Half)
1505 auto_nego |= ADVERTISE_10HALF;
1506 if (adv & ADVERTISED_10baseT_Full)
1507 auto_nego |= ADVERTISE_10FULL;
1508 if (adv & ADVERTISED_100baseT_Half)
1509 auto_nego |= ADVERTISE_100HALF;
1510 if (adv & ADVERTISED_100baseT_Full)
1511 auto_nego |= ADVERTISE_100FULL;
1512
françois romieu3577aa12009-05-19 10:46:48 +00001513 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1514
françois romieu4da19632011-01-03 15:07:55 +00001515 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
françois romieu3577aa12009-05-19 10:46:48 +00001516 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1517
1518 /* The 8100e/8101e/8102e do Fast Ethernet only. */
Francois Romieu826e6cb2011-03-11 20:30:24 +01001519 if (tp->mii.supports_gmii) {
Oliver Neukum54405cd2011-01-06 21:55:13 +01001520 if (adv & ADVERTISED_1000baseT_Half)
1521 giga_ctrl |= ADVERTISE_1000HALF;
1522 if (adv & ADVERTISED_1000baseT_Full)
1523 giga_ctrl |= ADVERTISE_1000FULL;
1524 } else if (adv & (ADVERTISED_1000baseT_Half |
1525 ADVERTISED_1000baseT_Full)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00001526 netif_info(tp, link, dev,
1527 "PHY does not support 1000Mbps\n");
Oliver Neukum54405cd2011-01-06 21:55:13 +01001528 goto out;
Francois Romieubcf0bf92006-07-26 23:14:13 +02001529 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530
françois romieu3577aa12009-05-19 10:46:48 +00001531 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
Francois Romieu623a1592006-05-14 12:42:14 +02001532
françois romieu4da19632011-01-03 15:07:55 +00001533 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1534 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
françois romieu3577aa12009-05-19 10:46:48 +00001535 } else {
1536 giga_ctrl = 0;
1537
1538 if (speed == SPEED_10)
1539 bmcr = 0;
1540 else if (speed == SPEED_100)
1541 bmcr = BMCR_SPEED100;
1542 else
Oliver Neukum54405cd2011-01-06 21:55:13 +01001543 goto out;
françois romieu3577aa12009-05-19 10:46:48 +00001544
1545 if (duplex == DUPLEX_FULL)
1546 bmcr |= BMCR_FULLDPLX;
Roger So2584fbc2007-07-31 23:52:42 +02001547 }
1548
françois romieu4da19632011-01-03 15:07:55 +00001549 rtl_writephy(tp, MII_BMCR, bmcr);
françois romieu3577aa12009-05-19 10:46:48 +00001550
Francois Romieucecb5fd2011-04-01 10:21:07 +02001551 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1552 tp->mac_version == RTL_GIGA_MAC_VER_03) {
françois romieu3577aa12009-05-19 10:46:48 +00001553 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
françois romieu4da19632011-01-03 15:07:55 +00001554 rtl_writephy(tp, 0x17, 0x2138);
1555 rtl_writephy(tp, 0x0e, 0x0260);
françois romieu3577aa12009-05-19 10:46:48 +00001556 } else {
françois romieu4da19632011-01-03 15:07:55 +00001557 rtl_writephy(tp, 0x17, 0x2108);
1558 rtl_writephy(tp, 0x0e, 0x0000);
françois romieu3577aa12009-05-19 10:46:48 +00001559 }
1560 }
1561
Oliver Neukum54405cd2011-01-06 21:55:13 +01001562 rc = 0;
1563out:
1564 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565}
1566
1567static int rtl8169_set_speed(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001568 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569{
1570 struct rtl8169_private *tp = netdev_priv(dev);
1571 int ret;
1572
Oliver Neukum54405cd2011-01-06 21:55:13 +01001573 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
Francois Romieu4876cc12011-03-11 21:07:11 +01001574 if (ret < 0)
1575 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576
Francois Romieu4876cc12011-03-11 21:07:11 +01001577 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1578 (advertising & ADVERTISED_1000baseT_Full)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
Francois Romieu4876cc12011-03-11 21:07:11 +01001580 }
1581out:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582 return ret;
1583}
1584
1585static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1586{
1587 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001588 int ret;
1589
Francois Romieu4876cc12011-03-11 21:07:11 +01001590 del_timer_sync(&tp->timer);
1591
Francois Romieuda78dbf2012-01-26 14:18:23 +01001592 rtl_lock_work(tp);
Francois Romieucecb5fd2011-04-01 10:21:07 +02001593 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
David Decotigny25db0332011-04-27 18:32:39 +00001594 cmd->duplex, cmd->advertising);
Francois Romieuda78dbf2012-01-26 14:18:23 +01001595 rtl_unlock_work(tp);
Francois Romieu5b0384f2006-08-16 16:00:01 +02001596
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597 return ret;
1598}
1599
Michał Mirosławc8f44af2011-11-15 15:29:55 +00001600static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1601 netdev_features_t features)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602{
Francois Romieud58d46b2011-05-03 16:38:29 +02001603 struct rtl8169_private *tp = netdev_priv(dev);
1604
Francois Romieu2b7b4312011-04-18 22:53:24 -07001605 if (dev->mtu > TD_MSS_MAX)
Michał Mirosław350fb322011-04-08 06:35:56 +00001606 features &= ~NETIF_F_ALL_TSO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607
Francois Romieud58d46b2011-05-03 16:38:29 +02001608 if (dev->mtu > JUMBO_1K &&
1609 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1610 features &= ~NETIF_F_IP_CSUM;
1611
Michał Mirosław350fb322011-04-08 06:35:56 +00001612 return features;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613}
1614
Francois Romieuda78dbf2012-01-26 14:18:23 +01001615static void __rtl8169_set_features(struct net_device *dev,
1616 netdev_features_t features)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001617{
1618 struct rtl8169_private *tp = netdev_priv(dev);
Ben Greear6bbe0212012-02-10 15:04:33 +00001619 netdev_features_t changed = features ^ dev->features;
Francois Romieuda78dbf2012-01-26 14:18:23 +01001620 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621
Ben Greear6bbe0212012-02-10 15:04:33 +00001622 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1623 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624
Ben Greear6bbe0212012-02-10 15:04:33 +00001625 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1626 if (features & NETIF_F_RXCSUM)
1627 tp->cp_cmd |= RxChkSum;
1628 else
1629 tp->cp_cmd &= ~RxChkSum;
Michał Mirosław350fb322011-04-08 06:35:56 +00001630
Ben Greear6bbe0212012-02-10 15:04:33 +00001631 if (dev->features & NETIF_F_HW_VLAN_RX)
1632 tp->cp_cmd |= RxVlan;
1633 else
1634 tp->cp_cmd &= ~RxVlan;
1635
1636 RTL_W16(CPlusCmd, tp->cp_cmd);
1637 RTL_R16(CPlusCmd);
1638 }
1639 if (changed & NETIF_F_RXALL) {
1640 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1641 if (features & NETIF_F_RXALL)
1642 tmp |= (AcceptErr | AcceptRunt);
1643 RTL_W32(RxConfig, tmp);
1644 }
Francois Romieuda78dbf2012-01-26 14:18:23 +01001645}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646
Francois Romieuda78dbf2012-01-26 14:18:23 +01001647static int rtl8169_set_features(struct net_device *dev,
1648 netdev_features_t features)
1649{
1650 struct rtl8169_private *tp = netdev_priv(dev);
1651
1652 rtl_lock_work(tp);
1653 __rtl8169_set_features(dev, features);
1654 rtl_unlock_work(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001655
1656 return 0;
1657}
1658
Francois Romieuda78dbf2012-01-26 14:18:23 +01001659
Linus Torvalds1da177e2005-04-16 15:20:36 -07001660static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1661 struct sk_buff *skb)
1662{
Jesse Grosseab6d182010-10-20 13:56:03 +00001663 return (vlan_tx_tag_present(skb)) ?
Linus Torvalds1da177e2005-04-16 15:20:36 -07001664 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1665}
1666
Francois Romieu7a8fc772011-03-01 17:18:33 +01001667static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001668{
1669 u32 opts2 = le32_to_cpu(desc->opts2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001670
Francois Romieu7a8fc772011-03-01 17:18:33 +01001671 if (opts2 & RxVlanTag)
1672 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
Eric Dumazet2edae082010-09-06 18:46:39 +00001673
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674 desc->opts2 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001675}
1676
Francois Romieuccdffb92008-07-26 14:26:06 +02001677static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001678{
1679 struct rtl8169_private *tp = netdev_priv(dev);
1680 void __iomem *ioaddr = tp->mmio_addr;
1681 u32 status;
1682
1683 cmd->supported =
1684 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1685 cmd->port = PORT_FIBRE;
1686 cmd->transceiver = XCVR_INTERNAL;
1687
1688 status = RTL_R32(TBICSR);
1689 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1690 cmd->autoneg = !!(status & TBINwEnable);
1691
David Decotigny70739492011-04-27 18:32:40 +00001692 ethtool_cmd_speed_set(cmd, SPEED_1000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001693 cmd->duplex = DUPLEX_FULL; /* Always set */
Francois Romieuccdffb92008-07-26 14:26:06 +02001694
1695 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001696}
1697
Francois Romieuccdffb92008-07-26 14:26:06 +02001698static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001699{
1700 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001701
Francois Romieuccdffb92008-07-26 14:26:06 +02001702 return mii_ethtool_gset(&tp->mii, cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001703}
1704
1705static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1706{
1707 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieuccdffb92008-07-26 14:26:06 +02001708 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001709
Francois Romieuda78dbf2012-01-26 14:18:23 +01001710 rtl_lock_work(tp);
Francois Romieuccdffb92008-07-26 14:26:06 +02001711 rc = tp->get_settings(dev, cmd);
Francois Romieuda78dbf2012-01-26 14:18:23 +01001712 rtl_unlock_work(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001713
Francois Romieuccdffb92008-07-26 14:26:06 +02001714 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001715}
1716
1717static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1718 void *p)
1719{
Francois Romieu5b0384f2006-08-16 16:00:01 +02001720 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721
Francois Romieu5b0384f2006-08-16 16:00:01 +02001722 if (regs->len > R8169_REGS_SIZE)
1723 regs->len = R8169_REGS_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724
Francois Romieuda78dbf2012-01-26 14:18:23 +01001725 rtl_lock_work(tp);
Francois Romieu5b0384f2006-08-16 16:00:01 +02001726 memcpy_fromio(p, tp->mmio_addr, regs->len);
Francois Romieuda78dbf2012-01-26 14:18:23 +01001727 rtl_unlock_work(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728}
1729
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001730static u32 rtl8169_get_msglevel(struct net_device *dev)
1731{
1732 struct rtl8169_private *tp = netdev_priv(dev);
1733
1734 return tp->msg_enable;
1735}
1736
1737static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1738{
1739 struct rtl8169_private *tp = netdev_priv(dev);
1740
1741 tp->msg_enable = value;
1742}
1743
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001744static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1745 "tx_packets",
1746 "rx_packets",
1747 "tx_errors",
1748 "rx_errors",
1749 "rx_missed",
1750 "align_errors",
1751 "tx_single_collisions",
1752 "tx_multi_collisions",
1753 "unicast",
1754 "broadcast",
1755 "multicast",
1756 "tx_aborted",
1757 "tx_underrun",
1758};
1759
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001760static int rtl8169_get_sset_count(struct net_device *dev, int sset)
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001761{
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001762 switch (sset) {
1763 case ETH_SS_STATS:
1764 return ARRAY_SIZE(rtl8169_gstrings);
1765 default:
1766 return -EOPNOTSUPP;
1767 }
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001768}
1769
Ivan Vecera355423d2009-02-06 21:49:57 -08001770static void rtl8169_update_counters(struct net_device *dev)
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001771{
1772 struct rtl8169_private *tp = netdev_priv(dev);
1773 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieucecb5fd2011-04-01 10:21:07 +02001774 struct device *d = &tp->pci_dev->dev;
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001775 struct rtl8169_counters *counters;
1776 dma_addr_t paddr;
1777 u32 cmd;
Ivan Vecera355423d2009-02-06 21:49:57 -08001778 int wait = 1000;
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001779
Ivan Vecera355423d2009-02-06 21:49:57 -08001780 /*
1781 * Some chips are unable to dump tally counters when the receiver
1782 * is disabled.
1783 */
1784 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1785 return;
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001786
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00001787 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001788 if (!counters)
1789 return;
1790
1791 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07001792 cmd = (u64)paddr & DMA_BIT_MASK(32);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001793 RTL_W32(CounterAddrLow, cmd);
1794 RTL_W32(CounterAddrLow, cmd | CounterDump);
1795
Ivan Vecera355423d2009-02-06 21:49:57 -08001796 while (wait--) {
1797 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
Ivan Vecera355423d2009-02-06 21:49:57 -08001798 memcpy(&tp->counters, counters, sizeof(*counters));
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001799 break;
Ivan Vecera355423d2009-02-06 21:49:57 -08001800 }
1801 udelay(10);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001802 }
1803
1804 RTL_W32(CounterAddrLow, 0);
1805 RTL_W32(CounterAddrHigh, 0);
1806
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00001807 dma_free_coherent(d, sizeof(*counters), counters, paddr);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001808}
1809
Ivan Vecera355423d2009-02-06 21:49:57 -08001810static void rtl8169_get_ethtool_stats(struct net_device *dev,
1811 struct ethtool_stats *stats, u64 *data)
1812{
1813 struct rtl8169_private *tp = netdev_priv(dev);
1814
1815 ASSERT_RTNL();
1816
1817 rtl8169_update_counters(dev);
1818
1819 data[0] = le64_to_cpu(tp->counters.tx_packets);
1820 data[1] = le64_to_cpu(tp->counters.rx_packets);
1821 data[2] = le64_to_cpu(tp->counters.tx_errors);
1822 data[3] = le32_to_cpu(tp->counters.rx_errors);
1823 data[4] = le16_to_cpu(tp->counters.rx_missed);
1824 data[5] = le16_to_cpu(tp->counters.align_errors);
1825 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1826 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1827 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1828 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1829 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1830 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1831 data[12] = le16_to_cpu(tp->counters.tx_underun);
1832}
1833
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001834static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1835{
1836 switch(stringset) {
1837 case ETH_SS_STATS:
1838 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1839 break;
1840 }
1841}
1842
Jeff Garzik7282d492006-09-13 14:30:00 -04001843static const struct ethtool_ops rtl8169_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001844 .get_drvinfo = rtl8169_get_drvinfo,
1845 .get_regs_len = rtl8169_get_regs_len,
1846 .get_link = ethtool_op_get_link,
1847 .get_settings = rtl8169_get_settings,
1848 .set_settings = rtl8169_set_settings,
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001849 .get_msglevel = rtl8169_get_msglevel,
1850 .set_msglevel = rtl8169_set_msglevel,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851 .get_regs = rtl8169_get_regs,
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001852 .get_wol = rtl8169_get_wol,
1853 .set_wol = rtl8169_set_wol,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001854 .get_strings = rtl8169_get_strings,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001855 .get_sset_count = rtl8169_get_sset_count,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001856 .get_ethtool_stats = rtl8169_get_ethtool_stats,
Richard Cochrane1593bb2012-04-03 22:59:35 +00001857 .get_ts_info = ethtool_op_get_ts_info,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001858};
1859
Francois Romieu07d3f512007-02-21 22:40:46 +01001860static void rtl8169_get_mac_version(struct rtl8169_private *tp,
Francois Romieu5d320a22011-05-08 17:47:36 +02001861 struct net_device *dev, u8 default_version)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001862{
Francois Romieu5d320a22011-05-08 17:47:36 +02001863 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu0e485152007-02-20 00:00:26 +01001864 /*
1865 * The driver currently handles the 8168Bf and the 8168Be identically
1866 * but they can be identified more specifically through the test below
1867 * if needed:
1868 *
1869 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
Francois Romieu01272152007-02-20 22:58:51 +01001870 *
1871 * Same thing for the 8101Eb and the 8101Ec:
1872 *
1873 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
Francois Romieu0e485152007-02-20 00:00:26 +01001874 */
Francois Romieu37441002011-06-17 22:58:54 +02001875 static const struct rtl_mac_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001876 u32 mask;
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001877 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878 int mac_version;
1879 } mac_info[] = {
Hayes Wangc2218922011-09-06 16:55:18 +08001880 /* 8168F family. */
1881 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1882 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1883
hayeswang01dc7fe2011-03-21 01:50:28 +00001884 /* 8168E family. */
Hayes Wang70090422011-07-06 15:58:06 +08001885 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
hayeswang01dc7fe2011-03-21 01:50:28 +00001886 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1887 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1888 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1889
Francois Romieu5b538df2008-07-20 16:22:45 +02001890 /* 8168D family. */
françois romieudaf9df62009-10-07 12:44:20 +00001891 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1892 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
françois romieudaf9df62009-10-07 12:44:20 +00001893 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
Francois Romieu5b538df2008-07-20 16:22:45 +02001894
françois romieue6de30d2011-01-03 15:08:37 +00001895 /* 8168DP family. */
1896 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1897 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
hayeswang4804b3b2011-03-21 01:50:29 +00001898 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
françois romieue6de30d2011-01-03 15:08:37 +00001899
Francois Romieuef808d52008-06-29 13:10:54 +02001900 /* 8168C family. */
Francois Romieu17c99292010-07-11 17:10:09 -07001901 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
Francois Romieuef3386f2008-06-29 12:24:30 +02001902 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
Francois Romieuef808d52008-06-29 13:10:54 +02001903 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
Francois Romieu7f3e3d32008-07-20 18:53:20 +02001904 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001905 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1906 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
Francois Romieu197ff762008-06-28 13:16:02 +02001907 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
Francois Romieu6fb07052008-06-29 11:54:28 +02001908 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
Francois Romieuef808d52008-06-29 13:10:54 +02001909 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001910
1911 /* 8168B family. */
1912 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1913 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1914 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1915 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1916
1917 /* 8101 family. */
hayeswang36a0e6c2011-03-21 01:50:30 +00001918 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
Hayes Wang5a5e4442011-02-22 17:26:21 +08001919 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1920 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1921 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001922 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1923 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1924 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1925 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1926 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1927 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001928 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001929 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001930 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001931 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1932 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001933 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1934 /* FIXME: where did these entries come from ? -- FR */
1935 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1936 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1937
1938 /* 8110 family. */
1939 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1940 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1941 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1942 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1943 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1944 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1945
Jean Delvaref21b75e2009-05-26 20:54:48 -07001946 /* Catch-all */
1947 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
Francois Romieu37441002011-06-17 22:58:54 +02001948 };
1949 const struct rtl_mac_info *p = mac_info;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950 u32 reg;
1951
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001952 reg = RTL_R32(TxConfig);
1953 while ((reg & p->mask) != p->val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954 p++;
1955 tp->mac_version = p->mac_version;
Francois Romieu5d320a22011-05-08 17:47:36 +02001956
1957 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1958 netif_notice(tp, probe, dev,
1959 "unknown MAC, using family default\n");
1960 tp->mac_version = default_version;
1961 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962}
1963
1964static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1965{
Francois Romieubcf0bf92006-07-26 23:14:13 +02001966 dprintk("mac_version = 0x%02x\n", tp->mac_version);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967}
1968
Francois Romieu867763c2007-08-17 18:21:58 +02001969struct phy_reg {
1970 u16 reg;
1971 u16 val;
1972};
1973
françois romieu4da19632011-01-03 15:07:55 +00001974static void rtl_writephy_batch(struct rtl8169_private *tp,
1975 const struct phy_reg *regs, int len)
Francois Romieu867763c2007-08-17 18:21:58 +02001976{
1977 while (len-- > 0) {
françois romieu4da19632011-01-03 15:07:55 +00001978 rtl_writephy(tp, regs->reg, regs->val);
Francois Romieu867763c2007-08-17 18:21:58 +02001979 regs++;
1980 }
1981}
1982
françois romieubca03d52011-01-03 15:07:31 +00001983#define PHY_READ 0x00000000
1984#define PHY_DATA_OR 0x10000000
1985#define PHY_DATA_AND 0x20000000
1986#define PHY_BJMPN 0x30000000
1987#define PHY_READ_EFUSE 0x40000000
1988#define PHY_READ_MAC_BYTE 0x50000000
1989#define PHY_WRITE_MAC_BYTE 0x60000000
1990#define PHY_CLEAR_READCOUNT 0x70000000
1991#define PHY_WRITE 0x80000000
1992#define PHY_READCOUNT_EQ_SKIP 0x90000000
1993#define PHY_COMP_EQ_SKIPN 0xa0000000
1994#define PHY_COMP_NEQ_SKIPN 0xb0000000
1995#define PHY_WRITE_PREVIOUS 0xc0000000
1996#define PHY_SKIPN 0xd0000000
1997#define PHY_DELAY_MS 0xe0000000
1998#define PHY_WRITE_ERI_WORD 0xf0000000
1999
Hayes Wang960aee62011-06-18 11:37:48 +02002000struct fw_info {
2001 u32 magic;
2002 char version[RTL_VER_SIZE];
2003 __le32 fw_start;
2004 __le32 fw_len;
2005 u8 chksum;
2006} __packed;
2007
Francois Romieu1c361ef2011-06-17 17:16:24 +02002008#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2009
2010static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
françois romieubca03d52011-01-03 15:07:31 +00002011{
Francois Romieub6ffd972011-06-17 17:00:05 +02002012 const struct firmware *fw = rtl_fw->fw;
Hayes Wang960aee62011-06-18 11:37:48 +02002013 struct fw_info *fw_info = (struct fw_info *)fw->data;
Francois Romieu1c361ef2011-06-17 17:16:24 +02002014 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2015 char *version = rtl_fw->version;
2016 bool rc = false;
françois romieubca03d52011-01-03 15:07:31 +00002017
Francois Romieu1c361ef2011-06-17 17:16:24 +02002018 if (fw->size < FW_OPCODE_SIZE)
2019 goto out;
Hayes Wang960aee62011-06-18 11:37:48 +02002020
2021 if (!fw_info->magic) {
2022 size_t i, size, start;
2023 u8 checksum = 0;
2024
2025 if (fw->size < sizeof(*fw_info))
2026 goto out;
2027
2028 for (i = 0; i < fw->size; i++)
2029 checksum += fw->data[i];
2030 if (checksum != 0)
2031 goto out;
2032
2033 start = le32_to_cpu(fw_info->fw_start);
2034 if (start > fw->size)
2035 goto out;
2036
2037 size = le32_to_cpu(fw_info->fw_len);
2038 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2039 goto out;
2040
2041 memcpy(version, fw_info->version, RTL_VER_SIZE);
2042
2043 pa->code = (__le32 *)(fw->data + start);
2044 pa->size = size;
2045 } else {
Francois Romieu1c361ef2011-06-17 17:16:24 +02002046 if (fw->size % FW_OPCODE_SIZE)
2047 goto out;
2048
2049 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2050
2051 pa->code = (__le32 *)fw->data;
2052 pa->size = fw->size / FW_OPCODE_SIZE;
2053 }
2054 version[RTL_VER_SIZE - 1] = 0;
2055
2056 rc = true;
2057out:
2058 return rc;
2059}
2060
Francois Romieufd112f22011-06-18 00:10:29 +02002061static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2062 struct rtl_fw_phy_action *pa)
Francois Romieu1c361ef2011-06-17 17:16:24 +02002063{
Francois Romieufd112f22011-06-18 00:10:29 +02002064 bool rc = false;
Francois Romieu1c361ef2011-06-17 17:16:24 +02002065 size_t index;
2066
Francois Romieu1c361ef2011-06-17 17:16:24 +02002067 for (index = 0; index < pa->size; index++) {
2068 u32 action = le32_to_cpu(pa->code[index]);
hayeswang42b82dc2011-01-10 02:07:25 +00002069 u32 regno = (action & 0x0fff0000) >> 16;
françois romieubca03d52011-01-03 15:07:31 +00002070
hayeswang42b82dc2011-01-10 02:07:25 +00002071 switch(action & 0xf0000000) {
2072 case PHY_READ:
2073 case PHY_DATA_OR:
2074 case PHY_DATA_AND:
2075 case PHY_READ_EFUSE:
2076 case PHY_CLEAR_READCOUNT:
2077 case PHY_WRITE:
2078 case PHY_WRITE_PREVIOUS:
2079 case PHY_DELAY_MS:
françois romieubca03d52011-01-03 15:07:31 +00002080 break;
2081
hayeswang42b82dc2011-01-10 02:07:25 +00002082 case PHY_BJMPN:
2083 if (regno > index) {
Francois Romieufd112f22011-06-18 00:10:29 +02002084 netif_err(tp, ifup, tp->dev,
Francois Romieucecb5fd2011-04-01 10:21:07 +02002085 "Out of range of firmware\n");
Francois Romieufd112f22011-06-18 00:10:29 +02002086 goto out;
hayeswang42b82dc2011-01-10 02:07:25 +00002087 }
2088 break;
2089 case PHY_READCOUNT_EQ_SKIP:
Francois Romieu1c361ef2011-06-17 17:16:24 +02002090 if (index + 2 >= pa->size) {
Francois Romieufd112f22011-06-18 00:10:29 +02002091 netif_err(tp, ifup, tp->dev,
Francois Romieucecb5fd2011-04-01 10:21:07 +02002092 "Out of range of firmware\n");
Francois Romieufd112f22011-06-18 00:10:29 +02002093 goto out;
hayeswang42b82dc2011-01-10 02:07:25 +00002094 }
2095 break;
2096 case PHY_COMP_EQ_SKIPN:
2097 case PHY_COMP_NEQ_SKIPN:
2098 case PHY_SKIPN:
Francois Romieu1c361ef2011-06-17 17:16:24 +02002099 if (index + 1 + regno >= pa->size) {
Francois Romieufd112f22011-06-18 00:10:29 +02002100 netif_err(tp, ifup, tp->dev,
Francois Romieucecb5fd2011-04-01 10:21:07 +02002101 "Out of range of firmware\n");
Francois Romieufd112f22011-06-18 00:10:29 +02002102 goto out;
hayeswang42b82dc2011-01-10 02:07:25 +00002103 }
2104 break;
2105
2106 case PHY_READ_MAC_BYTE:
2107 case PHY_WRITE_MAC_BYTE:
2108 case PHY_WRITE_ERI_WORD:
2109 default:
Francois Romieufd112f22011-06-18 00:10:29 +02002110 netif_err(tp, ifup, tp->dev,
hayeswang42b82dc2011-01-10 02:07:25 +00002111 "Invalid action 0x%08x\n", action);
Francois Romieufd112f22011-06-18 00:10:29 +02002112 goto out;
françois romieubca03d52011-01-03 15:07:31 +00002113 }
2114 }
Francois Romieufd112f22011-06-18 00:10:29 +02002115 rc = true;
2116out:
2117 return rc;
2118}
françois romieubca03d52011-01-03 15:07:31 +00002119
Francois Romieufd112f22011-06-18 00:10:29 +02002120static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2121{
2122 struct net_device *dev = tp->dev;
2123 int rc = -EINVAL;
2124
2125 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2126 netif_err(tp, ifup, dev, "invalid firwmare\n");
2127 goto out;
2128 }
2129
2130 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2131 rc = 0;
2132out:
2133 return rc;
2134}
2135
2136static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2137{
2138 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2139 u32 predata, count;
2140 size_t index;
2141
2142 predata = count = 0;
hayeswang42b82dc2011-01-10 02:07:25 +00002143
Francois Romieu1c361ef2011-06-17 17:16:24 +02002144 for (index = 0; index < pa->size; ) {
2145 u32 action = le32_to_cpu(pa->code[index]);
françois romieubca03d52011-01-03 15:07:31 +00002146 u32 data = action & 0x0000ffff;
hayeswang42b82dc2011-01-10 02:07:25 +00002147 u32 regno = (action & 0x0fff0000) >> 16;
2148
2149 if (!action)
2150 break;
françois romieubca03d52011-01-03 15:07:31 +00002151
2152 switch(action & 0xf0000000) {
hayeswang42b82dc2011-01-10 02:07:25 +00002153 case PHY_READ:
2154 predata = rtl_readphy(tp, regno);
2155 count++;
2156 index++;
françois romieubca03d52011-01-03 15:07:31 +00002157 break;
hayeswang42b82dc2011-01-10 02:07:25 +00002158 case PHY_DATA_OR:
2159 predata |= data;
2160 index++;
2161 break;
2162 case PHY_DATA_AND:
2163 predata &= data;
2164 index++;
2165 break;
2166 case PHY_BJMPN:
2167 index -= regno;
2168 break;
2169 case PHY_READ_EFUSE:
2170 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2171 index++;
2172 break;
2173 case PHY_CLEAR_READCOUNT:
2174 count = 0;
2175 index++;
2176 break;
2177 case PHY_WRITE:
2178 rtl_writephy(tp, regno, data);
2179 index++;
2180 break;
2181 case PHY_READCOUNT_EQ_SKIP:
Francois Romieucecb5fd2011-04-01 10:21:07 +02002182 index += (count == data) ? 2 : 1;
hayeswang42b82dc2011-01-10 02:07:25 +00002183 break;
2184 case PHY_COMP_EQ_SKIPN:
2185 if (predata == data)
2186 index += regno;
2187 index++;
2188 break;
2189 case PHY_COMP_NEQ_SKIPN:
2190 if (predata != data)
2191 index += regno;
2192 index++;
2193 break;
2194 case PHY_WRITE_PREVIOUS:
2195 rtl_writephy(tp, regno, predata);
2196 index++;
2197 break;
2198 case PHY_SKIPN:
2199 index += regno + 1;
2200 break;
2201 case PHY_DELAY_MS:
2202 mdelay(data);
2203 index++;
2204 break;
2205
2206 case PHY_READ_MAC_BYTE:
2207 case PHY_WRITE_MAC_BYTE:
2208 case PHY_WRITE_ERI_WORD:
françois romieubca03d52011-01-03 15:07:31 +00002209 default:
2210 BUG();
2211 }
2212 }
2213}
2214
françois romieuf1e02ed2011-01-13 13:07:53 +00002215static void rtl_release_firmware(struct rtl8169_private *tp)
2216{
Francois Romieub6ffd972011-06-17 17:00:05 +02002217 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2218 release_firmware(tp->rtl_fw->fw);
2219 kfree(tp->rtl_fw);
2220 }
2221 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
françois romieuf1e02ed2011-01-13 13:07:53 +00002222}
2223
François Romieu953a12c2011-04-24 17:38:48 +02002224static void rtl_apply_firmware(struct rtl8169_private *tp)
françois romieuf1e02ed2011-01-13 13:07:53 +00002225{
Francois Romieub6ffd972011-06-17 17:00:05 +02002226 struct rtl_fw *rtl_fw = tp->rtl_fw;
françois romieuf1e02ed2011-01-13 13:07:53 +00002227
2228 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
Francois Romieub6ffd972011-06-17 17:00:05 +02002229 if (!IS_ERR_OR_NULL(rtl_fw))
2230 rtl_phy_write_fw(tp, rtl_fw);
François Romieu953a12c2011-04-24 17:38:48 +02002231}
2232
2233static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2234{
2235 if (rtl_readphy(tp, reg) != val)
2236 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2237 else
2238 rtl_apply_firmware(tp);
françois romieuf1e02ed2011-01-13 13:07:53 +00002239}
2240
françois romieu4da19632011-01-03 15:07:55 +00002241static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002242{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002243 static const struct phy_reg phy_reg_init[] = {
françois romieu0b9b5712009-08-10 19:44:56 +00002244 { 0x1f, 0x0001 },
2245 { 0x06, 0x006e },
2246 { 0x08, 0x0708 },
2247 { 0x15, 0x4000 },
2248 { 0x18, 0x65c7 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002249
françois romieu0b9b5712009-08-10 19:44:56 +00002250 { 0x1f, 0x0001 },
2251 { 0x03, 0x00a1 },
2252 { 0x02, 0x0008 },
2253 { 0x01, 0x0120 },
2254 { 0x00, 0x1000 },
2255 { 0x04, 0x0800 },
2256 { 0x04, 0x0000 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002257
françois romieu0b9b5712009-08-10 19:44:56 +00002258 { 0x03, 0xff41 },
2259 { 0x02, 0xdf60 },
2260 { 0x01, 0x0140 },
2261 { 0x00, 0x0077 },
2262 { 0x04, 0x7800 },
2263 { 0x04, 0x7000 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002264
françois romieu0b9b5712009-08-10 19:44:56 +00002265 { 0x03, 0x802f },
2266 { 0x02, 0x4f02 },
2267 { 0x01, 0x0409 },
2268 { 0x00, 0xf0f9 },
2269 { 0x04, 0x9800 },
2270 { 0x04, 0x9000 },
2271
2272 { 0x03, 0xdf01 },
2273 { 0x02, 0xdf20 },
2274 { 0x01, 0xff95 },
2275 { 0x00, 0xba00 },
2276 { 0x04, 0xa800 },
2277 { 0x04, 0xa000 },
2278
2279 { 0x03, 0xff41 },
2280 { 0x02, 0xdf20 },
2281 { 0x01, 0x0140 },
2282 { 0x00, 0x00bb },
2283 { 0x04, 0xb800 },
2284 { 0x04, 0xb000 },
2285
2286 { 0x03, 0xdf41 },
2287 { 0x02, 0xdc60 },
2288 { 0x01, 0x6340 },
2289 { 0x00, 0x007d },
2290 { 0x04, 0xd800 },
2291 { 0x04, 0xd000 },
2292
2293 { 0x03, 0xdf01 },
2294 { 0x02, 0xdf20 },
2295 { 0x01, 0x100a },
2296 { 0x00, 0xa0ff },
2297 { 0x04, 0xf800 },
2298 { 0x04, 0xf000 },
2299
2300 { 0x1f, 0x0000 },
2301 { 0x0b, 0x0000 },
2302 { 0x00, 0x9200 }
2303 };
2304
françois romieu4da19632011-01-03 15:07:55 +00002305 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002306}
2307
françois romieu4da19632011-01-03 15:07:55 +00002308static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu5615d9f2007-08-17 17:50:46 +02002309{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002310 static const struct phy_reg phy_reg_init[] = {
Francois Romieua441d7b2007-08-17 18:26:35 +02002311 { 0x1f, 0x0002 },
2312 { 0x01, 0x90d0 },
2313 { 0x1f, 0x0000 }
2314 };
2315
françois romieu4da19632011-01-03 15:07:55 +00002316 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5615d9f2007-08-17 17:50:46 +02002317}
2318
françois romieu4da19632011-01-03 15:07:55 +00002319static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
françois romieu2e9558562009-08-10 19:44:19 +00002320{
2321 struct pci_dev *pdev = tp->pci_dev;
françois romieu2e9558562009-08-10 19:44:19 +00002322
Sergei Shtylyovccbae552011-07-22 05:37:24 +00002323 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2324 (pdev->subsystem_device != 0xe000))
françois romieu2e9558562009-08-10 19:44:19 +00002325 return;
2326
françois romieu4da19632011-01-03 15:07:55 +00002327 rtl_writephy(tp, 0x1f, 0x0001);
2328 rtl_writephy(tp, 0x10, 0xf01b);
2329 rtl_writephy(tp, 0x1f, 0x0000);
françois romieu2e9558562009-08-10 19:44:19 +00002330}
2331
françois romieu4da19632011-01-03 15:07:55 +00002332static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
françois romieu2e9558562009-08-10 19:44:19 +00002333{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002334 static const struct phy_reg phy_reg_init[] = {
françois romieu2e9558562009-08-10 19:44:19 +00002335 { 0x1f, 0x0001 },
2336 { 0x04, 0x0000 },
2337 { 0x03, 0x00a1 },
2338 { 0x02, 0x0008 },
2339 { 0x01, 0x0120 },
2340 { 0x00, 0x1000 },
2341 { 0x04, 0x0800 },
2342 { 0x04, 0x9000 },
2343 { 0x03, 0x802f },
2344 { 0x02, 0x4f02 },
2345 { 0x01, 0x0409 },
2346 { 0x00, 0xf099 },
2347 { 0x04, 0x9800 },
2348 { 0x04, 0xa000 },
2349 { 0x03, 0xdf01 },
2350 { 0x02, 0xdf20 },
2351 { 0x01, 0xff95 },
2352 { 0x00, 0xba00 },
2353 { 0x04, 0xa800 },
2354 { 0x04, 0xf000 },
2355 { 0x03, 0xdf01 },
2356 { 0x02, 0xdf20 },
2357 { 0x01, 0x101a },
2358 { 0x00, 0xa0ff },
2359 { 0x04, 0xf800 },
2360 { 0x04, 0x0000 },
2361 { 0x1f, 0x0000 },
2362
2363 { 0x1f, 0x0001 },
2364 { 0x10, 0xf41b },
2365 { 0x14, 0xfb54 },
2366 { 0x18, 0xf5c7 },
2367 { 0x1f, 0x0000 },
2368
2369 { 0x1f, 0x0001 },
2370 { 0x17, 0x0cc0 },
2371 { 0x1f, 0x0000 }
2372 };
2373
françois romieu4da19632011-01-03 15:07:55 +00002374 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieu2e9558562009-08-10 19:44:19 +00002375
françois romieu4da19632011-01-03 15:07:55 +00002376 rtl8169scd_hw_phy_config_quirk(tp);
françois romieu2e9558562009-08-10 19:44:19 +00002377}
2378
françois romieu4da19632011-01-03 15:07:55 +00002379static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
françois romieu8c7006a2009-08-10 19:43:29 +00002380{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002381 static const struct phy_reg phy_reg_init[] = {
françois romieu8c7006a2009-08-10 19:43:29 +00002382 { 0x1f, 0x0001 },
2383 { 0x04, 0x0000 },
2384 { 0x03, 0x00a1 },
2385 { 0x02, 0x0008 },
2386 { 0x01, 0x0120 },
2387 { 0x00, 0x1000 },
2388 { 0x04, 0x0800 },
2389 { 0x04, 0x9000 },
2390 { 0x03, 0x802f },
2391 { 0x02, 0x4f02 },
2392 { 0x01, 0x0409 },
2393 { 0x00, 0xf099 },
2394 { 0x04, 0x9800 },
2395 { 0x04, 0xa000 },
2396 { 0x03, 0xdf01 },
2397 { 0x02, 0xdf20 },
2398 { 0x01, 0xff95 },
2399 { 0x00, 0xba00 },
2400 { 0x04, 0xa800 },
2401 { 0x04, 0xf000 },
2402 { 0x03, 0xdf01 },
2403 { 0x02, 0xdf20 },
2404 { 0x01, 0x101a },
2405 { 0x00, 0xa0ff },
2406 { 0x04, 0xf800 },
2407 { 0x04, 0x0000 },
2408 { 0x1f, 0x0000 },
2409
2410 { 0x1f, 0x0001 },
2411 { 0x0b, 0x8480 },
2412 { 0x1f, 0x0000 },
2413
2414 { 0x1f, 0x0001 },
2415 { 0x18, 0x67c7 },
2416 { 0x04, 0x2000 },
2417 { 0x03, 0x002f },
2418 { 0x02, 0x4360 },
2419 { 0x01, 0x0109 },
2420 { 0x00, 0x3022 },
2421 { 0x04, 0x2800 },
2422 { 0x1f, 0x0000 },
2423
2424 { 0x1f, 0x0001 },
2425 { 0x17, 0x0cc0 },
2426 { 0x1f, 0x0000 }
2427 };
2428
françois romieu4da19632011-01-03 15:07:55 +00002429 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieu8c7006a2009-08-10 19:43:29 +00002430}
2431
françois romieu4da19632011-01-03 15:07:55 +00002432static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu236b8082008-05-30 16:11:48 +02002433{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002434 static const struct phy_reg phy_reg_init[] = {
Francois Romieu236b8082008-05-30 16:11:48 +02002435 { 0x10, 0xf41b },
2436 { 0x1f, 0x0000 }
2437 };
2438
françois romieu4da19632011-01-03 15:07:55 +00002439 rtl_writephy(tp, 0x1f, 0x0001);
2440 rtl_patchphy(tp, 0x16, 1 << 0);
Francois Romieu236b8082008-05-30 16:11:48 +02002441
françois romieu4da19632011-01-03 15:07:55 +00002442 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu236b8082008-05-30 16:11:48 +02002443}
2444
françois romieu4da19632011-01-03 15:07:55 +00002445static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu236b8082008-05-30 16:11:48 +02002446{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002447 static const struct phy_reg phy_reg_init[] = {
Francois Romieu236b8082008-05-30 16:11:48 +02002448 { 0x1f, 0x0001 },
2449 { 0x10, 0xf41b },
2450 { 0x1f, 0x0000 }
2451 };
2452
françois romieu4da19632011-01-03 15:07:55 +00002453 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu236b8082008-05-30 16:11:48 +02002454}
2455
françois romieu4da19632011-01-03 15:07:55 +00002456static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu867763c2007-08-17 18:21:58 +02002457{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002458 static const struct phy_reg phy_reg_init[] = {
Francois Romieu867763c2007-08-17 18:21:58 +02002459 { 0x1f, 0x0000 },
2460 { 0x1d, 0x0f00 },
2461 { 0x1f, 0x0002 },
2462 { 0x0c, 0x1ec8 },
2463 { 0x1f, 0x0000 }
2464 };
2465
françois romieu4da19632011-01-03 15:07:55 +00002466 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu867763c2007-08-17 18:21:58 +02002467}
2468
françois romieu4da19632011-01-03 15:07:55 +00002469static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
Francois Romieuef3386f2008-06-29 12:24:30 +02002470{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002471 static const struct phy_reg phy_reg_init[] = {
Francois Romieuef3386f2008-06-29 12:24:30 +02002472 { 0x1f, 0x0001 },
2473 { 0x1d, 0x3d98 },
2474 { 0x1f, 0x0000 }
2475 };
2476
françois romieu4da19632011-01-03 15:07:55 +00002477 rtl_writephy(tp, 0x1f, 0x0000);
2478 rtl_patchphy(tp, 0x14, 1 << 5);
2479 rtl_patchphy(tp, 0x0d, 1 << 5);
Francois Romieuef3386f2008-06-29 12:24:30 +02002480
françois romieu4da19632011-01-03 15:07:55 +00002481 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuef3386f2008-06-29 12:24:30 +02002482}
2483
françois romieu4da19632011-01-03 15:07:55 +00002484static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu867763c2007-08-17 18:21:58 +02002485{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002486 static const struct phy_reg phy_reg_init[] = {
Francois Romieua3f80672007-10-18 14:35:11 +02002487 { 0x1f, 0x0001 },
2488 { 0x12, 0x2300 },
Francois Romieu867763c2007-08-17 18:21:58 +02002489 { 0x1f, 0x0002 },
2490 { 0x00, 0x88d4 },
2491 { 0x01, 0x82b1 },
2492 { 0x03, 0x7002 },
2493 { 0x08, 0x9e30 },
2494 { 0x09, 0x01f0 },
2495 { 0x0a, 0x5500 },
2496 { 0x0c, 0x00c8 },
2497 { 0x1f, 0x0003 },
2498 { 0x12, 0xc096 },
2499 { 0x16, 0x000a },
Francois Romieuf50d4272008-05-30 16:07:07 +02002500 { 0x1f, 0x0000 },
2501 { 0x1f, 0x0000 },
2502 { 0x09, 0x2000 },
2503 { 0x09, 0x0000 }
Francois Romieu867763c2007-08-17 18:21:58 +02002504 };
2505
françois romieu4da19632011-01-03 15:07:55 +00002506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuf50d4272008-05-30 16:07:07 +02002507
françois romieu4da19632011-01-03 15:07:55 +00002508 rtl_patchphy(tp, 0x14, 1 << 5);
2509 rtl_patchphy(tp, 0x0d, 1 << 5);
2510 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu867763c2007-08-17 18:21:58 +02002511}
2512
françois romieu4da19632011-01-03 15:07:55 +00002513static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu7da97ec2007-10-18 15:20:43 +02002514{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002515 static const struct phy_reg phy_reg_init[] = {
Francois Romieuf50d4272008-05-30 16:07:07 +02002516 { 0x1f, 0x0001 },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002517 { 0x12, 0x2300 },
Francois Romieuf50d4272008-05-30 16:07:07 +02002518 { 0x03, 0x802f },
2519 { 0x02, 0x4f02 },
2520 { 0x01, 0x0409 },
2521 { 0x00, 0xf099 },
2522 { 0x04, 0x9800 },
2523 { 0x04, 0x9000 },
2524 { 0x1d, 0x3d98 },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002525 { 0x1f, 0x0002 },
2526 { 0x0c, 0x7eb8 },
Francois Romieuf50d4272008-05-30 16:07:07 +02002527 { 0x06, 0x0761 },
2528 { 0x1f, 0x0003 },
2529 { 0x16, 0x0f0a },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002530 { 0x1f, 0x0000 }
2531 };
2532
françois romieu4da19632011-01-03 15:07:55 +00002533 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuf50d4272008-05-30 16:07:07 +02002534
françois romieu4da19632011-01-03 15:07:55 +00002535 rtl_patchphy(tp, 0x16, 1 << 0);
2536 rtl_patchphy(tp, 0x14, 1 << 5);
2537 rtl_patchphy(tp, 0x0d, 1 << 5);
2538 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu7da97ec2007-10-18 15:20:43 +02002539}
2540
françois romieu4da19632011-01-03 15:07:55 +00002541static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu197ff762008-06-28 13:16:02 +02002542{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002543 static const struct phy_reg phy_reg_init[] = {
Francois Romieu197ff762008-06-28 13:16:02 +02002544 { 0x1f, 0x0001 },
2545 { 0x12, 0x2300 },
2546 { 0x1d, 0x3d98 },
2547 { 0x1f, 0x0002 },
2548 { 0x0c, 0x7eb8 },
2549 { 0x06, 0x5461 },
2550 { 0x1f, 0x0003 },
2551 { 0x16, 0x0f0a },
2552 { 0x1f, 0x0000 }
2553 };
2554
françois romieu4da19632011-01-03 15:07:55 +00002555 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu197ff762008-06-28 13:16:02 +02002556
françois romieu4da19632011-01-03 15:07:55 +00002557 rtl_patchphy(tp, 0x16, 1 << 0);
2558 rtl_patchphy(tp, 0x14, 1 << 5);
2559 rtl_patchphy(tp, 0x0d, 1 << 5);
2560 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu197ff762008-06-28 13:16:02 +02002561}
2562
françois romieu4da19632011-01-03 15:07:55 +00002563static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu6fb07052008-06-29 11:54:28 +02002564{
françois romieu4da19632011-01-03 15:07:55 +00002565 rtl8168c_3_hw_phy_config(tp);
Francois Romieu6fb07052008-06-29 11:54:28 +02002566}
2567
françois romieubca03d52011-01-03 15:07:31 +00002568static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu5b538df2008-07-20 16:22:45 +02002569{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002570 static const struct phy_reg phy_reg_init_0[] = {
françois romieubca03d52011-01-03 15:07:31 +00002571 /* Channel Estimation */
Francois Romieu5b538df2008-07-20 16:22:45 +02002572 { 0x1f, 0x0001 },
françois romieudaf9df62009-10-07 12:44:20 +00002573 { 0x06, 0x4064 },
2574 { 0x07, 0x2863 },
2575 { 0x08, 0x059c },
2576 { 0x09, 0x26b4 },
2577 { 0x0a, 0x6a19 },
2578 { 0x0b, 0xdcc8 },
2579 { 0x10, 0xf06d },
2580 { 0x14, 0x7f68 },
2581 { 0x18, 0x7fd9 },
2582 { 0x1c, 0xf0ff },
2583 { 0x1d, 0x3d9c },
Francois Romieu5b538df2008-07-20 16:22:45 +02002584 { 0x1f, 0x0003 },
françois romieudaf9df62009-10-07 12:44:20 +00002585 { 0x12, 0xf49f },
2586 { 0x13, 0x070b },
2587 { 0x1a, 0x05ad },
françois romieubca03d52011-01-03 15:07:31 +00002588 { 0x14, 0x94c0 },
2589
2590 /*
2591 * Tx Error Issue
Francois Romieucecb5fd2011-04-01 10:21:07 +02002592 * Enhance line driver power
françois romieubca03d52011-01-03 15:07:31 +00002593 */
Francois Romieu5b538df2008-07-20 16:22:45 +02002594 { 0x1f, 0x0002 },
françois romieudaf9df62009-10-07 12:44:20 +00002595 { 0x06, 0x5561 },
Francois Romieu5b538df2008-07-20 16:22:45 +02002596 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002597 { 0x05, 0x8332 },
françois romieubca03d52011-01-03 15:07:31 +00002598 { 0x06, 0x5561 },
2599
2600 /*
2601 * Can not link to 1Gbps with bad cable
2602 * Decrease SNR threshold form 21.07dB to 19.04dB
2603 */
2604 { 0x1f, 0x0001 },
2605 { 0x17, 0x0cc0 },
françois romieudaf9df62009-10-07 12:44:20 +00002606
2607 { 0x1f, 0x0000 },
françois romieubca03d52011-01-03 15:07:31 +00002608 { 0x0d, 0xf880 }
Francois Romieu5b538df2008-07-20 16:22:45 +02002609 };
françois romieubca03d52011-01-03 15:07:31 +00002610 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu5b538df2008-07-20 16:22:45 +02002611
françois romieu4da19632011-01-03 15:07:55 +00002612 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
Francois Romieu5b538df2008-07-20 16:22:45 +02002613
françois romieubca03d52011-01-03 15:07:31 +00002614 /*
2615 * Rx Error Issue
2616 * Fine Tune Switching regulator parameter
2617 */
françois romieu4da19632011-01-03 15:07:55 +00002618 rtl_writephy(tp, 0x1f, 0x0002);
2619 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2620 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
françois romieudaf9df62009-10-07 12:44:20 +00002621
françois romieudaf9df62009-10-07 12:44:20 +00002622 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002623 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002624 { 0x1f, 0x0002 },
2625 { 0x05, 0x669a },
Francois Romieu5b538df2008-07-20 16:22:45 +02002626 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002627 { 0x05, 0x8330 },
2628 { 0x06, 0x669a },
2629 { 0x1f, 0x0002 }
2630 };
2631 int val;
2632
françois romieu4da19632011-01-03 15:07:55 +00002633 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002634
françois romieu4da19632011-01-03 15:07:55 +00002635 val = rtl_readphy(tp, 0x0d);
françois romieudaf9df62009-10-07 12:44:20 +00002636
2637 if ((val & 0x00ff) != 0x006c) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002638 static const u32 set[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002639 0x0065, 0x0066, 0x0067, 0x0068,
2640 0x0069, 0x006a, 0x006b, 0x006c
2641 };
2642 int i;
2643
françois romieu4da19632011-01-03 15:07:55 +00002644 rtl_writephy(tp, 0x1f, 0x0002);
françois romieudaf9df62009-10-07 12:44:20 +00002645
2646 val &= 0xff00;
2647 for (i = 0; i < ARRAY_SIZE(set); i++)
françois romieu4da19632011-01-03 15:07:55 +00002648 rtl_writephy(tp, 0x0d, val | set[i]);
françois romieudaf9df62009-10-07 12:44:20 +00002649 }
2650 } else {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002651 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002652 { 0x1f, 0x0002 },
2653 { 0x05, 0x6662 },
Francois Romieu5b538df2008-07-20 16:22:45 +02002654 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002655 { 0x05, 0x8330 },
2656 { 0x06, 0x6662 }
Francois Romieu5b538df2008-07-20 16:22:45 +02002657 };
2658
françois romieu4da19632011-01-03 15:07:55 +00002659 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5b538df2008-07-20 16:22:45 +02002660 }
2661
françois romieubca03d52011-01-03 15:07:31 +00002662 /* RSET couple improve */
françois romieu4da19632011-01-03 15:07:55 +00002663 rtl_writephy(tp, 0x1f, 0x0002);
2664 rtl_patchphy(tp, 0x0d, 0x0300);
2665 rtl_patchphy(tp, 0x0f, 0x0010);
françois romieudaf9df62009-10-07 12:44:20 +00002666
françois romieubca03d52011-01-03 15:07:31 +00002667 /* Fine tune PLL performance */
françois romieu4da19632011-01-03 15:07:55 +00002668 rtl_writephy(tp, 0x1f, 0x0002);
2669 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2670 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
françois romieudaf9df62009-10-07 12:44:20 +00002671
françois romieu4da19632011-01-03 15:07:55 +00002672 rtl_writephy(tp, 0x1f, 0x0005);
2673 rtl_writephy(tp, 0x05, 0x001b);
François Romieu953a12c2011-04-24 17:38:48 +02002674
2675 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
françois romieubca03d52011-01-03 15:07:31 +00002676
françois romieu4da19632011-01-03 15:07:55 +00002677 rtl_writephy(tp, 0x1f, 0x0000);
françois romieudaf9df62009-10-07 12:44:20 +00002678}
2679
françois romieubca03d52011-01-03 15:07:31 +00002680static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
françois romieudaf9df62009-10-07 12:44:20 +00002681{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002682 static const struct phy_reg phy_reg_init_0[] = {
françois romieubca03d52011-01-03 15:07:31 +00002683 /* Channel Estimation */
françois romieudaf9df62009-10-07 12:44:20 +00002684 { 0x1f, 0x0001 },
2685 { 0x06, 0x4064 },
2686 { 0x07, 0x2863 },
2687 { 0x08, 0x059c },
2688 { 0x09, 0x26b4 },
2689 { 0x0a, 0x6a19 },
2690 { 0x0b, 0xdcc8 },
2691 { 0x10, 0xf06d },
2692 { 0x14, 0x7f68 },
2693 { 0x18, 0x7fd9 },
2694 { 0x1c, 0xf0ff },
2695 { 0x1d, 0x3d9c },
2696 { 0x1f, 0x0003 },
2697 { 0x12, 0xf49f },
2698 { 0x13, 0x070b },
2699 { 0x1a, 0x05ad },
2700 { 0x14, 0x94c0 },
2701
françois romieubca03d52011-01-03 15:07:31 +00002702 /*
2703 * Tx Error Issue
Francois Romieucecb5fd2011-04-01 10:21:07 +02002704 * Enhance line driver power
françois romieubca03d52011-01-03 15:07:31 +00002705 */
françois romieudaf9df62009-10-07 12:44:20 +00002706 { 0x1f, 0x0002 },
2707 { 0x06, 0x5561 },
2708 { 0x1f, 0x0005 },
2709 { 0x05, 0x8332 },
françois romieubca03d52011-01-03 15:07:31 +00002710 { 0x06, 0x5561 },
2711
2712 /*
2713 * Can not link to 1Gbps with bad cable
2714 * Decrease SNR threshold form 21.07dB to 19.04dB
2715 */
2716 { 0x1f, 0x0001 },
2717 { 0x17, 0x0cc0 },
françois romieudaf9df62009-10-07 12:44:20 +00002718
2719 { 0x1f, 0x0000 },
françois romieubca03d52011-01-03 15:07:31 +00002720 { 0x0d, 0xf880 }
françois romieudaf9df62009-10-07 12:44:20 +00002721 };
françois romieubca03d52011-01-03 15:07:31 +00002722 void __iomem *ioaddr = tp->mmio_addr;
françois romieudaf9df62009-10-07 12:44:20 +00002723
françois romieu4da19632011-01-03 15:07:55 +00002724 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
françois romieudaf9df62009-10-07 12:44:20 +00002725
2726 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002727 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002728 { 0x1f, 0x0002 },
2729 { 0x05, 0x669a },
2730 { 0x1f, 0x0005 },
2731 { 0x05, 0x8330 },
2732 { 0x06, 0x669a },
2733
2734 { 0x1f, 0x0002 }
2735 };
2736 int val;
2737
françois romieu4da19632011-01-03 15:07:55 +00002738 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002739
françois romieu4da19632011-01-03 15:07:55 +00002740 val = rtl_readphy(tp, 0x0d);
françois romieudaf9df62009-10-07 12:44:20 +00002741 if ((val & 0x00ff) != 0x006c) {
Joe Perchesb6bc7652010-12-21 02:16:08 -08002742 static const u32 set[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002743 0x0065, 0x0066, 0x0067, 0x0068,
2744 0x0069, 0x006a, 0x006b, 0x006c
2745 };
2746 int i;
2747
françois romieu4da19632011-01-03 15:07:55 +00002748 rtl_writephy(tp, 0x1f, 0x0002);
françois romieudaf9df62009-10-07 12:44:20 +00002749
2750 val &= 0xff00;
2751 for (i = 0; i < ARRAY_SIZE(set); i++)
françois romieu4da19632011-01-03 15:07:55 +00002752 rtl_writephy(tp, 0x0d, val | set[i]);
françois romieudaf9df62009-10-07 12:44:20 +00002753 }
2754 } else {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002755 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002756 { 0x1f, 0x0002 },
2757 { 0x05, 0x2642 },
2758 { 0x1f, 0x0005 },
2759 { 0x05, 0x8330 },
2760 { 0x06, 0x2642 }
2761 };
2762
françois romieu4da19632011-01-03 15:07:55 +00002763 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002764 }
2765
françois romieubca03d52011-01-03 15:07:31 +00002766 /* Fine tune PLL performance */
françois romieu4da19632011-01-03 15:07:55 +00002767 rtl_writephy(tp, 0x1f, 0x0002);
2768 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2769 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
françois romieudaf9df62009-10-07 12:44:20 +00002770
françois romieubca03d52011-01-03 15:07:31 +00002771 /* Switching regulator Slew rate */
françois romieu4da19632011-01-03 15:07:55 +00002772 rtl_writephy(tp, 0x1f, 0x0002);
2773 rtl_patchphy(tp, 0x0f, 0x0017);
françois romieudaf9df62009-10-07 12:44:20 +00002774
françois romieu4da19632011-01-03 15:07:55 +00002775 rtl_writephy(tp, 0x1f, 0x0005);
2776 rtl_writephy(tp, 0x05, 0x001b);
François Romieu953a12c2011-04-24 17:38:48 +02002777
2778 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
françois romieubca03d52011-01-03 15:07:31 +00002779
françois romieu4da19632011-01-03 15:07:55 +00002780 rtl_writephy(tp, 0x1f, 0x0000);
françois romieudaf9df62009-10-07 12:44:20 +00002781}
2782
françois romieu4da19632011-01-03 15:07:55 +00002783static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
françois romieudaf9df62009-10-07 12:44:20 +00002784{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002785 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002786 { 0x1f, 0x0002 },
2787 { 0x10, 0x0008 },
2788 { 0x0d, 0x006c },
2789
2790 { 0x1f, 0x0000 },
2791 { 0x0d, 0xf880 },
2792
2793 { 0x1f, 0x0001 },
2794 { 0x17, 0x0cc0 },
2795
2796 { 0x1f, 0x0001 },
2797 { 0x0b, 0xa4d8 },
2798 { 0x09, 0x281c },
2799 { 0x07, 0x2883 },
2800 { 0x0a, 0x6b35 },
2801 { 0x1d, 0x3da4 },
2802 { 0x1c, 0xeffd },
2803 { 0x14, 0x7f52 },
2804 { 0x18, 0x7fc6 },
2805 { 0x08, 0x0601 },
2806 { 0x06, 0x4063 },
2807 { 0x10, 0xf074 },
2808 { 0x1f, 0x0003 },
2809 { 0x13, 0x0789 },
2810 { 0x12, 0xf4bd },
2811 { 0x1a, 0x04fd },
2812 { 0x14, 0x84b0 },
2813 { 0x1f, 0x0000 },
2814 { 0x00, 0x9200 },
2815
2816 { 0x1f, 0x0005 },
2817 { 0x01, 0x0340 },
2818 { 0x1f, 0x0001 },
2819 { 0x04, 0x4000 },
2820 { 0x03, 0x1d21 },
2821 { 0x02, 0x0c32 },
2822 { 0x01, 0x0200 },
2823 { 0x00, 0x5554 },
2824 { 0x04, 0x4800 },
2825 { 0x04, 0x4000 },
2826 { 0x04, 0xf000 },
2827 { 0x03, 0xdf01 },
2828 { 0x02, 0xdf20 },
2829 { 0x01, 0x101a },
2830 { 0x00, 0xa0ff },
2831 { 0x04, 0xf800 },
2832 { 0x04, 0xf000 },
2833 { 0x1f, 0x0000 },
2834
2835 { 0x1f, 0x0007 },
2836 { 0x1e, 0x0023 },
2837 { 0x16, 0x0000 },
2838 { 0x1f, 0x0000 }
2839 };
2840
françois romieu4da19632011-01-03 15:07:55 +00002841 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5b538df2008-07-20 16:22:45 +02002842}
2843
françois romieue6de30d2011-01-03 15:08:37 +00002844static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2845{
2846 static const struct phy_reg phy_reg_init[] = {
2847 { 0x1f, 0x0001 },
2848 { 0x17, 0x0cc0 },
2849
2850 { 0x1f, 0x0007 },
2851 { 0x1e, 0x002d },
2852 { 0x18, 0x0040 },
2853 { 0x1f, 0x0000 }
2854 };
2855
2856 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857 rtl_patchphy(tp, 0x0d, 1 << 5);
2858}
2859
Hayes Wang70090422011-07-06 15:58:06 +08002860static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
hayeswang01dc7fe2011-03-21 01:50:28 +00002861{
2862 static const struct phy_reg phy_reg_init[] = {
2863 /* Enable Delay cap */
2864 { 0x1f, 0x0005 },
2865 { 0x05, 0x8b80 },
2866 { 0x06, 0xc896 },
2867 { 0x1f, 0x0000 },
2868
2869 /* Channel estimation fine tune */
2870 { 0x1f, 0x0001 },
2871 { 0x0b, 0x6c20 },
2872 { 0x07, 0x2872 },
2873 { 0x1c, 0xefff },
2874 { 0x1f, 0x0003 },
2875 { 0x14, 0x6420 },
2876 { 0x1f, 0x0000 },
2877
2878 /* Update PFM & 10M TX idle timer */
2879 { 0x1f, 0x0007 },
2880 { 0x1e, 0x002f },
2881 { 0x15, 0x1919 },
2882 { 0x1f, 0x0000 },
2883
2884 { 0x1f, 0x0007 },
2885 { 0x1e, 0x00ac },
2886 { 0x18, 0x0006 },
2887 { 0x1f, 0x0000 }
2888 };
2889
Francois Romieu15ecd032011-04-27 13:52:22 -07002890 rtl_apply_firmware(tp);
2891
hayeswang01dc7fe2011-03-21 01:50:28 +00002892 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2893
2894 /* DCO enable for 10M IDLE Power */
2895 rtl_writephy(tp, 0x1f, 0x0007);
2896 rtl_writephy(tp, 0x1e, 0x0023);
2897 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2898 rtl_writephy(tp, 0x1f, 0x0000);
2899
2900 /* For impedance matching */
2901 rtl_writephy(tp, 0x1f, 0x0002);
2902 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
Francois Romieucecb5fd2011-04-01 10:21:07 +02002903 rtl_writephy(tp, 0x1f, 0x0000);
hayeswang01dc7fe2011-03-21 01:50:28 +00002904
2905 /* PHY auto speed down */
2906 rtl_writephy(tp, 0x1f, 0x0007);
2907 rtl_writephy(tp, 0x1e, 0x002d);
2908 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2909 rtl_writephy(tp, 0x1f, 0x0000);
2910 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2911
2912 rtl_writephy(tp, 0x1f, 0x0005);
2913 rtl_writephy(tp, 0x05, 0x8b86);
2914 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2915 rtl_writephy(tp, 0x1f, 0x0000);
2916
2917 rtl_writephy(tp, 0x1f, 0x0005);
2918 rtl_writephy(tp, 0x05, 0x8b85);
2919 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2920 rtl_writephy(tp, 0x1f, 0x0007);
2921 rtl_writephy(tp, 0x1e, 0x0020);
2922 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2923 rtl_writephy(tp, 0x1f, 0x0006);
2924 rtl_writephy(tp, 0x00, 0x5a00);
2925 rtl_writephy(tp, 0x1f, 0x0000);
2926 rtl_writephy(tp, 0x0d, 0x0007);
2927 rtl_writephy(tp, 0x0e, 0x003c);
2928 rtl_writephy(tp, 0x0d, 0x4007);
2929 rtl_writephy(tp, 0x0e, 0x0000);
2930 rtl_writephy(tp, 0x0d, 0x0000);
2931}
2932
Hayes Wang70090422011-07-06 15:58:06 +08002933static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2934{
2935 static const struct phy_reg phy_reg_init[] = {
2936 /* Enable Delay cap */
2937 { 0x1f, 0x0004 },
2938 { 0x1f, 0x0007 },
2939 { 0x1e, 0x00ac },
2940 { 0x18, 0x0006 },
2941 { 0x1f, 0x0002 },
2942 { 0x1f, 0x0000 },
2943 { 0x1f, 0x0000 },
2944
2945 /* Channel estimation fine tune */
2946 { 0x1f, 0x0003 },
2947 { 0x09, 0xa20f },
2948 { 0x1f, 0x0000 },
2949 { 0x1f, 0x0000 },
2950
2951 /* Green Setting */
2952 { 0x1f, 0x0005 },
2953 { 0x05, 0x8b5b },
2954 { 0x06, 0x9222 },
2955 { 0x05, 0x8b6d },
2956 { 0x06, 0x8000 },
2957 { 0x05, 0x8b76 },
2958 { 0x06, 0x8000 },
2959 { 0x1f, 0x0000 }
2960 };
2961
2962 rtl_apply_firmware(tp);
2963
2964 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2965
2966 /* For 4-corner performance improve */
2967 rtl_writephy(tp, 0x1f, 0x0005);
2968 rtl_writephy(tp, 0x05, 0x8b80);
2969 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2970 rtl_writephy(tp, 0x1f, 0x0000);
2971
2972 /* PHY auto speed down */
2973 rtl_writephy(tp, 0x1f, 0x0004);
2974 rtl_writephy(tp, 0x1f, 0x0007);
2975 rtl_writephy(tp, 0x1e, 0x002d);
2976 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2977 rtl_writephy(tp, 0x1f, 0x0002);
2978 rtl_writephy(tp, 0x1f, 0x0000);
2979 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2980
2981 /* improve 10M EEE waveform */
2982 rtl_writephy(tp, 0x1f, 0x0005);
2983 rtl_writephy(tp, 0x05, 0x8b86);
2984 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2985 rtl_writephy(tp, 0x1f, 0x0000);
2986
2987 /* Improve 2-pair detection performance */
2988 rtl_writephy(tp, 0x1f, 0x0005);
2989 rtl_writephy(tp, 0x05, 0x8b85);
2990 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2991 rtl_writephy(tp, 0x1f, 0x0000);
2992
2993 /* EEE setting */
2994 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2995 ERIAR_EXGMAC);
2996 rtl_writephy(tp, 0x1f, 0x0005);
2997 rtl_writephy(tp, 0x05, 0x8b85);
2998 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2999 rtl_writephy(tp, 0x1f, 0x0004);
3000 rtl_writephy(tp, 0x1f, 0x0007);
3001 rtl_writephy(tp, 0x1e, 0x0020);
David S. Miller1805b2f2011-10-24 18:18:09 -04003002 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
Hayes Wang70090422011-07-06 15:58:06 +08003003 rtl_writephy(tp, 0x1f, 0x0002);
3004 rtl_writephy(tp, 0x1f, 0x0000);
3005 rtl_writephy(tp, 0x0d, 0x0007);
3006 rtl_writephy(tp, 0x0e, 0x003c);
3007 rtl_writephy(tp, 0x0d, 0x4007);
3008 rtl_writephy(tp, 0x0e, 0x0000);
3009 rtl_writephy(tp, 0x0d, 0x0000);
3010
3011 /* Green feature */
3012 rtl_writephy(tp, 0x1f, 0x0003);
3013 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3014 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3015 rtl_writephy(tp, 0x1f, 0x0000);
3016}
3017
Hayes Wangc2218922011-09-06 16:55:18 +08003018static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3019{
3020 static const struct phy_reg phy_reg_init[] = {
3021 /* Channel estimation fine tune */
3022 { 0x1f, 0x0003 },
3023 { 0x09, 0xa20f },
3024 { 0x1f, 0x0000 },
3025
3026 /* Modify green table for giga & fnet */
3027 { 0x1f, 0x0005 },
3028 { 0x05, 0x8b55 },
3029 { 0x06, 0x0000 },
3030 { 0x05, 0x8b5e },
3031 { 0x06, 0x0000 },
3032 { 0x05, 0x8b67 },
3033 { 0x06, 0x0000 },
3034 { 0x05, 0x8b70 },
3035 { 0x06, 0x0000 },
3036 { 0x1f, 0x0000 },
3037 { 0x1f, 0x0007 },
3038 { 0x1e, 0x0078 },
3039 { 0x17, 0x0000 },
3040 { 0x19, 0x00fb },
3041 { 0x1f, 0x0000 },
3042
3043 /* Modify green table for 10M */
3044 { 0x1f, 0x0005 },
3045 { 0x05, 0x8b79 },
3046 { 0x06, 0xaa00 },
3047 { 0x1f, 0x0000 },
3048
3049 /* Disable hiimpedance detection (RTCT) */
3050 { 0x1f, 0x0003 },
3051 { 0x01, 0x328a },
3052 { 0x1f, 0x0000 }
3053 };
3054
3055 rtl_apply_firmware(tp);
3056
3057 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3058
3059 /* For 4-corner performance improve */
3060 rtl_writephy(tp, 0x1f, 0x0005);
3061 rtl_writephy(tp, 0x05, 0x8b80);
3062 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3063 rtl_writephy(tp, 0x1f, 0x0000);
3064
3065 /* PHY auto speed down */
3066 rtl_writephy(tp, 0x1f, 0x0007);
3067 rtl_writephy(tp, 0x1e, 0x002d);
3068 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3069 rtl_writephy(tp, 0x1f, 0x0000);
3070 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3071
3072 /* Improve 10M EEE waveform */
3073 rtl_writephy(tp, 0x1f, 0x0005);
3074 rtl_writephy(tp, 0x05, 0x8b86);
3075 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3076 rtl_writephy(tp, 0x1f, 0x0000);
3077
3078 /* Improve 2-pair detection performance */
3079 rtl_writephy(tp, 0x1f, 0x0005);
3080 rtl_writephy(tp, 0x05, 0x8b85);
3081 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3082 rtl_writephy(tp, 0x1f, 0x0000);
3083}
3084
3085static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3086{
3087 rtl_apply_firmware(tp);
3088
3089 /* For 4-corner performance improve */
3090 rtl_writephy(tp, 0x1f, 0x0005);
3091 rtl_writephy(tp, 0x05, 0x8b80);
3092 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3093 rtl_writephy(tp, 0x1f, 0x0000);
3094
3095 /* PHY auto speed down */
3096 rtl_writephy(tp, 0x1f, 0x0007);
3097 rtl_writephy(tp, 0x1e, 0x002d);
3098 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3099 rtl_writephy(tp, 0x1f, 0x0000);
3100 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3101
3102 /* Improve 10M EEE waveform */
3103 rtl_writephy(tp, 0x1f, 0x0005);
3104 rtl_writephy(tp, 0x05, 0x8b86);
3105 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3106 rtl_writephy(tp, 0x1f, 0x0000);
3107}
3108
françois romieu4da19632011-01-03 15:07:55 +00003109static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu2857ffb2008-08-02 21:08:49 +02003110{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003111 static const struct phy_reg phy_reg_init[] = {
Francois Romieu2857ffb2008-08-02 21:08:49 +02003112 { 0x1f, 0x0003 },
3113 { 0x08, 0x441d },
3114 { 0x01, 0x9100 },
3115 { 0x1f, 0x0000 }
3116 };
3117
françois romieu4da19632011-01-03 15:07:55 +00003118 rtl_writephy(tp, 0x1f, 0x0000);
3119 rtl_patchphy(tp, 0x11, 1 << 12);
3120 rtl_patchphy(tp, 0x19, 1 << 13);
3121 rtl_patchphy(tp, 0x10, 1 << 15);
Francois Romieu2857ffb2008-08-02 21:08:49 +02003122
françois romieu4da19632011-01-03 15:07:55 +00003123 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu2857ffb2008-08-02 21:08:49 +02003124}
3125
Hayes Wang5a5e4442011-02-22 17:26:21 +08003126static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3127{
3128 static const struct phy_reg phy_reg_init[] = {
3129 { 0x1f, 0x0005 },
3130 { 0x1a, 0x0000 },
3131 { 0x1f, 0x0000 },
3132
3133 { 0x1f, 0x0004 },
3134 { 0x1c, 0x0000 },
3135 { 0x1f, 0x0000 },
3136
3137 { 0x1f, 0x0001 },
3138 { 0x15, 0x7701 },
3139 { 0x1f, 0x0000 }
3140 };
3141
3142 /* Disable ALDPS before ram code */
3143 rtl_writephy(tp, 0x1f, 0x0000);
3144 rtl_writephy(tp, 0x18, 0x0310);
3145 msleep(100);
3146
François Romieu953a12c2011-04-24 17:38:48 +02003147 rtl_apply_firmware(tp);
Hayes Wang5a5e4442011-02-22 17:26:21 +08003148
3149 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3150}
3151
Francois Romieu5615d9f2007-08-17 17:50:46 +02003152static void rtl_hw_phy_config(struct net_device *dev)
3153{
3154 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieu5615d9f2007-08-17 17:50:46 +02003155
3156 rtl8169_print_mac_version(tp);
3157
3158 switch (tp->mac_version) {
3159 case RTL_GIGA_MAC_VER_01:
3160 break;
3161 case RTL_GIGA_MAC_VER_02:
3162 case RTL_GIGA_MAC_VER_03:
françois romieu4da19632011-01-03 15:07:55 +00003163 rtl8169s_hw_phy_config(tp);
Francois Romieu5615d9f2007-08-17 17:50:46 +02003164 break;
3165 case RTL_GIGA_MAC_VER_04:
françois romieu4da19632011-01-03 15:07:55 +00003166 rtl8169sb_hw_phy_config(tp);
Francois Romieu5615d9f2007-08-17 17:50:46 +02003167 break;
françois romieu2e9558562009-08-10 19:44:19 +00003168 case RTL_GIGA_MAC_VER_05:
françois romieu4da19632011-01-03 15:07:55 +00003169 rtl8169scd_hw_phy_config(tp);
françois romieu2e9558562009-08-10 19:44:19 +00003170 break;
françois romieu8c7006a2009-08-10 19:43:29 +00003171 case RTL_GIGA_MAC_VER_06:
françois romieu4da19632011-01-03 15:07:55 +00003172 rtl8169sce_hw_phy_config(tp);
françois romieu8c7006a2009-08-10 19:43:29 +00003173 break;
Francois Romieu2857ffb2008-08-02 21:08:49 +02003174 case RTL_GIGA_MAC_VER_07:
3175 case RTL_GIGA_MAC_VER_08:
3176 case RTL_GIGA_MAC_VER_09:
françois romieu4da19632011-01-03 15:07:55 +00003177 rtl8102e_hw_phy_config(tp);
Francois Romieu2857ffb2008-08-02 21:08:49 +02003178 break;
Francois Romieu236b8082008-05-30 16:11:48 +02003179 case RTL_GIGA_MAC_VER_11:
françois romieu4da19632011-01-03 15:07:55 +00003180 rtl8168bb_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02003181 break;
3182 case RTL_GIGA_MAC_VER_12:
françois romieu4da19632011-01-03 15:07:55 +00003183 rtl8168bef_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02003184 break;
3185 case RTL_GIGA_MAC_VER_17:
françois romieu4da19632011-01-03 15:07:55 +00003186 rtl8168bef_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02003187 break;
Francois Romieu867763c2007-08-17 18:21:58 +02003188 case RTL_GIGA_MAC_VER_18:
françois romieu4da19632011-01-03 15:07:55 +00003189 rtl8168cp_1_hw_phy_config(tp);
Francois Romieu867763c2007-08-17 18:21:58 +02003190 break;
3191 case RTL_GIGA_MAC_VER_19:
françois romieu4da19632011-01-03 15:07:55 +00003192 rtl8168c_1_hw_phy_config(tp);
Francois Romieu867763c2007-08-17 18:21:58 +02003193 break;
Francois Romieu7da97ec2007-10-18 15:20:43 +02003194 case RTL_GIGA_MAC_VER_20:
françois romieu4da19632011-01-03 15:07:55 +00003195 rtl8168c_2_hw_phy_config(tp);
Francois Romieu7da97ec2007-10-18 15:20:43 +02003196 break;
Francois Romieu197ff762008-06-28 13:16:02 +02003197 case RTL_GIGA_MAC_VER_21:
françois romieu4da19632011-01-03 15:07:55 +00003198 rtl8168c_3_hw_phy_config(tp);
Francois Romieu197ff762008-06-28 13:16:02 +02003199 break;
Francois Romieu6fb07052008-06-29 11:54:28 +02003200 case RTL_GIGA_MAC_VER_22:
françois romieu4da19632011-01-03 15:07:55 +00003201 rtl8168c_4_hw_phy_config(tp);
Francois Romieu6fb07052008-06-29 11:54:28 +02003202 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02003203 case RTL_GIGA_MAC_VER_23:
Francois Romieu7f3e3d32008-07-20 18:53:20 +02003204 case RTL_GIGA_MAC_VER_24:
françois romieu4da19632011-01-03 15:07:55 +00003205 rtl8168cp_2_hw_phy_config(tp);
Francois Romieuef3386f2008-06-29 12:24:30 +02003206 break;
Francois Romieu5b538df2008-07-20 16:22:45 +02003207 case RTL_GIGA_MAC_VER_25:
françois romieubca03d52011-01-03 15:07:31 +00003208 rtl8168d_1_hw_phy_config(tp);
françois romieudaf9df62009-10-07 12:44:20 +00003209 break;
3210 case RTL_GIGA_MAC_VER_26:
françois romieubca03d52011-01-03 15:07:31 +00003211 rtl8168d_2_hw_phy_config(tp);
françois romieudaf9df62009-10-07 12:44:20 +00003212 break;
3213 case RTL_GIGA_MAC_VER_27:
françois romieu4da19632011-01-03 15:07:55 +00003214 rtl8168d_3_hw_phy_config(tp);
Francois Romieu5b538df2008-07-20 16:22:45 +02003215 break;
françois romieue6de30d2011-01-03 15:08:37 +00003216 case RTL_GIGA_MAC_VER_28:
3217 rtl8168d_4_hw_phy_config(tp);
3218 break;
Hayes Wang5a5e4442011-02-22 17:26:21 +08003219 case RTL_GIGA_MAC_VER_29:
3220 case RTL_GIGA_MAC_VER_30:
3221 rtl8105e_hw_phy_config(tp);
3222 break;
Francois Romieucecb5fd2011-04-01 10:21:07 +02003223 case RTL_GIGA_MAC_VER_31:
3224 /* None. */
3225 break;
hayeswang01dc7fe2011-03-21 01:50:28 +00003226 case RTL_GIGA_MAC_VER_32:
hayeswang01dc7fe2011-03-21 01:50:28 +00003227 case RTL_GIGA_MAC_VER_33:
Hayes Wang70090422011-07-06 15:58:06 +08003228 rtl8168e_1_hw_phy_config(tp);
3229 break;
3230 case RTL_GIGA_MAC_VER_34:
3231 rtl8168e_2_hw_phy_config(tp);
hayeswang01dc7fe2011-03-21 01:50:28 +00003232 break;
Hayes Wangc2218922011-09-06 16:55:18 +08003233 case RTL_GIGA_MAC_VER_35:
3234 rtl8168f_1_hw_phy_config(tp);
3235 break;
3236 case RTL_GIGA_MAC_VER_36:
3237 rtl8168f_2_hw_phy_config(tp);
3238 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02003239
Francois Romieu5615d9f2007-08-17 17:50:46 +02003240 default:
3241 break;
3242 }
3243}
3244
Francois Romieuda78dbf2012-01-26 14:18:23 +01003245static void rtl_phy_work(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003246{
Linus Torvalds1da177e2005-04-16 15:20:36 -07003247 struct timer_list *timer = &tp->timer;
3248 void __iomem *ioaddr = tp->mmio_addr;
3249 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3250
Francois Romieubcf0bf92006-07-26 23:14:13 +02003251 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003252
françois romieu4da19632011-01-03 15:07:55 +00003253 if (tp->phy_reset_pending(tp)) {
Francois Romieu5b0384f2006-08-16 16:00:01 +02003254 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003255 * A busy loop could burn quite a few cycles on nowadays CPU.
3256 * Let's delay the execution of the timer for a few ticks.
3257 */
3258 timeout = HZ/10;
3259 goto out_mod_timer;
3260 }
3261
3262 if (tp->link_ok(ioaddr))
Francois Romieuda78dbf2012-01-26 14:18:23 +01003263 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003264
Francois Romieuda78dbf2012-01-26 14:18:23 +01003265 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003266
françois romieu4da19632011-01-03 15:07:55 +00003267 tp->phy_reset_enable(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003268
3269out_mod_timer:
3270 mod_timer(timer, jiffies + timeout);
Francois Romieuda78dbf2012-01-26 14:18:23 +01003271}
3272
3273static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3274{
Francois Romieuda78dbf2012-01-26 14:18:23 +01003275 if (!test_and_set_bit(flag, tp->wk.flags))
3276 schedule_work(&tp->wk.work);
Francois Romieuda78dbf2012-01-26 14:18:23 +01003277}
3278
3279static void rtl8169_phy_timer(unsigned long __opaque)
3280{
3281 struct net_device *dev = (struct net_device *)__opaque;
3282 struct rtl8169_private *tp = netdev_priv(dev);
3283
Francois Romieu98ddf982012-01-31 10:47:34 +01003284 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003285}
3286
Linus Torvalds1da177e2005-04-16 15:20:36 -07003287static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3288 void __iomem *ioaddr)
3289{
3290 iounmap(ioaddr);
3291 pci_release_regions(pdev);
françois romieu87aeec72010-04-26 11:42:06 +00003292 pci_clear_mwi(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003293 pci_disable_device(pdev);
3294 free_netdev(dev);
3295}
3296
Francois Romieubf793292006-11-01 00:53:05 +01003297static void rtl8169_phy_reset(struct net_device *dev,
3298 struct rtl8169_private *tp)
3299{
Francois Romieu07d3f512007-02-21 22:40:46 +01003300 unsigned int i;
Francois Romieubf793292006-11-01 00:53:05 +01003301
françois romieu4da19632011-01-03 15:07:55 +00003302 tp->phy_reset_enable(tp);
Francois Romieubf793292006-11-01 00:53:05 +01003303 for (i = 0; i < 100; i++) {
françois romieu4da19632011-01-03 15:07:55 +00003304 if (!tp->phy_reset_pending(tp))
Francois Romieubf793292006-11-01 00:53:05 +01003305 return;
3306 msleep(1);
3307 }
Joe Perchesbf82c182010-02-09 11:49:50 +00003308 netif_err(tp, link, dev, "PHY reset failed\n");
Francois Romieubf793292006-11-01 00:53:05 +01003309}
3310
David S. Miller8decf862011-09-22 03:23:13 -04003311static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3312{
3313 void __iomem *ioaddr = tp->mmio_addr;
3314
3315 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3316 (RTL_R8(PHYstatus) & TBI_Enable);
3317}
3318
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003319static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003320{
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003321 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003322
Francois Romieu5615d9f2007-08-17 17:50:46 +02003323 rtl_hw_phy_config(dev);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003324
Marcus Sundberg773328942008-07-10 21:28:08 +02003325 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3326 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3327 RTL_W8(0x82, 0x01);
3328 }
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003329
Francois Romieu6dccd162007-02-13 23:38:05 +01003330 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3331
3332 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3333 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003334
Francois Romieubcf0bf92006-07-26 23:14:13 +02003335 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003336 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3337 RTL_W8(0x82, 0x01);
3338 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
françois romieu4da19632011-01-03 15:07:55 +00003339 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003340 }
3341
Francois Romieubf793292006-11-01 00:53:05 +01003342 rtl8169_phy_reset(dev, tp);
3343
Oliver Neukum54405cd2011-01-06 21:55:13 +01003344 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
Francois Romieucecb5fd2011-04-01 10:21:07 +02003345 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3346 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3347 (tp->mii.supports_gmii ?
3348 ADVERTISED_1000baseT_Half |
3349 ADVERTISED_1000baseT_Full : 0));
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003350
David S. Miller8decf862011-09-22 03:23:13 -04003351 if (rtl_tbi_enabled(tp))
Joe Perchesbf82c182010-02-09 11:49:50 +00003352 netif_info(tp, link, dev, "TBI auto-negotiating\n");
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003353}
3354
Francois Romieu773d2022007-01-31 23:47:43 +01003355static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3356{
3357 void __iomem *ioaddr = tp->mmio_addr;
3358 u32 high;
3359 u32 low;
3360
3361 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3362 high = addr[4] | (addr[5] << 8);
3363
Francois Romieuda78dbf2012-01-26 14:18:23 +01003364 rtl_lock_work(tp);
Francois Romieu773d2022007-01-31 23:47:43 +01003365
3366 RTL_W8(Cfg9346, Cfg9346_Unlock);
françois romieu908ba2b2010-04-26 11:42:58 +00003367
Francois Romieu773d2022007-01-31 23:47:43 +01003368 RTL_W32(MAC4, high);
françois romieu908ba2b2010-04-26 11:42:58 +00003369 RTL_R32(MAC4);
3370
Francois Romieu78f1cd02010-03-27 19:35:46 -07003371 RTL_W32(MAC0, low);
françois romieu908ba2b2010-04-26 11:42:58 +00003372 RTL_R32(MAC0);
3373
françois romieuc28aa382011-08-02 03:53:43 +00003374 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3375 const struct exgmac_reg e[] = {
3376 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3377 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3378 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3379 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3380 low >> 16 },
3381 };
3382
3383 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3384 }
3385
Francois Romieu773d2022007-01-31 23:47:43 +01003386 RTL_W8(Cfg9346, Cfg9346_Lock);
3387
Francois Romieuda78dbf2012-01-26 14:18:23 +01003388 rtl_unlock_work(tp);
Francois Romieu773d2022007-01-31 23:47:43 +01003389}
3390
3391static int rtl_set_mac_address(struct net_device *dev, void *p)
3392{
3393 struct rtl8169_private *tp = netdev_priv(dev);
3394 struct sockaddr *addr = p;
3395
3396 if (!is_valid_ether_addr(addr->sa_data))
3397 return -EADDRNOTAVAIL;
3398
3399 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3400
3401 rtl_rar_set(tp, dev->dev_addr);
3402
3403 return 0;
3404}
3405
Francois Romieu5f787a12006-08-17 13:02:36 +02003406static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3407{
3408 struct rtl8169_private *tp = netdev_priv(dev);
3409 struct mii_ioctl_data *data = if_mii(ifr);
3410
Francois Romieu8b4ab282008-11-19 22:05:25 -08003411 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3412}
Francois Romieu5f787a12006-08-17 13:02:36 +02003413
Francois Romieucecb5fd2011-04-01 10:21:07 +02003414static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3415 struct mii_ioctl_data *data, int cmd)
Francois Romieu8b4ab282008-11-19 22:05:25 -08003416{
Francois Romieu5f787a12006-08-17 13:02:36 +02003417 switch (cmd) {
3418 case SIOCGMIIPHY:
3419 data->phy_id = 32; /* Internal PHY */
3420 return 0;
3421
3422 case SIOCGMIIREG:
françois romieu4da19632011-01-03 15:07:55 +00003423 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
Francois Romieu5f787a12006-08-17 13:02:36 +02003424 return 0;
3425
3426 case SIOCSMIIREG:
françois romieu4da19632011-01-03 15:07:55 +00003427 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
Francois Romieu5f787a12006-08-17 13:02:36 +02003428 return 0;
3429 }
3430 return -EOPNOTSUPP;
3431}
3432
Francois Romieu8b4ab282008-11-19 22:05:25 -08003433static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3434{
3435 return -EOPNOTSUPP;
3436}
3437
Francois Romieufbac58f2007-10-04 22:51:38 +02003438static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3439{
3440 if (tp->features & RTL_FEATURE_MSI) {
3441 pci_disable_msi(pdev);
3442 tp->features &= ~RTL_FEATURE_MSI;
3443 }
3444}
3445
françois romieuc0e45c12011-01-03 15:08:04 +00003446static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3447{
3448 struct mdio_ops *ops = &tp->mdio_ops;
3449
3450 switch (tp->mac_version) {
3451 case RTL_GIGA_MAC_VER_27:
3452 ops->write = r8168dp_1_mdio_write;
3453 ops->read = r8168dp_1_mdio_read;
3454 break;
françois romieue6de30d2011-01-03 15:08:37 +00003455 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003456 case RTL_GIGA_MAC_VER_31:
françois romieue6de30d2011-01-03 15:08:37 +00003457 ops->write = r8168dp_2_mdio_write;
3458 ops->read = r8168dp_2_mdio_read;
3459 break;
françois romieuc0e45c12011-01-03 15:08:04 +00003460 default:
3461 ops->write = r8169_mdio_write;
3462 ops->read = r8169_mdio_read;
3463 break;
3464 }
3465}
3466
David S. Miller1805b2f2011-10-24 18:18:09 -04003467static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3468{
3469 void __iomem *ioaddr = tp->mmio_addr;
3470
3471 switch (tp->mac_version) {
3472 case RTL_GIGA_MAC_VER_29:
3473 case RTL_GIGA_MAC_VER_30:
3474 case RTL_GIGA_MAC_VER_32:
3475 case RTL_GIGA_MAC_VER_33:
3476 case RTL_GIGA_MAC_VER_34:
3477 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3478 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3479 break;
3480 default:
3481 break;
3482 }
3483}
3484
3485static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3486{
3487 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3488 return false;
3489
3490 rtl_writephy(tp, 0x1f, 0x0000);
3491 rtl_writephy(tp, MII_BMCR, 0x0000);
3492
3493 rtl_wol_suspend_quirk(tp);
3494
3495 return true;
3496}
3497
françois romieu065c27c2011-01-03 15:08:12 +00003498static void r810x_phy_power_down(struct rtl8169_private *tp)
3499{
3500 rtl_writephy(tp, 0x1f, 0x0000);
3501 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3502}
3503
3504static void r810x_phy_power_up(struct rtl8169_private *tp)
3505{
3506 rtl_writephy(tp, 0x1f, 0x0000);
3507 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3508}
3509
3510static void r810x_pll_power_down(struct rtl8169_private *tp)
3511{
David S. Miller1805b2f2011-10-24 18:18:09 -04003512 if (rtl_wol_pll_power_down(tp))
françois romieu065c27c2011-01-03 15:08:12 +00003513 return;
françois romieu065c27c2011-01-03 15:08:12 +00003514
3515 r810x_phy_power_down(tp);
3516}
3517
3518static void r810x_pll_power_up(struct rtl8169_private *tp)
3519{
3520 r810x_phy_power_up(tp);
3521}
3522
3523static void r8168_phy_power_up(struct rtl8169_private *tp)
3524{
3525 rtl_writephy(tp, 0x1f, 0x0000);
hayeswang01dc7fe2011-03-21 01:50:28 +00003526 switch (tp->mac_version) {
3527 case RTL_GIGA_MAC_VER_11:
3528 case RTL_GIGA_MAC_VER_12:
3529 case RTL_GIGA_MAC_VER_17:
3530 case RTL_GIGA_MAC_VER_18:
3531 case RTL_GIGA_MAC_VER_19:
3532 case RTL_GIGA_MAC_VER_20:
3533 case RTL_GIGA_MAC_VER_21:
3534 case RTL_GIGA_MAC_VER_22:
3535 case RTL_GIGA_MAC_VER_23:
3536 case RTL_GIGA_MAC_VER_24:
3537 case RTL_GIGA_MAC_VER_25:
3538 case RTL_GIGA_MAC_VER_26:
3539 case RTL_GIGA_MAC_VER_27:
3540 case RTL_GIGA_MAC_VER_28:
3541 case RTL_GIGA_MAC_VER_31:
3542 rtl_writephy(tp, 0x0e, 0x0000);
3543 break;
3544 default:
3545 break;
3546 }
françois romieu065c27c2011-01-03 15:08:12 +00003547 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3548}
3549
3550static void r8168_phy_power_down(struct rtl8169_private *tp)
3551{
3552 rtl_writephy(tp, 0x1f, 0x0000);
hayeswang01dc7fe2011-03-21 01:50:28 +00003553 switch (tp->mac_version) {
3554 case RTL_GIGA_MAC_VER_32:
3555 case RTL_GIGA_MAC_VER_33:
3556 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3557 break;
3558
3559 case RTL_GIGA_MAC_VER_11:
3560 case RTL_GIGA_MAC_VER_12:
3561 case RTL_GIGA_MAC_VER_17:
3562 case RTL_GIGA_MAC_VER_18:
3563 case RTL_GIGA_MAC_VER_19:
3564 case RTL_GIGA_MAC_VER_20:
3565 case RTL_GIGA_MAC_VER_21:
3566 case RTL_GIGA_MAC_VER_22:
3567 case RTL_GIGA_MAC_VER_23:
3568 case RTL_GIGA_MAC_VER_24:
3569 case RTL_GIGA_MAC_VER_25:
3570 case RTL_GIGA_MAC_VER_26:
3571 case RTL_GIGA_MAC_VER_27:
3572 case RTL_GIGA_MAC_VER_28:
3573 case RTL_GIGA_MAC_VER_31:
3574 rtl_writephy(tp, 0x0e, 0x0200);
3575 default:
3576 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3577 break;
3578 }
françois romieu065c27c2011-01-03 15:08:12 +00003579}
3580
3581static void r8168_pll_power_down(struct rtl8169_private *tp)
3582{
3583 void __iomem *ioaddr = tp->mmio_addr;
3584
Francois Romieucecb5fd2011-04-01 10:21:07 +02003585 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3586 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3587 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
hayeswang4804b3b2011-03-21 01:50:29 +00003588 r8168dp_check_dash(tp)) {
françois romieu065c27c2011-01-03 15:08:12 +00003589 return;
Hayes Wang5d2e1952011-02-22 17:26:22 +08003590 }
françois romieu065c27c2011-01-03 15:08:12 +00003591
Francois Romieucecb5fd2011-04-01 10:21:07 +02003592 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3593 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
françois romieu065c27c2011-01-03 15:08:12 +00003594 (RTL_R16(CPlusCmd) & ASF)) {
3595 return;
3596 }
3597
hayeswang01dc7fe2011-03-21 01:50:28 +00003598 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3599 tp->mac_version == RTL_GIGA_MAC_VER_33)
3600 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3601
David S. Miller1805b2f2011-10-24 18:18:09 -04003602 if (rtl_wol_pll_power_down(tp))
françois romieu065c27c2011-01-03 15:08:12 +00003603 return;
françois romieu065c27c2011-01-03 15:08:12 +00003604
3605 r8168_phy_power_down(tp);
3606
3607 switch (tp->mac_version) {
3608 case RTL_GIGA_MAC_VER_25:
3609 case RTL_GIGA_MAC_VER_26:
Hayes Wang5d2e1952011-02-22 17:26:22 +08003610 case RTL_GIGA_MAC_VER_27:
3611 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003612 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003613 case RTL_GIGA_MAC_VER_32:
3614 case RTL_GIGA_MAC_VER_33:
françois romieu065c27c2011-01-03 15:08:12 +00003615 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3616 break;
3617 }
3618}
3619
3620static void r8168_pll_power_up(struct rtl8169_private *tp)
3621{
3622 void __iomem *ioaddr = tp->mmio_addr;
3623
Francois Romieucecb5fd2011-04-01 10:21:07 +02003624 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3625 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3626 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
hayeswang4804b3b2011-03-21 01:50:29 +00003627 r8168dp_check_dash(tp)) {
françois romieu065c27c2011-01-03 15:08:12 +00003628 return;
Hayes Wang5d2e1952011-02-22 17:26:22 +08003629 }
françois romieu065c27c2011-01-03 15:08:12 +00003630
3631 switch (tp->mac_version) {
3632 case RTL_GIGA_MAC_VER_25:
3633 case RTL_GIGA_MAC_VER_26:
Hayes Wang5d2e1952011-02-22 17:26:22 +08003634 case RTL_GIGA_MAC_VER_27:
3635 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003636 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003637 case RTL_GIGA_MAC_VER_32:
3638 case RTL_GIGA_MAC_VER_33:
françois romieu065c27c2011-01-03 15:08:12 +00003639 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3640 break;
3641 }
3642
3643 r8168_phy_power_up(tp);
3644}
3645
Francois Romieud58d46b2011-05-03 16:38:29 +02003646static void rtl_generic_op(struct rtl8169_private *tp,
3647 void (*op)(struct rtl8169_private *))
françois romieu065c27c2011-01-03 15:08:12 +00003648{
3649 if (op)
3650 op(tp);
3651}
3652
3653static void rtl_pll_power_down(struct rtl8169_private *tp)
3654{
Francois Romieud58d46b2011-05-03 16:38:29 +02003655 rtl_generic_op(tp, tp->pll_power_ops.down);
françois romieu065c27c2011-01-03 15:08:12 +00003656}
3657
3658static void rtl_pll_power_up(struct rtl8169_private *tp)
3659{
Francois Romieud58d46b2011-05-03 16:38:29 +02003660 rtl_generic_op(tp, tp->pll_power_ops.up);
françois romieu065c27c2011-01-03 15:08:12 +00003661}
3662
3663static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3664{
3665 struct pll_power_ops *ops = &tp->pll_power_ops;
3666
3667 switch (tp->mac_version) {
3668 case RTL_GIGA_MAC_VER_07:
3669 case RTL_GIGA_MAC_VER_08:
3670 case RTL_GIGA_MAC_VER_09:
3671 case RTL_GIGA_MAC_VER_10:
3672 case RTL_GIGA_MAC_VER_16:
Hayes Wang5a5e4442011-02-22 17:26:21 +08003673 case RTL_GIGA_MAC_VER_29:
3674 case RTL_GIGA_MAC_VER_30:
françois romieu065c27c2011-01-03 15:08:12 +00003675 ops->down = r810x_pll_power_down;
3676 ops->up = r810x_pll_power_up;
3677 break;
3678
3679 case RTL_GIGA_MAC_VER_11:
3680 case RTL_GIGA_MAC_VER_12:
3681 case RTL_GIGA_MAC_VER_17:
3682 case RTL_GIGA_MAC_VER_18:
3683 case RTL_GIGA_MAC_VER_19:
3684 case RTL_GIGA_MAC_VER_20:
3685 case RTL_GIGA_MAC_VER_21:
3686 case RTL_GIGA_MAC_VER_22:
3687 case RTL_GIGA_MAC_VER_23:
3688 case RTL_GIGA_MAC_VER_24:
3689 case RTL_GIGA_MAC_VER_25:
3690 case RTL_GIGA_MAC_VER_26:
3691 case RTL_GIGA_MAC_VER_27:
françois romieue6de30d2011-01-03 15:08:37 +00003692 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003693 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003694 case RTL_GIGA_MAC_VER_32:
3695 case RTL_GIGA_MAC_VER_33:
Hayes Wang70090422011-07-06 15:58:06 +08003696 case RTL_GIGA_MAC_VER_34:
Hayes Wangc2218922011-09-06 16:55:18 +08003697 case RTL_GIGA_MAC_VER_35:
3698 case RTL_GIGA_MAC_VER_36:
françois romieu065c27c2011-01-03 15:08:12 +00003699 ops->down = r8168_pll_power_down;
3700 ops->up = r8168_pll_power_up;
3701 break;
3702
3703 default:
3704 ops->down = NULL;
3705 ops->up = NULL;
3706 break;
3707 }
3708}
3709
Hayes Wange542a222011-07-06 15:58:04 +08003710static void rtl_init_rxcfg(struct rtl8169_private *tp)
3711{
3712 void __iomem *ioaddr = tp->mmio_addr;
3713
3714 switch (tp->mac_version) {
3715 case RTL_GIGA_MAC_VER_01:
3716 case RTL_GIGA_MAC_VER_02:
3717 case RTL_GIGA_MAC_VER_03:
3718 case RTL_GIGA_MAC_VER_04:
3719 case RTL_GIGA_MAC_VER_05:
3720 case RTL_GIGA_MAC_VER_06:
3721 case RTL_GIGA_MAC_VER_10:
3722 case RTL_GIGA_MAC_VER_11:
3723 case RTL_GIGA_MAC_VER_12:
3724 case RTL_GIGA_MAC_VER_13:
3725 case RTL_GIGA_MAC_VER_14:
3726 case RTL_GIGA_MAC_VER_15:
3727 case RTL_GIGA_MAC_VER_16:
3728 case RTL_GIGA_MAC_VER_17:
3729 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3730 break;
3731 case RTL_GIGA_MAC_VER_18:
3732 case RTL_GIGA_MAC_VER_19:
3733 case RTL_GIGA_MAC_VER_20:
3734 case RTL_GIGA_MAC_VER_21:
3735 case RTL_GIGA_MAC_VER_22:
3736 case RTL_GIGA_MAC_VER_23:
3737 case RTL_GIGA_MAC_VER_24:
3738 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3739 break;
3740 default:
3741 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3742 break;
3743 }
3744}
3745
Hayes Wang92fc43b2011-07-06 15:58:03 +08003746static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3747{
3748 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3749}
3750
Francois Romieud58d46b2011-05-03 16:38:29 +02003751static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3752{
françois romieu9c5028e2012-03-02 04:43:14 +00003753 void __iomem *ioaddr = tp->mmio_addr;
3754
3755 RTL_W8(Cfg9346, Cfg9346_Unlock);
Francois Romieud58d46b2011-05-03 16:38:29 +02003756 rtl_generic_op(tp, tp->jumbo_ops.enable);
françois romieu9c5028e2012-03-02 04:43:14 +00003757 RTL_W8(Cfg9346, Cfg9346_Lock);
Francois Romieud58d46b2011-05-03 16:38:29 +02003758}
3759
3760static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3761{
françois romieu9c5028e2012-03-02 04:43:14 +00003762 void __iomem *ioaddr = tp->mmio_addr;
3763
3764 RTL_W8(Cfg9346, Cfg9346_Unlock);
Francois Romieud58d46b2011-05-03 16:38:29 +02003765 rtl_generic_op(tp, tp->jumbo_ops.disable);
françois romieu9c5028e2012-03-02 04:43:14 +00003766 RTL_W8(Cfg9346, Cfg9346_Lock);
Francois Romieud58d46b2011-05-03 16:38:29 +02003767}
3768
3769static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3770{
3771 void __iomem *ioaddr = tp->mmio_addr;
3772
3773 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3774 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3775 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3776}
3777
3778static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3779{
3780 void __iomem *ioaddr = tp->mmio_addr;
3781
3782 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3783 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3784 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3785}
3786
3787static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3788{
3789 void __iomem *ioaddr = tp->mmio_addr;
3790
3791 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3792}
3793
3794static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3795{
3796 void __iomem *ioaddr = tp->mmio_addr;
3797
3798 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3799}
3800
3801static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3802{
3803 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieud58d46b2011-05-03 16:38:29 +02003804
3805 RTL_W8(MaxTxPacketSize, 0x3f);
3806 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3807 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
Francois Romieu4512ff92011-12-22 18:59:37 +01003808 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
Francois Romieud58d46b2011-05-03 16:38:29 +02003809}
3810
3811static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3812{
3813 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieud58d46b2011-05-03 16:38:29 +02003814
3815 RTL_W8(MaxTxPacketSize, 0x0c);
3816 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3817 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
Francois Romieu4512ff92011-12-22 18:59:37 +01003818 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
Francois Romieud58d46b2011-05-03 16:38:29 +02003819}
3820
3821static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3822{
3823 rtl_tx_performance_tweak(tp->pci_dev,
3824 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3825}
3826
3827static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3828{
3829 rtl_tx_performance_tweak(tp->pci_dev,
3830 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3831}
3832
3833static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3834{
3835 void __iomem *ioaddr = tp->mmio_addr;
3836
3837 r8168b_0_hw_jumbo_enable(tp);
3838
3839 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3840}
3841
3842static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3843{
3844 void __iomem *ioaddr = tp->mmio_addr;
3845
3846 r8168b_0_hw_jumbo_disable(tp);
3847
3848 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3849}
3850
3851static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3852{
3853 struct jumbo_ops *ops = &tp->jumbo_ops;
3854
3855 switch (tp->mac_version) {
3856 case RTL_GIGA_MAC_VER_11:
3857 ops->disable = r8168b_0_hw_jumbo_disable;
3858 ops->enable = r8168b_0_hw_jumbo_enable;
3859 break;
3860 case RTL_GIGA_MAC_VER_12:
3861 case RTL_GIGA_MAC_VER_17:
3862 ops->disable = r8168b_1_hw_jumbo_disable;
3863 ops->enable = r8168b_1_hw_jumbo_enable;
3864 break;
3865 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3866 case RTL_GIGA_MAC_VER_19:
3867 case RTL_GIGA_MAC_VER_20:
3868 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3869 case RTL_GIGA_MAC_VER_22:
3870 case RTL_GIGA_MAC_VER_23:
3871 case RTL_GIGA_MAC_VER_24:
3872 case RTL_GIGA_MAC_VER_25:
3873 case RTL_GIGA_MAC_VER_26:
3874 ops->disable = r8168c_hw_jumbo_disable;
3875 ops->enable = r8168c_hw_jumbo_enable;
3876 break;
3877 case RTL_GIGA_MAC_VER_27:
3878 case RTL_GIGA_MAC_VER_28:
3879 ops->disable = r8168dp_hw_jumbo_disable;
3880 ops->enable = r8168dp_hw_jumbo_enable;
3881 break;
3882 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3883 case RTL_GIGA_MAC_VER_32:
3884 case RTL_GIGA_MAC_VER_33:
3885 case RTL_GIGA_MAC_VER_34:
3886 ops->disable = r8168e_hw_jumbo_disable;
3887 ops->enable = r8168e_hw_jumbo_enable;
3888 break;
3889
3890 /*
3891 * No action needed for jumbo frames with 8169.
3892 * No jumbo for 810x at all.
3893 */
3894 default:
3895 ops->disable = NULL;
3896 ops->enable = NULL;
3897 break;
3898 }
3899}
3900
Francois Romieu6f43adc2011-04-29 15:05:51 +02003901static void rtl_hw_reset(struct rtl8169_private *tp)
3902{
3903 void __iomem *ioaddr = tp->mmio_addr;
3904 int i;
3905
3906 /* Soft reset the chip. */
3907 RTL_W8(ChipCmd, CmdReset);
3908
3909 /* Check that the chip has finished the reset. */
3910 for (i = 0; i < 100; i++) {
3911 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3912 break;
Hayes Wang92fc43b2011-07-06 15:58:03 +08003913 udelay(100);
Francois Romieu6f43adc2011-04-29 15:05:51 +02003914 }
3915}
3916
Francois Romieub6ffd972011-06-17 17:00:05 +02003917static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3918{
3919 struct rtl_fw *rtl_fw;
3920 const char *name;
3921 int rc = -ENOMEM;
3922
3923 name = rtl_lookup_firmware_name(tp);
3924 if (!name)
3925 goto out_no_firmware;
3926
3927 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3928 if (!rtl_fw)
3929 goto err_warn;
3930
3931 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3932 if (rc < 0)
3933 goto err_free;
3934
Francois Romieufd112f22011-06-18 00:10:29 +02003935 rc = rtl_check_firmware(tp, rtl_fw);
3936 if (rc < 0)
3937 goto err_release_firmware;
3938
Francois Romieub6ffd972011-06-17 17:00:05 +02003939 tp->rtl_fw = rtl_fw;
3940out:
3941 return;
3942
Francois Romieufd112f22011-06-18 00:10:29 +02003943err_release_firmware:
3944 release_firmware(rtl_fw->fw);
Francois Romieub6ffd972011-06-17 17:00:05 +02003945err_free:
3946 kfree(rtl_fw);
3947err_warn:
3948 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3949 name, rc);
3950out_no_firmware:
3951 tp->rtl_fw = NULL;
3952 goto out;
3953}
3954
François Romieu953a12c2011-04-24 17:38:48 +02003955static void rtl_request_firmware(struct rtl8169_private *tp)
3956{
Francois Romieub6ffd972011-06-17 17:00:05 +02003957 if (IS_ERR(tp->rtl_fw))
3958 rtl_request_uncached_firmware(tp);
François Romieu953a12c2011-04-24 17:38:48 +02003959}
3960
Hayes Wang92fc43b2011-07-06 15:58:03 +08003961static void rtl_rx_close(struct rtl8169_private *tp)
3962{
3963 void __iomem *ioaddr = tp->mmio_addr;
Hayes Wang92fc43b2011-07-06 15:58:03 +08003964
Francois Romieu1687b562011-07-19 17:21:29 +02003965 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
Hayes Wang92fc43b2011-07-06 15:58:03 +08003966}
3967
françois romieue6de30d2011-01-03 15:08:37 +00003968static void rtl8169_hw_reset(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003969{
françois romieue6de30d2011-01-03 15:08:37 +00003970 void __iomem *ioaddr = tp->mmio_addr;
3971
Linus Torvalds1da177e2005-04-16 15:20:36 -07003972 /* Disable interrupts */
françois romieu811fd302011-12-04 20:30:45 +00003973 rtl8169_irq_mask_and_ack(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003974
Hayes Wang92fc43b2011-07-06 15:58:03 +08003975 rtl_rx_close(tp);
3976
Hayes Wang5d2e1952011-02-22 17:26:22 +08003977 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
hayeswang4804b3b2011-03-21 01:50:29 +00003978 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3979 tp->mac_version == RTL_GIGA_MAC_VER_31) {
françois romieue6de30d2011-01-03 15:08:37 +00003980 while (RTL_R8(TxPoll) & NPQ)
3981 udelay(20);
Hayes Wangc2218922011-09-06 16:55:18 +08003982 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3983 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3984 tp->mac_version == RTL_GIGA_MAC_VER_36) {
David S. Miller8decf862011-09-22 03:23:13 -04003985 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
Hayes Wang70090422011-07-06 15:58:06 +08003986 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3987 udelay(100);
Hayes Wang92fc43b2011-07-06 15:58:03 +08003988 } else {
3989 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3990 udelay(100);
françois romieue6de30d2011-01-03 15:08:37 +00003991 }
3992
Hayes Wang92fc43b2011-07-06 15:58:03 +08003993 rtl_hw_reset(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003994}
3995
Francois Romieu7f796d832007-06-11 23:04:41 +02003996static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
Francois Romieu9cb427b2006-11-02 00:10:16 +01003997{
3998 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu9cb427b2006-11-02 00:10:16 +01003999
4000 /* Set DMA burst size and Interframe Gap Time */
4001 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4002 (InterFrameGap << TxInterFrameGapShift));
4003}
4004
Francois Romieu07ce4062007-02-23 23:36:39 +01004005static void rtl_hw_start(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004006{
4007 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004008
Francois Romieu07ce4062007-02-23 23:36:39 +01004009 tp->hw_start(dev);
4010
Francois Romieuda78dbf2012-01-26 14:18:23 +01004011 rtl_irq_enable_all(tp);
Francois Romieu07ce4062007-02-23 23:36:39 +01004012}
4013
Francois Romieu7f796d832007-06-11 23:04:41 +02004014static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4015 void __iomem *ioaddr)
4016{
4017 /*
4018 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4019 * register to be written before TxDescAddrLow to work.
4020 * Switching from MMIO to I/O access fixes the issue as well.
4021 */
4022 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07004023 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
Francois Romieu7f796d832007-06-11 23:04:41 +02004024 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07004025 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
Francois Romieu7f796d832007-06-11 23:04:41 +02004026}
4027
4028static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4029{
4030 u16 cmd;
4031
4032 cmd = RTL_R16(CPlusCmd);
4033 RTL_W16(CPlusCmd, cmd);
4034 return cmd;
4035}
4036
Eric Dumazetfdd7b4c2009-06-09 04:01:02 -07004037static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
Francois Romieu7f796d832007-06-11 23:04:41 +02004038{
4039 /* Low hurts. Let's disable the filtering. */
Raimonds Cicans207d6e872009-10-26 10:52:37 +00004040 RTL_W16(RxMaxSize, rx_buf_sz + 1);
Francois Romieu7f796d832007-06-11 23:04:41 +02004041}
4042
Francois Romieu6dccd162007-02-13 23:38:05 +01004043static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4044{
Francois Romieu37441002011-06-17 22:58:54 +02004045 static const struct rtl_cfg2_info {
Francois Romieu6dccd162007-02-13 23:38:05 +01004046 u32 mac_version;
4047 u32 clk;
4048 u32 val;
4049 } cfg2_info [] = {
4050 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4051 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4052 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4053 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
Francois Romieu37441002011-06-17 22:58:54 +02004054 };
4055 const struct rtl_cfg2_info *p = cfg2_info;
Francois Romieu6dccd162007-02-13 23:38:05 +01004056 unsigned int i;
4057 u32 clk;
4058
4059 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
Francois Romieucadf1852008-01-03 23:38:38 +01004060 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
Francois Romieu6dccd162007-02-13 23:38:05 +01004061 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4062 RTL_W32(0x7c, p->val);
4063 break;
4064 }
4065 }
4066}
4067
Francois Romieue6b763e2012-03-08 09:35:39 +01004068static void rtl_set_rx_mode(struct net_device *dev)
4069{
4070 struct rtl8169_private *tp = netdev_priv(dev);
4071 void __iomem *ioaddr = tp->mmio_addr;
4072 u32 mc_filter[2]; /* Multicast hash filter */
4073 int rx_mode;
4074 u32 tmp = 0;
4075
4076 if (dev->flags & IFF_PROMISC) {
4077 /* Unconditionally log net taps. */
4078 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4079 rx_mode =
4080 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4081 AcceptAllPhys;
4082 mc_filter[1] = mc_filter[0] = 0xffffffff;
4083 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4084 (dev->flags & IFF_ALLMULTI)) {
4085 /* Too many to filter perfectly -- accept all multicasts. */
4086 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4087 mc_filter[1] = mc_filter[0] = 0xffffffff;
4088 } else {
4089 struct netdev_hw_addr *ha;
4090
4091 rx_mode = AcceptBroadcast | AcceptMyPhys;
4092 mc_filter[1] = mc_filter[0] = 0;
4093 netdev_for_each_mc_addr(ha, dev) {
4094 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4095 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4096 rx_mode |= AcceptMulticast;
4097 }
4098 }
4099
4100 if (dev->features & NETIF_F_RXALL)
4101 rx_mode |= (AcceptErr | AcceptRunt);
4102
4103 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4104
4105 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4106 u32 data = mc_filter[0];
4107
4108 mc_filter[0] = swab32(mc_filter[1]);
4109 mc_filter[1] = swab32(data);
4110 }
4111
4112 RTL_W32(MAR0 + 4, mc_filter[1]);
4113 RTL_W32(MAR0 + 0, mc_filter[0]);
4114
4115 RTL_W32(RxConfig, tmp);
4116}
4117
Francois Romieu07ce4062007-02-23 23:36:39 +01004118static void rtl_hw_start_8169(struct net_device *dev)
4119{
4120 struct rtl8169_private *tp = netdev_priv(dev);
4121 void __iomem *ioaddr = tp->mmio_addr;
4122 struct pci_dev *pdev = tp->pci_dev;
Francois Romieu07ce4062007-02-23 23:36:39 +01004123
Francois Romieu9cb427b2006-11-02 00:10:16 +01004124 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4125 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4126 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4127 }
4128
Linus Torvalds1da177e2005-04-16 15:20:36 -07004129 RTL_W8(Cfg9346, Cfg9346_Unlock);
Francois Romieucecb5fd2011-04-01 10:21:07 +02004130 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4131 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4132 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4133 tp->mac_version == RTL_GIGA_MAC_VER_04)
Francois Romieu9cb427b2006-11-02 00:10:16 +01004134 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4135
Hayes Wange542a222011-07-06 15:58:04 +08004136 rtl_init_rxcfg(tp);
4137
françois romieuf0298f82011-01-03 15:07:42 +00004138 RTL_W8(EarlyTxThres, NoEarlyTx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004139
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004140 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004141
Francois Romieucecb5fd2011-04-01 10:21:07 +02004142 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4143 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4144 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4145 tp->mac_version == RTL_GIGA_MAC_VER_04)
Francois Romieuc946b302007-10-04 00:42:50 +02004146 rtl_set_rx_tx_config_registers(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004147
Francois Romieu7f796d832007-06-11 23:04:41 +02004148 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
Francois Romieubcf0bf92006-07-26 23:14:13 +02004149
Francois Romieucecb5fd2011-04-01 10:21:07 +02004150 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4151 tp->mac_version == RTL_GIGA_MAC_VER_03) {
Joe Perches06fa7352007-10-18 21:15:00 +02004152 dprintk("Set MAC Reg C+CR Offset 0xE0. "
Linus Torvalds1da177e2005-04-16 15:20:36 -07004153 "Bit-3 and bit-14 MUST be 1\n");
Francois Romieubcf0bf92006-07-26 23:14:13 +02004154 tp->cp_cmd |= (1 << 14);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004155 }
4156
Francois Romieubcf0bf92006-07-26 23:14:13 +02004157 RTL_W16(CPlusCmd, tp->cp_cmd);
4158
Francois Romieu6dccd162007-02-13 23:38:05 +01004159 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4160
Linus Torvalds1da177e2005-04-16 15:20:36 -07004161 /*
4162 * Undocumented corner. Supposedly:
4163 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4164 */
4165 RTL_W16(IntrMitigate, 0x0000);
4166
Francois Romieu7f796d832007-06-11 23:04:41 +02004167 rtl_set_rx_tx_desc_registers(tp, ioaddr);
Francois Romieu9cb427b2006-11-02 00:10:16 +01004168
Francois Romieucecb5fd2011-04-01 10:21:07 +02004169 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4170 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4171 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4172 tp->mac_version != RTL_GIGA_MAC_VER_04) {
Francois Romieuc946b302007-10-04 00:42:50 +02004173 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4174 rtl_set_rx_tx_config_registers(tp);
4175 }
4176
Linus Torvalds1da177e2005-04-16 15:20:36 -07004177 RTL_W8(Cfg9346, Cfg9346_Lock);
Francois Romieub518fa82006-08-16 15:23:13 +02004178
4179 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4180 RTL_R8(IntrMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004181
4182 RTL_W32(RxMissed, 0);
4183
Francois Romieu07ce4062007-02-23 23:36:39 +01004184 rtl_set_rx_mode(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004185
4186 /* no early-rx interrupts */
4187 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
Francois Romieu07ce4062007-02-23 23:36:39 +01004188}
Linus Torvalds1da177e2005-04-16 15:20:36 -07004189
françois romieu650e8d52011-01-03 15:08:29 +00004190static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
Francois Romieudacf8152008-08-02 20:44:13 +02004191{
4192 u32 csi;
4193
4194 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
françois romieu650e8d52011-01-03 15:08:29 +00004195 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4196}
4197
françois romieue6de30d2011-01-03 15:08:37 +00004198static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4199{
4200 rtl_csi_access_enable(ioaddr, 0x17000000);
4201}
4202
françois romieu650e8d52011-01-03 15:08:29 +00004203static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4204{
4205 rtl_csi_access_enable(ioaddr, 0x27000000);
Francois Romieudacf8152008-08-02 20:44:13 +02004206}
4207
4208struct ephy_info {
4209 unsigned int offset;
4210 u16 mask;
4211 u16 bits;
4212};
4213
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004214static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
Francois Romieudacf8152008-08-02 20:44:13 +02004215{
4216 u16 w;
4217
4218 while (len-- > 0) {
4219 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4220 rtl_ephy_write(ioaddr, e->offset, w);
4221 e++;
4222 }
4223}
4224
Francois Romieub726e492008-06-28 12:22:59 +02004225static void rtl_disable_clock_request(struct pci_dev *pdev)
4226{
Jon Masone44daad2011-06-27 07:46:31 +00004227 int cap = pci_pcie_cap(pdev);
Francois Romieub726e492008-06-28 12:22:59 +02004228
4229 if (cap) {
4230 u16 ctl;
4231
4232 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4233 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4234 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4235 }
4236}
4237
françois romieue6de30d2011-01-03 15:08:37 +00004238static void rtl_enable_clock_request(struct pci_dev *pdev)
4239{
Jon Masone44daad2011-06-27 07:46:31 +00004240 int cap = pci_pcie_cap(pdev);
françois romieue6de30d2011-01-03 15:08:37 +00004241
4242 if (cap) {
4243 u16 ctl;
4244
4245 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4246 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4247 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4248 }
4249}
4250
Francois Romieub726e492008-06-28 12:22:59 +02004251#define R8168_CPCMD_QUIRK_MASK (\
4252 EnableBist | \
4253 Mac_dbgo_oe | \
4254 Force_half_dup | \
4255 Force_rxflow_en | \
4256 Force_txflow_en | \
4257 Cxpl_dbg_sel | \
4258 ASF | \
4259 PktCntrDisable | \
4260 Mac_dbgo_sel)
4261
Francois Romieu219a1e92008-06-28 11:58:39 +02004262static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4263{
Francois Romieub726e492008-06-28 12:22:59 +02004264 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4265
4266 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4267
Francois Romieu2e68ae42008-06-28 12:00:55 +02004268 rtl_tx_performance_tweak(pdev,
4269 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
Francois Romieu219a1e92008-06-28 11:58:39 +02004270}
4271
4272static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4273{
4274 rtl_hw_start_8168bb(ioaddr, pdev);
Francois Romieub726e492008-06-28 12:22:59 +02004275
françois romieuf0298f82011-01-03 15:07:42 +00004276 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieub726e492008-06-28 12:22:59 +02004277
4278 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
Francois Romieu219a1e92008-06-28 11:58:39 +02004279}
4280
4281static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4282{
Francois Romieub726e492008-06-28 12:22:59 +02004283 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4284
4285 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4286
Francois Romieu219a1e92008-06-28 11:58:39 +02004287 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
Francois Romieub726e492008-06-28 12:22:59 +02004288
4289 rtl_disable_clock_request(pdev);
4290
4291 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
Francois Romieu219a1e92008-06-28 11:58:39 +02004292}
4293
Francois Romieuef3386f2008-06-29 12:24:30 +02004294static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
Francois Romieu219a1e92008-06-28 11:58:39 +02004295{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004296 static const struct ephy_info e_info_8168cp[] = {
Francois Romieub726e492008-06-28 12:22:59 +02004297 { 0x01, 0, 0x0001 },
4298 { 0x02, 0x0800, 0x1000 },
4299 { 0x03, 0, 0x0042 },
4300 { 0x06, 0x0080, 0x0000 },
4301 { 0x07, 0, 0x2000 }
4302 };
4303
françois romieu650e8d52011-01-03 15:08:29 +00004304 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02004305
4306 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4307
Francois Romieu219a1e92008-06-28 11:58:39 +02004308 __rtl_hw_start_8168cp(ioaddr, pdev);
4309}
4310
Francois Romieuef3386f2008-06-29 12:24:30 +02004311static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4312{
françois romieu650e8d52011-01-03 15:08:29 +00004313 rtl_csi_access_enable_2(ioaddr);
Francois Romieuef3386f2008-06-29 12:24:30 +02004314
4315 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4316
4317 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4318
4319 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4320}
4321
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004322static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4323{
françois romieu650e8d52011-01-03 15:08:29 +00004324 rtl_csi_access_enable_2(ioaddr);
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004325
4326 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4327
4328 /* Magic. */
4329 RTL_W8(DBG_REG, 0x20);
4330
françois romieuf0298f82011-01-03 15:07:42 +00004331 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004332
4333 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4334
4335 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4336}
4337
Francois Romieu219a1e92008-06-28 11:58:39 +02004338static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4339{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004340 static const struct ephy_info e_info_8168c_1[] = {
Francois Romieub726e492008-06-28 12:22:59 +02004341 { 0x02, 0x0800, 0x1000 },
4342 { 0x03, 0, 0x0002 },
4343 { 0x06, 0x0080, 0x0000 }
4344 };
4345
françois romieu650e8d52011-01-03 15:08:29 +00004346 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02004347
4348 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4349
4350 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4351
Francois Romieu219a1e92008-06-28 11:58:39 +02004352 __rtl_hw_start_8168cp(ioaddr, pdev);
4353}
4354
4355static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4356{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004357 static const struct ephy_info e_info_8168c_2[] = {
Francois Romieub726e492008-06-28 12:22:59 +02004358 { 0x01, 0, 0x0001 },
4359 { 0x03, 0x0400, 0x0220 }
4360 };
4361
françois romieu650e8d52011-01-03 15:08:29 +00004362 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02004363
4364 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4365
Francois Romieu219a1e92008-06-28 11:58:39 +02004366 __rtl_hw_start_8168cp(ioaddr, pdev);
4367}
4368
Francois Romieu197ff762008-06-28 13:16:02 +02004369static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4370{
4371 rtl_hw_start_8168c_2(ioaddr, pdev);
4372}
4373
Francois Romieu6fb07052008-06-29 11:54:28 +02004374static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4375{
françois romieu650e8d52011-01-03 15:08:29 +00004376 rtl_csi_access_enable_2(ioaddr);
Francois Romieu6fb07052008-06-29 11:54:28 +02004377
4378 __rtl_hw_start_8168cp(ioaddr, pdev);
4379}
4380
Francois Romieu5b538df2008-07-20 16:22:45 +02004381static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4382{
françois romieu650e8d52011-01-03 15:08:29 +00004383 rtl_csi_access_enable_2(ioaddr);
Francois Romieu5b538df2008-07-20 16:22:45 +02004384
4385 rtl_disable_clock_request(pdev);
4386
françois romieuf0298f82011-01-03 15:07:42 +00004387 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu5b538df2008-07-20 16:22:45 +02004388
4389 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4390
4391 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4392}
4393
hayeswang4804b3b2011-03-21 01:50:29 +00004394static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4395{
4396 rtl_csi_access_enable_1(ioaddr);
4397
4398 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4399
4400 RTL_W8(MaxTxPacketSize, TxPacketMax);
4401
4402 rtl_disable_clock_request(pdev);
4403}
4404
françois romieue6de30d2011-01-03 15:08:37 +00004405static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4406{
4407 static const struct ephy_info e_info_8168d_4[] = {
4408 { 0x0b, ~0, 0x48 },
4409 { 0x19, 0x20, 0x50 },
4410 { 0x0c, ~0, 0x20 }
4411 };
4412 int i;
4413
4414 rtl_csi_access_enable_1(ioaddr);
4415
4416 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4417
4418 RTL_W8(MaxTxPacketSize, TxPacketMax);
4419
4420 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4421 const struct ephy_info *e = e_info_8168d_4 + i;
4422 u16 w;
4423
4424 w = rtl_ephy_read(ioaddr, e->offset);
4425 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4426 }
4427
4428 rtl_enable_clock_request(pdev);
4429}
4430
Hayes Wang70090422011-07-06 15:58:06 +08004431static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
hayeswang01dc7fe2011-03-21 01:50:28 +00004432{
Hayes Wang70090422011-07-06 15:58:06 +08004433 static const struct ephy_info e_info_8168e_1[] = {
hayeswang01dc7fe2011-03-21 01:50:28 +00004434 { 0x00, 0x0200, 0x0100 },
4435 { 0x00, 0x0000, 0x0004 },
4436 { 0x06, 0x0002, 0x0001 },
4437 { 0x06, 0x0000, 0x0030 },
4438 { 0x07, 0x0000, 0x2000 },
4439 { 0x00, 0x0000, 0x0020 },
4440 { 0x03, 0x5800, 0x2000 },
4441 { 0x03, 0x0000, 0x0001 },
4442 { 0x01, 0x0800, 0x1000 },
4443 { 0x07, 0x0000, 0x4000 },
4444 { 0x1e, 0x0000, 0x2000 },
4445 { 0x19, 0xffff, 0xfe6c },
4446 { 0x0a, 0x0000, 0x0040 }
4447 };
4448
4449 rtl_csi_access_enable_2(ioaddr);
4450
Hayes Wang70090422011-07-06 15:58:06 +08004451 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
hayeswang01dc7fe2011-03-21 01:50:28 +00004452
4453 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4454
4455 RTL_W8(MaxTxPacketSize, TxPacketMax);
4456
4457 rtl_disable_clock_request(pdev);
4458
4459 /* Reset tx FIFO pointer */
Francois Romieucecb5fd2011-04-01 10:21:07 +02004460 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4461 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
hayeswang01dc7fe2011-03-21 01:50:28 +00004462
Francois Romieucecb5fd2011-04-01 10:21:07 +02004463 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
hayeswang01dc7fe2011-03-21 01:50:28 +00004464}
4465
Hayes Wang70090422011-07-06 15:58:06 +08004466static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4467{
4468 static const struct ephy_info e_info_8168e_2[] = {
4469 { 0x09, 0x0000, 0x0080 },
4470 { 0x19, 0x0000, 0x0224 }
4471 };
4472
4473 rtl_csi_access_enable_1(ioaddr);
4474
4475 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4476
4477 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4478
4479 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4480 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4481 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4482 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4483 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4484 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4485 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4486 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4487 ERIAR_EXGMAC);
4488
Hayes Wang3090bd92011-09-06 16:55:15 +08004489 RTL_W8(MaxTxPacketSize, EarlySize);
Hayes Wang70090422011-07-06 15:58:06 +08004490
4491 rtl_disable_clock_request(pdev);
4492
4493 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4494 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4495
4496 /* Adjust EEE LED frequency */
4497 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4498
4499 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4500 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4501 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4502}
4503
Hayes Wangc2218922011-09-06 16:55:18 +08004504static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4505{
4506 static const struct ephy_info e_info_8168f_1[] = {
4507 { 0x06, 0x00c0, 0x0020 },
4508 { 0x08, 0x0001, 0x0002 },
4509 { 0x09, 0x0000, 0x0080 },
4510 { 0x19, 0x0000, 0x0224 }
4511 };
4512
4513 rtl_csi_access_enable_1(ioaddr);
4514
4515 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4516
4517 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4518
4519 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4520 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4521 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4522 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4523 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4524 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4525 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4526 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4527 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4528 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4529 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4530 ERIAR_EXGMAC);
4531
4532 RTL_W8(MaxTxPacketSize, EarlySize);
4533
4534 rtl_disable_clock_request(pdev);
4535
4536 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4537 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4538
4539 /* Adjust EEE LED frequency */
4540 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4541
4542 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4543 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4544 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4545}
4546
Francois Romieu07ce4062007-02-23 23:36:39 +01004547static void rtl_hw_start_8168(struct net_device *dev)
4548{
Francois Romieu2dd99532007-06-11 23:22:52 +02004549 struct rtl8169_private *tp = netdev_priv(dev);
4550 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu0e485152007-02-20 00:00:26 +01004551 struct pci_dev *pdev = tp->pci_dev;
Francois Romieu2dd99532007-06-11 23:22:52 +02004552
4553 RTL_W8(Cfg9346, Cfg9346_Unlock);
4554
françois romieuf0298f82011-01-03 15:07:42 +00004555 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu2dd99532007-06-11 23:22:52 +02004556
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004557 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Francois Romieu2dd99532007-06-11 23:22:52 +02004558
Francois Romieu0e485152007-02-20 00:00:26 +01004559 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
Francois Romieu2dd99532007-06-11 23:22:52 +02004560
4561 RTL_W16(CPlusCmd, tp->cp_cmd);
4562
Francois Romieu0e485152007-02-20 00:00:26 +01004563 RTL_W16(IntrMitigate, 0x5151);
4564
4565 /* Work around for RxFIFO overflow. */
françois romieu811fd302011-12-04 20:30:45 +00004566 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
Francois Romieuda78dbf2012-01-26 14:18:23 +01004567 tp->event_slow |= RxFIFOOver | PCSTimeout;
4568 tp->event_slow &= ~RxOverflow;
Francois Romieu0e485152007-02-20 00:00:26 +01004569 }
Francois Romieu2dd99532007-06-11 23:22:52 +02004570
4571 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4572
Francois Romieub8363902008-06-01 12:31:57 +02004573 rtl_set_rx_mode(dev);
4574
4575 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4576 (InterFrameGap << TxInterFrameGapShift));
Francois Romieu2dd99532007-06-11 23:22:52 +02004577
4578 RTL_R8(IntrMask);
4579
Francois Romieu219a1e92008-06-28 11:58:39 +02004580 switch (tp->mac_version) {
4581 case RTL_GIGA_MAC_VER_11:
4582 rtl_hw_start_8168bb(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004583 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004584
4585 case RTL_GIGA_MAC_VER_12:
4586 case RTL_GIGA_MAC_VER_17:
4587 rtl_hw_start_8168bef(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004588 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004589
4590 case RTL_GIGA_MAC_VER_18:
Francois Romieuef3386f2008-06-29 12:24:30 +02004591 rtl_hw_start_8168cp_1(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004592 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004593
4594 case RTL_GIGA_MAC_VER_19:
4595 rtl_hw_start_8168c_1(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004596 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004597
4598 case RTL_GIGA_MAC_VER_20:
4599 rtl_hw_start_8168c_2(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004600 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004601
Francois Romieu197ff762008-06-28 13:16:02 +02004602 case RTL_GIGA_MAC_VER_21:
4603 rtl_hw_start_8168c_3(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004604 break;
Francois Romieu197ff762008-06-28 13:16:02 +02004605
Francois Romieu6fb07052008-06-29 11:54:28 +02004606 case RTL_GIGA_MAC_VER_22:
4607 rtl_hw_start_8168c_4(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004608 break;
Francois Romieu6fb07052008-06-29 11:54:28 +02004609
Francois Romieuef3386f2008-06-29 12:24:30 +02004610 case RTL_GIGA_MAC_VER_23:
4611 rtl_hw_start_8168cp_2(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004612 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02004613
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004614 case RTL_GIGA_MAC_VER_24:
4615 rtl_hw_start_8168cp_3(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004616 break;
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004617
Francois Romieu5b538df2008-07-20 16:22:45 +02004618 case RTL_GIGA_MAC_VER_25:
françois romieudaf9df62009-10-07 12:44:20 +00004619 case RTL_GIGA_MAC_VER_26:
4620 case RTL_GIGA_MAC_VER_27:
Francois Romieu5b538df2008-07-20 16:22:45 +02004621 rtl_hw_start_8168d(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004622 break;
Francois Romieu5b538df2008-07-20 16:22:45 +02004623
françois romieue6de30d2011-01-03 15:08:37 +00004624 case RTL_GIGA_MAC_VER_28:
4625 rtl_hw_start_8168d_4(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004626 break;
Francois Romieucecb5fd2011-04-01 10:21:07 +02004627
hayeswang4804b3b2011-03-21 01:50:29 +00004628 case RTL_GIGA_MAC_VER_31:
4629 rtl_hw_start_8168dp(ioaddr, pdev);
4630 break;
4631
hayeswang01dc7fe2011-03-21 01:50:28 +00004632 case RTL_GIGA_MAC_VER_32:
4633 case RTL_GIGA_MAC_VER_33:
Hayes Wang70090422011-07-06 15:58:06 +08004634 rtl_hw_start_8168e_1(ioaddr, pdev);
4635 break;
4636 case RTL_GIGA_MAC_VER_34:
4637 rtl_hw_start_8168e_2(ioaddr, pdev);
hayeswang01dc7fe2011-03-21 01:50:28 +00004638 break;
françois romieue6de30d2011-01-03 15:08:37 +00004639
Hayes Wangc2218922011-09-06 16:55:18 +08004640 case RTL_GIGA_MAC_VER_35:
4641 case RTL_GIGA_MAC_VER_36:
4642 rtl_hw_start_8168f_1(ioaddr, pdev);
4643 break;
4644
Francois Romieu219a1e92008-06-28 11:58:39 +02004645 default:
4646 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4647 dev->name, tp->mac_version);
hayeswang4804b3b2011-03-21 01:50:29 +00004648 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004649 }
Francois Romieu2dd99532007-06-11 23:22:52 +02004650
Francois Romieu0e485152007-02-20 00:00:26 +01004651 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4652
Francois Romieub8363902008-06-01 12:31:57 +02004653 RTL_W8(Cfg9346, Cfg9346_Lock);
4654
Francois Romieu2dd99532007-06-11 23:22:52 +02004655 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
Francois Romieu07ce4062007-02-23 23:36:39 +01004656}
Linus Torvalds1da177e2005-04-16 15:20:36 -07004657
Francois Romieu2857ffb2008-08-02 21:08:49 +02004658#define R810X_CPCMD_QUIRK_MASK (\
4659 EnableBist | \
4660 Mac_dbgo_oe | \
4661 Force_half_dup | \
françois romieu5edcc532009-08-10 19:41:52 +00004662 Force_rxflow_en | \
Francois Romieu2857ffb2008-08-02 21:08:49 +02004663 Force_txflow_en | \
4664 Cxpl_dbg_sel | \
4665 ASF | \
4666 PktCntrDisable | \
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004667 Mac_dbgo_sel)
Francois Romieu2857ffb2008-08-02 21:08:49 +02004668
4669static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4670{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004671 static const struct ephy_info e_info_8102e_1[] = {
Francois Romieu2857ffb2008-08-02 21:08:49 +02004672 { 0x01, 0, 0x6e65 },
4673 { 0x02, 0, 0x091f },
4674 { 0x03, 0, 0xc2f9 },
4675 { 0x06, 0, 0xafb5 },
4676 { 0x07, 0, 0x0e00 },
4677 { 0x19, 0, 0xec80 },
4678 { 0x01, 0, 0x2e65 },
4679 { 0x01, 0, 0x6e65 }
4680 };
4681 u8 cfg1;
4682
françois romieu650e8d52011-01-03 15:08:29 +00004683 rtl_csi_access_enable_2(ioaddr);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004684
4685 RTL_W8(DBG_REG, FIX_NAK_1);
4686
4687 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4688
4689 RTL_W8(Config1,
4690 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4691 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4692
4693 cfg1 = RTL_R8(Config1);
4694 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4695 RTL_W8(Config1, cfg1 & ~LEDS0);
4696
Francois Romieu2857ffb2008-08-02 21:08:49 +02004697 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4698}
4699
4700static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4701{
françois romieu650e8d52011-01-03 15:08:29 +00004702 rtl_csi_access_enable_2(ioaddr);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004703
4704 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4705
4706 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4707 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004708}
4709
4710static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4711{
4712 rtl_hw_start_8102e_2(ioaddr, pdev);
4713
4714 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4715}
4716
Hayes Wang5a5e4442011-02-22 17:26:21 +08004717static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4718{
4719 static const struct ephy_info e_info_8105e_1[] = {
4720 { 0x07, 0, 0x4000 },
4721 { 0x19, 0, 0x0200 },
4722 { 0x19, 0, 0x0020 },
4723 { 0x1e, 0, 0x2000 },
4724 { 0x03, 0, 0x0001 },
4725 { 0x19, 0, 0x0100 },
4726 { 0x19, 0, 0x0004 },
4727 { 0x0a, 0, 0x0020 }
4728 };
4729
Francois Romieucecb5fd2011-04-01 10:21:07 +02004730 /* Force LAN exit from ASPM if Rx/Tx are not idle */
Hayes Wang5a5e4442011-02-22 17:26:21 +08004731 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4732
Francois Romieucecb5fd2011-04-01 10:21:07 +02004733 /* Disable Early Tally Counter */
Hayes Wang5a5e4442011-02-22 17:26:21 +08004734 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4735
4736 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
Hayes Wang4f6b00e52011-07-06 15:58:02 +08004737 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
Hayes Wang5a5e4442011-02-22 17:26:21 +08004738
4739 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4740}
4741
4742static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4743{
4744 rtl_hw_start_8105e_1(ioaddr, pdev);
4745 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4746}
4747
Francois Romieu07ce4062007-02-23 23:36:39 +01004748static void rtl_hw_start_8101(struct net_device *dev)
4749{
Francois Romieucdf1a602007-06-11 23:29:50 +02004750 struct rtl8169_private *tp = netdev_priv(dev);
4751 void __iomem *ioaddr = tp->mmio_addr;
4752 struct pci_dev *pdev = tp->pci_dev;
4753
Francois Romieuda78dbf2012-01-26 14:18:23 +01004754 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4755 tp->event_slow &= ~RxFIFOOver;
françois romieu811fd302011-12-04 20:30:45 +00004756
Francois Romieucecb5fd2011-04-01 10:21:07 +02004757 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4758 tp->mac_version == RTL_GIGA_MAC_VER_16) {
Jon Masone44daad2011-06-27 07:46:31 +00004759 int cap = pci_pcie_cap(pdev);
Francois Romieu9c14cea2008-07-05 00:21:15 +02004760
4761 if (cap) {
4762 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4763 PCI_EXP_DEVCTL_NOSNOOP_EN);
4764 }
Francois Romieucdf1a602007-06-11 23:29:50 +02004765 }
4766
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004767 RTL_W8(Cfg9346, Cfg9346_Unlock);
4768
Francois Romieu2857ffb2008-08-02 21:08:49 +02004769 switch (tp->mac_version) {
4770 case RTL_GIGA_MAC_VER_07:
4771 rtl_hw_start_8102e_1(ioaddr, pdev);
4772 break;
4773
4774 case RTL_GIGA_MAC_VER_08:
4775 rtl_hw_start_8102e_3(ioaddr, pdev);
4776 break;
4777
4778 case RTL_GIGA_MAC_VER_09:
4779 rtl_hw_start_8102e_2(ioaddr, pdev);
4780 break;
Hayes Wang5a5e4442011-02-22 17:26:21 +08004781
4782 case RTL_GIGA_MAC_VER_29:
4783 rtl_hw_start_8105e_1(ioaddr, pdev);
4784 break;
4785 case RTL_GIGA_MAC_VER_30:
4786 rtl_hw_start_8105e_2(ioaddr, pdev);
4787 break;
Francois Romieucdf1a602007-06-11 23:29:50 +02004788 }
4789
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004790 RTL_W8(Cfg9346, Cfg9346_Lock);
Francois Romieucdf1a602007-06-11 23:29:50 +02004791
françois romieuf0298f82011-01-03 15:07:42 +00004792 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieucdf1a602007-06-11 23:29:50 +02004793
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004794 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Francois Romieucdf1a602007-06-11 23:29:50 +02004795
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004796 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
Francois Romieucdf1a602007-06-11 23:29:50 +02004797 RTL_W16(CPlusCmd, tp->cp_cmd);
4798
4799 RTL_W16(IntrMitigate, 0x0000);
4800
4801 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4802
4803 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4804 rtl_set_rx_tx_config_registers(tp);
4805
Francois Romieucdf1a602007-06-11 23:29:50 +02004806 RTL_R8(IntrMask);
4807
Francois Romieucdf1a602007-06-11 23:29:50 +02004808 rtl_set_rx_mode(dev);
4809
4810 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004811}
4812
4813static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4814{
Francois Romieud58d46b2011-05-03 16:38:29 +02004815 struct rtl8169_private *tp = netdev_priv(dev);
4816
4817 if (new_mtu < ETH_ZLEN ||
4818 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004819 return -EINVAL;
4820
Francois Romieud58d46b2011-05-03 16:38:29 +02004821 if (new_mtu > ETH_DATA_LEN)
4822 rtl_hw_jumbo_enable(tp);
4823 else
4824 rtl_hw_jumbo_disable(tp);
4825
Linus Torvalds1da177e2005-04-16 15:20:36 -07004826 dev->mtu = new_mtu;
Michał Mirosław350fb322011-04-08 06:35:56 +00004827 netdev_update_features(dev);
4828
Stanislaw Gruszka323bb682010-10-20 22:25:41 +00004829 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004830}
4831
4832static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4833{
Al Viro95e09182007-12-22 18:55:39 +00004834 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004835 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4836}
4837
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004838static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4839 void **data_buff, struct RxDesc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004840{
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004841 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
Stanislaw Gruszka231aee62010-10-20 22:25:38 +00004842 DMA_FROM_DEVICE);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004843
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004844 kfree(*data_buff);
4845 *data_buff = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004846 rtl8169_make_unusable_by_asic(desc);
4847}
4848
4849static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4850{
4851 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4852
4853 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4854}
4855
4856static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4857 u32 rx_buf_sz)
4858{
4859 desc->addr = cpu_to_le64(mapping);
4860 wmb();
4861 rtl8169_mark_to_asic(desc, rx_buf_sz);
4862}
4863
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004864static inline void *rtl8169_align(void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004865{
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004866 return (void *)ALIGN((long)data, 16);
4867}
4868
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004869static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4870 struct RxDesc *desc)
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004871{
4872 void *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004873 dma_addr_t mapping;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004874 struct device *d = &tp->pci_dev->dev;
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004875 struct net_device *dev = tp->dev;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004876 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004877
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004878 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4879 if (!data)
4880 return NULL;
Francois Romieue9f63f32007-02-28 23:16:57 +01004881
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004882 if (rtl8169_align(data) != data) {
4883 kfree(data);
4884 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4885 if (!data)
4886 return NULL;
4887 }
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004888
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004889 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
Stanislaw Gruszka231aee62010-10-20 22:25:38 +00004890 DMA_FROM_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004891 if (unlikely(dma_mapping_error(d, mapping))) {
4892 if (net_ratelimit())
4893 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004894 goto err_out;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004895 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004896
4897 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004898 return data;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004899
4900err_out:
4901 kfree(data);
4902 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004903}
4904
4905static void rtl8169_rx_clear(struct rtl8169_private *tp)
4906{
Francois Romieu07d3f512007-02-21 22:40:46 +01004907 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004908
4909 for (i = 0; i < NUM_RX_DESC; i++) {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004910 if (tp->Rx_databuff[i]) {
4911 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004912 tp->RxDescArray + i);
4913 }
4914 }
4915}
4916
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004917static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004918{
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004919 desc->opts1 |= cpu_to_le32(RingEnd);
4920}
Francois Romieu5b0384f2006-08-16 16:00:01 +02004921
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004922static int rtl8169_rx_fill(struct rtl8169_private *tp)
4923{
4924 unsigned int i;
4925
4926 for (i = 0; i < NUM_RX_DESC; i++) {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004927 void *data;
Francois Romieu4ae47c22007-06-16 23:28:45 +02004928
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004929 if (tp->Rx_databuff[i])
Linus Torvalds1da177e2005-04-16 15:20:36 -07004930 continue;
Francois Romieubcf0bf92006-07-26 23:14:13 +02004931
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004932 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004933 if (!data) {
4934 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004935 goto err_out;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004936 }
4937 tp->Rx_databuff[i] = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004938 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004939
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004940 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4941 return 0;
4942
4943err_out:
4944 rtl8169_rx_clear(tp);
4945 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004946}
4947
Linus Torvalds1da177e2005-04-16 15:20:36 -07004948static int rtl8169_init_ring(struct net_device *dev)
4949{
4950 struct rtl8169_private *tp = netdev_priv(dev);
4951
4952 rtl8169_init_ring_indexes(tp);
4953
4954 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004955 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004956
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004957 return rtl8169_rx_fill(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004958}
4959
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004960static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004961 struct TxDesc *desc)
4962{
4963 unsigned int len = tx_skb->len;
4964
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004965 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4966
Linus Torvalds1da177e2005-04-16 15:20:36 -07004967 desc->opts1 = 0x00;
4968 desc->opts2 = 0x00;
4969 desc->addr = 0x00;
4970 tx_skb->len = 0;
4971}
4972
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004973static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4974 unsigned int n)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004975{
4976 unsigned int i;
4977
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004978 for (i = 0; i < n; i++) {
4979 unsigned int entry = (start + i) % NUM_TX_DESC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004980 struct ring_info *tx_skb = tp->tx_skb + entry;
4981 unsigned int len = tx_skb->len;
4982
4983 if (len) {
4984 struct sk_buff *skb = tx_skb->skb;
4985
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004986 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004987 tp->TxDescArray + entry);
4988 if (skb) {
Stanislaw Gruszkacac4b222010-10-20 22:25:40 +00004989 tp->dev->stats.tx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004990 dev_kfree_skb(skb);
4991 tx_skb->skb = NULL;
4992 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004993 }
4994 }
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004995}
4996
4997static void rtl8169_tx_clear(struct rtl8169_private *tp)
4998{
4999 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005000 tp->cur_tx = tp->dirty_tx = 0;
Igor Maravic036dafa2012-03-05 00:01:25 +01005001 netdev_reset_queue(tp->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005002}
5003
Francois Romieu4422bcd2012-01-26 11:23:32 +01005004static void rtl_reset_work(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005005{
David Howellsc4028952006-11-22 14:57:56 +00005006 struct net_device *dev = tp->dev;
Francois Romieu56de4142011-03-15 17:29:31 +01005007 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005008
Francois Romieuda78dbf2012-01-26 14:18:23 +01005009 napi_disable(&tp->napi);
5010 netif_stop_queue(dev);
5011 synchronize_sched();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005012
françois romieuc7c2c392011-12-04 20:30:52 +00005013 rtl8169_hw_reset(tp);
5014
Francois Romieu56de4142011-03-15 17:29:31 +01005015 for (i = 0; i < NUM_RX_DESC; i++)
5016 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5017
Linus Torvalds1da177e2005-04-16 15:20:36 -07005018 rtl8169_tx_clear(tp);
françois romieuc7c2c392011-12-04 20:30:52 +00005019 rtl8169_init_ring_indexes(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005020
Francois Romieuda78dbf2012-01-26 14:18:23 +01005021 napi_enable(&tp->napi);
Francois Romieu56de4142011-03-15 17:29:31 +01005022 rtl_hw_start(dev);
5023 netif_wake_queue(dev);
5024 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005025}
5026
5027static void rtl8169_tx_timeout(struct net_device *dev)
5028{
Francois Romieuda78dbf2012-01-26 14:18:23 +01005029 struct rtl8169_private *tp = netdev_priv(dev);
5030
5031 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005032}
5033
5034static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
Francois Romieu2b7b4312011-04-18 22:53:24 -07005035 u32 *opts)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005036{
5037 struct skb_shared_info *info = skb_shinfo(skb);
5038 unsigned int cur_frag, entry;
Jeff Garzika6343af2007-07-17 05:39:58 -04005039 struct TxDesc * uninitialized_var(txd);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005040 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005041
5042 entry = tp->cur_tx;
5043 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
Eric Dumazet9e903e02011-10-18 21:00:24 +00005044 const skb_frag_t *frag = info->frags + cur_frag;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005045 dma_addr_t mapping;
5046 u32 status, len;
5047 void *addr;
5048
5049 entry = (entry + 1) % NUM_TX_DESC;
5050
5051 txd = tp->TxDescArray + entry;
Eric Dumazet9e903e02011-10-18 21:00:24 +00005052 len = skb_frag_size(frag);
Ian Campbell929f6182011-08-31 00:47:06 +00005053 addr = skb_frag_address(frag);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005054 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00005055 if (unlikely(dma_mapping_error(d, mapping))) {
5056 if (net_ratelimit())
5057 netif_err(tp, drv, tp->dev,
5058 "Failed to map TX fragments DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005059 goto err_out;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00005060 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005061
Francois Romieucecb5fd2011-04-01 10:21:07 +02005062 /* Anti gcc 2.95.3 bugware (sic) */
Francois Romieu2b7b4312011-04-18 22:53:24 -07005063 status = opts[0] | len |
5064 (RingEnd * !((entry + 1) % NUM_TX_DESC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005065
5066 txd->opts1 = cpu_to_le32(status);
Francois Romieu2b7b4312011-04-18 22:53:24 -07005067 txd->opts2 = cpu_to_le32(opts[1]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005068 txd->addr = cpu_to_le64(mapping);
5069
5070 tp->tx_skb[entry].len = len;
5071 }
5072
5073 if (cur_frag) {
5074 tp->tx_skb[entry].skb = skb;
5075 txd->opts1 |= cpu_to_le32(LastFrag);
5076 }
5077
5078 return cur_frag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005079
5080err_out:
5081 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5082 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005083}
5084
Francois Romieu2b7b4312011-04-18 22:53:24 -07005085static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5086 struct sk_buff *skb, u32 *opts)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005087{
Francois Romieu2b7b4312011-04-18 22:53:24 -07005088 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
Michał Mirosław350fb322011-04-08 06:35:56 +00005089 u32 mss = skb_shinfo(skb)->gso_size;
Francois Romieu2b7b4312011-04-18 22:53:24 -07005090 int offset = info->opts_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005091
Francois Romieu2b7b4312011-04-18 22:53:24 -07005092 if (mss) {
5093 opts[0] |= TD_LSO;
5094 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5095 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005096 const struct iphdr *ip = ip_hdr(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005097
5098 if (ip->protocol == IPPROTO_TCP)
Francois Romieu2b7b4312011-04-18 22:53:24 -07005099 opts[offset] |= info->checksum.tcp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005100 else if (ip->protocol == IPPROTO_UDP)
Francois Romieu2b7b4312011-04-18 22:53:24 -07005101 opts[offset] |= info->checksum.udp;
5102 else
5103 WARN_ON_ONCE(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005104 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005105}
5106
Stephen Hemminger613573252009-08-31 19:50:58 +00005107static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5108 struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005109{
5110 struct rtl8169_private *tp = netdev_priv(dev);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005111 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005112 struct TxDesc *txd = tp->TxDescArray + entry;
5113 void __iomem *ioaddr = tp->mmio_addr;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005114 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005115 dma_addr_t mapping;
5116 u32 status, len;
Francois Romieu2b7b4312011-04-18 22:53:24 -07005117 u32 opts[2];
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005118 int frags;
Francois Romieu5b0384f2006-08-16 16:00:01 +02005119
Linus Torvalds1da177e2005-04-16 15:20:36 -07005120 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00005121 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005122 goto err_stop_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005123 }
5124
5125 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005126 goto err_stop_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005127
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005128 len = skb_headlen(skb);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005129 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00005130 if (unlikely(dma_mapping_error(d, mapping))) {
5131 if (net_ratelimit())
5132 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005133 goto err_dma_0;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00005134 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005135
5136 tp->tx_skb[entry].len = len;
5137 txd->addr = cpu_to_le64(mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005138
Francois Romieu2b7b4312011-04-18 22:53:24 -07005139 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5140 opts[0] = DescOwn;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005141
Francois Romieu2b7b4312011-04-18 22:53:24 -07005142 rtl8169_tso_csum(tp, skb, opts);
5143
5144 frags = rtl8169_xmit_frags(tp, skb, opts);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005145 if (frags < 0)
5146 goto err_dma_1;
5147 else if (frags)
Francois Romieu2b7b4312011-04-18 22:53:24 -07005148 opts[0] |= FirstFrag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005149 else {
Francois Romieu2b7b4312011-04-18 22:53:24 -07005150 opts[0] |= FirstFrag | LastFrag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005151 tp->tx_skb[entry].skb = skb;
5152 }
5153
Francois Romieu2b7b4312011-04-18 22:53:24 -07005154 txd->opts2 = cpu_to_le32(opts[1]);
5155
Igor Maravic036dafa2012-03-05 00:01:25 +01005156 netdev_sent_queue(dev, skb->len);
5157
Richard Cochran5047fb52012-03-10 07:29:42 +00005158 skb_tx_timestamp(skb);
5159
Linus Torvalds1da177e2005-04-16 15:20:36 -07005160 wmb();
5161
Francois Romieucecb5fd2011-04-01 10:21:07 +02005162 /* Anti gcc 2.95.3 bugware (sic) */
Francois Romieu2b7b4312011-04-18 22:53:24 -07005163 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005164 txd->opts1 = cpu_to_le32(status);
5165
Linus Torvalds1da177e2005-04-16 15:20:36 -07005166 tp->cur_tx += frags + 1;
5167
David Dillow4c020a92010-03-03 16:33:10 +00005168 wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005169
Francois Romieucecb5fd2011-04-01 10:21:07 +02005170 RTL_W8(TxPoll, NPQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005171
Francois Romieuda78dbf2012-01-26 14:18:23 +01005172 mmiowb();
5173
Linus Torvalds1da177e2005-04-16 15:20:36 -07005174 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
Francois Romieuae1f23f2012-01-31 00:00:19 +01005175 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5176 * not miss a ring update when it notices a stopped queue.
5177 */
5178 smp_wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005179 netif_stop_queue(dev);
Francois Romieuae1f23f2012-01-31 00:00:19 +01005180 /* Sync with rtl_tx:
5181 * - publish queue status and cur_tx ring index (write barrier)
5182 * - refresh dirty_tx ring index (read barrier).
5183 * May the current thread have a pessimistic view of the ring
5184 * status and forget to wake up queue, a racing rtl_tx thread
5185 * can't.
5186 */
Francois Romieu1e874e02012-01-27 15:05:38 +01005187 smp_mb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005188 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5189 netif_wake_queue(dev);
5190 }
5191
Stephen Hemminger613573252009-08-31 19:50:58 +00005192 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005193
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005194err_dma_1:
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005195 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00005196err_dma_0:
5197 dev_kfree_skb(skb);
5198 dev->stats.tx_dropped++;
5199 return NETDEV_TX_OK;
5200
5201err_stop_0:
Linus Torvalds1da177e2005-04-16 15:20:36 -07005202 netif_stop_queue(dev);
Francois Romieucebf8cc2007-10-18 12:06:54 +02005203 dev->stats.tx_dropped++;
Stephen Hemminger613573252009-08-31 19:50:58 +00005204 return NETDEV_TX_BUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005205}
5206
5207static void rtl8169_pcierr_interrupt(struct net_device *dev)
5208{
5209 struct rtl8169_private *tp = netdev_priv(dev);
5210 struct pci_dev *pdev = tp->pci_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005211 u16 pci_status, pci_cmd;
5212
5213 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5214 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5215
Joe Perchesbf82c182010-02-09 11:49:50 +00005216 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5217 pci_cmd, pci_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005218
5219 /*
5220 * The recovery sequence below admits a very elaborated explanation:
5221 * - it seems to work;
Francois Romieud03902b2006-11-23 00:00:42 +01005222 * - I did not see what else could be done;
5223 * - it makes iop3xx happy.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005224 *
5225 * Feel free to adjust to your needs.
5226 */
Francois Romieua27993f2006-12-18 00:04:19 +01005227 if (pdev->broken_parity_status)
Francois Romieud03902b2006-11-23 00:00:42 +01005228 pci_cmd &= ~PCI_COMMAND_PARITY;
5229 else
5230 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5231
5232 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005233
5234 pci_write_config_word(pdev, PCI_STATUS,
5235 pci_status & (PCI_STATUS_DETECTED_PARITY |
5236 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5237 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5238
5239 /* The infamous DAC f*ckup only happens at boot time */
5240 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
françois romieue6de30d2011-01-03 15:08:37 +00005241 void __iomem *ioaddr = tp->mmio_addr;
5242
Joe Perchesbf82c182010-02-09 11:49:50 +00005243 netif_info(tp, intr, dev, "disabling PCI DAC\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005244 tp->cp_cmd &= ~PCIDAC;
5245 RTL_W16(CPlusCmd, tp->cp_cmd);
5246 dev->features &= ~NETIF_F_HIGHDMA;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005247 }
5248
françois romieue6de30d2011-01-03 15:08:37 +00005249 rtl8169_hw_reset(tp);
Francois Romieud03902b2006-11-23 00:00:42 +01005250
Francois Romieu98ddf982012-01-31 10:47:34 +01005251 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005252}
5253
Igor Maravic036dafa2012-03-05 00:01:25 +01005254struct rtl_txc {
5255 int packets;
5256 int bytes;
5257};
5258
Francois Romieuda78dbf2012-01-26 14:18:23 +01005259static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005260{
Igor Maravic036dafa2012-03-05 00:01:25 +01005261 struct rtl8169_stats *tx_stats = &tp->tx_stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005262 unsigned int dirty_tx, tx_left;
Igor Maravic036dafa2012-03-05 00:01:25 +01005263 struct rtl_txc txc = { 0, 0 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07005264
Linus Torvalds1da177e2005-04-16 15:20:36 -07005265 dirty_tx = tp->dirty_tx;
5266 smp_rmb();
5267 tx_left = tp->cur_tx - dirty_tx;
5268
5269 while (tx_left > 0) {
5270 unsigned int entry = dirty_tx % NUM_TX_DESC;
5271 struct ring_info *tx_skb = tp->tx_skb + entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005272 u32 status;
5273
5274 rmb();
5275 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5276 if (status & DescOwn)
5277 break;
5278
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005279 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5280 tp->TxDescArray + entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005281 if (status & LastFrag) {
Igor Maravic036dafa2012-03-05 00:01:25 +01005282 struct sk_buff *skb = tx_skb->skb;
5283
5284 txc.packets++;
5285 txc.bytes += skb->len;
5286 dev_kfree_skb(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005287 tx_skb->skb = NULL;
5288 }
5289 dirty_tx++;
5290 tx_left--;
5291 }
5292
Igor Maravic036dafa2012-03-05 00:01:25 +01005293 u64_stats_update_begin(&tx_stats->syncp);
5294 tx_stats->packets += txc.packets;
5295 tx_stats->bytes += txc.bytes;
5296 u64_stats_update_end(&tx_stats->syncp);
5297
5298 netdev_completed_queue(dev, txc.packets, txc.bytes);
5299
Linus Torvalds1da177e2005-04-16 15:20:36 -07005300 if (tp->dirty_tx != dirty_tx) {
5301 tp->dirty_tx = dirty_tx;
Francois Romieuae1f23f2012-01-31 00:00:19 +01005302 /* Sync with rtl8169_start_xmit:
5303 * - publish dirty_tx ring index (write barrier)
5304 * - refresh cur_tx ring index and queue status (read barrier)
5305 * May the current thread miss the stopped queue condition,
5306 * a racing xmit thread can only have a right view of the
5307 * ring status.
5308 */
Francois Romieu1e874e02012-01-27 15:05:38 +01005309 smp_mb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005310 if (netif_queue_stopped(dev) &&
5311 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5312 netif_wake_queue(dev);
5313 }
Francois Romieud78ae2d2007-08-26 20:08:19 +02005314 /*
5315 * 8168 hack: TxPoll requests are lost when the Tx packets are
5316 * too close. Let's kick an extra TxPoll request when a burst
5317 * of start_xmit activity is detected (if it is not detected,
5318 * it is slow enough). -- FR
5319 */
Francois Romieuda78dbf2012-01-26 14:18:23 +01005320 if (tp->cur_tx != dirty_tx) {
5321 void __iomem *ioaddr = tp->mmio_addr;
5322
Francois Romieud78ae2d2007-08-26 20:08:19 +02005323 RTL_W8(TxPoll, NPQ);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005324 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005325 }
5326}
5327
Francois Romieu126fa4b2005-05-12 20:09:17 -04005328static inline int rtl8169_fragmented_frame(u32 status)
5329{
5330 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5331}
5332
Eric Dumazetadea1ac72010-09-05 20:04:05 -07005333static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005334{
Linus Torvalds1da177e2005-04-16 15:20:36 -07005335 u32 status = opts1 & RxProtoMask;
5336
5337 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
Shan Weid5d3ebe2010-11-12 00:15:25 +00005338 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07005339 skb->ip_summed = CHECKSUM_UNNECESSARY;
5340 else
Eric Dumazetbc8acf22010-09-02 13:07:41 -07005341 skb_checksum_none_assert(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005342}
5343
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005344static struct sk_buff *rtl8169_try_rx_copy(void *data,
5345 struct rtl8169_private *tp,
5346 int pkt_size,
5347 dma_addr_t addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005348{
Stephen Hemmingerb4496552007-06-17 01:06:49 +02005349 struct sk_buff *skb;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005350 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005351
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005352 data = rtl8169_align(data);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005353 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005354 prefetch(data);
5355 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5356 if (skb)
5357 memcpy(skb->data, data, pkt_size);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00005358 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5359
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005360 return skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005361}
5362
Francois Romieuda78dbf2012-01-26 14:18:23 +01005363static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005364{
5365 unsigned int cur_rx, rx_left;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005366 unsigned int count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005367
Linus Torvalds1da177e2005-04-16 15:20:36 -07005368 cur_rx = tp->cur_rx;
5369 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
Francois Romieu865c6522008-05-11 14:51:00 +02005370 rx_left = min(rx_left, budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005371
Richard Dawe4dcb7d32005-05-27 21:12:00 +02005372 for (; rx_left > 0; rx_left--, cur_rx++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005373 unsigned int entry = cur_rx % NUM_RX_DESC;
Francois Romieu126fa4b2005-05-12 20:09:17 -04005374 struct RxDesc *desc = tp->RxDescArray + entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005375 u32 status;
5376
5377 rmb();
David S. Miller8decf862011-09-22 03:23:13 -04005378 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005379
5380 if (status & DescOwn)
5381 break;
Richard Dawe4dcb7d32005-05-27 21:12:00 +02005382 if (unlikely(status & RxRES)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00005383 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5384 status);
Francois Romieucebf8cc2007-10-18 12:06:54 +02005385 dev->stats.rx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005386 if (status & (RxRWT | RxRUNT))
Francois Romieucebf8cc2007-10-18 12:06:54 +02005387 dev->stats.rx_length_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005388 if (status & RxCRC)
Francois Romieucebf8cc2007-10-18 12:06:54 +02005389 dev->stats.rx_crc_errors++;
Francois Romieu9dccf612006-05-14 12:31:17 +02005390 if (status & RxFOVF) {
Francois Romieuda78dbf2012-01-26 14:18:23 +01005391 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
Francois Romieucebf8cc2007-10-18 12:06:54 +02005392 dev->stats.rx_fifo_errors++;
Francois Romieu9dccf612006-05-14 12:31:17 +02005393 }
Ben Greear6bbe0212012-02-10 15:04:33 +00005394 if ((status & (RxRUNT | RxCRC)) &&
5395 !(status & (RxRWT | RxFOVF)) &&
5396 (dev->features & NETIF_F_RXALL))
5397 goto process_pkt;
5398
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005399 rtl8169_mark_to_asic(desc, rx_buf_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005400 } else {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005401 struct sk_buff *skb;
Ben Greear6bbe0212012-02-10 15:04:33 +00005402 dma_addr_t addr;
5403 int pkt_size;
5404
5405process_pkt:
5406 addr = le64_to_cpu(desc->addr);
Ben Greear79d0c1d2012-02-10 15:04:34 +00005407 if (likely(!(dev->features & NETIF_F_RXFCS)))
5408 pkt_size = (status & 0x00003fff) - 4;
5409 else
5410 pkt_size = status & 0x00003fff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005411
Francois Romieu126fa4b2005-05-12 20:09:17 -04005412 /*
5413 * The driver does not support incoming fragmented
5414 * frames. They are seen as a symptom of over-mtu
5415 * sized frames.
5416 */
5417 if (unlikely(rtl8169_fragmented_frame(status))) {
Francois Romieucebf8cc2007-10-18 12:06:54 +02005418 dev->stats.rx_dropped++;
5419 dev->stats.rx_length_errors++;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005420 rtl8169_mark_to_asic(desc, rx_buf_sz);
Richard Dawe4dcb7d32005-05-27 21:12:00 +02005421 continue;
Francois Romieu126fa4b2005-05-12 20:09:17 -04005422 }
5423
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005424 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5425 tp, pkt_size, addr);
5426 rtl8169_mark_to_asic(desc, rx_buf_sz);
5427 if (!skb) {
5428 dev->stats.rx_dropped++;
5429 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005430 }
5431
Eric Dumazetadea1ac72010-09-05 20:04:05 -07005432 rtl8169_rx_csum(skb, status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005433 skb_put(skb, pkt_size);
5434 skb->protocol = eth_type_trans(skb, dev);
5435
Francois Romieu7a8fc772011-03-01 17:18:33 +01005436 rtl8169_rx_vlan_tag(desc, skb);
5437
Francois Romieu56de4142011-03-15 17:29:31 +01005438 napi_gro_receive(&tp->napi, skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005439
Junchang Wang8027aa22012-03-04 23:30:32 +01005440 u64_stats_update_begin(&tp->rx_stats.syncp);
5441 tp->rx_stats.packets++;
5442 tp->rx_stats.bytes += pkt_size;
5443 u64_stats_update_end(&tp->rx_stats.syncp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005444 }
Francois Romieu6dccd162007-02-13 23:38:05 +01005445
5446 /* Work around for AMD plateform. */
Al Viro95e09182007-12-22 18:55:39 +00005447 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
Francois Romieu6dccd162007-02-13 23:38:05 +01005448 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5449 desc->opts2 = 0;
5450 cur_rx++;
5451 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005452 }
5453
5454 count = cur_rx - tp->cur_rx;
5455 tp->cur_rx = cur_rx;
5456
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005457 tp->dirty_rx += count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005458
5459 return count;
5460}
5461
Francois Romieu07d3f512007-02-21 22:40:46 +01005462static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005463{
Francois Romieu07d3f512007-02-21 22:40:46 +01005464 struct net_device *dev = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005465 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005466 int handled = 0;
Francois Romieu9085cdfa2012-01-26 12:59:08 +01005467 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005468
Francois Romieu9085cdfa2012-01-26 12:59:08 +01005469 status = rtl_get_events(tp);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005470 if (status && status != 0xffff) {
5471 status &= RTL_EVENT_NAPI | tp->event_slow;
5472 if (status) {
5473 handled = 1;
françois romieu811fd302011-12-04 20:30:45 +00005474
Francois Romieuda78dbf2012-01-26 14:18:23 +01005475 rtl_irq_disable(tp);
5476 napi_schedule(&tp->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005477 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005478 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005479 return IRQ_RETVAL(handled);
5480}
5481
Francois Romieuda78dbf2012-01-26 14:18:23 +01005482/*
5483 * Workqueue context.
5484 */
5485static void rtl_slow_event_work(struct rtl8169_private *tp)
5486{
5487 struct net_device *dev = tp->dev;
5488 u16 status;
5489
5490 status = rtl_get_events(tp) & tp->event_slow;
5491 rtl_ack_events(tp, status);
5492
5493 if (unlikely(status & RxFIFOOver)) {
5494 switch (tp->mac_version) {
5495 /* Work around for rx fifo overflow */
5496 case RTL_GIGA_MAC_VER_11:
5497 netif_stop_queue(dev);
Francois Romieu934714d2012-01-31 11:09:21 +01005498 /* XXX - Hack alert. See rtl_task(). */
5499 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005500 default:
5501 break;
5502 }
5503 }
5504
5505 if (unlikely(status & SYSErr))
5506 rtl8169_pcierr_interrupt(dev);
5507
5508 if (status & LinkChg)
5509 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5510
5511 napi_disable(&tp->napi);
5512 rtl_irq_disable(tp);
5513
5514 napi_enable(&tp->napi);
5515 napi_schedule(&tp->napi);
5516}
5517
Francois Romieu4422bcd2012-01-26 11:23:32 +01005518static void rtl_task(struct work_struct *work)
5519{
Francois Romieuda78dbf2012-01-26 14:18:23 +01005520 static const struct {
5521 int bitnr;
5522 void (*action)(struct rtl8169_private *);
5523 } rtl_work[] = {
Francois Romieu934714d2012-01-31 11:09:21 +01005524 /* XXX - keep rtl_slow_event_work() as first element. */
Francois Romieuda78dbf2012-01-26 14:18:23 +01005525 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5526 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5527 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5528 };
Francois Romieu4422bcd2012-01-26 11:23:32 +01005529 struct rtl8169_private *tp =
5530 container_of(work, struct rtl8169_private, wk.work);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005531 struct net_device *dev = tp->dev;
5532 int i;
Francois Romieu4422bcd2012-01-26 11:23:32 +01005533
Francois Romieuda78dbf2012-01-26 14:18:23 +01005534 rtl_lock_work(tp);
5535
Francois Romieu6c4a70c2012-01-31 10:56:44 +01005536 if (!netif_running(dev) ||
5537 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
Francois Romieuda78dbf2012-01-26 14:18:23 +01005538 goto out_unlock;
5539
5540 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5541 bool pending;
5542
Francois Romieuda78dbf2012-01-26 14:18:23 +01005543 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005544 if (pending)
5545 rtl_work[i].action(tp);
5546 }
5547
5548out_unlock:
5549 rtl_unlock_work(tp);
Francois Romieu4422bcd2012-01-26 11:23:32 +01005550}
5551
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005552static int rtl8169_poll(struct napi_struct *napi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005553{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005554 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5555 struct net_device *dev = tp->dev;
Francois Romieuda78dbf2012-01-26 14:18:23 +01005556 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5557 int work_done= 0;
5558 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005559
Francois Romieuda78dbf2012-01-26 14:18:23 +01005560 status = rtl_get_events(tp);
5561 rtl_ack_events(tp, status & ~tp->event_slow);
5562
5563 if (status & RTL_EVENT_NAPI_RX)
5564 work_done = rtl_rx(dev, tp, (u32) budget);
5565
5566 if (status & RTL_EVENT_NAPI_TX)
5567 rtl_tx(dev, tp);
5568
5569 if (status & tp->event_slow) {
5570 enable_mask &= ~tp->event_slow;
5571
5572 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5573 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005574
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005575 if (work_done < budget) {
Ben Hutchings288379f2009-01-19 16:43:59 -08005576 napi_complete(napi);
David Dillowf11a3772009-05-22 15:29:34 +00005577
Francois Romieuda78dbf2012-01-26 14:18:23 +01005578 rtl_irq_enable(tp, enable_mask);
5579 mmiowb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005580 }
5581
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005582 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005583}
Linus Torvalds1da177e2005-04-16 15:20:36 -07005584
Francois Romieu523a6092008-09-10 22:28:56 +02005585static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5586{
5587 struct rtl8169_private *tp = netdev_priv(dev);
5588
5589 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5590 return;
5591
5592 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5593 RTL_W32(RxMissed, 0);
5594}
5595
Linus Torvalds1da177e2005-04-16 15:20:36 -07005596static void rtl8169_down(struct net_device *dev)
5597{
5598 struct rtl8169_private *tp = netdev_priv(dev);
5599 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005600
Francois Romieu4876cc12011-03-11 21:07:11 +01005601 del_timer_sync(&tp->timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005602
Stephen Hemminger93dd79e2007-10-28 17:14:06 +01005603 napi_disable(&tp->napi);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005604 netif_stop_queue(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005605
Hayes Wang92fc43b2011-07-06 15:58:03 +08005606 rtl8169_hw_reset(tp);
Stanislaw Gruszka323bb682010-10-20 22:25:41 +00005607 /*
5608 * At this point device interrupts can not be enabled in any function,
Francois Romieu209e5ac2012-01-26 09:59:50 +01005609 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5610 * and napi is disabled (rtl8169_poll).
Stanislaw Gruszka323bb682010-10-20 22:25:41 +00005611 */
Francois Romieu523a6092008-09-10 22:28:56 +02005612 rtl8169_rx_missed(dev, ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005613
Linus Torvalds1da177e2005-04-16 15:20:36 -07005614 /* Give a racing hard_start_xmit a few cycles to complete. */
Francois Romieuda78dbf2012-01-26 14:18:23 +01005615 synchronize_sched();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005616
Linus Torvalds1da177e2005-04-16 15:20:36 -07005617 rtl8169_tx_clear(tp);
5618
5619 rtl8169_rx_clear(tp);
françois romieu065c27c2011-01-03 15:08:12 +00005620
5621 rtl_pll_power_down(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005622}
5623
5624static int rtl8169_close(struct net_device *dev)
5625{
5626 struct rtl8169_private *tp = netdev_priv(dev);
5627 struct pci_dev *pdev = tp->pci_dev;
5628
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005629 pm_runtime_get_sync(&pdev->dev);
5630
Francois Romieucecb5fd2011-04-01 10:21:07 +02005631 /* Update counters before going down */
Ivan Vecera355423d2009-02-06 21:49:57 -08005632 rtl8169_update_counters(dev);
5633
Francois Romieuda78dbf2012-01-26 14:18:23 +01005634 rtl_lock_work(tp);
Francois Romieu6c4a70c2012-01-31 10:56:44 +01005635 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005636
Linus Torvalds1da177e2005-04-16 15:20:36 -07005637 rtl8169_down(dev);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005638 rtl_unlock_work(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005639
Francois Romieu92a7c4e2012-03-10 10:42:12 +01005640 free_irq(pdev->irq, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005641
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00005642 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5643 tp->RxPhyAddr);
5644 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5645 tp->TxPhyAddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005646 tp->TxDescArray = NULL;
5647 tp->RxDescArray = NULL;
5648
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005649 pm_runtime_put_sync(&pdev->dev);
5650
Linus Torvalds1da177e2005-04-16 15:20:36 -07005651 return 0;
5652}
5653
Francois Romieudc1c00c2012-03-08 10:06:18 +01005654#ifdef CONFIG_NET_POLL_CONTROLLER
5655static void rtl8169_netpoll(struct net_device *dev)
5656{
5657 struct rtl8169_private *tp = netdev_priv(dev);
5658
5659 rtl8169_interrupt(tp->pci_dev->irq, dev);
5660}
5661#endif
5662
Francois Romieudf43ac72012-03-08 09:48:40 +01005663static int rtl_open(struct net_device *dev)
5664{
5665 struct rtl8169_private *tp = netdev_priv(dev);
5666 void __iomem *ioaddr = tp->mmio_addr;
5667 struct pci_dev *pdev = tp->pci_dev;
5668 int retval = -ENOMEM;
5669
5670 pm_runtime_get_sync(&pdev->dev);
5671
5672 /*
5673 * Rx and Tx desscriptors needs 256 bytes alignment.
5674 * dma_alloc_coherent provides more.
5675 */
5676 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5677 &tp->TxPhyAddr, GFP_KERNEL);
5678 if (!tp->TxDescArray)
5679 goto err_pm_runtime_put;
5680
5681 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5682 &tp->RxPhyAddr, GFP_KERNEL);
5683 if (!tp->RxDescArray)
5684 goto err_free_tx_0;
5685
5686 retval = rtl8169_init_ring(dev);
5687 if (retval < 0)
5688 goto err_free_rx_1;
5689
5690 INIT_WORK(&tp->wk.work, rtl_task);
5691
5692 smp_mb();
5693
5694 rtl_request_firmware(tp);
5695
Francois Romieu92a7c4e2012-03-10 10:42:12 +01005696 retval = request_irq(pdev->irq, rtl8169_interrupt,
Francois Romieudf43ac72012-03-08 09:48:40 +01005697 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5698 dev->name, dev);
5699 if (retval < 0)
5700 goto err_release_fw_2;
5701
5702 rtl_lock_work(tp);
5703
5704 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5705
5706 napi_enable(&tp->napi);
5707
5708 rtl8169_init_phy(dev, tp);
5709
5710 __rtl8169_set_features(dev, dev->features);
5711
5712 rtl_pll_power_up(tp);
5713
5714 rtl_hw_start(dev);
5715
5716 netif_start_queue(dev);
5717
5718 rtl_unlock_work(tp);
5719
5720 tp->saved_wolopts = 0;
5721 pm_runtime_put_noidle(&pdev->dev);
5722
5723 rtl8169_check_link_status(dev, tp, ioaddr);
5724out:
5725 return retval;
5726
5727err_release_fw_2:
5728 rtl_release_firmware(tp);
5729 rtl8169_rx_clear(tp);
5730err_free_rx_1:
5731 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5732 tp->RxPhyAddr);
5733 tp->RxDescArray = NULL;
5734err_free_tx_0:
5735 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5736 tp->TxPhyAddr);
5737 tp->TxDescArray = NULL;
5738err_pm_runtime_put:
5739 pm_runtime_put_noidle(&pdev->dev);
5740 goto out;
5741}
5742
Junchang Wang8027aa22012-03-04 23:30:32 +01005743static struct rtnl_link_stats64 *
5744rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005745{
5746 struct rtl8169_private *tp = netdev_priv(dev);
5747 void __iomem *ioaddr = tp->mmio_addr;
Junchang Wang8027aa22012-03-04 23:30:32 +01005748 unsigned int start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005749
Francois Romieuda78dbf2012-01-26 14:18:23 +01005750 if (netif_running(dev))
Francois Romieu523a6092008-09-10 22:28:56 +02005751 rtl8169_rx_missed(dev, ioaddr);
Francois Romieu5b0384f2006-08-16 16:00:01 +02005752
Junchang Wang8027aa22012-03-04 23:30:32 +01005753 do {
5754 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5755 stats->rx_packets = tp->rx_stats.packets;
5756 stats->rx_bytes = tp->rx_stats.bytes;
5757 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5758
5759
5760 do {
5761 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5762 stats->tx_packets = tp->tx_stats.packets;
5763 stats->tx_bytes = tp->tx_stats.bytes;
5764 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5765
5766 stats->rx_dropped = dev->stats.rx_dropped;
5767 stats->tx_dropped = dev->stats.tx_dropped;
5768 stats->rx_length_errors = dev->stats.rx_length_errors;
5769 stats->rx_errors = dev->stats.rx_errors;
5770 stats->rx_crc_errors = dev->stats.rx_crc_errors;
5771 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
5772 stats->rx_missed_errors = dev->stats.rx_missed_errors;
5773
5774 return stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005775}
5776
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005777static void rtl8169_net_suspend(struct net_device *dev)
Francois Romieu5d06a992006-02-23 00:47:58 +01005778{
françois romieu065c27c2011-01-03 15:08:12 +00005779 struct rtl8169_private *tp = netdev_priv(dev);
5780
Francois Romieu5d06a992006-02-23 00:47:58 +01005781 if (!netif_running(dev))
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005782 return;
Francois Romieu5d06a992006-02-23 00:47:58 +01005783
5784 netif_device_detach(dev);
5785 netif_stop_queue(dev);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005786
5787 rtl_lock_work(tp);
5788 napi_disable(&tp->napi);
Francois Romieu6c4a70c2012-01-31 10:56:44 +01005789 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005790 rtl_unlock_work(tp);
5791
5792 rtl_pll_power_down(tp);
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005793}
Francois Romieu5d06a992006-02-23 00:47:58 +01005794
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005795#ifdef CONFIG_PM
5796
5797static int rtl8169_suspend(struct device *device)
5798{
5799 struct pci_dev *pdev = to_pci_dev(device);
5800 struct net_device *dev = pci_get_drvdata(pdev);
5801
5802 rtl8169_net_suspend(dev);
Francois Romieu1371fa62007-04-02 23:01:11 +02005803
Francois Romieu5d06a992006-02-23 00:47:58 +01005804 return 0;
5805}
5806
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005807static void __rtl8169_resume(struct net_device *dev)
5808{
françois romieu065c27c2011-01-03 15:08:12 +00005809 struct rtl8169_private *tp = netdev_priv(dev);
5810
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005811 netif_device_attach(dev);
françois romieu065c27c2011-01-03 15:08:12 +00005812
5813 rtl_pll_power_up(tp);
5814
Francois Romieu6c4a70c2012-01-31 10:56:44 +01005815 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005816
Francois Romieu98ddf982012-01-31 10:47:34 +01005817 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005818}
5819
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005820static int rtl8169_resume(struct device *device)
Francois Romieu5d06a992006-02-23 00:47:58 +01005821{
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005822 struct pci_dev *pdev = to_pci_dev(device);
Francois Romieu5d06a992006-02-23 00:47:58 +01005823 struct net_device *dev = pci_get_drvdata(pdev);
Stanislaw Gruszkafccec102010-10-20 22:25:42 +00005824 struct rtl8169_private *tp = netdev_priv(dev);
5825
5826 rtl8169_init_phy(dev, tp);
Francois Romieu5d06a992006-02-23 00:47:58 +01005827
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005828 if (netif_running(dev))
5829 __rtl8169_resume(dev);
Francois Romieu5d06a992006-02-23 00:47:58 +01005830
Francois Romieu5d06a992006-02-23 00:47:58 +01005831 return 0;
5832}
5833
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005834static int rtl8169_runtime_suspend(struct device *device)
5835{
5836 struct pci_dev *pdev = to_pci_dev(device);
5837 struct net_device *dev = pci_get_drvdata(pdev);
5838 struct rtl8169_private *tp = netdev_priv(dev);
5839
5840 if (!tp->TxDescArray)
5841 return 0;
5842
Francois Romieuda78dbf2012-01-26 14:18:23 +01005843 rtl_lock_work(tp);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005844 tp->saved_wolopts = __rtl8169_get_wol(tp);
5845 __rtl8169_set_wol(tp, WAKE_ANY);
Francois Romieuda78dbf2012-01-26 14:18:23 +01005846 rtl_unlock_work(tp);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005847
5848 rtl8169_net_suspend(dev);
5849
5850 return 0;
5851}
5852
5853static int rtl8169_runtime_resume(struct device *device)
5854{
5855 struct pci_dev *pdev = to_pci_dev(device);
5856 struct net_device *dev = pci_get_drvdata(pdev);
5857 struct rtl8169_private *tp = netdev_priv(dev);
5858
5859 if (!tp->TxDescArray)
5860 return 0;
5861
Francois Romieuda78dbf2012-01-26 14:18:23 +01005862 rtl_lock_work(tp);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005863 __rtl8169_set_wol(tp, tp->saved_wolopts);
5864 tp->saved_wolopts = 0;
Francois Romieuda78dbf2012-01-26 14:18:23 +01005865 rtl_unlock_work(tp);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005866
Stanislaw Gruszkafccec102010-10-20 22:25:42 +00005867 rtl8169_init_phy(dev, tp);
5868
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005869 __rtl8169_resume(dev);
5870
5871 return 0;
5872}
5873
5874static int rtl8169_runtime_idle(struct device *device)
5875{
5876 struct pci_dev *pdev = to_pci_dev(device);
5877 struct net_device *dev = pci_get_drvdata(pdev);
5878 struct rtl8169_private *tp = netdev_priv(dev);
5879
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00005880 return tp->TxDescArray ? -EBUSY : 0;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005881}
5882
Alexey Dobriyan47145212009-12-14 18:00:08 -08005883static const struct dev_pm_ops rtl8169_pm_ops = {
Francois Romieucecb5fd2011-04-01 10:21:07 +02005884 .suspend = rtl8169_suspend,
5885 .resume = rtl8169_resume,
5886 .freeze = rtl8169_suspend,
5887 .thaw = rtl8169_resume,
5888 .poweroff = rtl8169_suspend,
5889 .restore = rtl8169_resume,
5890 .runtime_suspend = rtl8169_runtime_suspend,
5891 .runtime_resume = rtl8169_runtime_resume,
5892 .runtime_idle = rtl8169_runtime_idle,
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005893};
5894
5895#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5896
5897#else /* !CONFIG_PM */
5898
5899#define RTL8169_PM_OPS NULL
5900
5901#endif /* !CONFIG_PM */
5902
David S. Miller1805b2f2011-10-24 18:18:09 -04005903static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5904{
5905 void __iomem *ioaddr = tp->mmio_addr;
5906
5907 /* WoL fails with 8168b when the receiver is disabled. */
5908 switch (tp->mac_version) {
5909 case RTL_GIGA_MAC_VER_11:
5910 case RTL_GIGA_MAC_VER_12:
5911 case RTL_GIGA_MAC_VER_17:
5912 pci_clear_master(tp->pci_dev);
5913
5914 RTL_W8(ChipCmd, CmdRxEnb);
5915 /* PCI commit */
5916 RTL_R8(ChipCmd);
5917 break;
5918 default:
5919 break;
5920 }
5921}
5922
Francois Romieu1765f952008-09-13 17:21:40 +02005923static void rtl_shutdown(struct pci_dev *pdev)
5924{
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005925 struct net_device *dev = pci_get_drvdata(pdev);
françois romieu4bb3f522009-06-17 11:41:45 +00005926 struct rtl8169_private *tp = netdev_priv(dev);
françois romieu2a15cd22012-03-06 01:14:12 +00005927 struct device *d = &pdev->dev;
5928
5929 pm_runtime_get_sync(d);
Francois Romieu1765f952008-09-13 17:21:40 +02005930
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005931 rtl8169_net_suspend(dev);
5932
Francois Romieucecb5fd2011-04-01 10:21:07 +02005933 /* Restore original MAC address */
Ivan Veceracc098dc2009-11-29 23:12:52 -08005934 rtl_rar_set(tp, dev->perm_addr);
5935
Hayes Wang92fc43b2011-07-06 15:58:03 +08005936 rtl8169_hw_reset(tp);
françois romieu4bb3f522009-06-17 11:41:45 +00005937
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005938 if (system_state == SYSTEM_POWER_OFF) {
David S. Miller1805b2f2011-10-24 18:18:09 -04005939 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5940 rtl_wol_suspend_quirk(tp);
5941 rtl_wol_shutdown_quirk(tp);
françois romieuca52efd2009-07-24 12:34:19 +00005942 }
5943
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005944 pci_wake_from_d3(pdev, true);
5945 pci_set_power_state(pdev, PCI_D3hot);
5946 }
françois romieu2a15cd22012-03-06 01:14:12 +00005947
5948 pm_runtime_put_noidle(d);
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005949}
Francois Romieu5d06a992006-02-23 00:47:58 +01005950
Francois Romieue27566e2012-03-08 09:54:01 +01005951static void __devexit rtl_remove_one(struct pci_dev *pdev)
5952{
5953 struct net_device *dev = pci_get_drvdata(pdev);
5954 struct rtl8169_private *tp = netdev_priv(dev);
5955
5956 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5957 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5958 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5959 rtl8168_driver_stop(tp);
5960 }
5961
5962 cancel_work_sync(&tp->wk.work);
5963
5964 unregister_netdev(dev);
5965
5966 rtl_release_firmware(tp);
5967
5968 if (pci_dev_run_wake(pdev))
5969 pm_runtime_get_noresume(&pdev->dev);
5970
5971 /* restore original MAC address */
5972 rtl_rar_set(tp, dev->perm_addr);
5973
5974 rtl_disable_msi(pdev, tp);
5975 rtl8169_release_board(pdev, dev, tp->mmio_addr);
5976 pci_set_drvdata(pdev, NULL);
5977}
5978
Francois Romieufa9c3852012-03-08 10:01:50 +01005979static const struct net_device_ops rtl_netdev_ops = {
Francois Romieudf43ac72012-03-08 09:48:40 +01005980 .ndo_open = rtl_open,
Francois Romieufa9c3852012-03-08 10:01:50 +01005981 .ndo_stop = rtl8169_close,
5982 .ndo_get_stats64 = rtl8169_get_stats64,
5983 .ndo_start_xmit = rtl8169_start_xmit,
5984 .ndo_tx_timeout = rtl8169_tx_timeout,
5985 .ndo_validate_addr = eth_validate_addr,
5986 .ndo_change_mtu = rtl8169_change_mtu,
5987 .ndo_fix_features = rtl8169_fix_features,
5988 .ndo_set_features = rtl8169_set_features,
5989 .ndo_set_mac_address = rtl_set_mac_address,
5990 .ndo_do_ioctl = rtl8169_ioctl,
5991 .ndo_set_rx_mode = rtl_set_rx_mode,
5992#ifdef CONFIG_NET_POLL_CONTROLLER
5993 .ndo_poll_controller = rtl8169_netpoll,
5994#endif
5995
5996};
5997
Francois Romieu31fa8b12012-03-08 10:09:40 +01005998static const struct rtl_cfg_info {
5999 void (*hw_start)(struct net_device *);
6000 unsigned int region;
6001 unsigned int align;
6002 u16 event_slow;
6003 unsigned features;
6004 u8 default_ver;
6005} rtl_cfg_infos [] = {
6006 [RTL_CFG_0] = {
6007 .hw_start = rtl_hw_start_8169,
6008 .region = 1,
6009 .align = 0,
6010 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6011 .features = RTL_FEATURE_GMII,
6012 .default_ver = RTL_GIGA_MAC_VER_01,
6013 },
6014 [RTL_CFG_1] = {
6015 .hw_start = rtl_hw_start_8168,
6016 .region = 2,
6017 .align = 8,
6018 .event_slow = SYSErr | LinkChg | RxOverflow,
6019 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6020 .default_ver = RTL_GIGA_MAC_VER_11,
6021 },
6022 [RTL_CFG_2] = {
6023 .hw_start = rtl_hw_start_8101,
6024 .region = 2,
6025 .align = 8,
6026 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6027 PCSTimeout,
6028 .features = RTL_FEATURE_MSI,
6029 .default_ver = RTL_GIGA_MAC_VER_13,
6030 }
6031};
6032
6033/* Cfg9346_Unlock assumed. */
6034static unsigned rtl_try_msi(struct rtl8169_private *tp,
6035 const struct rtl_cfg_info *cfg)
6036{
6037 void __iomem *ioaddr = tp->mmio_addr;
6038 unsigned msi = 0;
6039 u8 cfg2;
6040
6041 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6042 if (cfg->features & RTL_FEATURE_MSI) {
6043 if (pci_enable_msi(tp->pci_dev)) {
6044 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6045 } else {
6046 cfg2 |= MSIEnable;
6047 msi = RTL_FEATURE_MSI;
6048 }
6049 }
6050 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6051 RTL_W8(Config2, cfg2);
6052 return msi;
6053}
6054
Francois Romieu3b6cf252012-03-08 09:59:04 +01006055static int __devinit
6056rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6057{
6058 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6059 const unsigned int region = cfg->region;
6060 struct rtl8169_private *tp;
6061 struct mii_if_info *mii;
6062 struct net_device *dev;
6063 void __iomem *ioaddr;
6064 int chipset, i;
6065 int rc;
6066
6067 if (netif_msg_drv(&debug)) {
6068 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6069 MODULENAME, RTL8169_VERSION);
6070 }
6071
6072 dev = alloc_etherdev(sizeof (*tp));
6073 if (!dev) {
6074 rc = -ENOMEM;
6075 goto out;
6076 }
6077
6078 SET_NETDEV_DEV(dev, &pdev->dev);
Francois Romieufa9c3852012-03-08 10:01:50 +01006079 dev->netdev_ops = &rtl_netdev_ops;
Francois Romieu3b6cf252012-03-08 09:59:04 +01006080 tp = netdev_priv(dev);
6081 tp->dev = dev;
6082 tp->pci_dev = pdev;
6083 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6084
6085 mii = &tp->mii;
6086 mii->dev = dev;
6087 mii->mdio_read = rtl_mdio_read;
6088 mii->mdio_write = rtl_mdio_write;
6089 mii->phy_id_mask = 0x1f;
6090 mii->reg_num_mask = 0x1f;
6091 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6092
6093 /* disable ASPM completely as that cause random device stop working
6094 * problems as well as full system hangs for some PCIe devices users */
6095 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6096 PCIE_LINK_STATE_CLKPM);
6097
6098 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6099 rc = pci_enable_device(pdev);
6100 if (rc < 0) {
6101 netif_err(tp, probe, dev, "enable failure\n");
6102 goto err_out_free_dev_1;
6103 }
6104
6105 if (pci_set_mwi(pdev) < 0)
6106 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6107
6108 /* make sure PCI base addr 1 is MMIO */
6109 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6110 netif_err(tp, probe, dev,
6111 "region #%d not an MMIO resource, aborting\n",
6112 region);
6113 rc = -ENODEV;
6114 goto err_out_mwi_2;
6115 }
6116
6117 /* check for weird/broken PCI region reporting */
6118 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6119 netif_err(tp, probe, dev,
6120 "Invalid PCI region size(s), aborting\n");
6121 rc = -ENODEV;
6122 goto err_out_mwi_2;
6123 }
6124
6125 rc = pci_request_regions(pdev, MODULENAME);
6126 if (rc < 0) {
6127 netif_err(tp, probe, dev, "could not request regions\n");
6128 goto err_out_mwi_2;
6129 }
6130
6131 tp->cp_cmd = RxChkSum;
6132
6133 if ((sizeof(dma_addr_t) > 4) &&
6134 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6135 tp->cp_cmd |= PCIDAC;
6136 dev->features |= NETIF_F_HIGHDMA;
6137 } else {
6138 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6139 if (rc < 0) {
6140 netif_err(tp, probe, dev, "DMA configuration failed\n");
6141 goto err_out_free_res_3;
6142 }
6143 }
6144
6145 /* ioremap MMIO region */
6146 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6147 if (!ioaddr) {
6148 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6149 rc = -EIO;
6150 goto err_out_free_res_3;
6151 }
6152 tp->mmio_addr = ioaddr;
6153
6154 if (!pci_is_pcie(pdev))
6155 netif_info(tp, probe, dev, "not PCI Express\n");
6156
6157 /* Identify chip attached to board */
6158 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6159
6160 rtl_init_rxcfg(tp);
6161
6162 rtl_irq_disable(tp);
6163
6164 rtl_hw_reset(tp);
6165
6166 rtl_ack_events(tp, 0xffff);
6167
6168 pci_set_master(pdev);
6169
6170 /*
6171 * Pretend we are using VLANs; This bypasses a nasty bug where
6172 * Interrupts stop flowing on high load on 8110SCd controllers.
6173 */
6174 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6175 tp->cp_cmd |= RxVlan;
6176
6177 rtl_init_mdio_ops(tp);
6178 rtl_init_pll_power_ops(tp);
6179 rtl_init_jumbo_ops(tp);
6180
6181 rtl8169_print_mac_version(tp);
6182
6183 chipset = tp->mac_version;
6184 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6185
6186 RTL_W8(Cfg9346, Cfg9346_Unlock);
6187 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6188 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6189 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6190 tp->features |= RTL_FEATURE_WOL;
6191 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6192 tp->features |= RTL_FEATURE_WOL;
6193 tp->features |= rtl_try_msi(tp, cfg);
6194 RTL_W8(Cfg9346, Cfg9346_Lock);
6195
6196 if (rtl_tbi_enabled(tp)) {
6197 tp->set_speed = rtl8169_set_speed_tbi;
6198 tp->get_settings = rtl8169_gset_tbi;
6199 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6200 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6201 tp->link_ok = rtl8169_tbi_link_ok;
6202 tp->do_ioctl = rtl_tbi_ioctl;
6203 } else {
6204 tp->set_speed = rtl8169_set_speed_xmii;
6205 tp->get_settings = rtl8169_gset_xmii;
6206 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6207 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6208 tp->link_ok = rtl8169_xmii_link_ok;
6209 tp->do_ioctl = rtl_xmii_ioctl;
6210 }
6211
6212 mutex_init(&tp->wk.mutex);
6213
6214 /* Get MAC address */
6215 for (i = 0; i < ETH_ALEN; i++)
6216 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6217 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6218
6219 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6220 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
Francois Romieu3b6cf252012-03-08 09:59:04 +01006221
6222 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6223
6224 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6225 * properly for all devices */
6226 dev->features |= NETIF_F_RXCSUM |
6227 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6228
6229 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6230 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6231 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6232 NETIF_F_HIGHDMA;
6233
6234 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6235 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6236 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6237
6238 dev->hw_features |= NETIF_F_RXALL;
6239 dev->hw_features |= NETIF_F_RXFCS;
6240
6241 tp->hw_start = cfg->hw_start;
6242 tp->event_slow = cfg->event_slow;
6243
6244 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6245 ~(RxBOVF | RxFOVF) : ~0;
6246
6247 init_timer(&tp->timer);
6248 tp->timer.data = (unsigned long) dev;
6249 tp->timer.function = rtl8169_phy_timer;
6250
6251 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6252
6253 rc = register_netdev(dev);
6254 if (rc < 0)
6255 goto err_out_msi_4;
6256
6257 pci_set_drvdata(pdev, dev);
6258
Francois Romieu92a7c4e2012-03-10 10:42:12 +01006259 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6260 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6261 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
Francois Romieu3b6cf252012-03-08 09:59:04 +01006262 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6263 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6264 "tx checksumming: %s]\n",
6265 rtl_chip_infos[chipset].jumbo_max,
6266 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6267 }
6268
6269 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6270 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6271 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6272 rtl8168_driver_start(tp);
6273 }
6274
6275 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6276
6277 if (pci_dev_run_wake(pdev))
6278 pm_runtime_put_noidle(&pdev->dev);
6279
6280 netif_carrier_off(dev);
6281
6282out:
6283 return rc;
6284
6285err_out_msi_4:
6286 rtl_disable_msi(pdev, tp);
6287 iounmap(ioaddr);
6288err_out_free_res_3:
6289 pci_release_regions(pdev);
6290err_out_mwi_2:
6291 pci_clear_mwi(pdev);
6292 pci_disable_device(pdev);
6293err_out_free_dev_1:
6294 free_netdev(dev);
6295 goto out;
6296}
6297
Linus Torvalds1da177e2005-04-16 15:20:36 -07006298static struct pci_driver rtl8169_pci_driver = {
6299 .name = MODULENAME,
6300 .id_table = rtl8169_pci_tbl,
Francois Romieu3b6cf252012-03-08 09:59:04 +01006301 .probe = rtl_init_one,
Francois Romieue27566e2012-03-08 09:54:01 +01006302 .remove = __devexit_p(rtl_remove_one),
Francois Romieu1765f952008-09-13 17:21:40 +02006303 .shutdown = rtl_shutdown,
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00006304 .driver.pm = RTL8169_PM_OPS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006305};
6306
Francois Romieu07d3f512007-02-21 22:40:46 +01006307static int __init rtl8169_init_module(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006308{
Jeff Garzik29917622006-08-19 17:48:59 -04006309 return pci_register_driver(&rtl8169_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006310}
6311
Francois Romieu07d3f512007-02-21 22:40:46 +01006312static void __exit rtl8169_cleanup_module(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006313{
6314 pci_unregister_driver(&rtl8169_pci_driver);
6315}
6316
6317module_init(rtl8169_init_module);
6318module_exit(rtl8169_cleanup_module);